08th week of 2021 patent applcation highlights part 55 |
Patent application number | Title | Published |
20210057248 | RETICLE POD HAVING SIDE CONTAINMENT OF RETICLE - A reticle pod includes an outer pod, an inner pod cover and an inner base plate. A reticle is supported on the base and is contained within the environment created by the inner pod cover and the inner pod base. The inner pod cover can include a plurality of reticle retainers configured to contact a side wall of the reticle and limit movement of the reticle in a horizontal direction. | 2021-02-25 |
20210057249 | SYSTEMS, APPARATUS, AND METHODS FOR AN IMPROVED LOAD PORT - A load port system includes an isolation compartment coupled to an equipment front end module (EFEM). Reactive gas is to be removed from the isolation compartment. The load port system further includes an elevator disposed in the isolation compartment. The elevator is coupled to an elevator arm that extends from the isolation compartment into the EFEM through an opening to raise and lower a carrier opener within the EFEM. | 2021-02-25 |
20210057250 | CONVEYANCE SYSTEM - A transport system includes a track, transport vehicles, an area controller, buffers, and a host controller. The area controller, when a number of the transport vehicles present within a control area is a predetermined number and when receiving a first transport command to convey an article from a transfer port to a transport destination outside the control area from the host controller, stores the first transport command and transmits a report that the first transport command is not able to be assigned to the transport vehicle to the host controller. The host controller, when receiving the report, when the buffer is present, transmits a command to delete the stored first transport command to the area controller, generates a second transport command to convey the article from the transfer port to the buffer, and transmits the second transport command to the area controller. | 2021-02-25 |
20210057251 | SUBSTRATE TRANSPORT ROBOT, SUBSTRATE TRANSPORT SYSTEM, AND SUBSTRATE TRANSPORT METHOD - A substrate transport robot includes: a base installed inside a transport chamber; an arm; a first hand and a second hand rotatable about a vertical hand axis and configured to support a substrate; and a controller. The controller performs: a first transfer process of causing the first hand to enter from the transport chamber into a storage chamber, and transferring the substrate between the first hand and a placing portion in the storage chamber; an exit process of causing the first hand to exit the storage chamber into the transport chamber; and a second transfer process of causing the second hand to enter from the transport chamber into the storage chamber. In the exit process, the hand axis moves away from a center line of an opening, such that the hand axis is farther from the center line than a reference position of the first hand is. | 2021-02-25 |
20210057252 | TRANSFER METHOD AND TRANSFER SYSTEM - A transfer method according to an exemplary embodiment includes: transferring a focus ring onto a stage by a transfer unit; transferring a measuring instrument into an inner region of the transferred focus ring and onto an electrostatic chuck; acquiring a measurement value group by the transferred measuring instrument; and adjusting a transfer position of the focus ring by the transfer unit such that the central position of the electrostatic chuck and the central position of the focus ring coincide with each other based on the measurement value group. | 2021-02-25 |
20210057253 | TRANSFER UNIT AND SUBSTRATE TREATING APPARATUS INCLUDING THE SAME - An apparatus for treating a substrate includes an index module and a treatment module that treats the substrate. The index module includes a load port on which a carrier having a plurality of substrates received therein is loaded and a transfer frame that is disposed between the treatment module and the load port and that transfers the substrate between the carrier loaded on the load port and the treatment module. The treatment module includes one or more process chambers and a transfer chamber that transfers the substrate to the process chambers. The transfer chamber includes a housing having a transfer space in which the substrate is transferred, a transfer robot that is disposed in the housing and that transfers the substrate between the process chambers, and an electrostatic pad that is provided in the transfer space and that electro-statically attracts particles in the housing. | 2021-02-25 |
20210057254 | METHOD FOR CONTROLLING CONVEYANCE SYSTEM, CONVEYANCE SYSTEM, AND MANAGEMENT DEVICE - A method for controlling a conveyance system includes transmitting, by a specific conveyance vehicle specific transfer location information to a management device, extracting from correspondence information by the management device, specific communication-device address information corresponding to the specific transfer location information received from the specific conveyance vehicle, and transmitting to the specific conveyance vehicle by the management device the specific communication-device address information extracted, and executing by the specific conveyance vehicle using the specific communication-device address information received from the management device communication with a first communication device connected to a first semiconductor manufacturing device to transfer a FOUP between the first semiconductor manufacturing device and the specific conveyance vehicle. | 2021-02-25 |
20210057255 | AUTOMATIC HANDLING BUFFER FOR BARE STOCKER - A buffer station for automatic material handling system can provide throughput improvement. Further, by storing to-be-accessed workpieces in the buffer stations of an equipment, the operation of the facility is not interrupted when the equipment is down. The buffer station can be incorporated in a stocker, such as bare wafer stocker. | 2021-02-25 |
20210057256 | CALIBRATION OF AN ALIGNER STATION OF A PROCESSING SYSTEM - A method for calibrating an aligner station of an electronics processing system is provided. A calibration is retrieved, by a first robot arm of a transfer chamber, from a processing chamber connected to the transfer chamber. The calibration object has a target orientation in the processing chamber. The calibration is placed, by the first robot art, in a load lock connected to the transfer chamber. The calibration is retrieved from the load lock by a second robot arm of a factory interface connected to the load lock. The calibration object is placed, by the second robot arm, at an aligner station housed in or connected to the factory interface. The calibration object has a first orientation at the aligner station. A difference is determined between the first orientation at the aligner station and an initial target orientation at the aligner station. The initial target orientation at the aligner station is associated with the target orientation in the processing chamber. A first characteristic error value associated with the processing chamber is determined based on the difference between the first orientation and the initial target orientation. The first characteristic error value is recorded in a storage medium. The aligner station is to use the first characteristic error value for alignment of objects to be placed in the processing chamber. | 2021-02-25 |
20210057257 | ELECTROSTATIC CHUCK AND MANUFACTURING METHOD THEREFOR - The present invention relates to a method for manufacturing an electrostatic chuck comprising: a base member of a metal material; and a dielectric layer, formed on an upper surface of the base member, including an electrode layer to the inside of which a DC power is applied. According to the present invention, the dielectric layer is formed of a ceramic material by using at least one selected from among a plasma spraying method and a sol-gel method, and thus can be provided with low porosity to increase in lifespan, and with high permittivity to increase in adhesion force to a substrate. | 2021-02-25 |
20210057258 | LASER TRANSFER APPARATUS AND TRANSFER METHOD USING THE SAME - The application is related to a laser transfer apparatus and a method performed by the laser transfer apparatus. The laser transfer apparatus may include: a laser oscillator configured to perform irradiation with a laser beam; a first stage movably disposed below the laser oscillator; a second stage movably disposed below the first stage; a flatness measurement sensor; and a controller. The controller may be configured to control, once a transfer substrate on which a plurality of light emitting diodes (LEDs) are arranged is loaded on the first stage, and a target substrate is loaded on the second stage, the flatness measurement sensor to measure flatness of each of the transfer substrate and the target substrate, and adjust a height of at least one of the first stage or the second stage based on the flatness. | 2021-02-25 |
20210057259 | SEMICONDUCTOR PACKAGE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE - A manufacturing method of a semiconductor device includes the following steps. A semiconductor wafer having an active side and a back side opposite to the active side is provided. A plurality of conductive bumps are provided on the active side. A protection film is laminated on the active side, wherein the protection film includes a dielectric film covering the plurality of conductive bumps and a cover film covering the dielectric film. A thinning process is performed on the back side to form a thinned semiconductor wafer. The cover film is removed from the dielectric film. A singularization process is performed on the thinned semiconductor wafer with the dielectric film to form a plurality of semiconductor devices. | 2021-02-25 |
20210057260 | PROCESSING METHOD FOR WAFER - A processing method for a wafer includes a thermocompression-bonding sheet arrangement step of arranging, on a front side of the wafer, a thermocompression-bonding sheet of a size sufficient to cover the wafer, an integration step of pressing the thermocompression-bonding sheet under heat by a planarizing member, so that the thermocompression-bonding sheet is planarized and the thermocompression-bonding sheet and the wafer are integrated together, a grinding step of holding the wafer on a side of the thermocompression-bonding sheet on a chuck table of a grinding apparatus and grinding the wafer to a desired thickness while supplying grinding water to a back side of the wafer, and a thermocompression-bonding sheet rinsing step of unloading the integrated wafer from the chuck table and rinsing the thermocompression-bonding sheet. | 2021-02-25 |
20210057261 | PROCESSING METHOD OF WAFER - A wafer processing method includes sticking an adhesive tape to the front surface of a wafer, disposing a thermocompression bonding sheet on the adhesive tape stuck to the front surface of the wafer. The thermocompression bonding sheet is heated and pressed by a flat member to execute pressure bonding of the thermocompression bonding sheet to the adhesive tape and integrate the thermocompression bonding sheet with the wafer. The processing method also includes holding the side of the thermocompression bonding sheet on a chuck table of a grinding apparatus and grinding the wafer into a desired thickness while supplying grinding water to the back surface of the wafer. The integrated wafer is separated from the chuck table and the thermocompression bonding sheet is separated from the adhesive tape. | 2021-02-25 |
20210057262 | WAFER INSPECTION APPARATUSES - A wafer inspection apparatus includes a support structure including a frame and vacuum chucks mounted thereon, each vacuum chuck having a support surface including a vacuum suction portion, the support structure configured to structurally support a wafer on one or more vacuum chucks, the frame defining an opening larger than an area of the wafer. The wafer inspection apparatus includes an electromagnetic wave emitter configured to irradiate an inspection electromagnetic wave to the wafer, a sensor configured to receive the inspection electromagnetic wave from the wafer based on the inspection electromagnetic wave passing through the wafer, and a driver configured to move at least one of the electromagnetic wave emitter or the frame to change an irradiation location of the wafer. Each vacuum chuck is configured to be selectively movable between a first location and a second location in relation to the frame. | 2021-02-25 |
20210057263 | SUBSTRATE BONDING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE BY USING THE SUBSTRATE BONDING APPARATUS - A substrate bonding apparatus includes a first bonding chuck configured to support a first substrate and a second bonding chuck configured to support a second substrate such that the second substrate faces the first substrate. The first bonding chuck includes a first base, a first deformable plate on the first base and configured to support the first substrate and configured to be deformed such that a distance between the first base and the first deformable plate is varied, and a first piezoelectric sheet on the first deformable plate and configured to be deformed in response to power applied thereto to deform the first deformable plate. | 2021-02-25 |
20210057264 | SEMICONDUCTOR WITH THROUGH-SUBSTRATE INTERCONNECT - Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via. | 2021-02-25 |
20210057265 | SEMICONDUCTOR DEVICE WITH AIR SPACER AND METHOD FOR PREPARING THE SAME - The present disclosure provides a semiconductor device and a method for preparing the semiconductor device. The method includes forming a first conductive layer over a substrate, forming a first dielectric structure over the first conductive layer, transforming a sidewall portion of the first conductive layer into a first transformed portion, removing the first transformed portion such that a width of the first dielectric structure is greater than a width of a remaining portion of the first conductive layer, and forming an inter-layer dielectric (ILD) layer covering sidewalls of the first dielectric structure such that a first air spacer is formed between the ILD layer and the remaining portion of the first conductive layer. | 2021-02-25 |
20210057266 | SEMICONDUCTOR STRUCTURE FORMATION - An example method includes patterning a working surface of a semiconductor wafer. The example method includes performing a first deposition of a dielectric material in high aspect ratio trenches. The example method further includes performing a high pressure, high temperature vapor etch to recess the dielectric material in the trenches and performing a second deposition of the dielectric material to continue filling the trenches. | 2021-02-25 |
20210057267 | METHOD OF HEALING AN IMPLANTED LAYER COMPRISING A HEAT TREATMENT PRIOR TO RECRYSTALLISATION BY LASER ANNEALING - The invention relates to a method of healing defects related to implantation of species in a donor substrate ( | 2021-02-25 |
20210057268 | METHOD FOR PRODUCING A DONOR SUBSTRATE FOR CREATING A THREE-DIMENSIONAL INTEGRATED STRUCTURE, AND METHOD FOR PRODUCING SUCH AN INTEGRATED STRUCTURE - A process for producing a donor substrate for creating a three-dimensional integrated structure comprises the following steps: providing a semiconductor substrate comprising a surface layer, referred to as an active layer, and a layer comprising a plurality of cavities extending beneath the active layer, each cavity being separated from an adjacent cavity by a partition, forming an electronic device in a region of the active layer located plumb with a cavity, depositing a protective mask on the active layer so as to cover the electronic device while at the same time exposing a region of the active layer located plumb with each partition, and implanting atomic species through regions of the active layer exposed by the mask to form a weakened zone in each partition. | 2021-02-25 |
20210057269 | SEMICONDUCTOR-ON-INSULATOR SUBSTATE FOR RF APPLICATIONS - A semiconductor-on-insulator substrate for use in RF applications, such as a silicon-on-insulator substrate, comprises a semiconductor top layer, a buried oxide layer and a passivation layer over a support substrate. In addition, a penetration layer is provided between the passivation layer and the silicon support substrate to ensure sufficient high resistivity below RF features and avoid increased migration of dislocations in the support substrate. RF devices may be fabricated on and/or in such a semiconductor-on-insulator substrate. | 2021-02-25 |
20210057270 | SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING THEREOF - A semiconductor wafer and method for manufacturing thereof are provided. The semiconductor wafer includes a handling substrate and a silicon layer over the handling substrate and having a {111} facet at an edge of a top surface of the silicon layer. The a defect count on the top surface of the silicon layer is less than about 15 each semiconductor wafer. The method includes the following operations: a semiconductor-on-insulator (SOI) substrate is provided, wherein the SOI substrate has a handling substrate, a silicon layer over the handling substrate, and a silicon germanium layer over the silicon layer; and the silicon germanium layer is etched at a first temperature with hydrochloric acid to expose a first surface of the silicon layer. | 2021-02-25 |
20210057271 | ETCH STOP MEMBER IN BURIED INSULATOR OF SOI SUBSTRATE TO REDUCE CONTACT EDGE PUNCH THROUGH - A method forms a trench isolation opening extending into an SOI substrate, and forms an etch stop member in a portion of the insulator layer abutting a side of the trench isolation opening. The etch stop member has a higher etch selectivity than the insulator layer of the SOI substrate. A trench isolation is formed in the trench isolation opening. A contact is formed to a portion of the semiconductor layer of the SOI substrate. The etch stop member is structured to prevent contact punch through to the base substrate of the SOI substrate. | 2021-02-25 |
20210057272 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - Semiconductor device and fabrication method are provided. The method for forming the semiconductor device includes providing a substrate; forming a dielectric layer on the substrate; forming a through hole in the dielectric layer, the through hole exposing a portion of a top surface of the substrate; performing a surface treatment process on the dielectric layer of sidewalls of the through hole; and filling a metal layer in the through hole. | 2021-02-25 |
20210057273 | Barrier-Less Structures - Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer. | 2021-02-25 |
20210057274 | METHOD OF COPPER PLATING FILLING - The disclosure discloses a copper plating filling process method, comprising the steps of: forming a trench or a through-hole in a dielectric layer; forming a copper seed layer on an inner surface of the hole; allowing a waiting time after forming the copper seed layer and before performing a copper plating process, wherein during the waiting time, a surface of the copper seed layer is oxidized to form a copper oxide layer; performing a reduction process on the copper oxide layer; and filling a copper layer into the hole in the copper plating process afterwards. The copper oxide layer on the surface of the copper seed layer is reduced to copper in the reduction process, and wherein a thickness of the copper seed layers on the inner surface of the hole is uniform. The hole can be a trench or a through-hole. | 2021-02-25 |
20210057275 | METHOD FOR FORMING A STRUCTURE WITH A HOLE - A method for forming a structure with a hole on a substrate is disclosed. The method may comprise: depositing a first structure on the substrate; etching a first part of the hole in the first structure; depositing a plug fill in the first part of the hole; depositing a second structure on top of the first structure; etching a second part of the hole substantially aligned with the first part of the hole in the second structure; and, etching the plug fill of the first part of the hole and thereby opening up the hole by dry etching. In this way 3-D NAND device may be provided. | 2021-02-25 |
20210057276 | Melting Laser Anneal Of Epitaxy Regions - A method includes forming a gate stack over a first semiconductor region, removing a second portion of the first semiconductor region on a side of the gate stack to form a recess, growing a second semiconductor region starting from the recess, implanting the second semiconductor region with an impurity, and performing a melting laser anneal on the second semiconductor region. A first portion of the second semiconductor region is molten during the melting laser anneal, and a second and a third portion of the second semiconductor region on opposite sides of the first portion are un-molten. | 2021-02-25 |
20210057277 | DISCRETE PIECE FORMING DEVICE AND DISCRETE PIECE FORMING METHOD - A discrete piece forming device EA that forms discrete pieces CP by dividing a work WF into pieces includes: a sheet pasting unit | 2021-02-25 |
20210057278 | METHODS OF MANUFACTURING SEMICONDUCTOR CHIP - Methods of manufacturing a semiconductor chip are provided. The methods may include providing a semiconductor substrate including integrated circuit regions and a cut region. The cut region may be between the integrated circuit regions. The methods may also include forming a modified layer by emitting a laser beam into the semiconductor substrate along the cut region, polishing an inactive surface of the semiconductor substrate to propagate a crack from the modified layer, and separating the integrated circuit regions along the crack. The cut region may include a plurality of multilayer metal patterns on an active surface of the semiconductor substrate, which is opposite to the inactive surface of the semiconductor substrate. The plurality of multilayer metal patterns may form a pyramid structure when viewed in cross section. | 2021-02-25 |
20210057279 | OPEN-DRAIN TRANSISTOR MONITORING CIRCUIT IN A MULTI-CHIP PACKAGE TO CONTROL POWER - A technique to provide power management for multiple dice. The technique provides for determining for each respective die of the multiple dice, power consumption for operating each respective die; and generating a respective signal from each respective die that corresponds to the power consumption of each respective die. The technique further provides, for each respective signal, driving a respective open-drain transistor to conduct, in which an output of each open-drain transistor connects to the common node and the common node connects to a reference voltage, to change a voltage of a common node corresponding to the respective signal; and utilizing the voltage of the common node to indicate total power consumption of the dice. | 2021-02-25 |
20210057280 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE - Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill. | 2021-02-25 |
20210057281 | IC INCLUDING STANDARD CELLS AND SRAM CELLS - An IC is provided. The IC includes a plurality of P-type gate-all-around (GAA) field-effect transistors (FETs). At least one first P-type GAA FET includes a plurality of silicon (Si) channel regions vertically stacked over an N-type well region. At least one second P-type GAA FET includes a plurality of silicon germanium (SiGe) channel regions vertically stacked over the N-type well region. | 2021-02-25 |
20210057282 | FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor device includes forming a first dummy gate structure and a second dummy gate structure over a fin protruding above a substrate, where the first dummy gate structure and the second dummy gate structure are surrounded by a dielectric layer; and replacing the first dummy gate structure and the second dummy gate structure with a first metal gate and a second metal gate, respectively, where the replacing includes: removing the first and the second dummy gate structures to form a first recess and a second recess in the dielectric layer, respectively; forming a gate dielectric layer in the first recess and in the second recess; forming an N-type work function layer and a capping layer successively over the gate dielectric layer in the second recess but not in the first recess; and filling the first recess and the second recess with an electrically conductive material. | 2021-02-25 |
20210057283 | METHOD FOR MANUFACTURING MICROELECTRONIC COMPONENTS - A method for producing a component is provided, a base of which is formed by transistors on a substrate, including: forming a gate area, spacers, and a protective coating partly covering the spacers and a sidewall portion of a cavity without covering a top face of the gate area and a base portion of the cavity; forming a contact module, the gate located in beneath the module; and removing part of the coating with an isotropic light-ion implantation to form modified superficial parts in a thickness, respectively, of the contact module, of the coating, and of the base portion, and with an application of a plasma to: etch the modified superficial parts to only preserve, in the coating, a residual part of the coating, and to form a silicon oxide-based film on exposed surfaces, respectively, of the contact module, of the cavity, and of the coating. | 2021-02-25 |
20210057284 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Disclosed are semiconductor devices and methods of fabricating the same. The method comprises sequentially stacking a lower sacrificial layer and an upper sacrificial layer on a substrate, patterning the upper sacrificial layer to form a first upper sacrificial pattern and a second upper sacrificial pattern, forming a first upper spacer and a second upper spacer on sidewalls of the first upper sacrificial pattern and a second upper sacrificial pattern, respectively, using the first and second upper spacers as an etching mask to pattern the lower sacrificial layer to form a plurality of lower sacrificial patterns, forming a plurality of lower spacers on sidewalls of the lower sacrificial patterns, and using the lower spacers as an etching mask to pattern the substrate. The first and second upper spacers are connected to each other. | 2021-02-25 |
20210057285 | FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD - A method includes forming a first dummy gate and a second dummy gate over a fin that protrudes above a substrate; replacing the first dummy gate and the second dummy gate with a first metal gate and a second metal gate, respectively; forming a dielectric cut pattern between the first and the second metal gates, the dielectric cut pattern extending further from the substrate than the first and the second metal gates; forming a patterned mask layer over the first metal gate, the second metal gate, and the dielectric cut pattern, an opening in the patterned mask layer exposing a portion of the first metal gate, a portion of the second metal gate, and a portion of the dielectric cut pattern underlying the opening; filling the opening with a first electrically conductive material; and recessing the first electrically conductive material below an upper surface of the dielectric cut pattern. | 2021-02-25 |
20210057286 | STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH FIN STRUCTURES - A structure and formation method of a semiconductor device is provided. The method includes forming a first, a second, a third, and a fourth fin structures over a substrate. The method also includes forming a first spacer layer over sidewalls of the first and the second fin structures. The method further includes forming a second spacer layer over the first spacer layer and sidewalls of the third and the fourth fin structures. In addition, the method includes forming a first blocking fin between the first and the second fin structures. The first blocking fin is separated from the first fin structure by portions of the first spacer layer and the second spacer layer. The method includes forming a second blocking fin between the third and the fourth fin structures. The second blocking fin is separated from the third fin structure by a portion of the second spacer layer. | 2021-02-25 |
20210057287 | Footing Removal in Cut-Metal Process - A method includes forming a gate stack, which includes a first portion over a portion of a first semiconductor fin, a second portion over a portion of a second semiconductor fin, and a third portion connecting the first portion to the second portion. An anisotropic etching is performed on the third portion of the gate stack to form an opening between the first portion and the second portion. A footing portion of the third portion remains after the anisotropic etching. The method further includes performing an isotropic etching to remove a metal gate portion of the footing portion, and filling the opening with a dielectric material. | 2021-02-25 |
20210057288 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Methods of fabricating semiconductor devices comprise forming first active patterns vertically spaced apart on a first active fin of a substrate and second active patterns vertically spaced apart on a second active fin of the substrate that has a first region on which the first active fin is formed and a second region on which the second active fin is formed, forming a first electrode layer on the first and second active fins and the first and second active patterns, forming a first mask pattern overlapping the first electrode layer on the first region, forming a second mask pattern overlapping the first electrode layer on the second region, and using the second mask pattern as an etching mask to etch the first mask pattern and the first electrode layer on the first region to form a first electrode pattern on the second region. | 2021-02-25 |
20210057289 | Method for Detecting Ultra-Small Defect on Wafer Surface - The present invention provides a method for detecting an ultra-small defect on a wafer surface, film layer having ultra-small defect that causes abnormalities on the surface of the film layer; form a photoresist pattern with a pattern defect; etching the film layer according to the photoresist pattern to form a film layer pattern with an enlarged defect; and scanning the film layer pattern by using a defect scanner to capture the enlarged defect. In this method, enlarging the size of the ultra-fine particle defect through the exposure defocusing principle; or by adding the photomask consisting of the repeating units, using the repetition pattern as the exposure pattern and combing with the repeating cell to cell comparison method, the capture ability of the detection machine is further improved. Therefore, it can be detected by amplifying the defects of ultrafine particles which cannot be detected by conventional methods. | 2021-02-25 |
20210057290 | SEMICONDUCTOR STRUCTURE AND TESTING METHOD THEREOF - A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer. | 2021-02-25 |
20210057291 | METHODS FOR MANUFACTURING A DISPLAY DEVICE - Methods for manufacturing a display device are provided. A representative method includes: providing a substrate, the substrate having an insulating layer with an opening and having a metal layer under the opening, wherein a part of the metal layer does not serves as a portion of a thin film transistor; providing a carrier substrate supporting a plurality of light emitting diodes; conducting a testing to the plurality of LEDs on the carrier substrate; transferring at least one of the plurality of LEDs from the carrier substrate to the opening of the substrate; and fixing the at least one of the plurality of LEDs to the substrate. | 2021-02-25 |
20210057292 | METHODS AND APPARATUS FOR DETERMINING ENDPOINTS FOR CHEMICAL MECHANICAL PLANARIZATION IN WAFER-LEVEL PACKAGING APPLICATIONS - Methods and apparatus for chemical mechanical planarization (CMP) of a polymer or epoxy-based layer. In some embodiments, the method may comprise obtaining an endpoint for polymer or epoxy-based material for use in a CMP process, the CMP process configured to polish polymer or epoxy-based material, monitoring the polymer or epoxy-based layer with an endpoint detection apparatus configured to monitor polymer or epoxy-based material, polishing the polymer or epoxy-based layer with the CMP process, detecting when the polymer or epoxy-based layer has reached the endpoint for the CMP process, and halting the CMP process when the endpoint is detected. The endpoint detection apparatus may further comprise an optical detection apparatus configured to operate at a wavelength of approximately 200 nm to approximately 1700 nm to reduce step height of the polymer or epoxy-based layer. | 2021-02-25 |
20210057293 | SEMICONDUCTOR DEVICE STRUCTURE WITH MAGNETIC ELEMENT IN TESTING REGION - A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a testing region and multiple first conductive lines over the testing region. The first conductive lines are electrically connected in series. The semiconductor device structure also includes multiple second conductive lines over the testing region. The second conductive lines are electrically connected in series, and the second conductive lines are physically separated from the first conductive lines. The semiconductor device structure further includes multiple magnetic structures wrapping around portions of the first conductive lines and wrapping around portions of the second conductive lines. The magnetic structures are arranged in a column. | 2021-02-25 |
20210057294 | PROCESS MONITOR CIRCUITRY WITH MEASUREMENT CAPABILITY - A process monitor circuitry is described that can measure the electron mobility (μ), oxide capacitance (C | 2021-02-25 |
20210057295 | SEMICONDUCTOR DEVICE - This semiconductor device is provided with a device substrate in which a semiconductor circuit including two high frequency amplifiers; a cap substrate and a sealing frame of a conductor which forms and air-tightly seals space surrounding an area, in which the semiconductor circuit is formed, between the device substrate and the cap substrate, wherein the sealing frame is configured as a line of a 90-degree hybrid circuit or a line of a rat-race circuit. | 2021-02-25 |
20210057296 | ELECTRIC COMPONENT EMBEDDED STRUCTURE - In an electric component embedded structure, a first electrode terminal provided on a first main surface includes an intra-area terminal, and the intra-area terminal is electrically connected to an overlap portion of an overlap wiring in a formation area of an electric component. Accordingly, a decrease in mounting area of the electric component embedded structure is achieved. The intra-area terminal can be electrically connected to a second electrode terminal provided on a second main surface via a first via-conductor, the overlap wiring, and a second via-conductor. The intra-area terminal is connected to a wiring (an overlap wiring) of a first insulating layer without additionally providing a rewiring layer causing an increase in thickness, and the increase in thickness is curbed, whereby a decrease in size of the electric component embedded structure is achieved. | 2021-02-25 |
20210057297 | PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME - A method for forming a package structure is provided. The method for forming a package structure includes bonding a package component to a first surface of a substrate through a plurality of first connectors. The package component includes an interposer, a first semiconductor die and a second semiconductor die over the interposer. The method for forming a package structure also includes forming a dam structure over the first surface of the substrate. The dam structure is around and separated from the package component. The method for forming a package structure further includes forming an underfill layer between the dam structure and the package component, and removing the dam structure after the underfill layer is formed. | 2021-02-25 |
20210057298 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - A semiconductor package including a semiconductor die, a molding compound and a redistribution structure is provided. The molding compound laterally wraps around the semiconductor die, wherein the molding compound includes a base material and a first filler particle and a second filler particle embedded in the base material. | 2021-02-25 |
20210057299 | SEMI-CONDUCTOR PACKAGE - A semiconductor package includes a substrate, a plurality of electronic components mounted on a first surface of the substrate, and an encapsulant disposed on the first surface of the substrate so that at least one of the plurality of electronic components is embedded in the encapsulant. The substrate includes a flow preventing portion including at least one flow preventing groove disposed in the first surface and adjacent to the encapsulant and/or at least one dam disposed on the first surface and adjacent to the encapsulant. | 2021-02-25 |
20210057300 | ELECTRONIC PACKAGE, ELECTRONIC PACKAGING MODULE HAVING THE ELECTRONIC PACKAGE, AND METHOD FOR FABRICATING THE ELECTRONIC PACKAGE - The present application provides an electronic package having an optoelectronic component and a laser component disposed on a packaging unit, with the optoelectronic component and the laser component being separated from each other. Since the laser component and the optoelectronic component are separated from each other, the electronic package has a reduced fabrication difficulty and a high yield rate. A method for fabricating the electronic package and an electronic packaging module having the electronic package are also provided. | 2021-02-25 |
20210057301 | FLEXIBLE SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A flexible semiconductor package includes a semiconductor chip accommodated in a cavity formed in a substrate, a molding layer covering an entire upper surface of the substrate and the cavity, and a wiring portion including an insulating layer and a redistribution member provided under lower surfaces of the substrate and the semiconductor chip, wherein the molding layer includes a pre-preg in which a resin is impregnated with a glass fabric, and the molding layer and the insulating layer are attached to the semiconductor chip accommodated in the cavity by a roll-to-roll continuous process. | 2021-02-25 |
20210057302 | Sensor Package and Method - In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die. | 2021-02-25 |
20210057303 | SEMICONDUCTOR DIE, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR PACKAGE - A semiconductor die is provided. The semiconductor die includes a semiconductor substrate, an interconnection structure, conductive pads, a first passivation layer, and a second passivation layer. The interconnection structure is disposed on the semiconductor substrate. The conductive pads are disposed over and electrically connected to the interconnection structure. The first passivation layer and the second passivation layer are sequentially stacked on the conductive pads. The first passivation layer and the second passivation layer fill a gap between two adjacent conductive pads. The first passivation layer includes a first section and a second section. The first section extends substantially parallel to a top surface of the interconnection structure. The second section faces a side surface of one of the conductive pads. Thicknesses of the first section and the second section are different. | 2021-02-25 |
20210057304 | HEAT-CONDUCTIVE SHEET - A heat-conducting sheet | 2021-02-25 |
20210057305 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - A semiconductor device includes a substrate, an insulating layer provided over the substrate, a collection of metal particles exposed on the surface of the insulating layer, and a diamond layer provided on the surface of the insulating layer on which the metal particles are exposed. By controlling the surface density and particle size of the metal particles on the surface of the insulating layer, the surface density of diamond nuclei that are formed on the surface is controlled. Diamond grains are formed by crystal growth using the diamond nuclei as starting material, thereby forming a diamond layer. The control of the surface density of the diamond nuclei results in forming, by the crystal growth, the diamond grains with a grain size exhibiting a relatively high thermal conductivity in the crystal growth initial layer of the diamond layer and improving the thermal conductivity between the diamond layer and the substrate. | 2021-02-25 |
20210057306 | HEAT DISSIPATION MODULE AND ELECTRONIC DEVICE - A heat dissipation module including a heat dissipation portion, a working fluid, and a buffer member is provided. The heat dissipation portion has a containing portion, the working fluid is contained in the containing portion, and the buffer member is connected to the containing portion. When the working fluid is heated, the buffer member is expanded to maintain a constant pressure within the containing portion. | 2021-02-25 |
20210057307 | SEMICONDUCTOR DEVICE - It is an object to reduce a difference in temperature of a refrigerant between an upstream side and a downstream side of a flow path even in a case where all semiconductor elements generate heat due to inverter operation and the like. A semiconductor device includes at least one semiconductor element, a base plate, a plurality of cooling fins, a jacket, and a partition. The partition is disposed below the plurality of cooling fins in the jacket. The partition has at least one inflow opening to allow the refrigerant having flowed in through the refrigerant inlet to flow through the plurality of cooling fins, and has a portion abutting the jacket on the side of the refrigerant inlet. The at least one inflow opening is located to correspond to the at least one semiconductor element. | 2021-02-25 |
20210057308 | PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME - A package structure and method of forming the same are provided. The package structure includes a die, a TIV, an encapsulant, an adhesion promoter layer, a RDL structure and a conductive terminal. The TIV is laterally aside the die. The encapsulant laterally encapsulates the die and the TIV. The adhesion promoter layer is sandwiched between the TIV and the encapsulant. The RDL structure is electrically connected to the die and the TIV. The conductive terminal is electrically connected to the die through the RDL structure. | 2021-02-25 |
20210057309 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure and the manufacturing method thereof are provided. A semiconductor structure includes a semiconductor substrate, a plurality of interconnecting layers, a first connector, and a second connector. The semiconductor substrate includes a plurality of semiconductor devices therein. The interconnecting layers are disposed over the semiconductor substrate and electrically coupled to the semiconductor devices. The first connector is disposed over the plurality of interconnecting layers and extends to be in contact with a first level of the plurality of interconnecting layers. The second connector is disposed over the plurality of interconnecting layers and substantially leveled with the first connector. The second connector extends further than the first connector to be in contact with a second level of the plurality of interconnecting layers between the first level of the plurality of interconnecting layers and the semiconductor substrate, and the first connector is wider than the second connector. | 2021-02-25 |
20210057310 | INTEGRATED CIRCUIT HAVING CONTACT JUMPER - An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern. | 2021-02-25 |
20210057311 | METHOD AND SYSTEM OF STRETCHING AN ACCEPTOR SUBSTRATE TO ADJUST PLACEMENT OF A COMPONENT - Disclosed herein is a system and method of adjusting a location of components on a receiving substrate. The method includes transferring a set of components from a donor substrate to a receiving substrate and stretching the receiving substrate in at least one direction so the components are in their final location. The system includes a set of components on a receiving substrate; and wherein the receiving substrate is configured to adjust the location of the set of components via elastic stretching in at least one direction. | 2021-02-25 |
20210057312 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor light emitting device includes a semiconductor light source, a resin package surrounding the semiconductor light source, and a lead fixed to the resin package. The lead is provided with a die bonding pad for bonding the semiconductor light source, and with an exposed surface opposite to the die bonding pad The exposed surface is surrounded by the resin package in the in-plane direction of the exposed surface. | 2021-02-25 |
20210057313 | SEMICONDUCTOR PACKAGE HAVING EXPOSED HEAT SINK FOR HIGH THERMAL CONDUCTIVITY - Provided is a semiconductor package having an exposed heat sink for high thermal conductivity. The semiconductor package includes at least one semiconductor chip | 2021-02-25 |
20210057314 | INTEGRATED CIRCUIT PACKAGE HAVING A LOW PROFILE - A method of providing a sensor IC package can include applying a film to a leadframe having first and second surfaces, mounting at least one component to the film, and applying a pre-mold material to cover at least a portion of the leadframe and the passive component while leaving a first side of the leadframe exposed. The film can be removed and a die attached to the first side of the leadframe. At least one electrical connection can be formed between the die and the leadframe. The assembly of the die, the leadframe, and the pre-mold material can be encapsulated with a final mold material to provide a low profile IC package. | 2021-02-25 |
20210057315 | POWER SWITCHING MODULAR ELEMENT AND DISMOUNTABLE ASSEMBLY OF A PLURALITY OF MODULAR ELEMENTS - The invention relates to a modular element ( | 2021-02-25 |
20210057316 | CHIP ON FILM AND DISPLAY DEVICE - A chip on film and a display device are disclosed. One connection end of the chip on film is disposed with a pin to be compatible to at least one plug interface disposed at a connection end of a flexible printed circuit board. A pin connect method in which the pin and the plug interface are matched is adopted in the connection between the flexible printed circuit board and the chip on film, which optimizes the bonding process between the flexible printed circuit board and the chip on film and saves material cost and equipment cost required for thermal-compression of the anisotropic conductive film. | 2021-02-25 |
20210057317 | SEMICONDUCTOR PACKAGE - A semiconductor package having a redistribution structure including a first face and a second face and a first semiconductor chip mounted on the first face. The semiconductor package may further include a first redistribution pad exposed from the second face of the redistribution structure and a second redistribution pad exposed from the second face of the redistribution structure. The semiconductor package may further include a first solder ball being in contact with the first redistribution pad and a second solder ball being in contact with the second redistribution pad. In some embodiments, a first distance of the first redistribution pad is smaller than a second distance of the second redistribution pad, the first and second distances are measured with respect to a reference plane that intersects a lower portion of the first solder ball and a lower portion of the second solder ball. | 2021-02-25 |
20210057318 | TOP-TO-BOTTOM INTERCONNECTS WITH MOLDED LEAD-FRAME MODULE FOR INTEGRATED-CIRCUIT PACKAGES - Disclosed embodiments include folded, top-to-bottom interconnects that couple a die side of an integrated-circuit package substrate, to a board as a complement to a ball-grid array for a flip-chip-mounted integrated-circuit die on the die side. The folded, top-to-bottom interconnect is in a molded frame that forms a perimeter around an infield to receive at least one flip-chip IC die. Power, ground and I/O interconnections shunt around the package substrate, and such shunting includes voltage regulation that need not be routed through the package substrate. | 2021-02-25 |
20210057319 | MULTI-PITCH BALL GRID ARRAY - A mixed pitch method of placing pads in a ball grid array (BGA) package having a BGA substrate and a plurality of connectors arranged in an array and connected via the pads to the BGA substrate. Selected pairs of the pads are placed on the BGA substrate at a distance defined by a first pitch P | 2021-02-25 |
20210057320 | PACKAGE STRUCTURE AND PREPARATION METHOD THEREOF - A method of preparing a package structure is provided, which includes providing a carrier plate including a supporting layer, a first release layer, and a first metal layer; forming a first dielectric layer over the first metal layer, the first dielectric layer having a plurality of holes, each of the holes having an end portion substantially coplanar with each other at a same plane; forming a plurality of conductive protrusions filling the holes, each of the conductive protrusions having a first end and a second end opposite thereto; forming a circuit layer structure including at least one circuit layer and at least one second dielectric layer, the circuit layer being connected to the second end, the second dielectric layer being disposed over the circuit layer; removing the carrier plate; and removing a portion of the first dielectric layer to expose the conductive protrusions. A package structure is also provided. | 2021-02-25 |
20210057321 | GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION - Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed. | 2021-02-25 |
20210057322 | Semiconductor Chip Comprising a Multiplicity of External Contacts, Chip Arrangement and Method for Checking an Alignment of a Position of a Semiconductor Chip - A semiconductor chip includes a mounting surface having a plurality of first conductive contacts and a second conductive contact, wherein each of the first contacts in the plurality is arranged in a regularly spaced apart array such that centroids of immediately adjacent ones of the first contacts are separated from one another in a first direction by a first distance, each of the first contacts in the plurality have an identical first lateral extent, and the second conductive contact is arranged between two of the first conductive contacts in the first direction such that first and second distances between the at least one second conductive contact and the two of the first conductive contacts are each less than the first distance. | 2021-02-25 |
20210057323 | GROOVE DESIGN TO FACILITATE FLOW OF A MATERIAL BETWEEN TWO SUBSTRATES - Systems, apparatuses, processing ( | 2021-02-25 |
20210057324 | POWER MODULE - A power module including a carrier assembly and a power device disposed on the carrier assembly is provided. The carrier assembly includes a bottom board, a circuit board, a lead frame, and a pad group. The circuit board is disposed on the bottom board and includes a device mounting portion and an extending portion protruding from a side of the device mounting portion. The lead frame disposed on the bottom board includes a first conductive portion and a second conductive portion insulated from each other. The extending portion of the circuit board is disposed between the first and second conductive portions, and an upper surface of the lead frame is flush with a top surface of the extending portion. A pad group includes a first pad disposed on the extending portion, a second pad and a third pad respectively disposed on the first and second conductive portions. | 2021-02-25 |
20210057325 | Integrated Circuits with Backside Power Rails - Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer. | 2021-02-25 |
20210057326 | INTERCONNECT STRUCTURE FABRICATED USING LITHOGRAPHIC AND DEPOSITION PROCESSES - Embodiments described herein provide techniques of forming an interconnect structure using lithographic and deposition processes. The interconnect structure can be used to couple components of a semiconductor package. For one example, a semiconductor package includes a die stack and an interconnect structure formed on the die stack. The die stack comprises a plurality of dies. Each die in the die stack comprises: a first surface; a second surface opposite the first surface; sidewall surfaces coupling the first surface to the second surface; and a pad on the first surface. A one sidewall surface of one of the dies has a sloped profile. The semiconductor package also includes an interconnect structure positioned on the first surfaces and the sidewall with the sloped profile. In this semiconductor package, the interconnect structure electrically couples the pad on each of the dies to each other. | 2021-02-25 |
20210057327 | INTERCONNECT DEVICE AND METHOD - In some embodiments of the method, patterning the opening includes: projecting a radiation beam toward the second dielectric layer, the radiation beam having a pattern of the opening. In some embodiments of the method, the single-patterning photolithography process is an extreme ultraviolet (EUV) lithography process. In some embodiments of the method, filling the opening with the conductive material includes: plating the conductive material in the opening; and planarizing the conductive material and the second dielectric layer to form the first metal line from remaining portions of the conductive material, top surfaces of the first metal line and the second dielectric layer being planar after the planarizing. | 2021-02-25 |
20210057328 | SEMICONDUCTOR CHIP INCLUDING LOW-K DIELECTRIC LAYER - A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess. | 2021-02-25 |
20210057329 | CO-INTEGRATED VERTICALLY STRUCTURED CAPACITIVE ELEMENT AND FABRICATION PROCESS - First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench. | 2021-02-25 |
20210057330 | SINGLE CHIP SIGNAL ISOLATOR - Methods and apparatus for a signal isolator IC package including a die having a first die portion isolated from a second die portion. The first die portion is surrounded on six sides by first insulative material and the second die portion is surrounded on six sides by second insulative material. The first die portion provides a first voltage domain and the second die portion provides a second voltage domain. The signal isolator comprises a first signal path between the first die portion and the second die portion, wherein the first signal path is isolated with respect to the first and second die portions. | 2021-02-25 |
20210057331 | SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE - A semiconductor package includes a semiconductor die encapsulated by an insulating encapsulation, a redistribution circuit structure disposed over the semiconductor die and the insulating encapsulation, the redistribution circuit structure being electrically connected to the semiconductor die; and a conductive feature having a first portion embedded in the redistribution circuit structure and a second portion connected to the first portion, the first portion having a first long axis and a first short axis perpendicular to the long axis in a top view, the second portion disposed over and electrically connected to the first portion. A semiconductor device having the semiconductor package, a circuit substrate and a circuit board is also provided. | 2021-02-25 |
20210057332 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes first and second semiconductor dies bonded together. The first semiconductor die includes a first semiconductor substrate, a first interconnect structure disposed below the first semiconductor substrate, and a first bonding conductor disposed below the first interconnect structure and electrically coupled to the first semiconductor substrate through the first interconnect structure. The second semiconductor die includes a second semiconductor substrate and a second interconnect structure disposed below and electrically coupled to the second semiconductor substrate, and a through semiconductor via penetrating through the second semiconductor substrate and extending into the second interconnect structure to be electrically coupled to the second interconnect structure. The first bonding conductor extends from the first interconnect structure towards the through semiconductor via to electrically connect the first semiconductor die to the second semiconductor die. The first bonding conductor corresponding to the through semiconductor via is smaller than the through semiconductor via. | 2021-02-25 |
20210057333 | Interconnect Structures with Low-Aspect-Ratio Contact Vias - Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a first conductive feature in a first dielectric layer, a second conductive feature aligned with and over the first conductive feature, a first insulation layer over the first dielectric layer and the second conductive feature, a second dielectric layer over the first insulating layer, and a contact via through the first insulation layer and the second dielectric layer. | 2021-02-25 |
20210057334 | Semiconductor Devices and Methods of Forming the Same - Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a metal feature in a first dielectric layer, an etch stop layer (ESL) over the metal feature, a second dielectric layer over the ESL, a third dielectric layer over the second dielectric layer, a patterned hard mask having a trench. The method further includes forming a via opening through the trench in the patterned hard mask, the second dielectric layer, the third dielectric layer, and the ESL to expose the metal feature, depositing a metal layer in the trench and the via opening to form a metal line and a metal contact via, respectively, and over the workpiece, removing the patterned hard mask between the metal line and the metal contact via, and depositing a fourth dielectric layer between the metal line and the metal contact via. | 2021-02-25 |
20210057335 | Graphene Enabled Selective Barrier Layer Formation - Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a graphene layer between the second contact feature and the first contact feature. | 2021-02-25 |
20210057336 | THREE-DIMENSIONAL MEMORY DEVICE CONTAINING HORIZONTAL AND VERTICAL WORD LINE INTERCONNECTIONS AND METHODS OF FORMING THE SAME - A method of forming a three-dimensional memory device includes forming a vertically alternating sequence of insulating layers and spacer material layers over a substrate, where the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers, forming multiple sets of stepped surfaces in terrace regions of the vertically alternating sequence, forming memory stack structures through memory array regions of the vertically alternating sequence, and forming a metal interconnect structure which electrically connects a portion of a topmost electrically conductive layer in the first memory array region and a portion of a topmost electrically conductive layer in the second memory array region, and which extends above a horizontal plane of the topmost electrically conductive layer in the first memory array region and a portion of a topmost electrically conductive layer in the second memory array region. | 2021-02-25 |
20210057337 | MULTIFUNCTIONAL MOLECULES FOR SELECTIVE POLYMER FORMATION ON CONDUCTIVE SURFACES AND STRUCTURES RESULTING THEREFROM - Multifunctional molecules for selective polymer formation on conductive surfaces, and the resulting structures, are described. In an example, an integrated circuit structure includes a lower metallization layer including alternating metal lines and dielectric lines above the substrate. A molecular brush layer is on the metal lines of the lower metallization layer, the molecular brush layer including multifunctional molecules. A triblock copolymer layer is above the lower metallization layer. The triblock copolymer layer includes a first segregated block component over the dielectric lines of the lower metallization layer, and alternating second and third segregated block components on the molecular brush layer on the metal lines of the lower metallization layer, where the third segregated block component is photosensitive. | 2021-02-25 |
20210057338 | SEMICONDUCTOR DEVICE AND OSCILLATOR - A semiconductor device includes a first high resistance pattern and a second high resistance pattern that are disposed along an X axis and are separated from each other, a coupling pattern that couples the first high resistance pattern and the second high resistance pattern, and a signal wiring disposed at a layer above the first high resistance pattern, the second high resistance pattern, and the coupling pattern. The coupling pattern includes a first portion that overlaps an end portion of the first high resistance pattern in a plan view at the layer above the first high resistance pattern, the coupling pattern includes a second portion that overlaps an end portion of the second high resistance pattern in a plan view at a layer above the second high resistance pattern, and the signal wiring is disposed along a Y axis that intersects the X axis in a plan view between an end of the coupling pattern at the first portion side and an end of the coupling pattern at the second portion side. | 2021-02-25 |
20210057339 | INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - An integrated circuit device includes a conductive line including a metal layer and an insulation capping structure covering the conductive line. The first insulation capping structure includes a first insulation capping pattern that is adjacent to the metal layer in the insulation capping structure and has a first density, and a second insulation capping pattern spaced apart from the metal layer with the first insulation capping pattern therebetween and having a second density that is greater than the first density. In order to manufacture the integrated circuit device, the conductive line having a metal layer is formed on a substrate, a first insulation capping layer having the first density is formed directly on the metal layer, and a second insulation capping layer having the second density that is greater than the first density is formed on the first insulation capping layer. | 2021-02-25 |
20210057340 | Methods for Reducing Dual Damascene Distortion - An integrated circuit structure includes a first low-k dielectric layer having a first k value, and a second low-k dielectric layer having a second k value lower than the first k value. The second low-k dielectric layer is overlying the first low-k dielectric layer. A dual damascene structure includes a via with a portion in the first low-k dielectric layer, and a metal line over and joined to the via. The metal line includes a portion in the second low-k dielectric layer. | 2021-02-25 |
20210057341 | BRIDGE SUPPORT STRUCTURE - A module including a first semiconductor device, a second semiconductor device, a bridge support structure and a base substrate. The semiconductor devices each having first bonding pads having a first solder joined with the base substrate and the semiconductor devices each having second and third bonding pads joined to second and third bonding pads on the bridge support structure by a second solder and a third solder, respectively, on the second and third bonding pads; the semiconductor devices positioned adjacent to each other such that the bridge support structure joins to both of the semiconductor devices by the second and third solders wherein the third bonding pads are larger than the second bonding pads and the third bonding pads are at a larger pitch than the second bonding pads. | 2021-02-25 |
20210057342 | DEVICE PACKAGES INCLUDING REDISTRIBUTION LAYERS WITH CARBON-BASED CONDUCTIVE ELEMENTS, AND METHODS OF FABRICATION - Semiconductor device packages include a redistribution layer (RDL) with carbon-based conductive elements. The carbon-based material of the RDL may have low electrical resistivity and may be thin (e.g., less than about 0.2 μm). Adjacent passivation material may also be thin (e.g., less than about 0.2 μm). Methods for forming the semiconductor device packages include forming the carbon-based material (e.g., at high temperatures (e.g., at least about 550° C.)) on an initial support wafer with a sacrificial substrate. Later or separately, components of a device region of the package may be formed and then joined to the initial support wafer before the sacrificial substrate is removed to leave the carbon-based material joined to the device region. | 2021-02-25 |
20210057343 | PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME - A package structure is provided. The package structure includes a first redistribution structure and an interposer over the first redistribution structure. The package structure also includes a molding compound layer surrounding the interposer, and a second redistribution structure over the interposer. The molding compound layer is between the first redistribution structure and the second redistribution structure. The package structure further includes a first semiconductor die and a second semiconductor die over the second redistribution structure. | 2021-02-25 |
20210057344 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a redistribution layer, a semiconductor chip on the redistribution layer, and a molding layer covering a sidewall of the semiconductor chip and a top surface and a sidewall of the redistribution layer. The sidewall of the redistribution layer is inclined with respect to a bottom surface of the redistribution layer, and a sidewall of the molding layer is spaced apart from the sidewall of the redistribution layer. | 2021-02-25 |
20210057345 | HIGH DENSITY INTERCONNECT STRUCTURES CONFIGURED FOR MANUFACTURING AND PERFORMANCE - Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via. | 2021-02-25 |
20210057346 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes dies, a redistribution structure, a conductive structure and connectors. The conductive plate is electrically connected to contact pads of at least two dies and is disposed on redistribution structure. The conductive structure includes a conductive plate and a solder cover, and the conductive structure extend over the at least two dies. The connectors are disposed on the redistribution structure, and at least one connector includes a conductive pillar. The conductive plate is at same level height as conductive pillar. The vertical projection of the conductive plate falls on spans of the at least two dies. | 2021-02-25 |
20210057347 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a semiconductor die and a redistribution structure. The redistribution structure is electrically connected to the semiconductor die. The redistribution structure includes dielectric layers, conductive traces and seal patterns. The conductive traces are embedded in the dielectric layers. At least one conductive trace of the conductive traces includes a via pattern and a routing pattern. The seal patterns are disposed on the conductive traces. One seal pattern of the seal patterns is disposed between a top surface of the routing pattern and a first dielectric layer of the dielectric layers. | 2021-02-25 |