09th week of 2009 patent applcation highlights part 15 |
Patent application number | Title | Published |
20090050977 | METHOD TO REDUCE BORON PENETRATION IN A SiGe BIPOLAR DEVICE - The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor region. A protective layer is formed over the polysilicon layer. The protective layer has a weight percent of hydrogen that is less than about 9% and is selective to silicon germanium (SiGe), such that SiGe does not form on the protective layer. This aspect further includes forming emitters for bipolar transistors in the bipolar transistor region, including forming a SiGe layer under a portion of the polysilicon layer. | 2009-02-26 |
20090050978 | SEMICONDUCTOR DEVICE - A disclosed semiconductor device includes a driver transistor including a source and a drain of a second conductive type provided with an interval therebetween in a semiconductor substrate of a first conductive type, a gate electrode extending in a predetermined direction and provided on the semiconductor substrate via a gate insulating film between the source and the drain, plural insular back gate diffusion layers of the first conductive type provided in the source so as to be in contact with the semiconductor substrate, wherein the back gate diffusion layers are spaced apart and arranged in the predetermined direction in the source, and a contact hole extending in the predetermined direction on the source and at least one of the back gate diffusion layers. | 2009-02-26 |
20090050979 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device having a semiconductor substrate, a first impurity region including a first conductive impurity formed in the semiconductor substrate, a first transistor and a second transistor formed in the first impurity region, a first stress film and a second stress having a first stress over the first transistor a and the second transistor, and a third stress film having a second stress different from the first stress provided in the first impurity region between the first stress film and the second stress film. | 2009-02-26 |
20090050980 | METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH SOURCE/DRAIN NITROGEN IMPLANT, AND RELATED DEVICE - A method of forming a semiconductor device with source/drain nitrogen implant, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate, implanting a dopant species into an active region adjacent to the gate stack, and reducing a diffusivity of the dopant species by implanting nitrogen into the active region. | 2009-02-26 |
20090050981 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased. | 2009-02-26 |
20090050982 | Method for Modulating the Effective Work Function - A new MOSFET device is described comprising a metal gate electrode, a gate dielectric and an interfacial layer. The interfacial layer comprises a lanthanum hafnium oxide material for modulating the effective work function of the metal gate. The gate dielectric material in contact with the interfacial layer is different that the interfacial layer material. A method for its manufacture is also provided and its applications. | 2009-02-26 |
20090050983 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - There is provided a trap memory device suppresses electric charges from flowing from the outside into a charge accumulation region and accumulated electric charges from diffusing to the outside or flowing out due to a defect. A gate conductor | 2009-02-26 |
20090050984 | MOS STRUCTURES THAT EXHIBIT LOWER CONTACT RESISTANCE AND METHODS FOR FABRICATING THE SAME - MOS structures that exhibit lower contact resistance and methods for fabricating such MOS structures are provided. In one method, a semiconductor substrate is provided and a gate stack is fabricated on the semiconductor substrate. An impurity-doped region within the semiconductor substrate aligned with the gate stack is formed. Adjacent contact fins extending from the impurity-doped region are fabricated and a metal silicide layer is formed on the contact fins. A contact to at least a portion of the metal silicide layer on at least one of the contact fins is fabricated. | 2009-02-26 |
20090050985 | Semiconductor device with increased channel length and method for fabricating the same - A semiconductor device with an increased channel length and a method for fabricating the same are provided. The semiconductor device includes: a substrate with an active region including a planar active region and a prominence active region formed on the planar active region; a gate insulation layer formed over the active region; and a gate structure including at least one gate lining layer encompassing the prominence active region on the gate insulation layer. | 2009-02-26 |
20090050986 | Method for Fabricating Sensor Chip, and Sensor Chip - A method for fabricating a sensor chip having a substrate, a cover layer, a spacer layer interposed between the substrate and the cover layer, and a hollow reaction section provided in the spacer layer, the method comprising the steps of: affixing two or more adhesive or bonding tapes onto a sheet where a plurality of substrates are to be formed or onto a plurality of substrates, to thus form a spacer layer; and forming a hollow reaction section from one or a plurality of gaps between the tapes, whereby volumetric variations or positional displacements of the hollow reaction section can be reduced. A sensor chip which can be fabricated by this method. | 2009-02-26 |
20090050987 | Fabrication of piezoelectric single crystalline thin layer on silicon wafer - The present invention relates a method of fabricating a piezoelectric device through micromachining piezoelectric-on-silicon wafer. The wafers are constructed so that piezoelectric layer is a single wafer having a thin layer from 5 to 50 μm. | 2009-02-26 |
20090050988 | MEMS APPARATUS AND METHOD OF MANUFACTURING THE SAME - A MEMS apparatus includes a MEMS unit formed on a semiconductor substrate and a cover provided with a pore and serving to seal the MEMS unit. The pore is sealed with a sealing material shaped in a sphere or a hemisphere. | 2009-02-26 |
20090050989 | Semiconductor device - A semiconductor device of the present invention includes a semiconductor substrate, a semiconductor element formed in the semiconductor substrate, a surface layer formed on the semiconductor substrate, and a capacitance type sensor formed on the surface layer. The surface layer has a planar portion whose surface is planar. The capacitance type sensor includes a lower thin film parallelly opposed to the surface of the planar portion and an upper thin film opposed to the lower thin film at a prescribed interval on the side opposite to the surface layer. | 2009-02-26 |
20090050990 | SEMICONDUCTOR SENSOR DEVICE AND METHOD FOR MANUFACTURING SAME - Provided is a semiconductor sensor device which is manufactured by an MEMS technology wherein machining technology and/or material technology is combined with semiconductor technology for detecting and measuring various physical quantities. In the semiconductor sensor device, cracks which generate in a cap chip and a molding resin are eliminated and air-tightness between a semiconductor sensor chip and the cap chip is ensured. The cracks due to vibration applied when being cut can be eliminated by having the circumference side surface of the cap chip as a wet-etched surface. Furthermore, insulation is ensured by coating the cap chip side surface with an insulating protection film. | 2009-02-26 |
20090050991 | Magnetic Element Having Low Saturation Magnetization - A magnetic device including a magnetic element is described. The magnetic element includes a fixed layer having a fixed layer magnetization, a spacer layer that is nonmagnetic, and a free layer having a free layer magnetization. The free layer is changeable due to spin transfer when a write current above a threshold is passed through the first free layer. The free layer is includes low saturation magnetization materials | 2009-02-26 |
20090050992 | AMORPHOUS SOFT MAGNETIC SHIELDING AND KEEPER FOR MRAM DEVICES - An amorphous soft magnetic thin film material for forming shielding and keeper applications in MRAM devices. The amorphous soft magnetic material may be deposited using Physical Vapor Deposition (PVD) in the presence of a magnetic field, in order to form shielding layers and keepers in a multi-layer metallization process. The soft magnetic material may be an amorphous metallic alloy, such as CoZrX, where X may be Ta, Nb, Pd and/or Rh. | 2009-02-26 |
20090050993 | PHOTOELECTRIC CONVERSION DEVICE AND MULTI-CHIP IMAGE SENSOR - A pixel space is narrowed without increasing PN junction capacitance. A photoelectric conversion device includes a plurality of pixels arranged therein, each including a first impurity region of a first conductivity type forming a photoelectric conversion region, a second impurity region of a second conductivity type forming a signal acquisition region arranged in the first impurity region, a third impurity region of the first conductivity type and a fourth impurity region of the first conductivity type are arranged in a periphery of each pixel for isolating the each pixel, the fourth impurity region is disposed between adjacent pixels, and an impurity concentration of the fourth impurity region is smaller than an impurity concentration of the third impurity region. | 2009-02-26 |
20090050994 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH ELECTRODE FOR EXTERNAL CONNECTION AND SEMICONDUCTOR DEVICE OBTAINED BY MEANS OF SAID METHOD - A circuit element is disposed on an organic substrate and is connected to a wiring pattern provided on the organic substrate. Internal connection electrodes are formed on a support of a conductive material through electrofomiing such that the internal connection electrodes are integrally connected to the support. First ends of the internal connection electrodes integrally connected by the support are connected to the wiring pattern. After the circuit element is resin-sealed, the support is removed so as to separate the internal connection electrodes from one another. Second ends of the internal connection electrodes are used as external connection electrodes on the front face, and external connection electrodes on the back face are connected to the wiring pattern. | 2009-02-26 |
20090050995 | Electronic device wafer level scale packges and fabrication methods thereof - Electronic device wafer level scale packages and fabrication methods thereof. A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A trench is formed by etching the semiconductor exposing an inter-layered dielectric (ILD) layer. An insulating layer is conformably deposited on the back of the semiconductor substrate. The insulating layer on the bottom of the trench is removed, and the ILD layer is subsequently removed exposing part of a pair of contact pads. A conductive layer is conformably formed on the back of the semiconductor. After the conductive layer is patterned, the conductive layer and the contact pads construct an L-shaped connection. Next, an exterior connection and terminal contact pads are subsequently formed. | 2009-02-26 |
20090050996 | Electronic device wafer level scale packages and fabrication methods thereof - Electronic device wafer level scale packages and fabrication methods thereof. A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A first trench is formed by etching the semiconductor exposing an inter-layered dielectric layer. An insulating layer is conformably deposited on the back of the semiconductor substrate. The insulating layer on the bottom of the first trench is removed to create a second trench. The insulating layer and the ILD layer are sequentially removed exposing part of a pair of contact pads. A conductive layer is conformably formed on the back of the semiconductor. After the conductive layer is patterned, the conductive layer and the contact pads construct an S-shaped connection. Next, an exterior connection and terminal contact pads are subsequently formed. | 2009-02-26 |
20090050997 | Solid-state image capturing device, manufacturing method for the solid-state image capturing device, and electronic information device - A solid-state image capturing device having a plurality of light receiving sections for performing photoelectrical conversion on and capturing image light from a subject is provided. In the light receiving sections, a low concentration opposite conductivity layer is provided either on a single conductivity substrate or a single conductivity layer, a high concentration opposite conductivity layer having a higher impurity concentration than the low concentration opposite conductivity layer is provided on the low concentration opposite conductivity layer, and a photodiode is constituted by a PN junction of the single conductivity substrate or the single conductivity layer and the low concentration opposite conductivity layer. | 2009-02-26 |
20090050998 | SEMICONDUCTOR DEVICE - In one embodiment of the present invention, a semiconductor device has a photodiode over a P-type substrate, an NPN transistor formed over the P-type substrate, an N | 2009-02-26 |
20090050999 | Apparatus for storing electrical energy - An apparatus to store electrical energy is provided. The apparatus includes a first magnetic section, a second magnetic section, and a semiconductor section configured between the first magnetic section and the second magnetic section, wherein the junction between the semiconductor section and the first and second magnetic section forms a diode barrier preventing current flow to store electrical energy. | 2009-02-26 |
20090051000 | SEMICONDUCTOR DEVICE STRUCTURE - A semiconductor device structure is provided. By placing an insulating dielectric material in the drift region of a device to modulate the electric field distribution and current flow in the drift region, the breakdown voltage of the device is increased while the turn-on impedance of the device is reduced. | 2009-02-26 |
20090051001 | ISOLATED VERTICAL POWER DEVICE STRUCTURE WITH BOTH N-DOPED AND P-DOPED TRENCHES - A method for manufacturing an isolated vertical power device includes forming, in a back surface of a first conductivity type substrate, back isolation wall trenches that surround a conduction region of the device. In a front surface of the substrate, front isolation wall trenches are formed around the conduction region. Thereafter, a film containing a second type dopant is deposited in the front and back isolation wall trenches. In the conduction region on the back surface, conduction region trenches are formed inside the perimeter of the isolation wall trenches. A first type dopant is deposited in the conduction region trenches. The dopants are diffused from the conduction region trenches and isolation wall trenches to form a first conductivity type conduction region structure and a second conductivity type isolation wall. | 2009-02-26 |
20090051002 | ELECTRICAL FUSE HAVING A THIN FUSELINK - A thin semiconductor layer is formed and patterned on a semiconductor substrate to form a thin semiconductor fuselink on shallow trench isolation and between an anode semiconductor region and a cathode semiconductor region. During metallization, the semiconductor fuselink is converted to a thin metal semiconductor alloy fuselink as all of the semiconductor material in the semiconductor fuselink reacts with a metal to form a metal semiconductor alloy. The inventive electrical fuse comprises the thin metal semiconductor alloy fuselink, a metal semiconductor alloy anode, and a metal semiconductor alloy cathode. The thin metal semiconductor alloy fuselink has a smaller cross-sectional area compared with prior art electrical fuses. Current density within the fuselink and the divergence of current at the interface between the fuselink and the cathode or anode comparable to prior art electrical fuses are obtained with less programming current than prior art electrical fuses. | 2009-02-26 |
20090051003 | Methods and Structures Involving Electrically Programmable Fuses - A method for fabricating an eFuse, the method comprising disposing a crystalline silicon eFuse on a substrate having a fuse link portion, a first contact portion, and a second contact portion, wherein the fuse link is oriented parallel to the silicon crystal { | 2009-02-26 |
20090051004 | Surface Mount Components Joined Between a Package Substrate and a Printed Circuit Board - A microelectronic package and a method of forming the package. The package includes a first level package mounted to a carrier. The first level package includes a package substrate having a die side and a carrier side; and a microelectronic die mounted on the package substrate at the die side thereof. The carrier has a substrate side, and the first level package is mounted on the carrier at the substrate side thereof. A rigid body is attached to the carrier side of the substrate at an attachment location of the substrate and to the substrate side of the carrier at an attachment location of the carrier, the attachment location of the carrier being electrically unconnected, the rigid body being configured and disposed to provide structural support between the substrate and the carrier. | 2009-02-26 |
20090051005 | METHOD OF FABRICATING INDUCTOR IN SEMICONDUCTOR DEVICE - A method of fabricating an inductor in a semiconductor device is disclosed. Embodiments include forming a first metal wire in a trench formed by etching a layer of a semiconductor substrate, forming an insulating layer over the substrate including the first metal wire, forming a via hole by etching the insulating layer to expose a portion of the first metal wire, forming a plated layer by electroplating to partially fill the via hole with the plated layer, and forming a second metal wire over the insulating layer including the plated layer. | 2009-02-26 |
20090051006 | N CELL HEIGHT DECOUPLING CIRCUIT - A decoupling circuit disposed between a first rail and a second rail, where a third power rail is disposed between the first and second rails. A resistor having a first electrode and a second electrode is disposed between the first and second rails. Two capacitors are disposed between the first and second rails. The resistor is connected to the third rail and the two capacitors. In this manner, the two capacitors are connected in series with respect to the resistor, and in parallel with respect to one another. A first of the two capacitors is connected to the first rail, and a second of the two capacitors is connected to the second rail. At least one of the resistor and the two capacitors is disposed at least in part beneath the third rail. | 2009-02-26 |
20090051007 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device is composed of: an interconnect made of a first conductive film and a second conductive film that are stacked in sequence from the interconnect underside on an insulating film formed on a substrate; and a capacitor composed of a lower capacitor electrode made of the first conductive film, a dielectric film formed on the lower capacitor electrode, and an upper capacitor electrode made of the second conductive film and formed on the dielectric film. | 2009-02-26 |
20090051008 | Semiconductor device having a resistor and methods of forming the same - In a semiconductor device and a method of making the same, the semiconductor device comprises a substrate including a first region and a second region. At least one first gate structure is on the substrate in the first region, the at least one first gate structure including a first gate insulating layer and a first gate electrode layer on the first gate insulating layer. At least one isolating structure is in the substrate in the second region, a top surface of the isolating structure being lower in height than a top surface of the substrate. At least one resistor pattern is on the at least one isolating structure. | 2009-02-26 |
20090051009 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME AND RESISTOR - Formed on an insulator are an N | 2009-02-26 |
20090051010 | IC package sacrificial structures for crack propagation confinement - Systems and methods for preventing damage to a unit with preventive structures are presented. In an embodiment, a unit of a collection of units includes a functional area and a preventive structure configured to prevent cracks from propagating into the functional area. | 2009-02-26 |
20090051011 | Semiconductor device having seal ring structure and method of forming the same - A semiconductor device of the present invention includes a seal ring structure. The seal ring structure includes a first metal layer including a though hole, the through hole having a bottom portion filled with an insulating material, and a second metal layer formed on the first metal layer. The second metal layer has a projected portion projecting from a bottom of the second metal layer and the projected portion is inserted into a top portion of the through hole. | 2009-02-26 |
20090051012 | Through-hole interconnection structure for semiconductor wafer - A through-hole interconnection structure for a semiconductor wafer, in which: the each wafer includes at least a first wafer and a second wafer electrically connected to the first wafer; an electrical signal connecting section of the second wafer is provided to protrude from a bonding surface of the second wafer, the bonding surface being bonded with the first wafer; and the electrical signal connecting section has a cross section with a curved line or two or more straight lines extending in different directions when the second wafer is seen along a cross section parallel to the bonding surface. | 2009-02-26 |
20090051013 | SEMICONDUCTOR WAFER FOR SEMICONDUCTOR COMPONENTS AND PRODUCTION METHOD - A semiconductor wafer for semiconductor components and to a method for its production is disclosed. In one embodiment, the semiconductor wafer includes a front side with an adjoining near-surface active zone as basic material for semiconductor component structures. The rear side of the semiconductor wafer is adjoined by a getter zone for gettering impurity atoms in the semiconductor wafer. The getter zone contains oxygen precipitates. In the near-surface active zone, atoms of doping material are located on lattice vacancies. The atoms of doping material have a higher diffusion coefficient that the oxygen atoms. | 2009-02-26 |
20090051014 | Method of fabricating semiconductor device having silicide layer and semiconductor device fabricated thereby - A method of fabricating a semiconductor device having a silicide layer and a semiconductor device fabricated by the method are provided. The method may involve providing a semiconductor substrate having an active region and a field region, and forming a plurality of gate patterns on each of the active region and the field region. The plurality of gate patterns may each have a sidewall spacer. The plurality of gate patterns on the field region include at least two adjacent gate patterns. The method may involve forming a silicide blocking layer pattern that masks a portion of the field region that exists between each of the adjacent gate patterns on the field region. The method may also involve forming a silicide layer on the active region and any of the plurality of the gate patterns that are not masked by the silicide blocking layer pattern. | 2009-02-26 |
20090051015 | SEMICONDUCTOR DEVICE AND PRINTED CIRCUIT BOARD - For a multi-terminal semiconductor package, such as a BGA or a CSP, that handles high-speed differential signals, a high-speed signal is assigned to the innermost located electrode pad on an interposer substrate, and the electrode pad is connected to the outermost located ball pad on the interposer substrate. With this arrangement, the length of a plating stub can be considerably reduced, and the adverse affect on a signal waveform can be minimized. This arrangement is especially effective for differential signal lines. | 2009-02-26 |
20090051016 | ELECTRONIC COMPONENT WITH BUFFER LAYER - An electronic component includes a metal substrate, a semiconductor chip configured to be attached to the metal substrate, and a buffer layer positioned between the metal substrate and the semiconductor chip configured to mechanically decouple the semiconductor chip and the metal substrate. The buffer layer extends across less than an entire bottom surface of the semiconductor chip. | 2009-02-26 |
20090051017 | Lead Frame with Non-Conductive Connective Bar - An electronic component includes a lead frame, a semiconductor chip and an encapsulating body. The lead frame includes a heat spreader area, a plurality of conductive lead fingers, at least one non-conductive tie bar, and a metal joint. The metal joint connects the at least one non-conductive tie bar to the heat spreader area. The semiconductor chip is provided on a die pad located on the heat spreader area. The encapsulating body covers at least part of the semiconductor chip, at least part of the at least one non-conductive tie bar and part of the lead frame. | 2009-02-26 |
20090051018 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - In various embodiments, semiconductor components and methods to manufacture these components are disclosed. In one embodiment, a method to manufacture a semiconductor component is disclosed. The semiconductor includes a heat sink and a semiconductor die that has a first terminal on a top surface of the semiconductor die, a second terminal on the top surface of the die, and a third terminal on the bottom surface of the die. The method includes attaching a first portion of a leadframe structure to the first terminal of the semiconductor die. The method further includes attaching the second terminal of the semiconductor die to the heat sink after the attaching of the first portion of the leadframe structure to the first terminal of the semiconductor die, wherein the leadframe structure is spaced apart from the heat sink and is electrically isolated from the heat sink. Other embodiments are described and claimed. | 2009-02-26 |
20090051019 | Multi-chip module package - A multi-chip module package is provided, which includes a first chip mounted on via a first conductive adhesive and electrically connected to a first chip carrier, a second chip mounted on via a second conductive adhesive and electrically connected to a second chip carrier which is spaced apart from the first chip carrier, wherein the second conductive adhesive is made of an adhesive material the same as that of the first conductive material, a plurality of conductive elements to electrically connect the first chip to the second chip and an encapsulant encapsulating the first chip, the first chip carrier, the second chip, the second chip carrier and the plurality of conductive elements, allowing a portion of both chip carriers to be exposed to the encapsulant, so that the first chip and second chip are able to be insulated by the separation of the first and second chip carriers. | 2009-02-26 |
20090051020 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A semiconductor memory device includes: A method of manufacturing a semiconductor device, wherein a semiconductor chip is mounted on a lead frame including a plurality of lead lines, and terminals included in the semiconductor chip are connected to the lead lines, thereby to manufacture the semiconductor device, comprising the steps of:
| 2009-02-26 |
20090051021 | SEMICONDUCTOR CHIP STACK-TYPE PACKAGE AND METHOD OF FABRICATING THE SAME - Embodiments of the inventive concept provide a semiconductor chip stack-type package. The package comprises a lead frame including a die paddle part and a lead part, a first semiconductor chip group and a second semiconductor chip group stacked sequentially and mounted on one surface of the die paddle part, a first wiring board between the first semiconductor chip group and the second semiconductor chip group, and second semiconductor chip group bonding wires for electrically connecting the second semiconductor chip group to the first wiring board. End portions of the first wiring board are electrically connected to inner leads of the lead part, which is adjacent to the die paddle part. | 2009-02-26 |
20090051022 | LEAD FRAME STRUCTURE - A lead frame structure includes a lead frame, a partial plated portion, a semiconductor element, a Pb-free solder and a mold resin. The partial plated portion is formed on a part of a surface of the lead frame. The partial plated portion is made of a noble metal. The semiconductor element is bonded with the partial plated portion through a Pb-free solder and is electrically connected to the lead frame through the Pb-free solder and the partial plated portion. The mold resin encloses the semiconductor element and the lead frame other than a coupling portion, which is to be electrically coupled to an external device. | 2009-02-26 |
20090051023 | STACK PACKAGE AND METHOD OF FABRICATING THE SAME - Provided is a stack package comprising: a substrate comprising a cavity; a first semiconductor chip disposed in the cavity; and a second semiconductor chip stacked on the substrate and electrically connected to the substrate by a plurality of conductive external terminals such as conductive bumps. Since both a horizontal packaging method using bonding wires and a flip-chip packaging method are used and the bonding wires of the horizontal package and the conductive external terminals for the flip-chip bonding are formed on substantially the same plane, the total height of the stack package is reduced. | 2009-02-26 |
20090051024 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure relates to a chip-embedded semiconductor package electrically connected to a second semiconductor component. The semiconductor package structure comprises a first packaging substrate having a first surface, a second surface and at least a first cavity penetrating through the first surface and the second surface. The semiconductor package structure includes a first semiconductor component with electrode pads disposed in the first cavity. A first build-up circuit structure comprising a plurality of third and fourth conductive pads, and a second semiconductor component with electrode pads is disposed on surfaces of the third conductive pads by a first conductive element. The semiconductor package structure also includes a second conductive element disposed on the fourth conductive pads of the first build-up circuit structure of the first packaging substrate and a stacked structure electrically connecting the stacked structure to the first build-up circuit structure disposed on the first packaging substrate. | 2009-02-26 |
20090051025 | FAN OUT TYPE WAFER LEVEL PACKAGE STRUCTURE AND METHOD OF THE SAME - To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dies with a side by side structure or a stacking structure. | 2009-02-26 |
20090051026 | PROCESS FOR FORMING METAL FILM AND RELEASE LAYER ON POLYMER - A process for forming a releasable metal film includes depositing a metal onto a polymeric sheet such that the metal layer provides a low adhesive interface and exhibits relatively low stress. A barrier layer is then deposited onto the surface of the low adhesion interface. A thin film of a stress relief layer of silicon dioxide, aluminum oxide, copper or aluminum is then deposited followed by addition of a second barrier layer onto the stress relief layer. The stress relief layer provides compressive relief to balance the tensile stress of the so-stacked metal films. An additional solderable layer maybe added for soldering applications. To fabricate the working device with sputtering tools, an extremely high gas pressure is used to achieve low adhesion force between the wettable metallic layer and the polymeric carrier film. | 2009-02-26 |
20090051027 | Method of Manufacture and Identification of Semiconductor Chip Marked For Identification with Internal Marking Indicia and Protection Thereof by Non-black Layer and Device Produced Thereby - An electronic integrated circuit has a planar front surface and a planar backsurface. Internal marking indicia identification are marked upon an marking surface on the exterior surface of the chip. The internal identification indicia on the chip surface are protected against remarking by a non-black, colored, optically transmissive layer, so the indicia are visible through the optically transmissive material. Electrical interconnection means connect to the electrical contact site through the package. There is least one electrical contact site on an exterior surface of the chip. | 2009-02-26 |
20090051028 | ELECTRONIC DEVICE AND ELECTRONIC APPARATUS - An electronic device includes a semiconductor device and a wiring substrate having a wiring pattern. The semiconductor device includes: a semiconductor chip having an electrode; a convex-shaped resin protrusion provided on a surface of the semiconductor chip, the surface having the electrode; and wiring having a plurality of electrical coupling sections which are aligned on the resin protrusion and electrically coupled to the electrode. The semiconductor device is mounted to the wiring substrate so that the electrical coupling sections and the wiring pattern are brought into contact and electrically coupled with each other. The plurality of electrical coupling sections brought into contact with the wiring pattern include curved or bent shapes projecting in a longitudinal direction of the resin protrusion. | 2009-02-26 |
20090051029 | FLIP-CHIP TYPE SEMICONDUCTOR DEVICE - A flip-chip type semiconductor device includes a semiconductor substrate. A plurality of electrode terminals are provided and arranged on a top surface of the semiconductor substrate, a sealing resin layer is formed on the top surface of the semiconductor substrate such that the electrode terminals are completely covered with the sealing resin layer. | 2009-02-26 |
20090051030 | SEMICONDUCTOR PACKAGE WITH PAD PARTS ELECTRICALLY CONNECTED TO BONDING PADS THROUGH RE-DISTRIBUTION LAYERS - The semiconductor package includes: a semiconductor chip module having multiple adjacently arranged or integrally formed semiconductor chips each with a bonding pad group and a connection member electrically connecting each of the bonding pads included in the first bonding pad group to the corresponding bonding pad in the second bonding pad group. In the present invention pad parts can be formed on the outside of the semiconductor chip module to conform with the standards of JEDEC. These pad parts are then connected to the semiconductor chips bonding pads through re-distribution layers. The pad parts of the semiconductor package can then conform to the JEDEC standards even while having a semiconductor chip with bonding pads smaller than the standards. | 2009-02-26 |
20090051031 | Package structure and manufacturing method thereof - A package structure and a manufacturing method thereof are provided. The package structure comprises a carrier, a chip, at least one wire, a molding compound, at least one first solder ball and at least one second solder ball. The carrier has a chip chamber passing through the first surface and the second surface. The chip is disposed in the chip chamber, and an active surface of the chip is coplanar with the first surface. During packaging, the first surface and the active surface are both tightly pasted on a carrier tape to facilitate the subsequent wire bonding and sealing process. Afterwards, the carrier tape is removed for exposing the active surface and the first surface, and the active surface of the chip is coplanar with the first surface of the carrier, hence simplifying the packaging process and reducing the thickness of the package structure. | 2009-02-26 |
20090051032 | PATTERNED NANOSCOPIC ARTICLES AND METHODS OF MAKING THE SAME - Nanowire articles and methods of making the same are disclosed. A conductive article includes a plurality of inter-contacting nanowire segments that define a plurality of conductive pathways along the article. The nanowire segments may be semiconducting nanowires, metallic nanowires, nanotubes, single walled carbon nanotubes, multi-walled carbon nanotubes, or nanowires entangled with nanotubes. The various segments may have different lengths and may include segments having a length shorter than the length of the article. A strapping material may be positioned to contact a portion of the plurality of nanowire segments. The strapping material may be patterned to create the shape of a frame with an opening that exposes an area of the nanowire fabric. Such a strapping layer may also be used for making electrical contact to the nanowire fabric especially for electrical stitching to lower the overall resistance of the fabric. | 2009-02-26 |
20090051033 | RELIABILITY IMPROVEMENT OF METAL-INTERCONNECT STRUCTURE BY CAPPING SPACERS - The present invention relates to a metal-interconnect structure for electrically connecting integrated-circuit elements in an integrated-circuit device. It solves several problems of operational reliability in damascene interconnect structures, due to corner effects and structural defects present at top edges of interconnect lines fabricated according to prior-art processing technologies. In alternative configurations of the metal interconnect structure, capping spacers ( | 2009-02-26 |
20090051034 | Semiconductor device and method for the same - A method for forming a semiconductor device is provided. The method includes the following steps. A substrate having a first contact is provided. A layered structure is formed on the substrate. A recess is formed into the layered structure to expose at least a portion of the first contact. A glue layer is formed on the layered structure and the at least a portion of the first contact. The glue layer is removed from the at least a portion of the first contact. A second contact is formed contacting the first contact and the glue layer. | 2009-02-26 |
20090051035 | SEMICONDUCTOR INTEGRATED CIRCUIT - The semiconductor integrated circuit includes: a first wiring layer including a plurality of first interconnects formed to run in a first direction; a second wiring layer formed above the first wiring layer, the second wiring layer including a plurality of second interconnects formed to run in a second direction vertical to the first direction; and a third wiring layer formed above the second wiring layer, the third wiring layer including a plurality of third interconnects formed to run in the same direction as the second direction. | 2009-02-26 |
20090051036 | Semiconductor Package Having Buss-Less Substrate - A ball grid array device with an insulating substrate ( | 2009-02-26 |
20090051037 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF - A semiconductor device relating to the present invention has multiple gate electrodes arranged on a semiconductor substrate at a narrow spacing and an interlayer insulating film covering the gate electrodes. The interlayer insulating film consists of a hygroscopic insulating film filling gate electrode spacing with a thinner thickness on the gate electrodes than the film thickness on the flat surface of the semiconductor substrate and low-hygroscopic insulating film formed on the hygroscopic insulating film. This structure enables suppressing an increase of contact resistance due to H | 2009-02-26 |
20090051038 | SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR CONSTITUENT AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor constituent having a semiconductor substrate and a plurality of electrodes for external connection provided under the semiconductor substrate. An under-layer insulating film is provided under and around the semiconductor constituent. A plurality of under-layer wires are provided under the under-layer insulating film and electrically connected to the electrodes for external connection of the semiconductor constituent. An insulating layer is provided around the semiconductor constituent and on the under-layer insulating film. A frame-like insulating substrate is embedded in an upper surface of the insulating layer and positioned around the semiconductor constituent. A plurality of upper-layer wires are provided on the insulating substrate. A base plate on which the semiconductor constituent and the insulating layer are mounted is removed. | 2009-02-26 |
20090051039 | THROUGH-SUBSTRATE VIA FOR SEMICONDUCTOR DEVICE - A semiconductor device including a substrate having a front surface and a back surface is provided. A plurality of interconnect layers are formed on the front surface and have a first surface opposite the front surface of the substrate. A tapered profile via extends from the first surface of the plurality of interconnect layers to the back surface of the substrate. In one embodiment, a insulating layer is formed on the substrate and includes an opening, and wherein the opening includes conductive material providing contact to the tapered profile via. | 2009-02-26 |
20090051040 | POWER LAYOUT OF INTEGRATED CIRCUITS AND DESIGNING METHOD THEREOF - The invention discloses a technique for designing the power layout of an integrated circuit. The power layout design forms a power mesh and a power ring with a plurality of metal trunks with uniform line width. In particular, the power ring includes a plurality of metal rings, which are formed by arranging denser layout of the metal trunks with uniform line width. The power ring serves as a function of receiving and providing a power source to the elements of the integrated circuit. | 2009-02-26 |
20090051041 | MULTILAYER WIRING SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, AND SUBSTRATE FOR USE IN IC INSPECTION DEVICE AND METHOD FOR MANUFACTURING THE SAME - A multilayer wiring substrate includes one or more resin dielectric layers ( | 2009-02-26 |
20090051042 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate that has an integrated circuit; a plurality of electrodes that is formed on the semiconductor substrate, the plurality of the electrodes being electrically coupled to the integrated circuit; a passivation film that is formed on the semiconductor substrate, the passivation film having an opening on at least a part of one of the plurality of electrodes; a resin protrusion that is disposed on the passivation film; and a plurality of wiring lines that extend to a surface of the resin protrusion, each of the plurality of wiring lines extending from one of the plurality of the electrodes, a first portion of each of the plurality of wiring lines being positioned at an uppermost edge of the resin protrusion, a second portion of each of the plurality of wiring lines being positioned between one of the plurality of electrodes and the uppermost edge of the resin protrusion, a width of the first portion of each of the plurality of wiring lines being narrower than a width of at least a part of the second portion of each of the plurality of wiring lines. | 2009-02-26 |
20090051043 | DIE STACKING IN MULTI-DIE STACKS USING DIE SUPPORT MECHANISMS - Systems, methods, and devices that facilitate stacking dies in a multi-die stack using die support mechanisms (DSMs) are presented. DSMs are employed to place a smaller die and attached wires underneath a larger die. DSMs can be placed on each side of the smaller die where the larger die overhangs when placed above the smaller die. The DSMs can be optimally sized to provide support to the larger die to reduce overhang and sagging, while providing a buffer region to protect the smaller die and associated wires. DSMs are employed to facilitate stacking dies that are the same or similar in size by placing a DSM between the dies. The DSM can be optimally sized to provide a buffer region to protect the wires bonded to the top side of the lower die from the upper die, while minimizing overhang to provide support to the upper die. | 2009-02-26 |
20090051044 | Wafer-level packaged structure and method for making the same - A wafer-level packaging method is shown below: providing an un-cut wafer having a front side and a back side. A plurality of cutting lines is formed on the front side of the wafer so as to define the positions of each chip module such as a wireless module. The next step is providing an extendible film attached onto the back side of the wafer. Next is dicing the wafer along the cutting line to separate each chip module and expending the extendible film so that a gap is formed between each chip module. At last, filling a packaging compound onto the front side and the lateral side of the chip module produces a packaged structure. As mentioned above, the structure is employed for protecting the external surface of the chip. | 2009-02-26 |
20090051045 | Semiconductor package apparatus - A semiconductor package apparatus comprises: at least one semiconductor chip; and a circuit board on which the semiconductor chip is installed, wherein at least one conductive plane for improving power and/or ground characteristics is positioned on a side of the semiconductor chip. In this manner, fabrication cost for the semiconductor package apparatus can be mitigated, and power and/or ground characteristics can be improved so as to readily control impedance of signal lines. As a result, reliability of the operation of the semiconductor package apparatus can be improved, and noise and malfunction can be prevented. | 2009-02-26 |
20090051046 | Semiconductor device and manufacturing method for the same - A semiconductor substrate provided with an integrated circuit is polished by CMP or the like, and the semiconductor substrate is made into a thin film by forming an embrittlement layer in the semiconductor substrate and separating a part of the semiconductor substrate; thus, semiconductor chips such as IC chips and LSI chips which are thinner than ever are obtained. Moreover, such thinned LSI chips are stacked and electrically connected through wirings penetrating through the semiconductor substrate; thus, a three dimensional semiconductor integrated circuit with improved packing density is obtained. | 2009-02-26 |
20090051047 | Semiconductor apparatus and method of manufacturing the same - There is provided a semiconductor apparatus which includes a substrate, a semiconductor chip mounted above the substrate, a first resin filled between the substrate and the semiconductor chip, and a second resin formed on the substrate and extending from a side surface of the semiconductor chip toward an outer edge of the substrate. The second resin extends from an intersection of an extension of the side surface of the semiconductor chip and the substrate toward the outer edge of the substrate so that a first stress generated on a contact surface between the first resin and the semiconductor chip and a second stress generated on a contact surface between the first resin or the second resin and the substrate balance out each other. | 2009-02-26 |
20090051048 | Package structure and manufacturing method thereof - A package structure and a manufacturing method thereof are provided. The package structure includes a carrier, a chip-bonding structure and a chip. The chip-bonding structure is formed on a first surface of the carrier. The chip-bonding structure includes a cavity, a dam, several via holes and several solder bumps. The solder bumps are received in the via holes and are correspond to the first connecting pads located on the carrier. The chip is embedded in the cavity of the chip-bonding structure. An active surface of the chip is tightly pasted on the first surface of the chip-bonding structure, and the first solder pads form electrical contact with the corresponding solder bumps. The chip of the package structure is precisely disposed on the carrier, not only simplifying the manufacturing process but also forming stable electrical connection between the chip and the carrier of the package structure. | 2009-02-26 |
20090051049 | Semiconductor device, substrate and semiconductor device manufacturing method - The semiconductor device can prevent damages on a semiconductor chip even when a soldering material is used for bonding the back surface of the semiconductor chip to the junction plane of a chip junction portion such as an island or a die pad. This semiconductor device includes a semiconductor chip and a chip junction portion having a junction plane that is bonded to the back surface of the semiconductor chip with a soldering material. The junction plane is smaller in size than the back surface of the semiconductor chip. This semiconductor device may further include a plurality of extending portions which extend respectively from the periphery of the junction plane to directions parallel with the junction plane. | 2009-02-26 |
20090051050 | CORNER I/O PAD DENSITY - An integrated circuit die has a plurality of I/O cells disposed about its periphery, each I/O cell having an I/O bonding pad. A first group of I/O cells is disposed at the periphery of the die at locations away from corners of the die, each of the first group of I/O cells having an I/O pad disposed thereon and spaced at a first distance from the periphery of the die. A second group of I/O cells is disposed at the periphery of the die at locations away from corners of the die, each of the second group of I/O cells having an I/O pad disposed thereon and spaced at a distance from the periphery of the die more than the first distance, the distance increasing as a function of the proximity of each I/O cell to a corner of the die. | 2009-02-26 |
20090051051 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first insulator film having a first opening, a first wiring layer extending from the first opening onto the first insulator film, a first semiconductor chip mounted on the first insulator film so as to be electrically coupled with the first wiring layer, and a resin portion applied on the first insulation film to cover the first semiconductor chip. | 2009-02-26 |
20090051052 | Semiconductor device - A semiconductor device includes a molding resin layer and a semiconductor element encapsulated with the molding resin layer. The molding resin layer has an opening. A surface of the semiconductor element is partially exposed outside the molding resin layer through the opening. A groove is located in the surface of the semiconductor element around the opening of the molding resin layer. The groove is filled with the molding resin layer to produce anchor effect that enhances adhesive force of the molding resin layer to the surface of the semiconductor element around the opening. | 2009-02-26 |
20090051053 | EPOXY RESIN COMPOSITION AND SEMICONDUCTOR APPARATUS - The object of the present invention is to provide an epoxy resin composition which is excellent in flash characteristics and thermal conductivity, and gives an area mounting type semiconductor apparatus having little warpage and excellent temperature cycle properties. According to the present invention, there is provided an epoxy resin composition for semiconductor encapsulation which comprises, as essential components, (A) a spherical alumina, (B) an ultrafine silica having a specific surface area of 120-280 m | 2009-02-26 |
20090051054 | FUEL SUPPLY DEVICE FOR ENGINE - A fuel supply device for an engine includes a fuel tank positioned such that, at least when the fuel tank is filled with fuel, a first fuel level in the fuel tank is higher than a minimum required second fuel level in a float chamber. A bypass passage that bypasses a fuel pump is provided, and an on-off valve is disposed in the bypass passage. The fuel supply device is capable of improving a starting characteristic of the engine during an off period of the fuel pump without increasing a head difference between the first and second fuel levels. | 2009-02-26 |
20090051055 | Integrated nano-bubble generating apparatus - An integrated nano-bubble generating apparatus comprising a pressure tank integrated with components constituted as a system and a power portion to be selectively adapted to a system so as to enlarge the use scope of the system, which comprises an integrated bubble generating portion including a three-directional electronic valve supplying water flowing in an inflowing pipe to any one of a bubble generating portion and the power portion, a pressure sensing portion sensing a pressure in the inflowing pipe, a first vacuum chamber providing outer air to the pressure tank, the power control portion controlling the three-directional electronic valve, the pressure sensing portion and the first vacuum chamber and the pressure tank mixing water and air under an inner predetermined pressure and shattering water, physically, to generate nano-bubble water; and the power portion including a pump operated by a motor to supply water flowing in the inflowing pipe to the bubble generating portion and a second vacuum chamber supplying outer air via a check valve with air flowing in an air supplying pipe to the pump and a power control power portion controlling the check valve and the m valve second vacuum chamber, in which the integrated bubble generating portion is direct-coupled to a water faucet or a shower tap to generate nano-bubble water only with subsistence water being physically shattered a few times without the power portion. | 2009-02-26 |
20090051056 | Apparatus for producing microbubble liquid and device for atomizing air bubbles using the same - There are provided a microbubble liquid producing apparatus capable of effectively producing microbubble liquid containing fully microscopic air bubbles, and a device for atomizing air bubbles using the microbubble liquid producing apparatus. | 2009-02-26 |
20090051057 | Diffuser For Aeration - Disclosed is a diffuser installation structure capable of improving uniformity of air bubbles discharged from air bubble discharge holes, restricting the formation of dead zone air bubble discharge holes, and having the tolerance against design deviation. In the installation structure for a diffuser comprising at least one air feeding port and an air bubble discharge wall having a plurality of air bubble discharge holes, the air bubble discharge wall is inclined upward in the direction of increasing distance relative to the air feeding port. | 2009-02-26 |
20090051058 | Method for producing polarized, polarizer, polarizing plate, optical film, and image display device - A method for producing a polarizer of the present invention comprises: subjecting a polyvinyl alcohol film to at least a dyeing process, a crosslinking process and a stretching process; and then subjecting the polyvinyl alcohol film to a washing process with an aqueous solution containing 1 to 50% by weight of an alcohol and 0.5 to 10% by weight of an iodide compound. A polarizer produced by the production method has high transmittance and high degree of polarization. | 2009-02-26 |
20090051059 | METHODS FOR FORMATION OF AN OPHTHALMIC LENS PRECURSOR AND LENS - This invention discloses methods for generating one or both of an ophthalmic lens precursor with at least a portion of one surface free-formed from a Reactive Mixture. In some embodiments, an ophthalmic lens precursor is formed on a substrate with an arcuate optical quality surface via a source of actinic radiation controllable to cure a definable portion of a volume of Reactive Mixture. | 2009-02-26 |
20090051060 | PREPARATION OF ANTIMICROBIAL CONTACT LENSES WITH REDUCED HAZE USING SWELLING AGENTS - This invention relates to antimicrobial lenses containing metals and methods for their production. | 2009-02-26 |
20090051061 | PROCESS FOR PELLETIZING POLYMER MELTS COMPRISING LOW-BOILING SUBSTANCES - The invention relates to a process for pelletizing polymer melts, at above ambient pressure, in a pelletizing chamber into which a cutting apparatus has been inserted. In a first step, the pelletizing chamber is flooded with a gas which is inert toward the polymer melt and whose pressure is that at which the pelletizing process is carried out. The polymer melt is then injected into the pelletizing chamber. Finally, the gas is displaced from the pelletizing chamber via a liquid as soon as the polymer melt begins to flow through the cutting apparatus, this melt being cut into pellets. | 2009-02-26 |
20090051062 | METHODS AND APPARATUS FOR FABRICATING STRUCTURES - Methods and apparatus for fabricating structures, extrusion units, and structures fabricated using such methods and apparatus are disclosed. The apparatus may include a support configured for rotation about a central axis, a carriage that may move along the support when the support rotates about the central axis such that the carriage may move along a first spiral path about the central axis, and an extrusion unit that may be supported by the carriage and may move along a second spiral path as the carriage moves along the first spiral path. The extrusion units may be configured to extrude a strip of material through an extrusion die as the extrusion unit moves along a previously extruded strip of material such that the extruded strip may be fused onto the previously extruded strip as the extruded and previously extruded strips pass the extrusion die. | 2009-02-26 |
20090051063 | METHOD OF EXTRUSION OF PARTICULATE PASTES OR SUSPENSIONS - The extrusion of a green body from a paste or suspension of particulate solids in a liquid is conducted by a process which includes the steps of introducing flowable paste or suspension into an inlet end of a moulding passage which is defined by walls having at least one partially liquid-permeable wall section; applying pressure to the paste or suspension, thereby to remove from the passage at least a major portion of the liquid of the paste or suspension, by establishing a pressure differential across the liquid permeable section, so as to form in the passage a non-flowable body of consolidated particulate solids of the paste or suspension, and to extrude the non-flowable body progressively from an outlet end of the passage. The magnitude of the pressure, the rate of removal of liquid and the rate of extrusion are controlled to maintain the non-flowable body at a length which extends back from the outlet end of the passage and across and beyond the liquid-permeable wall section to provide a portion of the body upstream of the liquid-permeable wall section. Liquid is removed from the passage by constant pressure filtration in which liquid being forced from the suspension is filtered through the portion of the non-flowable body maintained upstream of the liquid permeable section. | 2009-02-26 |
20090051064 | Molding Machine Monitoring Apparatus, Method, and Program - An object is to make it possible to calculate and set a threshold used for determining whether a molded product is good or defective, for each molding shot, to thereby enable an operator of a molding machine to easily set the threshold, and to determine whether a molded product is good or defective, while using a proper threshold, to thereby maintain a proper percent defective and enable accurate determination for molded products. To achieve the above object, there are provided a numerical value detection section which detects a numerical value representing a molding condition of a molding machine; a relation-deriving section which derives a relation between threshold and percent defective on the basis of the detected numerical value; a threshold-setting section which sets, in accordance with the derived relation, a threshold corresponding to a previously set target value of the percent defective; and a determination section which determines whether a molded product is good or defective through comparison between the detected numerical value and the set threshold. | 2009-02-26 |
20090051065 | Method for Post-Mold Treatment of a Molded Article and an Apparatus for Implementing the Method - Embodiments of the present invention teach a method for post-mold treatment of a molded article and an apparatus for implementing the method. For example, a method of post-mold treatment of a molded article is provided. The method can be implemented in a molded article receptacle. The method comprises at a first instance in time, subjecting the molded article to a first type of post-mold treatment; and at a second instance in time, subjecting the molded article to a second type of post-mold treatment. | 2009-02-26 |
20090051066 | AUTOMOTIVE ARMREST WITH SOFT FEEL AND METHOD OF MAKING THE SAME - The present invention provides for an improved armrest with a soft feel for use in a trim assembly, and to a continuous two-shot molding operation that may be continuously performed utilizing a single mold assembly. In an exemplary embodiment, a trim assembly includes an integrated armrest formed by injecting a first material into a first shot mold cavity in a first shot of a molding operation. An armrest cover is molded to at least a portion of the armrest by injecting into a mold chamber a second foamed material in a second shot of the molding operation to provide the armrest with a soft feel. The second foamed material includes a foamed material that produces a soft, outer skin and a light, cellular inner core such that when a force is applied to the cover, the skin will deform and compress the inner core, providing a soft-touch feel to the armrest. | 2009-02-26 |
20090051067 | RTM Molding Method - Provided is an RTM molding method enabling to yield an FRP molded body formed so as to be increased in the fiber volume content and to thereby be made more excellent in strength and lightweightness. The resin composition is a chain-curing resin composition, and after the initiation of the curing of the resin composition, the highest temperature at the curing head of the resin composition, undergoing chain curing, within 10 seconds after the initiation of the curing is increased to be higher by 50° C. or more than the temperature of the resin composition at after the impregnation and before the curing, and thus, the resin composition is chain-cured with a Vf of 41% or more. | 2009-02-26 |
20090051068 | Method for Producing Molded Bodies from Proteins - The invention relates to a method for producing molded bodies from proteins by ionic liquids, in particular in 1,3-dialkyl-imidazolium-acetates or 1,3-dialkyl-imidazolium-chloride as solvents in which the protein is dissolved, the solution is formed into fibers and foils, or membranes, respectively, the protein is regenerated by precipitation in protide solutions, the solvent is separated by washing and the molded bodies are tried. Furthermore the invention relates to molded bodies produced by said method. | 2009-02-26 |
20090051069 | RAPID RECONFIGURABLE FUSELAGE MANDREL - A system and method for making and using a reconfigurable composite part mandrel operable in the manufacture of composite parts. The system may comprise an assembly fixture, a generic mandrel, a reconfigurable simulated skin, a reconfigurable frame portion, and state-changing material operable to harden into a desired configuration for forming a particular composite part. The method of forming and using the reconfigurable composite part mandrel may comprise: inserting the simulated skin within the assembly fixture, inserting or assembling the frame portion within the assembly fixture; inserting the generic mandrel into the assembly fixture; filling a cavity between the generic mandrel and the assembly fixture with the state-changing mixture to encapsulate the frame portion; hardening the state-changing mixture; and removing the assembly fixture and the simulated skin. | 2009-02-26 |
20090051070 | METHOD FOR PRODUCING INJECTION-MOLDED PARTS - In a method for producing injection-molded parts, PET material is processed and/or plasticized by means of a twin-screw extruder having a plurality of processing zones. At least two processing zones are implemented as degassing zones. The processed and/or plasticized material is transferred to a transfer reservoir and then further processed by a piston unit. | 2009-02-26 |
20090051071 | DIELECTRIC SUBSTANCE AND METHOD OF PRODUCING THE SAME - This invention provides a method for producing a dielectric substance having excellent dielectric properties and being biodegradable, such method comprising subjecting silk protein to molding. | 2009-02-26 |
20090051072 | Method of manufacturing safety cones from recycled materials - A method of manufacturing safety cones from recycled materials is disclosed. Recycled materials are disposed into a molding machine, which turns them into safety cone molds. A dye containing plastic powders, solvent, and colors is coated on the surface of the safety cone mold, rendering a colored safety cone. Therefore, the production cost can be reduced, and the color can stay longer. | 2009-02-26 |
20090051073 | Combination Thermoforming Trim Press and Comminuting Apparatus - A combination thermoforming trim press and comminuting apparatus is provided. The combination includes a horizontal trim press, a comminuting apparatus, and a height-adjustable delivery chute. The trim press has an exit for downwardly delivering a scrap web of thermoformable sheet material. The comminuting apparatus is provided beneath the exit and has an entrance for receiving the scrap web. The height-adjustable delivery chute is provided between the trim press exit and the comminuting apparatus entrance and includes a first section, a second section telescopically received relative to the first section to provide height adjustment, and a fastener for securing the chute at a selected height to substantially close any gaps between the trim press exit, the comminuting apparatus entrance and the delivery chute to eliminate any need for a shielding cage to prevent internal finger and limb access by an operator. | 2009-02-26 |
20090051074 | Lubricated bridge - An apparatus and method provide for the extrusion of green brick material around a hole-generating member and the use of a lubrication fluid between the hole-generating member and the green brick material to reduce friction therebetween during extrusion, thus enabling the formation of larger sized holes in the bricks formed thereby. | 2009-02-26 |
20090051075 | METHODS OF FORMING IMPRINT ON RESIN-MOLDED PRODUCT, AND RESIN-MOLDED PRODUCT - A method of forming an identifying imprint on a resin-molded product, includes the step of dividing a material into a first portion and a second portion, to form an identifying surface on at least one of the first portion and the second portion. The method also includes the steps of molding a resin material into the resin-molded product, and transferring an imprint of the identifying surface onto the resin-molded product. | 2009-02-26 |
20090051076 | Method and Apparatus for Providing polymer to be Used at Vacuum Infusion - The invention relates to a method of producing a shell member of fibre composite material by means of vacuum infusion, where the fibre material is impregnated with liquid polymer, and applying a mould ( | 2009-02-26 |