09th week of 2014 patent applcation highlights part 15 |
Patent application number | Title | Published |
20140054709 | Transistor Devices, Memory Cells, And Arrays Of Memory Cells - A transistor device includes a pair of source/drain regions having a channel region there-between. A first gate is proximate the channel region. A gate dielectric is between the first gate and the channel region. A second gate is proximate the channel region. A programmable material is between the second gate and the channel region. The programmable material includes at least one of a) a multivalent metal oxide portion and an oxygen-containing dielectric portion, or b) a multivalent metal nitride portion and a nitrogen-containing dielectric portion. Memory cells and arrays of memory cells are disclosed. | 2014-02-27 |
20140054710 | Reduction of Proximity Effects in Field-Effect Transistors with Embedded Silicon-Germanium Source and Drain Regions - An integrated circuit and method of fabricating the same utilizing embedded silicon-germanium (SiGe) source/drain regions, and in which the proximity effect of nearby shallow trench isolation structures is reduced. Embedded SiGe source/drain structures are formed by selective epitaxy into recesses etched into the semiconductor surface, on either side of each gate electrode. The SiGe structures overfill the recesses by at least about 30% of the depth of the recesses, as measured from the interface between the channel region and the overlying gate dielectric at the edge of the gate electrode. This overfill has been observed to reduce proximity effects of nearby shallow trench isolation structures on nearby transistors. Additional reduction in the proximity effect can be obtained by ensuring sufficient spacing between the edge of the gate electrode and a parallel edge of the nearest shallow trench isolation structure. | 2014-02-27 |
20140054711 | System and Method for a Vertical Tunneling Field-Effect Transistor Cell - A semiconductor device cell is disclosed. The semiconductor device cell includes a transistor gate having a gating surface and a contacting surface and a source region contacted by a source contact. The semiconductor device cell further includes a drain region contacted by a drain contact, wherein the drain contact is not situated opposite the source contact with respect to the gating surface of the transistor gate. Additional semiconductor device cells in which the gate contact is closer to the source contact than to the drain contact are disclosed. | 2014-02-27 |
20140054712 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - A semiconductor device using a small-sized metal contact as a program gate of an antifuse, and a method of fabricating the same are described. The semiconductor device includes a metal contact structure formed on a semiconductor substrate of a peripheral circuit area, and includes a first gate insulating layer to be ruptured. A gate structure is formed on the semiconductor substrate to one side of the metal contact structure. | 2014-02-27 |
20140054713 | SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME - A semiconductor device including: a first gate pattern disposed in a peripheral region of a substrate; a second gate pattern disposed in a cell region of the substrate; a first insulator formed on sidewalls of the first gate pattern; and a second insulator formed on sidewalls of the second gate pattern, wherein a dielectric constant of the first insulator is different from a dielectric constant of the second insulator, and wherein a height of the second insulator is greater than a height of the second gate pattern. | 2014-02-27 |
20140054714 | REPLACEMENT GATE FABRICATION METHODS - Semiconductor devices and related fabrication methods are provided. An exemplary fabrication method involves forming a pair of gate structures having a dielectric region disposed between a first gate structure of the pair and a second gate structure of the pair, and forming a voided region in the dielectric region between the first gate structure and the second gate structure. The first and second gate structures each include a first gate electrode material, wherein the method continues by removing the first gate electrode material to provide second and third voided regions corresponding to the gate structures and forming a second gate electrode material in the first voided region, the second voided region, and the third voided region. | 2014-02-27 |
20140054715 | SEMICONDUCTOR DEVICE WITH AN INCLINED SOURCE/DRAIN AND ASSOCIATED METHODS - A semiconductor device includes a semiconductor substrate having a channel region therein, a gate structure above the channel region, and source and drain regions on opposite sides of the gate structure. A respective contact is on each of the source and drain regions. At least one of the source and drain regions has an inclined upper contact surface with the respective contact. The inclined upper contact surface has at least a 50% greater area than would a corresponding flat contact surface. | 2014-02-27 |
20140054716 | SRAM Cells with Dummy Insertions - A device includes a first pull-up transistor, a second pull-up transistor, and a dummy gate electrode between the first and the second pull-up transistors. The first and the second pull-up transistors are included in a first Static Random Access Memory (SRAM) cell. | 2014-02-27 |
20140054717 | INTEGRATION OF MULTIPLE THRESHOLD VOLTAGE DEVICES FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR USING FULL METAL GATE - A substrate is provided, having formed thereon a first region and a second region of a complementary type to the first region. A gate dielectric is deposited over the substrate, and a first full metal gate stack is deposited over the gate dielectric. The first full metal gate stack is removed over the first region to produce a resulting structure. Over the resulting structure, a second full metal gate stack is deposited, in contact with the gate dielectric over the first region. The first and second full metal gate stacks are encapsulated. | 2014-02-27 |
20140054718 | Arrays of Vertically-Oriented Transistors, And Memory Arrays Including Vertically-Oriented Transistors - An array includes vertically-oriented transistors. The array includes rows of access lines and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. Individual of the columns include a data/sense line interconnecting transistors in that column. The array includes a plurality of conductive lines which individually extend longitudinally parallel and laterally between immediately adjacent of the data/sense lines. Additional embodiments are disclosed. | 2014-02-27 |
20140054719 | SEMICONDUCTOR DEVICE WITH RESISTANCE CIRCUIT - A semiconductor device has a resistance circuit including a resistance element as a first thin film arranged on an isolation oxide film provided on a surface of a semiconductor substrate, a second thin film comprised of silicon nitride formed on the first thin film, an intermediate insulating film formed on the second thin film, a contact hole passing through the second thin film, and a metal wiring formed on the contract hole. The first thin film has a low concentration impurity region and a high concentration impurity region at each of both ends of the low concentration impurity region. The second thin film is formed on the first thin film so as to be disposed on each of the high concentration impurity regions but not on the low concentration impurity region. An insulated gate field effect transistor is provided in a region of the semiconductor substrate surrounded by the isolation oxide film. | 2014-02-27 |
20140054720 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEROF - A method for fabricating a semiconductor device is provided. A first polysilicon layer of a first conductivity type is provided on a substrate having first and second active regions. An ion implantation process is performed in the polysilicon layer corresponding to the second active region by using a dopant of a second conductivity type opposite to the first conductivity type, and silane plasma is introduced during the ion implantation process to form a second polysilicon layer thereon and convert the first conductivity type of the first polysilicon layer corresponding to the second active region to the second conductivity type. The first and second polysilicon layers are patterned to form a first gate layer corresponding to the first active region and a second gate layer corresponding to the second active region. A semiconductor device is also provided. | 2014-02-27 |
20140054721 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device, and a method of fabricating the same, include a substrate including two-dimensionally arranged active portions, device isolation patterns extending along sidewalls of the active portions, each of the device isolation patterns including first and second device isolation patterns, gate patterns extending across the active portions and the device isolation patterns, each of the gate patterns including a gate insulating layer, a gate line and a gate capping pattern, and ohmic patterns on the active portions, respectively. Top surfaces of the first device isolation pattern and the gate insulating layer may be lower than those of the second device isolation pattern and the gate capping pattern, respectively, and the ohmic patterns may include an extending portion on the first insulating layer. | 2014-02-27 |
20140054722 | FINFET CELL ARCHITECTURE WITH POWER TRACES - A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions. | 2014-02-27 |
20140054723 | ISOLATION STRUCTURES FOR FINFET SEMICONDUCTOR DEVICES - One illustrative device disclosed herein includes a plurality of fins separated by a trench formed in a semiconducting substrate, a first layer of insulating material positioned in the trench, the first layer of insulating material having an upper surface that is below an upper surface of the substrate, an isolation layer positioned within the trench above the first layer of insulating material, the isolation layer having an upper surface that is below the upper surface of the substrate, a second layer of insulating material positioned within the trench above the isolation layer, the second layer of insulating material having an upper surface that is below the upper surface of the substrate, and a gate structure positioned above the second layer of insulating material. | 2014-02-27 |
20140054724 | ALIGNED GATE-ALL-AROUND STRUCTURE - Among other things, a semiconductor device comprising an aligned gate and a method for forming the semiconductor device are provided. The semiconductor device comprises a gate formed according to a multi-gate structure, such as a gate-all-around structure. A first gate portion of the gate is formed above a first channel of the semiconductor device. A second gate portion of the gate is formed below the first channel, and is aligned with the first gate portion. In an example of forming the gate, a cavity is etched within a semiconductor layer formed above a substrate. A dielectric layer is formed around at least some of the cavity to define a region of the cavity within which the second gate portion is to be formed in a self-aligned manner with the first gate portion. In this way, the semiconductor device comprises a first gate portion aligned with a second gate portion. | 2014-02-27 |
20140054725 | TRANSISTOR DEVICE AND FABRICATION METHOD - Various embodiments provide transistors and fabrication methods. An exemplary transistor can include a silicon nitride layer disposed between a gate dielectric layer and a gate electrode layer. The silicon nitride layer can have a first surface in contact with the gate dielectric layer and a second surface in contact with the gate electrode layer. The second surface can include silicon atoms having a concentration higher than the first surface. A sidewall spacer can be formed on the semiconductor substrate along sidewalls of each of the gate electrode layer, the silicon nitride layer, and the gate dielectric layer. The disclosed transistor can have a reduced turn-on voltage with reduced power consumption. | 2014-02-27 |
20140054726 | METHOD OF PRODUCING SEMICONDUCTOR WAFER, SEMICONDUCTOR WAFER, METHOD OF PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - There is provided a fabrication technique of a MOS structure that has a small EOT without increasing the interface trap density. More specifically, provided is a method of producing a semiconductor wafer that includes a semiconductor crystal layer, an interlayer made of an oxide, nitride, or oxynitride of a semiconductor crystal constituting the semiconductor crystal layer, and a first insulating layer made of an oxide and in which the semiconductor crystal layer, the interlayer, and the first insulating layer are arranged in the stated order. The method includes (a) forming the first insulating layer on an original semiconductor crystal layer, and (b) exposing a surface of the first insulating layer with a nitrogen plasma to nitride, oxidize, or oxynitride a part of the original semiconductor crystal layer, thereby forming the interlayer, together with the semiconductor crystal layer that is the rest of the original semiconductor crystal layer. | 2014-02-27 |
20140054727 | METHOD OF SELECTIVELY DEGLAZING P205 - A method of forming a transistor is disclosed, in which gate-to-substrate leakage is addressed by forming and maintaining a conformal oxide layer overlying the transistor gate. Using the method disclosed for an n-type device, the conformal oxide layer can be formed as part of the source-drain doping process. Subsequent removal of residual phosphorous dopants from the surface of the oxide layer is accomplished without significant erosion of the oxide layer. The removal step uses a selective deglazing process that employs a hydrolytic reaction, and an acid-base neutralization reaction that includes an ammonium hydroxide component. | 2014-02-27 |
20140054728 | SEMICONDUCTOR STRUCTURES PROVIDED WITHIN A CAVITY AND RELATED DESIGN STRUCTURES - Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity. The method for forming the cavity further includes forming at least one first vent hole of a first dimension which is sized to avoid or minimize material deposition on a beam structure during sealing processes. The method for forming the cavity further includes forming at least one second vent hole of a second dimension, larger than the first dimension. | 2014-02-27 |
20140054729 | MEMS DEVICE, ELECTRONIC APPARATUS, AND MANUFACTURING METHOD OF MEMS DEVICE - A MEMS device includes a first oxide film that is laminated on a main surface of a wafer substrate, a lower-layer wire portion that is provided on the first oxide film, a nitride film that is laminated so as to cover the first oxide film and the lower-layer wire portion, a sidewall portion that is laminated on the nitride film and is formed in a frame shape, a cavity portion that is partitioned by the sidewall portion, and a MEMS structure that is disposed in the cavity portion, in which the nitride film includes a through hole reaching the lower-layer wire portion, and in which the MEMS structure is electrically connected to the lower-layer wire portion by an electrical connection portion provided in the through hole. | 2014-02-27 |
20140054730 | SYSTEM AND METHOD FOR FORMING A BURIED LOWER ELECTRODE IN CONJUNCTION WITH AN ENCAPSULATED MEMS DEVICE - A system and method for forming a sensor device with a buried first electrode includes providing a first silicon portion with an electrode layer and a second silicon portion with a device layer. The first silicon portion and the second silicon portion are adjoined along a common oxide layer formed on the electrode layer of the first silicon portion and the device layer of the second silicon portion. The resulting multi-silicon stack includes a buried lower electrode that is further defined by a buried oxide layer, a highly-doped ion implanted region, or a combination thereof. The multi-silicon stack has a plurality of silicon layers and silicon dioxide layers with electrically isolated regions in each layer allowing for both the lower electrode and an upper electrode. The multi-silicon stack further includes a spacer that enables the lower electrode to be accessible from a topside of the sensor device. | 2014-02-27 |
20140054731 | MEMS PRESSURE SENSOR WITH MULTIPLE MEMBRANE ELECTRODES - In one embodiment, a MEMS sensor includes a first fixed electrode in a first layer, a cavity defined above the first fixed electrode, a membrane extending over the cavity, a first movable electrode defined in the membrane and located substantially directly above the first fixed electrode, and a second movable electrode defined at least partially within the membrane and located at least partially directly above the cavity. | 2014-02-27 |
20140054732 | METHOD AND APPARATUS FOR RELEASE-ASSISTED MICROCONTACT PRINTING OF MEMS - The disclosure provides methods and apparatus for release-assisted microcontact printing of MEMS. Specifically, the principles disclosed herein enable patterning diaphragms and conductive membranes on a substrate having articulations of desired shapes and sizes. Such diaphragms deflect under applied pressure or force (e.g., electrostatic, electromagnetic, acoustic, pneumatic, mechanical, etc.) generating a responsive signal. Alternatively, the diaphragm can be made to deflect in response to an external bias to measure the external bias/phenomenon. The disclosed principles enable transferring diaphragms and/or thin membranes without rupturing. | 2014-02-27 |
20140054733 | SINGLE-CHIP REFERENCED FULL-BRIDGE MAGNETIC FIELD SENSOR - The present invention discloses a single-chip referenced full-bridge magnetoresistive magnetic-field sensor. The single-chip sensor is a Wheatstone bridge arrangement of magnetoresistive sensing elements and reference elements. The sensing elements and reference elements are formed from either magnetic tunnel junctions or giant magnetoresistive materials. The sensitivity of the reference and sensor elements is controlled through one or a combination of magnetic bias, exchange bias, shielding, or shape anisotropy. Moreover, the bridge output is tuned by setting the ratio of the reference and sensor arm resistance values to a predetermined ratio that optimizes the bridge output for offset and symmetry. The single-chip referenced-bridge magnetic field sensor of the present invention exhibits excellent temperature stability, low offset voltage, and excellent voltage symmetry. | 2014-02-27 |
20140054734 | METHOD FOR PRODUCING A SEMICONDUCTOR ELEMENT OF A DIRECT-CONVERTING X-RAY DETECTOR - A production method of a semiconductor element of a direct-converting x-ray detector is disclosed, wherein at least one intermediate layer is applied to a semiconductor layer and at least one contact layer is applied to an exposed intermediate layer by chemically currentless deposition of a contact material from a solution in each instance. The materials for the individual layers are selected such that the electrochemical potential of the materials of the at least one intermediate layer is greater than the electrochemical potential of at least one element of the semiconductor layer and the electrochemical potential of the contact material of the contract layer is greater than the electrochemical potential of the materials of the intermediate layers. Semiconductor elements produced in accordance with the method, an x-ray detector with semiconductor elements, an x-ray system with an x-ray detector and also a CT system with an x-ray detector are also disclosed. | 2014-02-27 |
20140054735 | PHOTOELECTRIC CONVERSION MODULE - A photoelectric conversion module is disclosed. In one aspect, the photoelectric conversion module includes 1) first and second conductive substrates facing each other and 2) first and second grid electrodes formed between and respectively electrically connected to the first and second conductive substrates. The photoelectric conversion module also includes a first isolation electrode interposed between and contacting the first conductive substrate and the second grid electrode. The second grid electrode may have a top surface that tightly contacts the first isolation electrode so as to substantially prevent an electrolyte from permeating between the top surface of the second grid electrode and the first isolation electrode. | 2014-02-27 |
20140054736 | METHOD AND APPARATUS FOR REDUCING SIGNAL LOSS IN A PHOTO DETECTOR - Photonic structures and methods of formation are disclosed in which a photo detector interface having crystalline misfit dislocations is displaced with respect to a waveguide core to reduce effects of dark current on a detected optical signal. | 2014-02-27 |
20140054737 | SOLID-STATE IMAGING DEVICE AND METHOD FOR FABRICATING THE SAME - A solid-state imaging device includes: a substrate; an insulator layer formed on the substrate; a semiconductor layer formed on the insulator layer; and a silicon layer formed on the semiconductor layer. The silicon layer includes a plurality of pixels each including a photoelectric converter configured to convert light into signal charge, and a circuit configured to read the signal charge, and a refractive index of the insulator layer is lower than a refractive index of the semiconductor layer. | 2014-02-27 |
20140054738 | CURABLE RESIN COMPOSITION, OPTICAL MEMBER SET, METHOD OF PRODUCING THE SAME, AND SOLID STATE IMAGING DEVICE USING THE SAME - A curable resin composition, for forming a first optical member of an optical member set, the optical member having the first optical member and a second optical member covered with the first optical member, the first optical member being formed by curing a siloxane resin, comprising: a siloxane resin, a surfactant, and a solvent, the siloxane resin and the surfactant being contained in the solvent, the surfactant having a polyoxyalkylene structure, the siloxane resin being defined in 65% by mass to 100% by mass thereof having a particular polysilsesquioxane structure. | 2014-02-27 |
20140054739 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - There is provided a semiconductor device including a substrate made from a semiconductor material, and layers that are made from plural kinds of materials and formed over the substrate. An opening portion that is formed to penetrate at least a layer formed as an insulating film among the layers formed over the substrate and expose a surface of an electrode pad is filled with aluminum or an aluminum alloy. | 2014-02-27 |
20140054740 | CMOS BOLOMETER - A method of manufacturing a semiconductor device includes forming at least one sacrificial layer on a substrate during a complementary metal-oxide-semiconductor (CMOS) process. An absorber layer is deposited on top of the at least one sacrificial layer. A portion of the at least one sacrificial layer beneath the absorber layer is removed to form a gap over which a portion of the absorber layer is suspended. The sacrificial layer can be an oxide of the CMOS process with the oxide being removed to form the gap using a selective hydrofluoric acid vapor dry etch release process. The sacrificial layer can also be a polymer layer with the polymer layer being removed to form the gap using an O | 2014-02-27 |
20140054741 | POWER SEMICONDUCTOR DEVICES, METHODS, AND STRUCTURES WITH EMBEDDED DIELECTRIC LAYERS CONTAINING PERMANENT CHARGES - Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region. | 2014-02-27 |
20140054742 | Semiconductor Structure - Various embodiments provide a semiconductor structure. The semiconductor structure may include a semiconductor substrate; a via extending through the semiconductor substrate; and a capacitive structure surrounding at least a portion of the via. The capacitive structure may include a metal layer formed on the semiconductor substrate. | 2014-02-27 |
20140054743 | Isolated Through Silicon Vias in RF Technologies - Disclosed are a structure for providing electrical isolation in a semiconductor substrate and an associated method for the structure's fabrication. The structure includes a deep trench isolation loop having a first depth disposed in the semiconductor substrate. A dielectric material is disposed in the deep trench isolation loop and one or more through silicon vias (TSVs), having a second depth, are disposed in the semiconductor substrate and within a perimeter of the deep trench isolation loop. A portion of the semiconductor substrate surrounding the deep trench isolation loop may be doped. A metallic filler may be disposed within the one or more TSVs and the metallic filler may be in direct electrical contact with the semiconductor substrate. | 2014-02-27 |
20140054744 | Isolation Structure Profile for Gap Filing - An trench isolation structure and method for manufacturing the trench isolation structure are disclosed. An exemplary trench isolation structure includes a first portion and a second portion. The first portion extends from a surface of a semiconductor substrate to a first depth in the semiconductor substrate, and has a width that tapers from a first width at the surface of the semiconductor substrate to a second width at the first depth, the first width being greater than the second width. The second portion extends from the first depth to a second depth in the semiconductor substrate, and has substantially the second width from the first depth to the second depth. | 2014-02-27 |
20140054745 | MEMORY CELL SUPPORT LATTICE - Memory cell support lattices and methods of forming the same are described herein. As an example, a method of forming a memory cell support lattice includes forming a mask on a number of capacitor elements in an array, such that a space between vertically and horizontally adjacent capacitor elements is fully covered and a space between diagonally adjacent capacitor elements is partially covered and forming a support lattice in a support material by etching the support material to remove portions of the support material below the openings in the mask. | 2014-02-27 |
20140054746 | RESISTANCE STRUCTURE, INTEGRATED CIRCUIT, AND METHOD OF FABRICATING RESISTANCE STRUCTURE - A resistance structure including: a conductive layer provided at a surface layer portion of a semiconductor substrate; a first resistance element having long sides and short sides provided over the conductive layer with an insulating film interposed; a second resistance element having long sides and short sides provided over the conductive layer with the insulating film interposed and disposed such that one long side thereof opposes one long side of the first resistance element; first wiring that is connected to one end of the first resistance element; second wiring that is connected to one end of the second resistance element; third wiring that connects the other end of the first resistance element with the other end of the second resistance element; and a connection portion that connects any of the first wiring, the second wiring and the third wiring with the conductive layer. | 2014-02-27 |
20140054747 | BIPOLAR TRANSISTOR - A bipolar transistor having an upper surface, comprises a multilevel collector structure formed in a base region of opposite conductivity type and having a first part of a first vertical extent coupled to a collector contact, an adjacent second part having a second vertical extent a third part of a third vertical extent and desirably of a depth different from a depth of the second part, coupled to the second part by a fourth part desirably having a fourth vertical extent less than the third vertical extent. A first base region portion overlies the second part, a second base region portion separates the third part from an overlying base contact region, and other base region portions laterally surround and underlie the multilevel collector structure. An emitter proximate the upper surface is laterally spaced from the multilevel collector structure. This combination provides improved gain, Early Voltage and breakdown voltages. | 2014-02-27 |
20140054748 | EDGE TRIMMING METHOD FOR SEMICONDUCTOR WAFER AND SEMICONDUCTOR WAFER HAVING TRIMMED EDGE - An edge trimming method includes providing a semiconductor wafer having a front side and a backside, trimming an edge of a periphery of the semiconductor wafer from the front side to form at least a notch region around the periphery of the front side of the semiconductor wafer, and providing the front side of the semiconductor wafer to a handle wafer. The notch region comprises a first wall and a second wall, and the first and the second wall are perpendicular to each other. | 2014-02-27 |
20140054749 | SEMICONDUCTOR DEVICE - The present invention provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Dummy vias are formed in each layer on a dicing region side. The dummy vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the dummy vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented. | 2014-02-27 |
20140054750 | Scribe line structure for wafer dicing and method of making the same - A scribe line structure between die regions is disclosed. The scribe line structure includes a dielectric layer disposed on a substrate; and a plurality of metal structures arranged up-and-down in the dielectric layer on the substrate, the plurality of metal structures comprising metal layers and metal vias, wherein the metal vias are disposed on the dicing path and regions outside the dicing path and the metal vias on the dicing path have a lower metal density than the metal vias not on the dicing path. | 2014-02-27 |
20140054751 | SEMICONDUCTOR DEVICE - A semiconductor device comprises: a semiconductor package having a top surface, a bottom surface, and a through hole provided from the top surface to the bottom surface; and an electrode inserted into the through hole of the semiconductor package. The semiconductor package includes: an insulating substrate; a semiconductor chip on the insulating substrate; an electrode pattern on the insulating substrate and connected to the semiconductor chip; a resin sealing the insulating substrate, the semiconductor chip, and the electrode pattern; and an electrode section on an inner wall of the through hole and connected to the electrode pattern. The through hole penetrates the insulating substrate and the resin. The electrode inserted into the through hole is connected to the electrode section inside the semiconductor package. | 2014-02-27 |
20140054752 | SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF - A semiconductor memory device and a fabrication method thereof capable of improving electric contact characteristic between an access device and a lower electrode are provided. The semiconductor memory device includes an access device formed in a pillar shape on a semiconductor substrate, a first conductive layer formed over the access device, a protection layer formed on an edge of the first conductive layer to a predetermined thickness, and a lower electrode connected to the first conductive layer. | 2014-02-27 |
20140054753 | NANO-MESHED STRUCTURE PATTERN ON SAPPHIRE SUBSTRATE BY METAL SELF-ARRANGEMENT - The present disclosure provides a nano-meshed patterned substrate and a method of forming the same. In an embodiment, a metal layer is formed on a substrate, and a heat treatment is performed on the substrate and the metal layer so that the metal layer is transformed into a nano-meshed metal structure. The substrate is then etched using the nano-meshed metal structure as an etch mask. After removing the nano-meshed metal structure, a nano-meshed patterned substrate is obtained. | 2014-02-27 |
20140054754 | OPTICALLY REACTIVE MASKING - Systems and methods are presented for filling an opening with material of a high integrity. A material having properties in a first physical state suitable for formation of a hard mask layer and in a second physical state having properties facilitating removal of the former hard mask layer is utilized. Utilizing the material as a mask layer and subsequently removing the material enables a number of mask layers to be minimized in a subsequent filling operation (e.g., metallization). Material amenable to being in a first physical state and a second physical state is an optically reactive material. The optically reactive dielectric can comprise an element or compound which can act as an agent/catalyst in the optical conversion process along with any element or compound which can act as an accelerator for the optical reaction. Conversion can be brought about by exposure to electromagnetic radiation and/or application of thermal energy. | 2014-02-27 |
20140054755 | METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES, AND RELATED SEMICONDUCTOR DEVICE STRUCTURES - A method of forming a semiconductor device structure comprises forming at least one reflective structure comprising at least two dielectric materials having different refractive indices over at least one radiation-sensitive structure, the at least one reflective structure configured to substantially reflect therefrom radiation within a predetermined wavelength range and to substantially transmit therethrough radiation within a different predetermined wavelength range. Additional methods of forming a semiconductor device structure are described. Semiconductor device structures are also described. | 2014-02-27 |
20140054756 | ANTI SPACER PROCESS AND SEMICONDUCTOR STRUCTURE GENERATED BY THE ANTI SPACER PROCESS - An anti spacer process, which comprises: (a) providing a resist layer including a non-uniform shape; (b) coating a target layer above the resist layer; (c) providing anti spacer trenches (spa) between the target layer and the resist layer; and (d) connecting at least part of the anti spacer trenches (spa) together to isolate a first part of the target layer and a second part of the target layer. | 2014-02-27 |
20140054757 | SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device which can reduce a heat stress to a solder layer while suppressing an increase of thermal resistance is provided. | 2014-02-27 |
20140054758 | STACKED DUAL CHIP PACKAGE HAVING LEVELING PROJECTIONS - The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication. | 2014-02-27 |
20140054759 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented. | 2014-02-27 |
20140054760 | PACKAGE-ON-PACKAGE SEMICONDUCTOR DEVICE - A semiconductor device and method of forming the semiconductor device, the semiconductor device includes a package having at least one first die and at least one second die. The semiconductor device further includes a set of conductive elements electrically connecting the at least one first and the at least one second die to a substrate. The semiconductor device further includes a thermal contact pad between the at least one first die and the at least one second die, to thermally isolate the at least one first die from the at least one second die. | 2014-02-27 |
20140054761 | On-Chip Heat Spreader - A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader. | 2014-02-27 |
20140054762 | SEMICONDUCTOR MODULE COOLER - A semiconductor module cooler supplies a cooling medium to a cooling medium jacket from outside to cool a plurality of semiconductor elements thermally connected to the cooling medium jacket through a heat sink. The cooling medium jacket has a cooling fin cooling room including an opening for inserting cooling fins, and cooling the cooling fins; a cooling medium introduction port to introduce the cooling medium; a cooling medium diffusion room to diffuse and supply the cooling medium to the cooling fin cooling room; a cooling medium diffusion wall provided in the cooling medium diffusion room in which the cooling medium diffused by the cooling medium diffusion room flows over to be introduced to the cooling fin cooling room side; a cooling medium discharge port discharging the cooling medium to the outside; and a cooling medium convergence room provided between the cooling fin cooling room and the cooling medium discharge port. | 2014-02-27 |
20140054763 | THIN WAFER HANDLING AND KNOWN GOOD DIE TEST METHOD - A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate. | 2014-02-27 |
20140054764 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a semiconductor substrate, a contact pad overlying the semiconductor substrate, an interconnect layer overlying the contact pad, a passivation layer formed between the contact pad and the interconnect layer, a bump overlying the interconnect layer, and a protection layer overlying the interconnect layer and the passivation layer and covering a lower portion of the bump. The protection layer includes a curved surface region. | 2014-02-27 |
20140054765 | DRIVING CHIP AND METHOD OF MANUFACTURING THE SAME - A driving chip and a method of manufacturing the driving chip are disclosed. In one aspect, the method includes forming an inside metal portion of a connection terminal on a base element by patterning a first metal layer; forming a first insulating layer on the inside metal portion of the connection terminal; forming an inside metal portion of a dummy terminal on the first insulating layer by patterning a second metal layer; and forming a bump portion on the inside metal portion of the connection terminal and on a second metal portion of the dummy terminal. The driving chip may suppress warp transformation or pressure mark of the driving chip and thus, the reliability of the driving chip may be improved. | 2014-02-27 |
20140054766 | LEAD-FREE SOLDER BUMP BONDING STRUCTURE - According to a lead-free solder bump bonding structure, by causing the interface (IMC interface) of the intermetallic compound layer at a lead-free-solder-bump side to have scallop shapes of equal to or less than 0.02 [portions/μm] without forming in advance an Ni layer as a barrier layer on the surfaces of respective Cu electrodes of first and second electronic components like conventional technologies, a Cu diffusion can be inhibited, thereby inhibiting an occurrence of an electromigration. Hence, the burden at the time of manufacturing can be reduced by what corresponds to an omission of the formation process of the Ni layer as a barrier layer on the Cu electrode surfaces, and thus a lead-free solder bump bonding structure can be provided which reduces a burden at the time of manufacturing in comparison with conventional technologies and which can inhibit an occurrence of an electromigration. | 2014-02-27 |
20140054767 | TERMINAL STRUCTURE AND SEMICONDUCTOR DEVICE - The present invention relates to a terminal structure comprising; a base material | 2014-02-27 |
20140054768 | TERMINAL STRUCTURE AND SEMICONDUCTOR DEVICE - The present invention relates to a terminal structure comprising: a base material | 2014-02-27 |
20140054769 | TERMINAL STRUCTURE, AND SEMICONDUCTOR ELEMENT AND MODULE SUBSTRATE COMPRISING THE SAME - A preferred terminal structure comprises a base material; an electrode formed on the base material; an insulating covering layer formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under bump metal layer containing Ni, filling the opening on the electrode; and a dome-shaped bump containing Sn and Ti, covering the under bump metal layer, wherein at least part of the under bump metal layer has a portion sandwiched between the external electrode and the insulating covering layer. | 2014-02-27 |
20140054770 | TERMINAL STRUCTURE, AND SEMICONDUCTOR ELEMENT AND MODULE SUBSTRATE COMPRISING THE SAME - A preferred terminal structure comprises a base material; an electrode formed on the base material; an insulating covering layer formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under bump metal layer containing Ni, formed in a region in the opening on the electrode so that an upper surface of the metal layer is at a position lower than an upper surface of the insulating covering layer in a peripheral edge portion of the opening; and a dome-shaped bump containing Sn and Ti, formed in a region in the opening on the under bump metal layer, wherein an end portion of a boundary between the under bump metal layer and the bump is in contact with an inner wall of the opening portion in the insulating covering layer. | 2014-02-27 |
20140054771 | Method for Self-Assembly of Substrates and Devices Obtained Thereof - A method for defining regions with different surface liquid tension properties on a substrate is disclosed. The method includes: providing a substrate with a main surface having a first surface liquid tension property that is at least partially covered with a seed layer; forming at least one micro-bump on the seed layer leaving part of the seed layer exposed; patterning the exposed seed layer to expose part of the main surface; forming at least one closed-loop structure that encloses a region of the main surface and the at least one micro-bump; and chemically treating the main surface of the substrate to provide on a surface of at least one closed-loop structure and the at least one micro-bump a second surface liquid tension property. The second surface liquid tension property is substantially different from the first surface liquid tension property of the main surface and is liquid phobic. | 2014-02-27 |
20140054772 | SEMICONDUCTOR PACKAGES INCLUDING THROUGH ELECTRODES AND METHODS OF MANUFACTURING THE SAME - A semiconductor package includes a substrate and a plurality of semiconductor chips stacked on the substrate. Each of the semiconductor chips has a front surface, a rear surface opposite to the front surface, a sidewall surface connecting the front surface to the rear surface, a vertical through electrode extending from the front surface toward the rear surface with a predetermined depth, and a horizontal through electrode laterally extending from the sidewall surface to be connected to the vertical through electrode. At least one connection member is disposed on the sidewall surfaces of the semiconductor chips to connect the horizontal through electrodes of the semiconductor chips to each other. Related methods are also provided. | 2014-02-27 |
20140054773 | ELECTRONIC COMPONENT BUILT-IN SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - An electronic component built-in substrate, includes a lower wiring substrate, an electronic component mounted on the lower wiring substrate, an intermediate wiring substrate including an opening portion in which the electronic component is mounted, and arranged in a periphery of the electronic component, and connected to the lower wiring substrate via a first conductive ball, an upper wiring substrate arranged over the electronic component and the intermediate wiring substrate, and connected to the intermediate wiring substrate via a second conductive ball, and a resin filled into respective areas between the lower wiring substrate, the intermediate wiring substrate, and the upper wiring substrate, and sealing the electronic component, wherein the first conductive ball and the second conductive ball are arranged in displaced positions mutually. | 2014-02-27 |
20140054774 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A first through hole | 2014-02-27 |
20140054775 | SEMICONDUCTOR DEVICES INCLUDING METAL-SILICON-NITRIDE PATTERNS AND METHODS OF FORMING THE SAME - A semiconductor memory device can include a first conductive line crossing over a field isolation region and crossing over an active region of the device, where the first conductive line can include a first conductive pattern being doped, a second conductive pattern, and a metal-silicon-nitride pattern between the first and second conductive patterns and can be configured to provide a contact at a lower boundary of the metal-silicon-nitride pattern with the first conductive pattern and configured to provide a diffusion barrier at an upper boundary of the metal-silicon-nitride pattern with the second conductive pattern. | 2014-02-27 |
20140054776 | METHODS, DEVICES, AND MATERIALS FOR METALLIZATION - A method of making an electronic device which in one embodiment comprises providing a substrate, electrolessly depositing a barrier metal at least on portions of the substrate, and using wet chemistry such as electroless deposition to deposit a substantially gold-free wetting layer having solder wettability onto the barrier metal. An electronic device which in one embodiment comprises a metallization stack. The metallization stack comprises a barrier metal deposited electrolessly and a substantially gold-free wetting layer deposited on the barrier metal, and the wetting layer is wettable by solder. | 2014-02-27 |
20140054777 | SEMICONDUCTOR DEVICE WITH COPPER WIREBOND SITES AND METHODS OF MAKING SAME - Semiconductor devices with external wirebond sites that include copper and methods for fabricating such semiconductor devices are disclosed. One embodiment of a method for fabricating a semiconductor device comprises forming a dielectric layer on an active side of a semiconductor substrate. The dielectric layer has openings aligned with corresponding wirebond sites at the active side of the substrate. The method further includes forming a plurality of wirebond sites located at the openings in the dielectric layer. The wirebond sites are electrically coupled to an integrated circuit in the semiconductor substrate and electrically isolated from each other. Individual wirebond sites are formed by electrolessly depositing nickel into the openings and forming a wirebond film on the nickel without forming a seam between the nickel and the dielectric layer. | 2014-02-27 |
20140054778 | SEMICONDUCTOR DEVICE HAVING A COPPER PLUG - Disclosed is a semiconductor device wherein an insulation layer has a via opening with an aluminum layer in the via opening and in contact with the last wiring layer of the device. There is a barrier layer on the aluminum layer followed by a copper plug which fills the via opening. Also disclosed is a process for making the semiconductor device. | 2014-02-27 |
20140054779 | Semiconductor Having a High Aspect Ratio Via - The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer. | 2014-02-27 |
20140054780 | Method for Manufacturing an Electronic Module and an Electronic Module - A number of semiconductor chips each include a first main face and a second main face opposite from the first main face. The second main face includes at least one electrical contact element. The semiconductor chips are placed on a carrier. A material layer is applied into intermediate spaces between adjacent semiconductor chips. The carrier is removed and a first electrical contact layer is applied to the first main faces of the semiconductor chips so that the electrical contact layer is electrically connected with each one of the electrical contact elements. | 2014-02-27 |
20140054781 | Copper Ball Bond Features and Structure - An integrated circuit wire bond connection is provided having an aluminum bond pad ( | 2014-02-27 |
20140054782 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device according to an embodiment, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a high melting metal film on a side wall and a bottom surface of the opening; forming a seed film of copper (Cu) on the high melting metal film; performing nitriding process after the seed film is formed; and performing electroplating process, in which a Cu film is buried in the opening while energizing the seed film after performing nitriding process. | 2014-02-27 |
20140054783 | STACKED MICROELECTRONIC PACKAGES HAVING SIDEWALL CONDUCTORS AND METHODS FOR THE FABRICATION THEREOF - Methods for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging a plurality of microelectronic device panels in a panel stack. Each microelectronic device panel contains plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are created in the panel stack exposing the plurality of package edge conductors, and a plurality of sidewall conductors is formed interconnecting different ones of the package edge conductors exposed through the trenches. The panel stack is then separated into a plurality of stacked microelectronic packages each including at least two microelectronic devices electrically interconnected by at least one of the plurality of sidewall conductors included within the stacked microelectronic package. | 2014-02-27 |
20140054784 | Integrated Circuit Connector Access Region and Method for Making - A connector access region of an integrated circuit device includes a set of parallel conductors, extending in a first direction, and interlayer connectors. The conductors comprise a set of electrically conductive contact areas on different conductors which define a contact plane with the conductors extending below the contact plane. A set of the contact areas define a line at an oblique angle, such as less than 45° or 5° to 27°, to the first direction. The interlayer connectors are in electrical contact with the contact areas and extend above the contact plane. At least some of the interlayer connectors overlie but are electrically isolated from the electrical conductors adjacent to the contact areas with which the interlayer connectors are in electrical contact. The set of parallel conductors may include a set of electrically conductive layers with the contact plane being generally perpendicular to the electrically conductive layers. | 2014-02-27 |
20140054785 | CHIP PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING SAME - A chip package structure includes a first wiring layer, a first solder mask layer, a chip and a plurality of third contact pads. The third contact pads are formed on the first wiring layer. The third contact pads and the first wiring layer are unitarily formed. The first solder mask layer is formed on the first wiring layer. The first solder mask layer defines a plurality of first openings to expose portions of the first wiring layers. The portions of the first wiring layers exposed to the first openings serve as first contact pads. The chip is mounted on the first solder mask layer and is electrically connected to the first contact pads. This disclosure further relates to a method of manufacturing the chip package structure. | 2014-02-27 |
20140054786 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess. | 2014-02-27 |
20140054787 | METHODS OF FORMING A STACK OF ELECTRODES AND THREE-DIMENSIONAL SEMICONDUCTOR DEVICES FABRICATED THEREBY - Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other. | 2014-02-27 |
20140054788 | METHOD FOR FABRICATING NANOGAP ELECTRODES, NANOGAP ELECTRODES ARRAY, AND NANODEVICE WITH THE SAME - A substrate | 2014-02-27 |
20140054789 | Multi-Level Vertical Plug Formation With Stop Layers of Increasing Thicknesses - A method is provided for use with an IC device including a stack including a plurality of conductive layers interleaved with a plurality of dielectric layers, for forming interlayer connectors extending from a connector surface to respective conductive layers. The method forms landing areas on the plurality of conductive layers in the stack. The landing areas are without overlying conductive layers in the stack. The method forms etch stop layers over corresponding landing areas. The etch stop layers have thicknesses that correlate with depths of the corresponding landing areas. The method fills over the landing areas and the etch stop layers with a dielectric fill material. Using a patterned etching process, the method forms a plurality of vias extending through the dielectric fill material and the etch stop layers to the landing areas in the plurality of conductive layers. | 2014-02-27 |
20140054790 | THREE-DIMENSIONAL INTEGRTED CIRCUIT STRUCTURE AND METHOD OF ALUMINUM NITRIDE INTERPOSER SUBSTRATE - A three-dimensional integrateds circuit structure includes a first metal circuit substrate, an interposer substrate disposed on the first metal circuit substrate and electrically connected therewith, and at least one semiconductor component disposed on the interposer substrate. The interposer substrate is used to dissipate the heat generated by the operation of the semiconductor components, so as to achieve the objective of increasing the lifespan of the semiconductor components. | 2014-02-27 |
20140054791 | THROUGH SILICON VIA PACKAGING STRUCTURES AND FABRICATION METHOD - A method is provided for fabricating a through silicon via packaging structure. The method includes providing a first type substrate, and forming a second type substrate deferent from the first type substrate on the first type substrate. The method also includes forming a semiconductor device on a first surface of the second type substrate, and forming an interlayer dielectric layer on the first surface of the second type substrate. Further, the method includes forming a metal interconnection structure in the interlayer dielectric layer, and forming a through silicon via structure perforating the second type substrate and electrically connecting with the metal interconnection structure. Further, the method also includes removing the first type substrate using a gas etching process or a wet etching process to expose a second surface of the second type substrate and a bottom surface of the through silicon via structure. | 2014-02-27 |
20140054792 | PACKAGE ASSEMBLY AND METHOD OF MANUFACTURING THE SAME - A package assembly includes a substrate, an electronic component, and an encapsulation body. The electronic component is located on the substrate and electrically connected to the substrate. The encapsulation body encapsulates the electronic component with the substrate. A portion of the substrate corresponding to the electronic component defines a plurality of through holes. A diameter of each of the plurality of through holes gradually reduces from a top surface of the substrate toward a bottom surface of the substrate. The plurality of through holes prevent melting remnants of the encapsulation body from flowing outside of the substrate. | 2014-02-27 |
20140054793 | Chip on Film (COF) Substrate, COF Package and Display Device Including the Same - A COF substrate may include a base film, first upper conductive patterns, at least one second upper conductive pattern and lower conductive patterns. The first upper conductive patterns may be arranged on an upper surface of the base film. Each of the first upper conductive patterns may have an inner pattern and an outer pattern spaced apart from each other. The second upper conductive pattern may be arranged on the upper surface of the base film between the first upper conductive patterns. The lower conductive patterns may be arranged on a lower surface of the base film. The lower conductive patterns may be electrically connected between the inner pattern and the outer pattern. Thus, conductive materials causing a short between the panel patterns may not exist between the inner pattern and the outer pattern on the upper surface of the base film. | 2014-02-27 |
20140054794 | MEMORY PROCESS AND MEMORY STRUCTURE MADE THEREBY - A memory process is described. A substrate is provided, having therein trenches and conductive lines buried in the trenches and having thereon an array area, wherein each of the conductive lines has an array portion in the array area. A contact area apart from the array area is defined on the substrate, wherein each of the conductive lines has a contact portion in the contact area. The substrate between the contact portions of the conductive lines is etched down to below the tops of the conductive layers to form gaps between the contact portions of the conductive lines. The gaps are then filled with an insulating layer. | 2014-02-27 |
20140054795 | Electronic Assembly With Three Dimensional Inkjet Printed Traces - One method of making an electronic assembly includes mounting one electrical substrate on another electrical substrate with a face surface on the one substrate oriented transversely of a face surface of the other substrate. The method also includes inkjet printing on the face surfaces a conductive trace that connects an electrical contact on the one substrate with an electrical connector on the other substrate. An electronic assembly may include a first substrate having a generally flat surface with a first plurality of electrical contacts thereon; a second substrate having a generally flat surface with a second plurality of electrical contacts thereon, the surface of the second substrate extending transversely of the surface of said first substrate; and at least one continuous conductive ink trace electrically connecting at least one of the first plurality of electrical contacts with at least one of the second plurality of electrical contacts. | 2014-02-27 |
20140054796 | STACKED MICROELECTRONIC PACKAGES HAVING PATTERENED SIDEWALL CONDUCTORS AND METHODS FOR THE FABRICATION THEREOF - Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package. | 2014-02-27 |
20140054797 | STACKED MICROELECTRONIC PACKAGES HAVING SIDEWALL CONDUCTORS AND METHODS FOR THE FABRICATION THEREOF - Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors. | 2014-02-27 |
20140054798 | SENSOR PACKAGES AND METHOD OF PACKAGING DIES OF DIFFERING SIZES | 2014-02-27 |
20140054799 | Three-Dimensional Multichip Module - A three-dimensional multichip module includes a first integrated circuit chip having at least one first high-temperature functional area and one first low-temperature functional area, and at least one second integrated circuit chip having a second high-temperature functional area and a second low-temperature functional area. The second high-temperature functional area is arranged opposite the first low-temperature functional area. As an alternative, at least one low-temperature chip having only one low-temperature functional area can also be arranged between the first and second chips. | 2014-02-27 |
20140054800 | METHOD FOR MANUFACTURING A METAL PAD STRUCTURE OF A DIE, A METHOD FOR MANUFACTURING A BOND PAD OF A CHIP, A DIE ARRANGEMENT AND A CHIP ARRANGEMENT - A method for manufacturing a metal pad structure of a die is provided, the method including: forming a metal pad between encapsulation material of the die, wherein the metal pad and the encapsulation material are separated from each other by a gap; and forming additional material in the gap to narrow at least a part of the gap. | 2014-02-27 |
20140054801 | ELECTRONIC DEVICE - An electronic device includes a core circuit and multiple pad units. The core circuit includes multiple core MOS and the multiple pad units are respectively electrically connected to the core circuit. Each pad unit includes at least one pad MOS. A core gate in each core MOS and a pad gate in each pad MOS extend along the same direction or extend parallel with each other. | 2014-02-27 |
20140054802 | Semiconductor Device and Method of Forming RDL Using UV-Cured Conductive Ink Over Wafer Level Package - A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A patterned trench is formed in the first insulating layer. A conductive ink is deposited in the patterned trench by disposing a stencil over the first insulating layer with an opening aligned with the patterned trench and depositing the conductive ink through the opening in the stencil into the patterned trench. | 2014-02-27 |
20140054803 | COMPOUND BARRIER LAYER, METHOD FOR FORMING THE SAME AND PACKAGE STRUCTURE USING THE SAME - An embodiment of the invention provides a compound barrier layer, including: a first barrier layer disposed on a substrate; and a second barrier layer disposed on the first barrier layer, wherein the first barrier layer and second barrier layer both include a plurality of alternately arranged inorganic material regions and organo-silicon material regions and the inorganic material regions and the organo-silicon material regions of the first barrier layer and second barrier layer are alternatively stacked vertically. | 2014-02-27 |
20140054804 | MEMBRANE HUMIDIFIER FOR A FUEL CELL - The present disclosure provides a membrane humidifier for a fuel cell including: a case; a hollow fiber membrane module covering the case; a housing coupled to both ends of the hollow fiber membrane module; a plurality of hollow fiber membranes arranged in the case; and a hollow fiber membrane guide structure installed at one end or both ends of the hollow fiber membrane module and having a potting material layer formed therein to fix the plurality of hollow fiber membranes. | 2014-02-27 |
20140054805 | DEVICES AND PROCESSES FOR FABRICATING MULTI-COMPONENT OPTICAL SYSTEMS - The present disclosure relates to devices and processes for fabricating a multi-component optical system. A device is an integral mold comprising an attachment portion and a cup portion having a cavity, and the mold further comprises a first optical component. The cavity of the mold contains additional optical components to form a multi-component optical system blank. Another device is a multi-component optical system blank. A process for fabricating a multi-component optical system blank comprises providing an integral mold comprising a first optical component, adding at least a second optical component, shaping the mold after addition of an optical component, and shaping the resultant blank into an optical system. A further device is a multi-component optical system produced in a process disclosed herein. | 2014-02-27 |
20140054806 | METHOD FOR DECORATING PLASTIC PACKAGE - In a method for decorating a plastic package, on at least a part of a surface of the plastic package, portions which are different in optical characteristics from the surface are periodically arranged to decorate the surface. | 2014-02-27 |
20140054807 | Methods For Forming A Lens Plate For An Integrated Camera Using UV-Transparent Molds And Methods For Forming UV-Transparent Molds - Suspended lenses in a spacer wafer and lens-in-a-pocket structures are replicated from UV-transparent molds. The fabrication of UV-transparent molds can include providing a substrate with pedestals, fabricating a lens on each pedestal using a step-and-repeat process, replicating an intermediate mold from the substrate with pedestals having lenses on the pedestals, and replicating a UV-transparent mold from the intermediate mold. The fabrication of UV-transparent molds can also include providing a substrate with holes, fabricating a lens in each hole and replicating a UV-transparent mold from the substrate with the holes having the lenses. | 2014-02-27 |
20140054808 | METHOD FOR PRODUCTION OF PARTICLES OF PHARMACEUTICAL SUBSTANCES AND THE USE THEREOF - The invention relates to a method for producing particles with a length-width ratio of less than about 1.4 from a pharmaceutical substance, which method includes the following stages, that is: (a) provision of a melt of the pharmaceutical substance; (b) production of droplets of the melt by spraying into a processing chamber; (c) repeated guiding of solid particles past sprayed droplets in the processing chamber with the aid of a process gas jet which is guided in a defined way and whose temperature is fixed, depending on the solidification point of the melt, so that at least some of the droplets come into contact with particles and solidify thereon; (d) removal of particles from the processing chamber as a function of the particle size. The invention further relates to particles of pharmaceutical substances and the use thereof. | 2014-02-27 |