09th week of 2020 patent applcation highlights part 66 |
Patent application number | Title | Published |
20200066573 | DUAL-DEPTH STI CAVITY EXTENSION AND METHOD OF PRODUCTION THEREOF | 2020-02-27 |
20200066574 | ENGINEERED SUBSTRATE STRUCTURE AND METHOD OF MANUFACTURE | 2020-02-27 |
20200066575 | Single Trench Damascene Interconnect Using TiN HMO | 2020-02-27 |
20200066576 | REDUCING CONTACT RESISTANCE IN VIAS FOR COPPER INTERCONNECTS | 2020-02-27 |
20200066577 | VIA CLEANING TO REDUCE RESISTANCE | 2020-02-27 |
20200066578 | CONDUCTIVE PATTERNS, SEMICONDUCTOR DEVICES COMPRISING THE CONDUCTIVE PATTERNS, AND RELATED METHODS AND SYSTEMS | 2020-02-27 |
20200066579 | Power Semiconductor Device with Reliably Verifiable p-contact and Method | 2020-02-27 |
20200066580 | INTEGRATED CIRCUIT AND FABRICATION METHOD THEREOF | 2020-02-27 |
20200066581 | Metal-Based Etch-Stop Layer | 2020-02-27 |
20200066582 | SEMICONDUCTOR PACKAGE DEVICE WITH INTEGRATED ANTENNA AND MANUFACTURING METHOD THEREOF | 2020-02-27 |
20200066583 | DUAL SILICIDE LINER FLOW FOR ENABLING LOW CONTACT RESISTANCE | 2020-02-27 |
20200066584 | INTEGRATED CIRCUIT (IC) STRUCTURE FOR HIGH PERFORMANCE AND FUNCTIONAL DENSITY | 2020-02-27 |
20200066585 | INTERCONNECTS FORMED BY A METAL DISPLACEMENT REACTION | 2020-02-27 |
20200066586 | CONTROLLING BACK-END-OF-LINE DIMENSIONS OF SEMICONDUCTOR DEVICES | 2020-02-27 |
20200066587 | SEMICONDUCTOR DEVICE WITH AN INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME | 2020-02-27 |
20200066588 | METHODS, APPARATUS, AND MANUFACTURING SYSTEM FOR SELF-ALIGNED PATTERNING OF CONTACTS IN A SEMICONDUCTOR DEVICE | 2020-02-27 |
20200066589 | CATERPILLAR TRENCHES FOR EFFICIENT WAFER DICING | 2020-02-27 |
20200066590 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | 2020-02-27 |
20200066591 | CATERPILLAR TRENCHES FOR EFFICIENT WAFER DICING | 2020-02-27 |
20200066592 | SEMICONDUCTOR SUBSTRATE DIE SAWING SINGULATION SYSTEMS AND METHODS | 2020-02-27 |
20200066593 | DEVICE WITH HIGHLY ACTIVE ACCEPTOR DOPING AND METHOD OF PRODUCTION THEREOF | 2020-02-27 |
20200066594 | LOW THERMAL BUDGET TOP SOURCE AND DRAIN REGION FORMATION FOR VERTICAL TRANSISTORS | 2020-02-27 |
20200066595 | SEMICONDUCTOR FIN DESIGN TO MITIGATE FIN COLLAPSE | 2020-02-27 |
20200066596 | Method of Manufacture of a FinFET Device | 2020-02-27 |
20200066597 | Forming Gate Contact Over Active Free of Metal Recess | 2020-02-27 |
20200066598 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF | 2020-02-27 |
20200066599 | SELF-ALIGNED VERTICAL FIN FIELD EFFECT TRANSISTOR WITH REPLACEMENT GATE STRUCTURE | 2020-02-27 |
20200066600 | Reducing Off-State Leakage Current in Si/SiGe Dual Channel CMOS | 2020-02-27 |
20200066601 | METHOD FOR FORMING SEMICONDUCTOR DEVICE AND RESULTING DEVICE | 2020-02-27 |
20200066602 | SINGLE METALLIZATION SCHEME FOR GATE, SOURCE, AND DRAIN CONTACT INTEGRATION | 2020-02-27 |
20200066603 | REPLACEMENT METAL GATE PROCESS FOR VERTICAL TRANSPORT FIELD-EFFECT TRANSISTORS WITH MULTIPLE THRESHOLD VOLTAGES | 2020-02-27 |
20200066604 | GATE-LAST PROCESS FOR VERTICAL TRANSPORT FIELD-EFFECT TRANSISTOR | 2020-02-27 |
20200066605 | SEMICONDUCTOR SUBSTRATE MANUFACTURING METHOD | 2020-02-27 |
20200066606 | METROLOGY METHOD | 2020-02-27 |
20200066607 | SUPPRESSING INTERFACIAL REACTIONS BY VARYING THE WAFER TEMPERATURE THROUGHOUT DEPOSITION | 2020-02-27 |
20200066608 | ELECTRONIC DEVICE | 2020-02-27 |
20200066609 | RESIN ENCAPSULATED POWER SEMICONDUCTOR MODULE WITH EXPOSED TERMINAL AREAS | 2020-02-27 |
20200066610 | ELECTRONIC MODULE | 2020-02-27 |
20200066611 | SEMICONDUCTOR DEVICE | 2020-02-27 |
20200066612 | SEMICONDUCTOR DEVICE PACKAGE | 2020-02-27 |
20200066613 | FAN-OUT SEMICONDUCTOR PACKAGE | 2020-02-27 |
20200066614 | CARBON NANOTUBE-BASED THERMAL INTERFACE MATERIALS AND METHODS OF MAKING AND USING THEREOF | 2020-02-27 |
20200066615 | ELECTRONIC MODULE AND METHOD FOR THE PRODUCTION THEREOF | 2020-02-27 |
20200066616 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS | 2020-02-27 |
20200066617 | LOW CAPACITANCE THROUGH SUBSTRATE VIA STRUCTURES | 2020-02-27 |
20200066618 | PACKAGED DEVICE HAVING SELECTIVE LEAD PULLBACK FOR DIMPLE DEPTH CONTROL | 2020-02-27 |
20200066619 | SEMICONDUCTOR DEVICE | 2020-02-27 |
20200066620 | SEMICONDUCTOR DEVICE | 2020-02-27 |
20200066621 | PACKAGED INTEGRATED CIRCUIT DEVICE WITH RECESS STRUCTURE | 2020-02-27 |
20200066622 | METHODS TO INCORPORATE THIN FILM CAPACITOR SHEETS (TFC-S) IN THE BUILD-UP FILMS | 2020-02-27 |
20200066623 | WIRING SUBSTRATE, SEMICONDUCTOR PACKAGE HAVING THE WIRING SUBSTRATE, AND MANUFACTURING METHOD THEREOF | 2020-02-27 |
20200066624 | FLIP-CHIP PACKAGE SUBSTRATE AND METHOD FOR PREPARING THE SAME | 2020-02-27 |
20200066625 | REDISTRIBUTION LAYERS INCLUDING REINFORCEMENT STRUCTURES AND RELATED SEMICONDUCTOR DEVICE PACKAGES, SYSTEMS AND METHODS | 2020-02-27 |
20200066626 | POCKET STRUCTURES, MATERIALS, AND METHODS FOR INTEGRATED CIRCUIT PACKAGE SUPPORTS | 2020-02-27 |
20200066627 | MULTI-LAYER EMBEDDED MAGNETIC INDUCTOR COIL | 2020-02-27 |
20200066628 | Structures With Deformable Conductors | 2020-02-27 |
20200066629 | ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES | 2020-02-27 |
20200066630 | STRUCTURE AND METHOD OF METAL WRAPAROUND FOR LOW VIA RESISTANCE | 2020-02-27 |
20200066631 | SEMICONDUCTOR CHIP, PACKAGE STRUCTURE, AND PACAKGE-ON-PACKAGE STRUCTURE | 2020-02-27 |
20200066632 | METHOD OF FORMING A STRAIGHT VIA PROFILE WITH PRECISE CRITICAL DIMENSION CONTROL | 2020-02-27 |
20200066633 | Semiconductor Devices Employing a Barrier Layer | 2020-02-27 |
20200066634 | PACKAGE-INTEGRATED MULTI-TURN COIL EMBEDDED IN A PACKAGE MAGNETIC CORE | 2020-02-27 |
20200066635 | DUAL-MODE WIRELESS CHARGING DEVICE | 2020-02-27 |
20200066636 | E-FUSE AND MANUFACTURING METHOD THEREOF, AND MEMORY CELL | 2020-02-27 |
20200066637 | Integrated Assemblies Having Metal-Containing Regions Coupled with Semiconductor Regions | 2020-02-27 |
20200066638 | DUAL METAL-INSULATOR-SEMICONDUCTOR CONTACT STRUCTURE AND FORMULATION METHOD | 2020-02-27 |
20200066639 | SEMICONDUCTOR PACKAGE | 2020-02-27 |
20200066640 | HYBRID TECHNOLOGY 3-D DIE STACKING | 2020-02-27 |
20200066641 | RLINK - DIE TO DIE CHANNEL INTERCONNECT CONFIGURATIONS TO IMPROVE SIGNALING | 2020-02-27 |
20200066642 | INTEGRATED FAN-OUT PACKAGE AND METHOD FOR FABRICATING THE SAME | 2020-02-27 |
20200066643 | Multi-Stacked Package-on-Package Structures | 2020-02-27 |
20200066644 | EMBEDDED SUBSTRATE AND METHOD FOR MANUFACTURING EMBEDDED SUBSTRATE | 2020-02-27 |
20200066645 | MICROELECTRONIC DEVICES AND METHODS FOR ENHANCING INTERCONNECT RELIABILITY PERFORMANCE USING TUNGSTEN CONTAINING ADHESION LAYERS TO ENABLE COBALT INTERCONNECTS | 2020-02-27 |
20200066646 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 2020-02-27 |
20200066647 | SEMICONDUCTOR DEVICE | 2020-02-27 |
20200066648 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE | 2020-02-27 |
20200066649 | SELF-ALIGNED REGISTER STRUCTURE FOR BASE POLYSILICON AND PREPARATION METHOD THEREOF | 2020-02-27 |
20200066650 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE COMPRISING THE SAME | 2020-02-27 |
20200066651 | MULTIPLE RETICLE FIELD SEMICONDUCTOR DEVICES | 2020-02-27 |
20200066652 | ELECTRONICS PACKAGE INCLUDING INTEGRATED ELECTROMAGNETIC INTERFERENCE SHIELD AND METHOD OF MANUFACTURING THEREOF | 2020-02-27 |
20200066653 | CONFORMAL DUMMY DIE | 2020-02-27 |
20200066654 | STANDOFF MEMBERS FOR SEMICONDUCTOR PACKAGE | 2020-02-27 |
20200066655 | DIE BACK SIDE STRUCTURES FOR WARPAGE CONTROL | 2020-02-27 |
20200066656 | GUARD RING FOR PHOTONIC INTEGRATED CIRCUIT DIE | 2020-02-27 |
20200066657 | DIE SEAL RING AND MANUFACTURING METHOD THEREOF | 2020-02-27 |
20200066658 | PACKAGE-LEVEL NOISE FILTERING FOR EMI RFI MITIGATION | 2020-02-27 |
20200066659 | WIREBOND AND LEADFRAME MAGNETIC INDUCTORS | 2020-02-27 |
20200066660 | SEAL RING INDUCTOR AND METHOD OF FORMING THE SAME | 2020-02-27 |
20200066661 | ON-CHIP INTEGRATED CAVITY RESONATOR | 2020-02-27 |
20200066662 | SEMICONDUCTOR PACKAGE AND ANTENNA MODULE INCLUDING THE SAME | 2020-02-27 |
20200066663 | MICROELECTRONIC DEVICES DESIGNED WITH 3D STACKED ULTRA THIN PACKAGE MODULES FOR HIGH FREQUENCY COMMUNICATIONS | 2020-02-27 |
20200066664 | 3DI Solder Cup | 2020-02-27 |
20200066665 | SEMICONDUCTOR DEVICE | 2020-02-27 |
20200066666 | SEMICONDUCTOR CHIP | 2020-02-27 |
20200066667 | METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURE FOR JOINING WAFERS AND RESULTING STRUCTURE | 2020-02-27 |
20200066668 | Semiconductor Device | 2020-02-27 |
20200066669 | FILLER PARTICLE POSITION AND DENSITY MANIPULATION WITH APPLICATIONS IN THERMAL INTERFACE MATERIALS | 2020-02-27 |
20200066670 | ACTIVE PACKAGE SUBSTRATE HAVING ANISOTROPIC CONDUCTIVE LAYER | 2020-02-27 |
20200066671 | THERMALLY CONDUCTIVE MOLDING COMPOUND STRUCTURE FOR HEAT DISSIPATION IN SEMICONDUCTOR PACKAGES | 2020-02-27 |
20200066672 | CHIP COMPONENT | 2020-02-27 |