09th week of 2018 patent applcation highlights part 66 |
Patent application number | Title | Published |
20180061471 | APPARATUSES AND METHODS INCLUDING FERROELECTRIC MEMORY AND FOR ACCESSING FERROELECTRIC MEMORY - Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node. The voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second voltage and the second node is driven to the first voltage responsive to the voltage of the first node being less than the second node. | 2018-03-01 |
20180061472 | SEMICONDUCTOR SYSTEM - A semiconductor system may include: an external channel including a CA (Command/Address) channel, and first and second data channels; and first and second semiconductor chips, which are coupled in common to the CA channel and coupled to respective different ones of the first and second data channels, and each of which includes a coupling information pad. A first value may be inputted to the coupling information pad of one of the first and second semiconductor chips that is coupled to the first data channel, and a second value may be inputted to the coupling information pad of the other semiconductor chip that is coupled to the second data channel. Each of the first and second semiconductor chips selectively stores setting information using CA information applied to the CA channel and a value inputted to the corresponding coupling information pad. | 2018-03-01 |
20180061473 | MEMORY STORAGE APPARATUS AND OPERATING METHOD THEREOF - A memory storage apparatus having a plurality of operating modes is provided. The memory storage apparatus includes a memory control circuit and a memory cell array circuit. The memory control circuit controls the memory storage apparatus to operate in one of the operating modes. The memory control circuit controls the memory storage apparatus to operate in a first operating mode and controls the memory storage apparatus to switch from the first operating mode to a second operating mode to refresh storage data of the memory cell array circuit. The memory storage apparatus operates in a third operating mode to refresh storage data in the memory storage apparatus. An operating voltage of the memory storage apparatus operating in the second operating mode is smaller than an operating voltage of the memory storage apparatus operating in the third operating mode. | 2018-03-01 |
20180061474 | SEMICONDUCTOR DEVICES - A semiconductor device includes a bank address generation circuit, a row/column address generation circuit, and an operation control circuit. The bank address generation circuit generates a bank address signal according to a bank group selection signal which is generated in response to a first temperature code and a second temperature code. The row/column address generation circuit generates a row address signal and a column address signal according to an area selection signal which is generated in response to a third temperature code and a fourth temperature code. The operation control circuit performs a data scrub operation on a cell which is accessed by the bank address signal, the row address signal and the column address signal. | 2018-03-01 |
20180061475 | DEVICE HAVING MULTIPLE SWITCHING BUFFERS FOR DATA PATHS CONTROLLED BASED ON IO CONFIGURATION MODES - A device includes a first data terminal, a second data terminal, a first switching buffer coupled between a data node and the first data terminal and a second switching buffer coupled between the data node and the second data terminal. The first switching buffer and the second switching buffer are arranged such that a distance between the first switching buffer and the second data terminal is shorter than a distance between the second switching buffer and the second data terminal and that a distance between the first switching buffer and the first data terminal is shorter than a distance between the second switching buffer and the first data terminal. | 2018-03-01 |
20180061476 | REFRESH CONTROL CIRCUIT FOR TARGET REFRESH OPERATION OF SEMICONDUCTOR MEMORY DEVICE, AND OPERATING METHOD THEREOF - A semiconductor memory device may include: a memory cell region including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines; and a refresh control block suitable for performing a first refresh operation onto the plurality of the word lines in response to a refresh signal, counting the number of active signals that are inputted between at least two neighboring refresh signals and when the counted number of the active signals is equal to or greater than a reference number, performing a second refresh operation onto a word line corresponding to a target address. | 2018-03-01 |
20180061477 | APPARATUSES AND METHODS INCLUDING TWO TRANSISTOR-ONE CAPACITOR MEMORY AND FOR ACCESSING SAME - Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage. | 2018-03-01 |
20180061478 | DOUBLE DATA RATE COMMAND BUS - A memory subsystem includes a command address bus capable to be operated at double data rate. A memory circuit includes N command signal lines that operate at a data rate of 2R to receive command information from a memory controller. The memory circuit includes 2N command signal lines that operate at a data rate of R to transfer the commands to one or more memory devices. While ratios of 1:2 are specified, similar techniques can be used to send command signals at higher data rates over fewer signal lines from a host to a logic circuit, which then transfers the command signals at lower data rates over more signal lines. | 2018-03-01 |
20180061479 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A semiconductor memory device may include a sense amplifier for sensing and amplifying data of a bit line pair with pull-up and pull-down driving voltages; a voltage supplier for supplying a power supply voltage or an internal voltage lower than the power supply voltage as the pull-up driving voltage through a pull-up power supply line in response to a first or second pull-up control signal, and supplying a ground voltage as the pull-down driving voltage through a pull-down power supply line in response to a pull-down control signal; a voltage detector for detecting a voltage level of the power supply voltage and outputting a detection signal; and a control signal generator for generating the first and second pull-up control signals, and the pull-down control signal and delaying an enabling timing of one of the first pull-up and pull-down control signals in response to the detection signal. | 2018-03-01 |
20180061480 | SEMICONDUCTOR DEVICE - A semiconductor device includes an equalizing circuit and a control circuit. The equalizing circuit executes an operation of pre-charging the signal input/output line pair used for data inputting/outputting and an operation of equalizing it independently of each other. In case a plurality of data write operations occur in succession, the control circuit halts pre-charge control in the equalizing circuit in the course of consecutive write operations. | 2018-03-01 |
20180061481 | Memory Arrays - Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells are along the columns of the memory array. Capacitive units are along the columns of the memory array and are interspersed amongst the memory cells. The capacitive units are not utilized for data storage during operation of the memory array, but rather are utilized for reducing parasitic capacitance between adjacent bitlines. | 2018-03-01 |
20180061482 | High-density magnetic memory device - A high-density magnetic memory device includes: a heavy metal strip or an antiferromagnet strip with a thickness of 0-20 nm, and a plurality of magnetic tunnel junctions manufactured thereon, wherein each of the magnetic tunnel junctions represents a memory bit, which from bottom to top comprises a first ferromagnetic metal with a thickness of 0-3 nm, an oxide with a thickness of 0-2 nm, a second ferromagnetic metal with a thickness of 0-3 nm, a synthetic antiferromagnetic layer with a thickness of 10-20 nm and a No. X top electrode with a thickness of 10-200 nm, wherein an X value is a serial number of the memory bit; two ends of the heavy metal strip or the antiferromagnet strip are respectively plated with a first bottom electrode and a second bottom electrode. The write operation for the memory device of the present invention is accomplished by applying unidirectional write currents. | 2018-03-01 |
20180061483 | A TEMPERATURE-DEPENDENT REFRESH CIRCUIT CONFIGURED TO INCREASE OR DECREASE A COUNT VALUE OF A REFRESH TIMER ACCORDING TO A SELF-REFRESH SIGNAL - Systems and apparatuses for memory devices utilizing a continuous self-refresh timer are provided. An example apparatus includes a self-refresh timer configured to generate a signal periodically, wherein a period of the signal is based on a self-refresh refresh time interval, wherein the self-refresh refresh time interval is dependent on temperature information. The apparatus may further include a memory bank comprising at least a first subarray and in communication with a first subarray refresh circuit, which may include a first refresh status counter. The first refresh status counter may be in communication with the self-refresh timer and configured to receive the signal from the self-refresh timer, change a count value of the first refresh status counter in a first direction each time the signal is received, and change the count value of the first refresh status counter in a second direction each time the first subarray is refreshed. | 2018-03-01 |
20180061484 | Systems and Methods for Memory Refresh Timing - In an embodiment, an integrated circuit (IC) and a memory device are configured to operate in a “normal” mode and a “self refresh” mode. The IC may generate refresh commands according to a refresh interval during normal mode. The memory device may be responsible for refresh during the self refresh mode. The IC may ensure that the amount of time that has expired in the current refresh interval prior to entering self refresh mode is retained, so that a remaining amount of time may expire after self refresh mode is exited prior to generating the initial refresh command after exiting self refresh mode. Similarly, the memory device may retain the amount of time that has expired in the current self refresh interval prior to exiting self refresh, so that a remaining amount of time may expire after self refresh mode is entered again prior to performing an initial self refresh. | 2018-03-01 |
20180061485 | REFRESH CONTROL CIRCUIT AND MEMORY DEVICE INCLUDING SAME - A memory device may include: at least one memory bank; and a control circuit suitable for: refreshing the at least one memory bank through a first refresh operation in response to a refresh command; and refreshing the at least one memory bank through a second refresh operation when an active operation is performed between a current refresh command and a previous refresh command. | 2018-03-01 |
20180061486 | ULTRA-LOW-VOLTAGE CMOS CIRCUIT AND THE SAME FOR MEMORY - A memory includes a plurality of memory cells and a plurality of peripheral circuits. Each memory cell has a first inverter and a second inverter, the first inverter is supplied by a first power supply rail and a second power supply rail, and the second inverter is supplied by a third power supply rail and a fourth power supply rail. A first voltage difference is applied across the first power supply rail and the second power supply rail, a second voltage difference is applied across the third power supply rail and the fourth power supply rail, and the first voltage difference is less than the second voltage difference. The plurality of peripheral circuits use at least one of boosted power supplies corresponding to the second voltage difference and gate-source differentially-driven circuits. | 2018-03-01 |
20180061487 | Two-Port SRAM Connection Structure - A static random access memory (SRAM) device is provided in accordance with some embodiments. The SRAM device comprises a plurality of two-port SRAM arrays, which comprise a plurality of two-port SRAM cells. Each two-port SRAM cell comprises a write port portion, a read port portion, a first plurality of metal lines located in a first metal layer, a second plurality of metal lines located in a second metal layer, a third plurality of metal lines located in a third metal layer a plurality of edge cells, a plurality of well strap cells, and a plurality of jumper structures. Each jumper structure comprises first, second, and third metal landing pads located in the second metal layer and electrically connecting metal lines of the first and third metal layers. | 2018-03-01 |
20180061488 | WRITE ASSIST CIRCUIT OF MEMORY DEVICE - A device including a memory cell and write assist circuit is disclosed. The memory cell includes a first inverter and a second inverter cross-coupled with the first inverter. The first inverter is operated with a first operational voltage and a third operational voltage, and the second inverter is operated with a second operational voltage and a fourth operational voltage. The write assist circuit is coupled to the memory cell. During a write operation of the memory cell, the write assist circuit is configured to adjust a voltage level of the first operational voltage, the second operational voltage, the third operation voltage, the fourth operation voltage, or a combination thereof, by a bias voltage difference. | 2018-03-01 |
20180061489 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell. | 2018-03-01 |
20180061490 | PHASE CHANGE MEMORY DEVICES INCLUDING TWO-DIMENSIONAL MATERIAL AND METHODS OF OPERATING THE SAME - A phase change memory device may include a phase change layer that includes a two-dimensional (2D) material. The phase change layer may include a layered structure that includes one or more layers of 2D material. The phase change layer may be provided between a first electrode and a second electrode, and the phase of at least a portion of one or more of the layers of 2D material may be changed based on an electrical signal applied to the phase change layer through the first electrode and the second electrode. The 2D material may include a chalcogenide-based material or phosphorene. The 2D material may be associated with a phase change temperature that is greater than or equal to about 200° C. and lower than or equal to about 500° C. | 2018-03-01 |
20180061491 | SEMICONDUCTOR SYSTEM INCLUDING A PHASE CHANGEABLE MEMORY DEVICE - A semiconductor system may be provided. The semiconductor system may include a phase changeable memory device. The phase changeable memory device may include a phase changeable memory cell array, the phase changeable memory cell array may include a plurality of word lines, a plurality of bit lines overlapped with the word lines and phase changeable memory cells respectively connected to overlapping points between the word lines and the bit lines, and the phase changeable memory cell may include a phase changeable material. The semiconductor system may include a controller. The controller may be configured to provide the phase changeable memory device with a command and an address for controlling the phase changeable memory device. | 2018-03-01 |
20180061492 | WRITE BANDWIDTH ENHANCEMENT SCHEME IN PHASE CHANGE MEMORY - In an aspect of the disclosure, a method and an apparatus are provided. The apparatus may be a phase change memory (PCM). The PCM including, first and second phase change memory cells. The PCM including a bitline coupled to the first and the second phase change memory cells. The PCM including a memory controller configured to simultaneously write to the first and the second phase change memory cells by applying designated pulse waveforms to the bitline and wordlines. | 2018-03-01 |
20180061493 | SEMICONDUCTOR MEMORY APPARATUS FOR ADJUSTING VOLTAGE LEVEL OF GLOBAL WORD LINE, AND OPERATING METHOD THEREOF - A semiconductor memory apparatus may include a memory cell, a write driver, and a voltage adjustment circuit. The write driver may provide the memory cell with a program current based on a write data. The voltage adjustment circuit may adjust a voltage level of a global word line coupled to the memory cell when a current flowing through the memory cell or the voltage level of the global word line is greater than a threshold value. | 2018-03-01 |
20180061494 | STORAGE DEVICE AND COPY-BACK METHOD THEREOF - A copy-back method of a storage device includes reading a memory data from a source area of the storage device. A number of error bits of the memory data is determined. An inspection read operation is performed if the number of error bits exceeds a reference value. The memory data is written to a destination area of the storage device if the number of error bits does not exceed the reference value. | 2018-03-01 |
20180061495 | LEVEL SHIFTER CIRCUIT - A level shifter circuit is designed to shift an input signal that switches within a first voltage range to supply an output signal that switches within a second voltage range, higher than the first voltage range. A first inverter stage has an input receiving the input signal and also has an output. A first capacitive element is connected between the output of the first input inverter stage and a first holding node. A latch stage is connected between the first holding node and a second holding node that is coupled to an output terminal, on which the output signal is present. The first input inverter stage is designed to operate in the first voltage range, and the latch stage is designed to operate in the second voltage range. | 2018-03-01 |
20180061496 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device improving a high-temperature data retention is provided. Here, a flash memory includes an erasing element erasing a selected storage cell in a storage cell array. The erasing element further includes an applying element, a verifying element, and a decision element. The applying element applies a monitoring erasing pulse to a monitoring storage cell before starting an erasing operation for selecting the storage cell. The verifying element performs a verification of the monitoring storage cell to which the monitoring erasing pulse is applied. The decision element detennines ISPE conditions based on a verification result of the verifying element. The erasing element erases the storage cell according to the determined ISPE conditions. | 2018-03-01 |
20180061497 | TEMPERATURE COMPENSATION IN MEMORY SENSING - Sense circuits and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level capacitively coupled to the sense node during the sense operation. | 2018-03-01 |
20180061498 | FLASH MEMORY DEVICE - A flash memory controller is configured to hold a read pattern defining an order of selection of read options specifying a parameter value for a read from the flash memory chip. The flash memory controller is configured to execute error correction on data read from the flash memory chip in accordance with the read command. The flash memory controller is configured to designate a next read option specified in the read pattern to read the data from the flash memory chip in a case where all errors in the read data are not corrected by the error correction. | 2018-03-01 |
20180061499 | CIRCUIT AND METHOD FOR BIASING NONVOLATILE MEMORY CELLS - A circuit for biasing non-volatile memory cells includes a dummy decoding path between a global bias line and a biasing node, a reference current generator coupled to the dummy decoding path and configured to supply a reference current, a biasing stage configured to set a cell bias voltage on the biasing node, and a compensation stage configured to compensate a current absorption of the biasing stage at the biasing node so that the reference current will flow through the dummy decoding path. | 2018-03-01 |
20180061500 | BOOSTER CIRCUIT - A booster circuit includes a charge pump circuit and a clock processing circuit. The clock processing circuit includes a first transistor of a first conductivity type, a second transistor of a second conductivity type, and a third transistor of a third conductivity type. The first and second transistors are connected in series between a high-voltage node and a low-voltage node, and gates of the first and second transistors are connected to each other. The third transistor is connected in parallel with the first transistor between the high-voltage node and an output terminal of the clock processing circuit that is connected to a node between the first transistor and the second transistor and to the charge pump circuit. | 2018-03-01 |
20180061501 | MEMORY DEVICE AND METHOD OF OPERATING THE SAME - Provided herein are a memory device and a method of operating the same. The memory device includes a memory block including a plurality of stacked sub-memory blocks, peripheral circuits configured to perform program, read and erase operations on the memory block or on a block selected from among the sub-memory blocks, and control logic configured to control the peripheral circuits so that, during a read operation on the memory block, if a block on which a partial erase operation has been performed is not present among the sub-memory blocks, voltages to be used for the read operation are set and so that, if a block on which the partial erase operation has been performed is present among the sub-memory blocks, the voltages to be used for the read operation are varied depending on a position of a sub-memory block that is a target of the read operation. | 2018-03-01 |
20180061502 | MEMORY ARRAY, AND METHOD FOR READING, PROGRAMMING AND ERASING MEMORY ARRAY - Memory arrays and reading, programming and erasing methods of the memory arrays are provided. An exemplary memory array includes a plurality of memory columns. Each memory column has a plurality of flash memory cells. The memory columns are divided into at least two blocks. At least one source pull down column is disposed between the two adjacent blocks. Each source pull down column has a plurality of flash memory cells. A source of each flash memory cell in the source pull down column is coupled to sources of the flash memory cells of the plurality memory columns in a same row as the flash memory cell in the source pull down column to pull down a source of a selected flash memory cell to 0 V. | 2018-03-01 |
20180061503 | MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A memory device and a programming method thereof are provided, and the programming method of the memory device includes following steps. A memory cell grouping procedure is performed to divide a plurality of memory cells into a plurality of groups. After the memory cell grouping procedure is performed, a programming procedure is performed, and the programming procedure includes following steps. A first programming pulse, a second programming pulse and a verification pulse are provided to a word line. A first group is programmed by the first programming pulse, and a second group is programmed by the second programming pulse. Whether the first group and the second group respectively pass a verification operation is determined by the verification pulse. | 2018-03-01 |
20180061504 | Non-Volatile Memory Devices Having Temperature and Location Dependent Word Line Operating Voltages - A non-volatile memory device includes: a memory cell array including a memory cell string including a ground selection transistor and a plurality of serially connected non-volatile memory cells; a ground selection line connected to the ground selection transistor and a plurality of word lines connected to the plurality of memory cells; a voltage generator configured to generate a program verification voltage and a read voltage applied to the plurality of word lines; and a control circuit configured to control a compensation for the program verification voltage based on a program verification temperature offset, and control a to compensation for the read voltage based on a read temperature offset. | 2018-03-01 |
20180061505 | Leakage Current Detection In 3D Memory - Technology is described herein for detecting a leakage current between a block select line and a conductive region that exists in multiple blocks of memory cells in a plane. The conductive region may be shared by at least one memory cell in multiple blocks. One example of the conductive region is a common source line that includes one or more local source lines and one or more global source lines. If the leakage current were to become high enough, the electrical short between the conductive region and the block select line could cause a plane level failure. If the leakage current is less than an amount that would cause a plane failure, but that indicates that the non-volatile memory device is susceptible to a plane failure, data may be moved out of the plane before the plane failure occurs. Thus, data loss may be prevented. | 2018-03-01 |
20180061506 | SEMICONDUCTOR APPARATUS, LIQUID DISCHARGE HEAD SUBSTRATE, LIQUID DISCHARGE HEAD, AND LIQUID DISCHARGE APPARATUS - A semiconductor apparatus includes a transistor connected to a first potential terminal having a first potential, an anti-fuse element connected between the transistor and a second potential terminal having a second potential, a resistive element connected in parallel with the anti-fuse element between the transistor and the second potential terminal, and a temperature adjustment unit disposed to face the resistive element. | 2018-03-01 |
20180061507 | FUSE STATE SENSING CIRCUITS, DEVICES AND METHODS - Fuse state sensing circuits, devices and methods. In some embodiments, a fuse state sensing circuit can include an enable block configured to enable a flow of a fuse current resulting from a supply voltage to a fuse element upon receipt of an enable signal substantially at the same time as when the supply voltage is applied. The fuse state sensing circuit can further include a current control block tailored to control an amount of the fuse current. The fuse state sensing circuit can further include a decision block implemented to generate an output representative of a state of the fuse element based on the fuse current, with the output being generated during a ramp-up portion of the application of the supply voltage. | 2018-03-01 |
20180061508 | SHIFT REGISTER UNIT AND METHOD FOR DRIVING THE SAME, CORRESPONDING GATE DRIVING CIRCUIT AND DISPLAY DEVICE - The disclosure discloses a shift register and a method for driving the same, a corresponding gate driving circuit and a display device. In the shift register, a pull-up driving unit is connected with a pull-up unit via a pull-up node, a discharge auxiliary unit is used for pulling low the potential of the pull-up node according to a discharge control signal, a discharge driving unit is used for pulling high the potential of a gate line connected with the signal output terminal of the shift register according to the discharge control signal, and a reset unit is further used for pulling low again the potential of the gate line connected with the signal output terminal of the shift register, after the discharge driving unit pulls high the potential of the gate line and the outputting of it finishes. | 2018-03-01 |
20180061509 | BUILT-IN SELF-TEST (BIST) ENGINE CONFIGURED TO STORE A PER PATTERN BASED FAIL STATUS IN A PATTERN MASK REGISTER - A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns. | 2018-03-01 |
20180061510 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - A data storage device includes a nonvolatile memory device; and a control unit suitable for controlling a program operation for memory cells of a page of the nonvolatile memory device, and processing a program fail in the case where the program operation fails, wherein the control unit adjusts a read voltage for discriminating an erase state and a program state having a threshold voltage most adjacent to the erase state, reads out data by applying the adjusted read voltage to the memory cells of the page, and performs an error handling operation to data stored in the memory cells of the page according to a result of comparing a reference value and a number of flipped bits of the data read out by applying the varied read voltage. | 2018-03-01 |
20180061511 | IN-VESSEL ROD HANDLING SYSTEMS - A rod transfer assembly has an outer rotating plug. A pick-up arm assembly extends from the outer rotating plug and includes a pivoting arm. An inner rotating plug is disposed off-center from and within the outer rotating plug and is rotatable independent of a rotation of the outer rotating plug. An access port rotating plug is disposed off-center from and within the inner rotating plug and is rotatable independent of rotation of the outer and inner rotating plugs. A pull arm extends from the access port rotating plug. | 2018-03-01 |
20180061512 | Reactor Control Rod Driving Mechanism - A control rod driving mechanism, comprising a sealing shell assembly, a travel casing fixedly connected to the sealing shell assembly, a coil assembly sleeved on the sealing shell assembly, and a hook assembly disposed in the sealing shell assembly, wherein the sealing shell assembly comprises a sealing shell and a tube base, and the sealing shell and the tube base form an integral structure. The integral structure eliminates the process for welding the tube base to the sealing shell. In this way, the time for manufacturing and assembling the overall reactor might be saved. Also, compared with the prior art, the reactor employing such scheme would reduce one nuclear first class weld, lowering the risk of leakage. In sum, the structure described above extends the service life of the control rod driving mechanism, and remarkably decreases the work for in-service inspection of the control rod driving mechanism. | 2018-03-01 |
20180061513 | NUCLEAR REACTOR, IN PARTICULAR LIQUID-METAL-COOLED COMPACT NUCLEAR REACTOR - The present invention relates to a nuclear reactor ( | 2018-03-01 |
20180061514 | SELF-DIAGNOSIS AND ACCIDENT-HANDLING UNMANNED NUCLEAR REACTOR - The application provides a self-diagnosis and accident-handling unmanned nuclear reactor, which: can passively cool down excessively generated heat without an operation of an operator when a malfunction of the nuclear reactor has occurred, wherein a cooling operation for safety measures can be carried out in a completely passive manner without a separate control command by a change in environmental conditions such as the structure and pressure of the nuclear reactor; and has a simpler structure compared to that of a conventional nuclear reactor safety system. It also provides a self-diagnosis and accident-handling unmanned nuclear reactor, which performs heat exchange by using a two-phase heat transfer mechanism, wherein heat exchange performance is maximized by introducing a spray-type heat exchanger having an optimized structure in which channels are three-dimensionally arranged, and can also easily and passively control heat exchange without a separate control means by using saturated steam pressure. | 2018-03-01 |
20180061515 | SYSTEM AND METHOD OF STORING AND/OR TRANSFERRING HIGH LEVEL RADIOACTIVE WASTE - A module for storing high level radioactive waste includes an outer shell, having a hermetically closed bottom end, and an inner shell forming a cavity and being positioned inside the outer shell to form a space therebetween. At least one divider extends from the top to the bottom of the inner shell to create a plurality of inlet passageways through the space, each inlet passageway connecting to a bottom portion of the cavity. A plurality of inlet ducts each connect at least one of the inlet passageways and ambient atmosphere, and each includes an inlet duct cover affixed atop a surrounding inlet wall, the inlet wall being peripherally perforated. A removable lid is positioned atop the inner shell and has at least one outlet passageway connecting the cavity and the ambient atmosphere, the lid and the top of the inner shell being configured to form a hermetic seal therebetween. | 2018-03-01 |
20180061516 | PRODUCTION OF MOLYBDENUM-99 USING ELECTRON BEAMS - An apparatus for producing | 2018-03-01 |
20180061517 | Highly Conductive Graphitic Films and Production Process - A process for producing a graphitic film comprising the steps of (a) mixing humic acid (HA) with a carbon precursor polymer and a liquid to form a slurry and forming the slurry into a wet film under the influence of an orientation-inducing stress field to align the HA molecules on a solid substrate; (b) removing the liquid to form a precursor polymer composite film wherein HA occupies a weight fraction of 1% to 99%; (c) carbonizing the precursor polymer composite film at a carbonization temperature of at least 300° C. to obtain a carbonized composite film; and (d) thermally treating the carbonized composite film at a final graphitization temperature higher than 1,500° C. to obtain the graphitic film. Preferably, the carbon precursor polymer is selected from the group consisting of polyimide, polyamide, polyoxadiazole, polybenzoxazole, polybenzobisoxazole, polythiazole, polybenzothiazole, polybenzobisthiazole, poly(p-phenylene vinylene), polybenzimidazole, polybenzobisimidazole, and combinations thereof. | 2018-03-01 |
20180061518 | ELECTRICALLY CONDUCTIVE MATERIALS - Methods of forming an electrically conductive carbon allotrope material comprise depositing a first material comprising a polymer and a sulfonic acid onto a carbon allotrope material to form a second material. The methods comprise curing the second material. Methods of heating a surface of a vehicle component comprise applying a voltage to a material comprising a carbon allotrope material, a polymer, and a sulfonic acid. The material is disposed on a surface of a vehicle component. Electrically conductive materials comprise at least one polymer, at least one sulfonic acid, and a carbon allotrope material. | 2018-03-01 |
20180061519 | CONDUCTIVE RESIN COMPOSITION AND ELECTRONIC CIRCUIT MEMBER USING THE SAME - The present invention relates to a conductive resin composition comprising, as essential components, a resin (A), a curing agent (B) reacting with the resin (A), and a conductive filler (C), wherein the resin (A) has a functional group, a functional group equivalent of 400 g/eq or more and 10,000 g/eq or less, a Tg (glass transition temperature) or a softening point of 40° C. or less, or an elastic modulus of less than 1.0 GPa at 30° C., and wherein the conductive filler (C) is made of a conductive material having a volume specific resistivity of 1×10 | 2018-03-01 |
20180061520 | CONDUCTIVE COPPER PASTE, CONDUCTIVE COPPER PASTE CURED FILM, AND SEMICONDUCTOR DEVICE - The purpose of the present invention is to provide a conductive copper paste which is curable in an ambient atmosphere, has a long pot life, and, has a low specific resistance even under a high-temperature and short-time curing condition, wherein the specific resistance after curing does not greatly vary depending on a copper powder content. The conductive copper paste provided is characterized by containing (A) a copper powder, (B) a thermosetting resin, (C) a fatty acid that is liquid at normal temperature, and (D) triethanolamine. Preferably, component (B) is a resol-type phenol resin. More preferably, the content of component (B) is 10 to 20 parts by mass with respect to a total of 100 parts by mass of component (A) and component (B). | 2018-03-01 |
20180061521 | Transparent Conductive Film - A transparent conductive film ( | 2018-03-01 |
20180061522 | COPOLYMER, METHOD FOR ITS PRODUCTION, WIRE COATING RESIN MATERIAL AND ELECTRIC WIRE - To provide an ETFE copolymer and a wire coating resin material capable of forming a coating layer which is excellent in stress cracking resistance under a high temperature and which has a high heat resistance temperature, and an electric wire having a coating layer which is excellent in stress cracking resistance under a high temperature and which has a high heat resistance temperature. A copolymer comprising structural units derived from ethylene, structural units derived from tetrafluoroethylene, and structural units derived from a third monomer, wherein in an elution curve obtained by a temperature rising elution fractionation method with respect to the copolymer, a ratio (L/H) of a proportion (L: area %) of components with elution temperatures of from 190 to 200° C. to a proportion (H: area %) of components with elution temperatures of at least 205° C., and a proportion (M: mol %) of structural units derived from the third monomer based on all structural units of the copolymer, satisfy a relation of log (L/H)/M≧0.90. | 2018-03-01 |
20180061523 | THERMALLY CONDUCTIVE ELECTRICAL INSULATION MATERIAL - A thermally conductive, electrical insulating paper having a thermal conductivity greater than 0.4 W/m-K is described. The thermally conductive, electrical insulating paper is a nonwoven paper that comprises aramid fibers, an aramid pulp, a binder material; and a synergistic blend of thermally conductive fillers, wherein the synergistic blend comprises a primary thermally conductive filler; and a secondary thermally conductive filler. | 2018-03-01 |
20180061524 | DEVICES AND SYSTEMS FOR OBTAINING CONDUCTANCE DATA AND METHODS OF MANUFACTURING AND USING THE SAME - Devices and systems for obtaining conductance data and methods of manufacturing and using the same. In at least one embodiment of a device of the present disclosure, the device is an elongated body with at least one groove defined therein, the at least one groove configured to receive one or more conductor wires therein. In another embodiment, the device is an elongated core body having a plurality of conductive elements positioned thereon and a coating to result in a device having an overall round-cross section. | 2018-03-01 |
20180061525 | COATED ELECTRIC WIRE AND MULTI-CORE CABLE FOR VEHICLES - A multi-core cable for vehicles comprises two power lines, two signal lines, two electric wires, and a jacket. The two power lines are the same in size and material, each comprise an insulation layer composed of an inner layer and an outer layer, and are excellent in abrasion resistance and bending resistance. The two signal lines are the same in size and material and the two lines are twisted as a set to constitute a twisted pair of the signal lines. The two electric wires are the same in size and material and the two wires are twisted as a set to constitute a twisted pair of the electric wires. The two power lines, the twisted pair of the signal lines, and the twisted pair of the electric wires are integrally twisted. | 2018-03-01 |
20180061526 | INSULATED WIRE - An insulated wire that has a stranded wire conductor, and an insulator that covers an outer circumference of the stranded wire conductor. The stranded wire conductor is made up of at least a plurality of copper-based element wires twisted together, and has been heat-treated after circular compression. The copper-based element wire(s) has (have) an Ni-based plated layer on the surface. The Ni-based plated later has been compressed by the circular compression. The insulator is composed of a cross-linked ethylene-tetrafluoroethylene based copolymer, and has a heating deformation rate in the range of 65% or more, as determined under predetermined conditions using predetermined formulae in conformity with ISO6722. | 2018-03-01 |
20180061527 | CABLE AND EXPLOSION-PROOF SYSTEM - A cable includes electric wires, an outer cover, a first cover, and a second cover. Each of the electric wires includes a conductive core and an insulator covering the conductive core. The outer cover covers the electric wires and extends from a first atmosphere to a second atmosphere less explosive than the first atmosphere. An outer surface of the outer cover is supported by a partition separating the first atmosphere from the second atmosphere. The first cover includes a thermosetting resin and covers an exposed portion of the electric wires, which is not covered by the outer cover in the second atmosphere. The second cover covers the first cover and includes a material higher in fracture strength than the thermosetting resin. | 2018-03-01 |
20180061528 | DEVICE FOR DISTRIBUTING HYBRID TRUNK CABLE - A transition assembly for a hybrid trunk cable includes: a hybrid trunk cable comprising a plurality of power conductors and a plurality of optical fibers surrounded by a jacket; a transition cup having a cavity, the hybrid trunk cable entering a first end of the transition cup; a plurality of power cords exiting a second end of the transition cup, each of the power cords electrically connected to a respective power conductor; a plurality of fiber optic cords exiting the second end of the transition cup, each of the fiber optic cords optically connected to a respective optical fiber; and a weather-resistant material residing in the cavity of the transition cup to protect the power cords and the fiber optic cords within the cavity. | 2018-03-01 |
20180061529 | POWER/FIBER HYBRID CABLE - The present disclosure relates to a hybrid cable having a jacket with a central portion positioned between left and right portions. The central portion contains at least one optical fiber and the left and right portions contain electrical conductors. The left and right portions can be manually torn from the central portion. | 2018-03-01 |
20180061530 | HIGH FREQUENCY SIGNAL TRANSMISSION DEVICE - The instant disclosure relates to a high frequency signal transmission device which includes an insulation cover, at least one flexible flat cable, and an electrical connector assembly. The insulation cover has an accommodation space, the at least one flexible flat cable is disposed in the accommodation space, and the electrical connector assembly is electrically connected to one end of the at least one flexible flat cable. The at least one flexible flat cable includes a plurality of conductors, an insulation layer, a polyolefin resin layer, and a shielding layer. The insulation layer is laminated over the conductors. The polyolefin resin layer is attached to the insulation layer by a first low-k dielectric adhesive layer, and the shielding layer is attached to the polyolefin resin layer by another first low-k dielectric adhesive layer. | 2018-03-01 |
20180061531 | ADDITIVE COMMUNICATION CABLE AND AD HOC HARNESSES - Embodiments are directed to a method for manufacturing a product comprising: establishing, by a computing device comprising a processor, at least one parameter of a particular instance of a component to be used in the product, adapting, by the computing device, a baseline model of the component based on the at least one parameter to accommodate use of the particular instance of the component, growing a structure based on the adapted model to accommodate the particular instance of the component using an additive manufacturing technique, coupling the structure to the particular instance of the component, growing an electrical harness by using additive printing to establish an electrical cable, and assembling the product by coupling the electrical harness to the particular instance of the component. | 2018-03-01 |
20180061532 | METHOD FOR PRODUCING ELECTRIC WIRE - The invention provides a method for producing an electric wire with a low dielectric loss. The method for producing an electric wire includes a coating step of coating a core wire with a mixture of a high-molecular-weight polytetrafluoroethylene (A) and a non-fibrillatable low-molecular-weight polytetrafluoroethylene (B); a first heating step of heating the coated core wire up to the first melting point of the low-molecular-weight polytetrafluoroethylene (B) or higher; a second heating step of heating the coated core wire to 150° C. to 300° C.; and a cooling step of cooling the coated core wire. | 2018-03-01 |
20180061533 | RESISTOR ELEMENT AND RESISTOR ELEMENT ASSEMBLY - A resistor element includes a base substrate having first and second surfaces opposing each other; a resistor layer disposed on the first surface of the base substrate; first and second terminals disposed on opposing end portions of the base substrate, respectively, and electrically connected to opposing sides of the resistor layer, respectively; a third terminal disposed between the first terminal and the second terminal on the second surface of the base substrate and spaced apart from the first terminal and the second terminal; and electrostatic discharge (ESD)-preventing members connecting the first terminal and the third terminal to each other and connecting the second terminal and the third terminal to each other. | 2018-03-01 |
20180061534 | ADHESIVE POSITIVE TEMPERATURE COEFFICIENT MATERIAL - Positive temperature coefficient (PTC) devices and methods to manufacture PTC devices are disclosed. A PTC device or apparatus may include a grafted polymer. Furthermore, the PTC device may include a conductive filler included in the polymer material. The PTC device may include at least one conductive layer dispose over a surface of the PTC device. | 2018-03-01 |
20180061535 | A VARISTOR AND PRODUCTION METHOD THEREOF - The present invention relates to a product and fabrication method for a varistor comprising a solid phase of zinc oxide particles substantially uniformly dispersed within a resin media. The varistor of the present invention is synthesised by mixing a substantially homogenous mixture of solid zinc oxide particles and a resin media, and heating the mixture under conditions to melt the resin and suspend the solid zinc oxide particles therein. | 2018-03-01 |
20180061536 | CHIP RESISTOR - The present invention relates to a chip resistor. A method of manufacturing a chip resistor comprising steps of: preparing an insulating substrate squarely segmented with vertical slits and horizontal slits, applying on the insulating substrate a conductive paste crossing over the horizontal slits, applying a resistor paste on the insulating substrate, forming trimming grooves to adjust resistivity of the resistor layers, and splitting the insulating substrate to form chip resistors, wherein the conductive paste comprises (i) a conductive powder comprising an agglomerated metal powder, wherein particle diameter (D50) of the agglomerated metal powder is 3 to 12 μm and specific surface area (SA) of the agglomerated metal powder is 3.1 to 8.0 m | 2018-03-01 |
20180061537 | OXIDE SUPERCONDUCTOR AND METHOD FOR MANUFACTURING THE SAME - An oxide superconductor of an embodiment includes an oxide superconductor layer having a continuous Perovskite structure including rare earth elements, barium (Ba), and copper (Cu). The rare earth elements include a first element which is praseodymium, at least one second element selected from the group consisting of neodymium, samarium, europium, and gadolinium, at least one third element selected from the group consisting of yttrium, terbium, dysprosium, and holmium, and at least one fourth element selected from the group consisting of erbium, thulium, ytterbium, and lutetium. When the number of atoms of the first element is N(PA), the number of atoms of the second element is N(SA), and the number of atoms of the fourth element is N(CA), 1.5×(N(PA)+N(SA))≦N(CA) or 2×(N(CA)−N(PA))≦N(SA) is satisfied. | 2018-03-01 |
20180061538 | HO AND W-CONTAINING RARE-EARTH MAGNET - Disclosed is a Ho and W-containing rare-earth magnet. The rare-earth magnet comprises a R | 2018-03-01 |
20180061539 | MAGNETIC MATERIAL, PERMANENT MAGNET, ROTARY ELECTRICAL MACHINE, AND VEHICLE - An magnetic material is a magnetic material expressed by a composition formula: (R | 2018-03-01 |
20180061540 | METHOD FOR PRODUCING A SINTERED R-IRON-BORON MAGNET - A method for producing a sintered R-iron (Fe)-boron (B) magnet, the method including: (1) producing a sintered magnet R1-Fe—B-M; (2) washing the sintered magnet using an acid solution and deionized water, successively, and drying the sintered magnet to yield a treated magnet; (3) mixing a heavy rare earth element powder RX, an organic solid powder EP and an organic solvent ET to yield a slurry RXE, coating the slurry RXE on the surface of the treated magnet, and drying the treated magnet to yield a treatment unit; and (4) heating, quenching, and then aging the treatment unit. | 2018-03-01 |
20180061541 | SUPERCONDUCTING COIL AND SUPERCONDUCTING DEVICE - A superconducting coil of an embodiment includes a superconducting wire including an oxide superconductor layer. The oxide superconductor layer has a continuous Perovskite structure including rare earth elements, barium (Ba), and copper (Cu). The rare earth elements include a first element which is praseodymium (Pr), at least one second element selected from the group consisting of neodymium (Nd), samarium (Sm), europium (Eu), and gadolinium (Gd), at least one third element selected from the group consisting of yttrium (Y), terbium (Tb), dysprosium (Dy), and holmium (Ho), and at least one fourth element selected from the group consisting of erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu). | 2018-03-01 |
20180061542 | Improved Superconductor Compositions - A superconductor tape may be fabricated via Metal Organic Chemical Vapor Deposition (MOCVD) to achieve peel strengths greater than approximately 4.5 N/cm. The superconductor tape may be fabricated via MOCVD with a REBCO composition that includes the elements Samarium (Sm)-Barium(Ba)-Copper(Cu)-Oxygen(O). Varying levels of Copper (Cu) content can achieve peel strengths ranging between approximately 4.5 N/cm to approximately 8.0 N/cm. | 2018-03-01 |
20180061543 | 3D PRINTER WITH HOVERING PRINTING HEAD OR PRINTING BED - A three-dimensional printing device includes a movable unit with a superconductor and a printing head arrangement for printing a printing material, a magnetic field generator adapted to generate a magnetic field, and a control device. The magnetic field generator and the movable unit are adapted for coupling in a force-locking manner by means of frozen magnetic flux, and the controlling device is adapted to control a magnetic field strength of the magnetic field generator. | 2018-03-01 |
20180061544 | ELECTROMAGNETIC DRIVER - In a main magnetic circuit, first pulling force generated based on a first component of the magnetic flux flowing through the main magnetic path pulls a movable core in a reciprocation direction of the movable core. The first pulling force increases with a reduction of a dimension of the gap. In an auxiliary magnetic circuit, second pulling force generated based on the second component of the magnetic flux flowing through the auxiliary magnetic path pulls the movable core in the reciprocation direction of the movable core. In the auxiliary magnetic circuit, the second pulling force with the dimension of the gap being within a first range is changed to be higher than the second pulling force with the dimension of the gap being within a second range, the second range being smaller than the first range. | 2018-03-01 |
20180061545 | THIN FILM MAGNET AND METHOD FOR MANUFACTURING THIN FILM MAGNET - A thin film magnet includes a substrate, an oxidation-inhibiting layer in an amorphous state disposed on an upper surface of the substrate, a first magnetic layer disposed on the oxidation-inhibiting layer, an intermediate layer disposed on the first magnetic layer, a second magnetic layer disposed on the intermediate layer, and a second oxidation-inhibiting layer in an amorphous state disposed above the second magnetic layer. The intermediate layer contains metal particles. The metal particles are diffused in the first magnetic layer and the second magnetic layer. The concentration of the metal particles in a part of the first magnetic layer decreases as the distance from the intermediate layer to the part of the first magnetic layer increases. The concentration of the metal particles in a part of the second magnetic layer decreases as the distance from the intermediate layer to the part of the second magnetic layer increases. | 2018-03-01 |
20180061546 | Cover For Tissue Penetrating Device With Integrated Magnets And Magnetic Shielding - A cover for magnetizing a shaft of a tissue-penetrating medical device is disclosed including a sleeve member having a hollow body to form a protective closure over the shaft of the tissue-penetrating medical device. The proximal end of the hollow body provides a receiving space for receiving the shaft of the tissue-penetrating medical device. One or more magnet is disposed on the sleeve member. A magnetic shield composed of one or more shielding materials associated with the cover that minimizes any effects to the clinical environment from magnetic fields generated within the cover. Medical devices and methods of magnetizing the shaft of a tissue-penetrating medical device using the cover are also disclosed. | 2018-03-01 |
20180061547 | INDUCTOR HAVING HIGH CURRENT COIL WITH LOW DIRECT CURRENT RESISTANCE - An inductor and method for making the same are provided. The inductor includes a coil formed from a conductor and having a serpentine shape. The coil may have an “S”-shape. The coil has two leads extending from opposite ends of the coil. An inductor body surrounds the coil and portions of the leads. The leads may be wrapped around the body to create contact points on the exterior of the inductor. | 2018-03-01 |
20180061548 | COMPOSITE FERRITE SHEET, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE INCLUDING THE SAME - A composite ferrite sheet may include a ferrite sheet, and composite sheets attached to both surfaces of the ferrite sheet, respectively, and having insulating properties. The composite sheet may be formed of a resin containing metal powder particles. The composite ferrite sheet may be easily manufactured and have improved shielding performance. | 2018-03-01 |
20180061549 | METHOD AND DEVICE FOR MANUFACTURING TRANSFORMERS WITH A CORE MADE OF AMORPHOUS MATERIAL, AND TRANSFORMER THUS PRODUCED - A device for the production of a transformer is disclosed, comprised of at least two electrically conductive windings (A, B, C) adjacent to one another, and a ferromagnetic core ( | 2018-03-01 |
20180061550 | MAGNETIC COMPOSITION AND INDUCTOR INCLUDING THE SAME - A magnetic composition includes first, second, and third magnetic metal particles. The first magnetic metal particles have an average particle size of | 2018-03-01 |
20180061551 | PASSIVE ELECTRONIC COMPONENT - There is provided a passive electronic component that achieves proper recognition of a marker portion thereof that indicates a winding start position and a winding direction of a coil conductor as well as a posture and an orientation of the component. The passive electronic component is a laminated type electronic component and has an insulator portion, a terminal electrode electrically connected to a conductor portion provided inside the insulator portion and formed on a surface of the insulator portion, and a marker portion for indicating a winding start position and a winding direction of a conductor or a posture and an orientation of the component. The marker portion is disposed in a recessed portion on the surface of the insulator portion. | 2018-03-01 |
20180061552 | THIN FILM TYPE COIL COMPONENT - A thin film type coil component that includes a body having a coil embedded therein and including a composite of magnetic powder particles and a polymer, and external electrodes disposed on at least portions of external surfaces of the body. The body includes an upper body portion disposed on an upper surface of the coil, a lower body portion disposed on a lower surface of the coil, and a central body portion disposed between the upper body portion and the lower body portion and including a central portion of the coil. The upper body portion and the lower body portion include a stacked structure of a plurality of magnetic sheets, each magnetic sheet including the composite of the magnetic powder particles and the polymer. | 2018-03-01 |
20180061553 | CHIP ELECTRONIC COMPONENT INCLUDING STRESS BUFFER LAYER - A chip electronic component includes a body including a coil portion disposed therein and a magnetic metallic powder, and a stress buffer layer disposed on a surface of the body. A Young's modulus of the stress buffer layer is less than that of the body. | 2018-03-01 |
20180061554 | ELECTRONIC COMPONENT - An electronic component having a main body includes a plurality of insulator layers laminated in a lamination direction. A primary coil is disposed in the main body and includes one or more primary coil conductor layers. A secondary coil is disposed in the main body and includes one or more secondary coil conductor layers. A tertiary coil is disposed in the main body and includes one or more tertiary coil conductor layers. The plurality of insulator layers includes a first insulator layer including a portion interposed between the primary coil conductor layer and the secondary coil conductor layer, a second insulator layer including a portion interposed between the secondary coil conductor layer and the tertiary coil conductor layer, and a third insulator layer including a portion interposed between the tertiary coil conductor layer and the primary coil conductor layer. | 2018-03-01 |
20180061555 | INDUCTOR AND METHOD OF MANUFACTURING THE SAME - There are provided an inductor and a method of manufacturing the same. The inductor includes: a body including a plurality of coil layers and high-rigidity insulating layers disposed on and beneath the plurality of coil layers; and external electrodes disposed on external surfaces of the body and connected to the coil layers. Build-up insulating layers are disposed between the high-rigidity insulating layers to cover the coil layers, and the high-rigidity insulating layers have a Young's modulus greater than that of the build-up insulating layers. | 2018-03-01 |
20180061556 | COIL ELEMENT - One object is to provide a coil element capable of enhancing reliability of joint strength of a coil conductor wire, while achieving a reduction in resistance and a size reduction. A coil element includes a core member, a coil conductor wire, and a terminal electrode. The core member has a columnar portion. The coil conductor wire has a coil portion wound on the columnar portion and a flat-shaped connection end portion provided in each of both end portions of the coil portion. The terminal electrode has an electrode layer and a joint layer. The electrode layer is formed on a surface of the core member and opposed to the connection end portion in its thickness direction. The joint layer includes a cavity portion locally provided between the connection end portion and the electrode layer and joins the connection end portion and the electrode layer to each other. | 2018-03-01 |
20180061557 | RESONANT HIGH CURRENT DENSITY TRANSFORMER WITH IMPROVED STRUCTURE - A resonant high current density transformer with an improved structure includes a secondary insulating bobbin, a primary insulating bobbin and a core assembly. The secondary insulating bobbin includes a base. Two posts extend from a first side of the base, and a raised plate extends from a second side of the base, the second side is opposite to the first side. The two posts and the raised plate form a receiving space for receiving an insulating sheath having a plurality of sleeves. A secondary winding is provided on each of the sleeve. The primary insulating bobbin having a tunnel is provided at one side of the secondary insulating bobbin. The surface of the primary insulating bobbin is provided with a primary winding and covered by an insulating cover. A core assembly includes a first core and a second core. A first primary core column and a second primary core column opposite to each other extend from a side of the first and second cores, respectively, and a plurality of first secondary core columns and a plurality of second secondary core columns extend from another side of the first and second cores, respectively. The first primary core column and the second primary core column are inserted into the tunnel of the primary insulating bobbin, while each of the first secondary core columns and each of the second secondary core columns are inserted into a corresponding one of the sleeves. As a result, the secondary windings are capable of withstanding large current. Their overall length covers the air gap of the core assembly, thus achieving magnetic shielding. Meanwhile, production and assembly processes are simplified. | 2018-03-01 |
20180061558 | TERMINAL PLATE MEMBER OF COIL COMPONENT AND METHOD FOR MANUFACTURING ELECTRONIC COMPONENT - A terminal plate member on which a terminal of a coil component is mounted including: an annular frame having an inner peripheral edge; a pair of extension members extending from the inner peripheral edge of the annular frame toward an inner space of the annular frame member in a first direction; and a deformable section provided in the annular frame at proximal end of one of the pair of extension members, the deformable section having a more easily deformable property than other sections of the annular frame when force is applied. The deformable section is provided along at least an entire width in a second direction of the one of the pair of extension members. The second direction is perpendicular to the first direction. | 2018-03-01 |
20180061559 | INSULATION BOBBIN AND WINDING PRODUCTS - An insulation bobbin includes a winding portion, an outer stopper portion and an inner stopper portion. The winding portion includes a body and two sidewalls respectively and perpendicularly connected to two first sides of the body. A length of a first side edge of each of the sidewalls is greater than a length of a second side edge, and a connecting edge of each of the sidewalls connects a first bottom edge and the second side edge. The outer stopper portion connects one of the second sides of the body and the first side edge of each of the sidewalls. The inner stopper portion connects the other one of the second sides of the body and the second side edge of each of the sidewalls. There is a height difference between the first bottom edge of each of the sidewalls and a second bottom edge of the inner stopper portion. | 2018-03-01 |
20180061560 | MULTIPLE PHASE POWER CONVERTERS HAVING INTEGRATED MAGNETIC CORES FOR TRANSFORMER AND INDUCTOR WINDINGS - A multiphase DC/DC power converter includes a magnetic core having a plurality of core sections and defining a plurality of magnetic flux paths, and a plurality of winding including a plurality of transformer winding sets and a plurality of inductor windings. Each transformer winding set includes a primary winding and a secondary winding wound about at least one core section of the plurality of core sections. Each inductor winding is wound about another core section of the plurality of core sections. Magnetic flux generated by one transformer winding set of the plurality of transformer winding sets substantially cancels magnetic flux generated by at least one adjacent transformer winding set of the plurality of transformer winding sets. Magnetic flux generated by one inductor winding of the plurality of inductor windings substantially cancels magnetic flux generated by at least one adjacent inductor winding of the plurality of inductor windings. | 2018-03-01 |
20180061561 | INDUCTOR ARRAY COMPONENT AND BOARD FOR MOUNTING THE SAME - An inductor array component includes a body including a plurality of coil portions a coil included in the coil portions, external electrodes connected to both end portions of the coil and disposed on an outer surface of the body, a first blocking layer disposed between the coil portions, and a second blocking layer disposed within the first blocking layer. | 2018-03-01 |
20180061562 | INDUCTOR AND PROTECTION CIRCUIT - To provide an inductor capable of suppressing decrease of inductance in large current without magnetically saturating a magnetic core in large current of several thousand amperes like serge current and to provide a protection circuit using the inductor. The inductor is formed of an iron-based magnetic core | 2018-03-01 |
20180061563 | MULTI-COIL BASE PAD WITH ANGLED STRUCTURE - An apparatus for wirelessly transferring charging power is provided. The apparatus comprises a first coil, as second coil, a ferrite structure positioned on one side of the first coil and the second coil. The ferrite structure includes a first angled surface at an outer side of the first coil and a second angled surface at an outer side of the second coil. The ferrite structure further includes a substantially flat surface at an inner side of the first coil and an inner side of the second coil. The first angled surface and the second angled surface are at an angle to the flat surface. | 2018-03-01 |
20180061564 | TRANSMISSION COIL MODULE FOR WIRELESS POWER TRANSMITTER - A transmitting coil module for wirelessly transmitting power, the transmitting coil module including at least one transmission coil having a hollow portion in a center area thereof; a shield disposed below the at least one transmission coil; and a metal sheet disposed below the shield. Further, the shield includes at least one functional hole in a region corresponding to the hollow portion of the at least one transmission coil. | 2018-03-01 |
20180061565 | TRANSMISSION COIL MODULE FOR WIRELESS POWER TRANSMITTER - A wireless power transmission coil module including a plurality of transmission coils for wirelessly transmitting power; a shield disposed below the plurality of transmission coils; a metal plate disposed below the shield; and a connector electrically connected to the plurality of transmission coils. The metal plate includes a recess having a space for disposing the connector, and the connector includes an inner portion overlapping the shield and an outer portion without overlapping with the shield. | 2018-03-01 |
20180061566 | TRANS INDUCTOR AND POWER CONVERTER USING THE SAME - A trans inductor having a powdery magnetic substance and a power converter using the trans inductor are provided. The trans inductor and the power converter reduce peak current flowing in an inverter power module (IGBT), improve inverter efficiency, reduce output RMS current (output effective current) and reduce capacitor consumption by applying a material with properties that are resistant against current saturation instead of a core material of a conventional trans inductor employed in a power converter. Accordingly, an inductance decreasing rate due to core saturation when high current is generated is improved and current flowing in a switch device is prevented from being abruptly increased. | 2018-03-01 |
20180061567 | CORE AND COIL MOLDING STRUCTURE AND MANUFACTURING METHOD THEREOF - Provided are a core and coil molding structure and a manufacturing method thereof which are capable of eliminating a void between coil layers to prevent foreign materials from entering therein, and which improve the vibration resistance and shock resistance of a reactor. A core and coil molding structure includes a coil that is a rectangular coil, a core yoke member in a block shape, and a resin member molding at least a part of those. The presence of a positioning member in a pin shape which positions the coil within a mold forms a groove in the inner circumference of the coil in the resin member. | 2018-03-01 |
20180061568 | METHOD FOR PRODUCING SINTERED R-IRON-BORON MAGNET - A method for producing a sintered R-iron (Fe)-boron (B) magnet, the method including: (1) producing a sintered magnet R1-Fe—B-M, where R1 is neodymium (Nd), praseodymium (Pr), terbium (Tb), dysprosium (Dy), gadolinium (Gd), holmium (Ho), or a combination thereof; M is titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), cobalt (Co), nickel (Ni), gallium (Ga), calcium (Ca), copper (Cu), Zinc (Zn), silicon (Si), aluminum (Al), magnesium (Mg), zirconium (Zr), niobium (Nb), hafnium (Hf), tantalum (Ta), tungsten (W), molybdenum (Mo), or a combination thereof; (2) removing oil, washing using an acid solution, activating, and washing using deionized water the sintered magnet, successively; (3) mixing a superfine terbium powder, an organic solvent, and an antioxidant to yield a homogeneous slurry, coating the homogeneous slurry on the surface of the sintered magnet; and (4) sintering and aging the sintered magnet. | 2018-03-01 |
20180061569 | METHODS OF MANUFACTURE OF AN INDUCTIVE COMPONENT AND AN INDUCTIVE COMPONENT - The disclosure relates to the manufacture of inductive components, in particular transformers, using a combination of microfabrication techniques and discrete component placement. By using a prefabricated core, the core may be made much thicker than one that is deposited using microfabrication techniques. As such, saturation occurs later and the efficiency of the transformer is improved. This is done at a much lower cost than the cost of producing a thicker core by depositing multiple layers using microfabrication techniques. | 2018-03-01 |
20180061570 | CAPACITOR WITH IMPROVED HEAT DISSIPATION - A capacitor comprises a first winding member, where the first winding member comprises a first dielectric layer and a first conductive layer. A second winding member comprises a second dielectric layer and second conductive layer. The first winding member is interleaved, partially or entirely, with the second winding layer. A dielectric package is adapted to at least radially contain or border the first winding member and the second winding member. A first metallic member has a generally planar, radially extending surface for electrically and mechanically contacting an upper portion the first conductive layer. A second metallic member has a generally planar, radially extending surface for electrically and mechanically contacting a lower portion of the second conductive layer. | 2018-03-01 |