09th week of 2018 patent applcation highlights part 69 |
Patent application number | Title | Published |
20180061771 | SURFACE TREATMENT FOR SEMICONDUCTOR STRUCTURE - A method includes forming a dielectric layer and forming a metallic conductor at least partially in the dielectric layer. Formation of the metallic conductor at least partially in the dielectric layer includes performing a planarization process. The method further includes treating respective surface areas of the dielectric layer and the metallic conductor, after the planarization process, to modify the respective surface areas of the dielectric layer and the metallic conductor. In one example, the surface treatment is a neutral atom beam treatment. | 2018-03-01 |
20180061772 | Semiconductor Lithography Alignment Feature with Epitaxy Blocker - A type III-V semiconductor substrate is provided. Semiconductor material is removed from the type III-V semiconductor substrate such that the type III-V semiconductor substrate comprises one or more alignment features extending away from a main lateral surface. Each of the alignment features includes a first lateral surface that is vertically offset from the main lateral surface, and first and second vertical sidewalls that extend between the first lateral surface and the main lateral surface. An epitaxy blocker is formed on the first and second vertical sidewalls of each alignment feature. A type III-V semiconductor regrown layer is epitaxially grown on a portion of the semiconductor wafer that includes the one or more alignment features. The epitaxy blocker prevents the type III-V semiconductor regrown layer from forming on the first and second vertical sidewalls of the one or more alignment features. | 2018-03-01 |
20180061773 | REGISTRATION MARK FORMATION DURING SIDEWALL IMAGE TRANSFER PROCESS - Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least one selected mandrel and the patterned hard mask. | 2018-03-01 |
20180061774 | Wire Bond Wires for Interference Shielding - Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region. | 2018-03-01 |
20180061775 | LOW PROFILE PASSIVE ON GLASS (PoG) DEVICE COMPRISING A DIE - A device that includes a single substrate layer, a plurality of interconnects over the single substrate layer, the plurality of interconnects configured to operate as at least one passive component, a first die coupled to the single substrate layer and the plurality of interconnects, and an encapsulation layer that at least partially encapsulates the first die and the plurality of interconnects configured to operate as at least one passive component. In some implementations, the single substrate layer, the first die and the encapsulation layer comprise an overall thickness of about 225 microns (μm) or less. In some implementations, the single substrate layer comprises a thickness of about 75 microns (μm) or less. | 2018-03-01 |
20180061776 | SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device package comprises a semiconductor device, a first encapsulant surrounding the semiconductor device, a second encapsulant covering the semiconductor device and the first encapsulant, and a redistribution layer extending through the second encapsulant and electrically connected to the semiconductor device. | 2018-03-01 |
20180061777 | TILED-STRESS-ALLEVIATING PAD STRUCTURE - Structure and method for reducing thermal-mechanical stresses generated for a semiconductor device are provided, which includes a tiled-stress-alleviating pad structure. | 2018-03-01 |
20180061778 | PACKAGING FOR HIGH SPEED CHIP TO CHIP COMMUNICATION - Disclosed are chip packaging structures for high speed chip to chip and chip to carrier communications and methods of making such structures. The chip packaging structures do not require an interposer containing through silicon vias and/or provide structures having reduced warping. | 2018-03-01 |
20180061779 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first substrate, a second substrate, a first pad, a second pad, a first micro-bump, a first resin layer, and an insulating layer. The first substrate has a first semiconductor layer and a first wire layer. The second substrate has a second semiconductor layer and a second wire layer. The insulating layer contains an insulating material having hygroscopic properties lower than hygroscopic properties of the first resin layer. The insulating layer penetrates the second substrate and the first resin layer. The insulating layer surrounds the first micro-bump in a first cross section which passes through the first micro-bump, the first resin layer, and the insulating layer and is parallel to the first surface. | 2018-03-01 |
20180061780 | ACTIVE TAMPER DETECTION CIRCUIT WITH BYPASS DETECTION AND METHOD THEREFOR - An active tamper detection circuit with bypass detection is provided. A bypass detection circuit is coupled to an active mesh loop. The bypass detector includes a voltage comparator with a variable hysteresis control circuit and a calibration engine. The bypass detector detects a change in impedance in the mesh when an attacker attempts to bypass the active loop using a wire. As part of a boot-up sequence, the calibration engine runs a hysteresis sweep on the voltage comparator and stores a hysteresis sweep boot-up signature. When bypass protection is enabled, the bypass detector runs a hysteresis sweep of the voltage comparator periodically at a predetermined interval. Each sweep generates a generated signature that is compared to the stored boot-up signature. Any signature mismatch will be signaled as an impedance mismatch, or tamper. The hysteresis step size is also programmable. The calibration engine can make small changes to the boot-up signature to allow for small voltage variations. | 2018-03-01 |
20180061781 | CHIP PROTECTED AGAINST BACK-FACE ATTACKS - A semiconductor chip includes at least two insulated vias passing through the chip from the front face to the rear face in which, on the side of the rear face, the vias are connected to one and the same conducting strip and, on the side of the front face, each via is separated from a conducting pad by a layer of a dielectric. | 2018-03-01 |
20180061782 | ACTIVATING REACTIONS IN INTEGRATED CIRCUITS THROUGH ELECTRICAL DISCHARGE - Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated circuit is provided having reactive material capable of being activated by electrical discharge, without requiring a battery or similar external power source, to produce an exothermic reaction that erases and/or destroys one or more semiconductor devices on the integrated circuit. | 2018-03-01 |
20180061783 | Lid Structure for a Semiconductor Device Package and Method for Forming the Same - A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a die structure formed over the substrate. The semiconductor device structure also includes a lid structure formed over the die structure. The lid structure includes a top portion with a top length and a bottom portion with a bottom length, and the top length is greater than the bottom length. The semiconductor device structure also includes a package layer formed between the lid structure and the die structure, and a sidewall of the bottom portion of the lid structure is not aligned with a sidewall of the die structure. | 2018-03-01 |
20180061784 | MULTI-DIE INTEGRATED CIRCUIT DEVICE WITH CAPACITIVE OVERVOLTAGE PROTECTION - An electronic device includes a package, a plurality of external leads extending outside the package, a first die within the package having one or more first contacts electrically coupled to at least a first one of the external leads, and a second die within the package having one or more second contacts electrically coupled to at least a second one of the external leads. A capacitive coupling may be positioned between the first and second die to allow electrostatic discharge (ESD) current to flow between the first die and the second die in response to an ESD event and to electrically isolate the first and second die from each other in the absence of the ESD event. | 2018-03-01 |
20180061785 | POWER TRANSISTOR WITH HARMONIC CONTROL - A system and method for a packaged device with harmonic control are presented. In one embodiment, a device includes a substrate and a transistor die coupled to the substrate. The transistor die includes a plurality of transistor cells. Each transistor cell in the plurality of transistor cells includes a control (e.g., gate) terminal. The device includes a second die coupled to the substrate. The second die includes a plurality of individual shunt capacitors coupled between the control terminals of the plurality of transistor cells and a ground reference node. The capacitance values of at least two of the shunt capacitors are significantly different. | 2018-03-01 |
20180061786 | SEMICONDUCTOR PACKAGE INTEGRATED WITH MEMORY DIE - A semiconductor package structure is provided. The semiconductor package structure includes a package substrate. An integrated circuit (IC) die having a radio frequency (RF) circuit and a memory die are stacked over the package substrate. The memory die entirely covers a first surface portion of the package substrate to define a second surface portion of the package substrate exposed from the memory die, and the IC die partially covers the first surface portion and the second surface portion of the package substrate. The RF circuit includes a first sensitive device region corresponding to the second surface portion of the package substrate and a second sensitive device region corresponding to the first surface portion of the package substrate and offsetting a memory input/output (I/O) electrical path of the memory die, as viewed from a top-view perspective. | 2018-03-01 |
20180061787 | Semiconductor Package - A semiconductor device is disclosed. The semiconductor device comprises a redistribution structure, a processor die, and a metal post. The metal post has a first end, and a second end. The metal post is connected to the redistribution structure at the first end. The first end has a first width. The second end has a second width. The metal post has a waist width. The first width is greater than the waist width. The second width is greater than the waist width. The metal post has a side surface. The side surface is inwardly curved or outwardly curved. | 2018-03-01 |
20180061788 | CHIP PACKAGE ARRAY, AND CHIP PACKAGE - A chip package array including a plurality of chip packages is provided. The chip packages are suitable for array arrangement to form the chip package array. Each of the chip packages includes a redistribution structure, a supporting structure, a chip, and an encapsulated material. The supporting structure is disposed on the redistribution structure and has an opening. The chip is disposed on the redistribution structure and located in the opening. The encapsulated material is located between the opening and the chip, wherein the encapsulated material is filled between the opening and the chip, and the chip and the supporting structure are respectively connected to the redistribution structure. | 2018-03-01 |
20180061789 | ELECTRONIC STRUCTURE, AND ELECTRONIC STRUCTURE ARRAY - An electronic structure is provided with a redistribution structure and the following elements. A first supporting structure has a first opening and is disposed on a first surface of the redistribution structure. A second supporting structure has a second opening and is disposed on a second surface of the redistribution structure opposite to the first surface. A first bonding protruding portions are disposed on the first surface of the redistribution structure and located in the first opening. A second bonding protruding portions are disposed on the second surface of the redistribution structure and located in the second opening. A first encapsulated material is filled between the first opening and the first bonding protruding portions. A second encapsulated material is filled between the second opening and the second bonding protruding portions. An electronic structure array is also provided. | 2018-03-01 |
20180061790 | ELECTRONIC STRUCTURE PROCESS - An electronic structure process includes the following steps. A redistribution structure and a carrier plate are provided. A plurality of first bonding protruding portions and a first supporting structure are formed on the redistribution structure. A first encapsulated material is formed and filled between a first opening and the first bonding protruding portions. The carrier plate is removed. A plurality of second bonding protruding portions and a second supporting structure are formed on the redistribution structure. A second encapsulated material is formed and filled between a second opening and the second bonding protruding portions. | 2018-03-01 |
20180061791 | SEMICONDUCTOR COPPER METALLIZATION STRUCTURE AND RELATED METHODS - Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip. | 2018-03-01 |
20180061792 | UBM (UNDER BUMP METAL) ELECTRODE STRUCTURE FOR RADIATION DETECTOR, RADIATION DETECTOR AND PRODUCTION METHOD THEREOF - An UBM electrode structure body for a radiation detector and a radiation detector arranged with the UBM electrode structure body are provided for suppressing peeling and having high electrode adhesion. In addition, a manufacturing method of an UBM electrode structure body for a radiation detector and a manufacturing method of a radiation detector using the UBM electrode structure body are provided in which peeling does not occur during UBM structure formation, a solder bonding process or bonding of a signal line to a Pt layer. The UBM electrode structure body for a radiation detector of the present invention is arranged with a CdTe substrate or CdZnTe substrate and a Pt electrode layer arranged on the CdTe substrate or CdZnTe substrate, adhesion of the Pt electrode layer with respect to the CdTe substrate or the CdZnTe substrate being 0.5 N/cm or more. | 2018-03-01 |
20180061793 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure includes a substrate, a patterned solder resist layer, a plurality of solders, a chip and a polymer gel. The substrate includes a plurality of solder pads. The patterned solder resist layer is disposed on the substrate and includes a plurality of stepped openings. The stepped openings expose the solder pads respectively. The solders are disposed on the solder pads and located in the stepped openings respectively. The chip is disposed on the substrate and includes an active surface and a plurality of bond pads. The bond pads are disposed on the active surface and connected to the solder pads by the solders. The polymer gel fills between a top surface of the patterned solder resist layer and the active surface. The polymer gel at least surrounds a disposing region of the solders and fills between two adjacent solders. | 2018-03-01 |
20180061794 | FAN-OUT SEMICONDUCTOR PACKAGE - A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a second connection member disposed on the first connection member and the active surface of the semiconductor chip; a resin layer disposed on the encapsulant; and a rear redistribution layer embedded in the encapsulant so that one surface thereof is exposed by the encapsulant, wherein the resin layer covers at least portions of the exposed one surface of the rear redistribution layer, and the rear redistribution layer is electrically connected to the redistribution layer of the first connection member through connection members formed in first openings penetrating through the resin layer and the encapsulant. | 2018-03-01 |
20180061795 | FAN-OUT SEMICONDUCTOR PACKAGE - A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; and an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip. The first interconnection member includes a first insulating layer in contact with the second interconnection member, a first redistribution layer disposed on a surface of the first insulating layer in contact with the second interconnection member and electrically connected to the connection pads, and a blocking layer disposed on the surface of the first insulating layer on which the first redistribution layer is disposed and surrounding the through-hole. | 2018-03-01 |
20180061796 | METHOD OF FORMING A SOLDER BUMP STRUCTURE - A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer. | 2018-03-01 |
20180061797 | METHOD OF FORMING A SOLDER BUMP STRUCTURE - A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer. | 2018-03-01 |
20180061798 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first carrier including a first pad, a second carrier including a second pad disposed opposite to the first pad, a joint coupled with and standing on the first pad, a joint encapsulating the post and bonding the first pad with the second pad, a first entire contact interface between the first pad and the joint, a second entire contact interface between the first pad and the post, and a third entire contact interface between the joint and the second pad. The first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces. A distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface. The second entire contact interface is a continuous surface. | 2018-03-01 |
20180061799 | REDUCTION OF SOLDER INTERCONNECT STRESS - A first electrical contact and second contact is upon an interposer and/or upon a processing device. The first contact includes a minor axis and a major axis. The second contact includes diameter axes. The first contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The first electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The first electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring first electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring first electrical contacts within the electrical contact grid may differ relative thereto. | 2018-03-01 |
20180061800 | REDUCTION OF SOLDER INTERCONNECT STRESS - An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto. | 2018-03-01 |
20180061801 | FAN-OUT SEMICONDUCTOR PACKAGE MODULE - A fan-out semiconductor package module includes: a fan-out semiconductor package including a first interconnection member having a through-hole, a semiconductor chip disposed in the through-hole, an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip, a second interconnection member disposed on the first interconnection member and the semiconductor chip, a third interconnection member disposed on the encapsulant, first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the third interconnection member, the first to third interconnection members including, respectively, redistribution layers electrically connected to connection pads of the semiconductor chip; and a component package stacked on the fan-out semiconductor package and including a wiring substrate connected to the second interconnection member through the first connection terminals and a plurality of mounted components mounted on the wiring substrate. | 2018-03-01 |
20180061802 | POWER SEMICONDUCTOR DEVICE COMPRISING A SUBSTRATE AND LOAD CURRENT TERMINAL ELEMENTS - The invention relates to a power semiconductor device with a substrate with a cooling device and power semiconductor components connected thereon, having load current terminal elements and a cooling device. Pressure devices have a pressure element is arranged movably in a direction normal (N) to the substrate, and an elastic deformation element between the pressure element and a load current terminal element. The pressure element presses the assigned load current terminal element against an electrically conductive contact area of the substrate via the elastic deformation element and provides electrically conductive pressure contacting of the assigned load current terminal element with the substrate. The electrical connection of the power semiconductor device is improved. | 2018-03-01 |
20180061803 | BONDING DEVICE | 2018-03-01 |
20180061804 | METAL BONDING PADS FOR PACKAGING APPLICATIONS - Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices. | 2018-03-01 |
20180061805 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package structure includes at least one semiconductor die, at least one conductive pillar, an encapsulant and a circuit structure. The semiconductor die has an active surface. The conductive pillar is disposed adjacent to the active surface of the semiconductor die. The encapsulant covers the semiconductor die and the conductive pillar. The encapsulant defines at least one groove adjacent to and surrounding the conductive pillar. The circuit structure is electrically connected to the conductive pillar. | 2018-03-01 |
20180061806 | Semiconductor Device and Method of Forming SIP with Electrical Component Terminals Extending Out from Encapsulant - A semiconductor device has a carrier with an adhesive layer formed over the carrier. Alignment marks are provided for picking and placing the electrical component on the carrier or adhesive layer. An electrical component is disposed on the adhesive layer by pressing terminals of the electrical component into the adhesive layer. The electrical component can be a semiconductor die, discrete component, electronic module, and semiconductor package. A leadframe is disposed over the adhesive layer. A shielding layer is formed over the electrical component. An encapsulant is deposited over the electrical component. The carrier and adhesive layer are removed so that the terminals of the electrical component extend out from the encapsulant for electrical interconnect. A substrate includes a plurality of conductive traces. The semiconductor device is disposed on the substrate with the terminals of the electrical component in contact with the conductive traces. | 2018-03-01 |
20180061807 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a first substrate, a second substrate, a sealing member, a first conductive member, and a second conductive member. Electronic components are disposed on both surfaces of the first substrate. The second substrate is disposed on a surface of the first substrate. The sealing member is disposed on both surfaces of the first substrate to cover the electronic components. The first conductive member is disposed on the second substrate. The second conductive member is disposed on the sealing member connected to the first conductive member. | 2018-03-01 |
20180061808 | PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THEREOF - A package structure includes a package, at least one second molding material, and at least one electronic component. The package includes at least one first semiconductor device therein, a first molding material, at least one dielectric layer and at least one redistribution line. The first molding material is at least in contact with at least one sidewall of the first semiconductor device. The dielectric layer is over the first semiconductor device and the first molding material. The redistribution line is present at least partially in the dielectric layer and is electrically connected to the first semiconductor device. The second molding material is present on the package. The electronic component is present on the package and is external to the second molding material. | 2018-03-01 |
20180061809 | ELECTRONIC PACKAGE STRUCTURE WITH MULTIPLE ELECTRONIC COMPONENTS - An electronic package structure is provided, which includes: a first carrier having an opening; at least a first electronic component and a plurality of conductive elements disposed on the first carrier; a second carrier bonded to the conductive elements; at least a second electronic component disposed on the second carrier and received in the opening of the first carrier; and an encapsulant formed on the first carrier and the second carrier and encapsulating the first electronic component, the second electronic component and the conductive elements. By receiving the second electronic component in the opening of the first carrier, the present disclosure reduces the height of the electronic package structure. The present disclosure further provides a method for fabricating the electronic package structure. | 2018-03-01 |
20180061810 | ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME - An electronic package is provided, which includes: a first substrate; a first electronic component disposed on the first substrate; a second substrate stacked on the first substrate through a plurality of first conductive elements and a plurality of second conductive elements and bonded to the first electronic component through a bonding layer; and a first encapsulant formed between the first substrate and the second substrate. The first conductive elements are different in structure from the second conductive elements so as to prevent a mold flow of the first encapsulant from generating an upward pushing force during a molding process and hence avoid cracking of the second substrate. The present disclosure further provides a method for fabricating the electronic package. | 2018-03-01 |
20180061811 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a first chip, a second chip, a plurality of first conductive bumps, a plurality of second conductive bumps and an underfill. The first chip includes a first active surface having a chip bonding zone, a plurality of first inner pads in the chip bonding zone and a plurality of first outer pads out of the chip bonding zone. The second chip is flipped on the chip bonding zone. The first conductive bumps are disposed on the first outer pads. The second conductive bumps are disposed between the first inner pads of the first chip and a plurality of second pads of the second chip. The underfill is disposed on the first active surface and covers the second conductive bumps, at least a part of each second chip lateral and at least a part of each first conductive bump. Multiple semiconductor package manufacturing methods are further provided. | 2018-03-01 |
20180061812 | METHODS OF MANUFACTURING SEMICONDUCTOR PACKAGES - Methods of manufacturing a semiconductor package are provided. The methods may include manufacturing a semiconductor chip in a first semiconductor manufacturing environment and mounting the semiconductor chip on an upper surface of a printed circuit board. The method may also include forming a molding member in a second semiconductor manufacturing environment that is different from the first semiconductor manufacturing environment, forming a capping member including a material different from the molding member and covering an exposed outer surface of the molding member, and attaching a carrier substrate onto the capping member. The semiconductor chip may be between the printed circuit board and the carrier substrate. The method may further include forming a redistribution line layer on a lower surface of the printed circuit board in a third semiconductor manufacturing environment, forming an external connection member on the redistribution line layer, and removing the carrier substrate. | 2018-03-01 |
20180061813 | SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device package including a first encapsulation layer, a redistribution layer disposed on the first encapsulation layer, a first die disposed on the redistribution layer, a second encapsulation layer covering the first die and the redistribution layer, and an electrical connection terminal electrically connected to the redistribution layer. The first encapsulation layer has a first surface and a second surface different from the first surface. The first encapsulation layer surrounds a portion of the electrical connection terminal and exposes the electrical connection terminal. | 2018-03-01 |
20180061814 | BACKLIGHT SYSTEM AND METHOD FOR MANUFACTURING THEREOF - A backlight system includes a backlight module. The backlight module includes a light source array with a plurality of micro LEDs. The backlight module defines a plurality of lighting regions having a constant size. A number of the micro LEDs in each lighting region is random. The micro LEDs in each lighting region comprises a plurality of positive micro LEDs located in a forward manner and a plurality of negative micro LEDs located in a reverse manner. | 2018-03-01 |
20180061815 | SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package device comprises a circuit layer, an electronic component disposed on the circuit layer, a package element and a first encapsulant. The package element is disposed on the circuit layer. The package element includes at least two electrical contacts electrically connected to the circuit layer. The first encapsulant is disposed on the circuit layer. The first encapsulant encapsulates the electronic component and the package element and exposes the electrical contacts of the package element. | 2018-03-01 |
20180061816 | SEMICONDUCTOR PACKAGES - A semiconductor package is disclosed. The semiconductor package comprises a lower package including a first substrate and a semiconductor chip on the first substrate, a second substrate on the lower package, interconnect terminals between the first substrate and the second substrate, and an adhesive pattern between a top surface of the semiconductor chip and a bottom surface of the second substrate. The adhesive pattern extends along an edge of the semiconductor chip. The adhesive pattern exposes a top surface of a central zone of the semiconductor chip. | 2018-03-01 |
20180061817 | SELF-ALIGNED THREE DIMENSIONAL CHIP STACK AND METHOD FOR MAKING THE SAME - Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the first stair, wherein the at least one additional chip is vertically spaced apart from the first chip. | 2018-03-01 |
20180061818 | Semiconductor Device and Method of Manufacturing - A semiconductor device includes a first chip, a dielectric layer over the first chip, and a second chip over the dielectric layer. A conductive layer is embedded in the dielectric layer and is electrically coupled to the first chip and the second chip. The second chip includes an optical component. The first chip and the second chip are arranged on opposite sides of the dielectric layer in a thickness direction of the dielectric layer. | 2018-03-01 |
20180061819 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device includes forming a first masking layer and second masking layer over a substrate. The first masking layer includes an opening over an active area and a spacer in the substrate, and the second masking layer blocks a portion of the opening in the first masking layer. The method includes performing an etching process, using the first masking layer and the second masking layer as an etching mask, to form a contact opening which exposes a portion of the active area and a portion of the spacer, and forming a contact plug in the contact opening and over the exposed portion of the active area and the exposed portion of the spacer. | 2018-03-01 |
20180061820 | MULTI-DIE INTEGRATED CIRCUIT DEVICE WITH OVERVOLTAGE PROTECTION - An apparatus includes a package, a plurality of external connections extending outside the package, and a first die having a first electrical contact coupled to a first connection of the plurality of external connections. The apparatus also includes a second die having a second electrical contact coupled to a second connection of the plurality of external connections. A conductor is electrically coupled between the first contact and the second contact to allow electrostatic discharge current to flow between the first die to the second die. | 2018-03-01 |
20180061821 | SEMICONDUCTOR DEVICE - The present disclosure provides a semiconductor device that may improve the discharge capacity with respect to ESD without increasing the surface area of the semiconductor device. The semiconductor device includes: a first conductive portion including plural portions, each of the plural portions having a first type of conductivity, and each of the plural portions extending in a first direction and being arranged in parallel at a distance from each other in a second direction that intersects the first direction; and a second conductive portion including an island portion provided between the respective plural portions of the first conductive portion and extending in the first direction, the second conductive portion having a second type of conductivity that is different from the first type of conductivity. | 2018-03-01 |
20180061822 | SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a semiconductor integrated circuit includes: a protection circuit including a first diode whose cathode is connected to a first wiring having a power-supply voltage and whose anode is connected to a first node, and a second diode whose anode is connected to a second wiring having a reference voltage and whose cathode is connected to the first node; a protection resistor that is connected to the first node at one end thereof and is connected to a second node at the other end thereof; a buffer circuit that is connected between the first wiring and the second wiring and has an input terminal to which a voltage at the second node is input; and a switching element that is connected between the first wiring and the second node. | 2018-03-01 |
20180061823 | Semiconductor Device Having an Electrostatic Discharge Protection Structure - A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. A first isolation layer is provided over the first surface of the semiconductor body. The semiconductor device further includes an electrostatic discharge protection structure over the first isolation layer. The electrostatic discharge protection structure has a first terminal region of a first conductivity type and a second terminal region of a second conductivity type opposite to the first conductivity type. | 2018-03-01 |
20180061824 | ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE AND FABRICATING METHOD THEREOF - An electrostatic discharge protection structure and a fabricating method thereof are provided. The electrostatic discharge protection structure comprises: a substrate; multiple fin portions arranged on the substrate; a gate structure on the substrate across the fin portions, and on a portion of top surfaces and sidewalls of the fin portions; a first groove in the substrate and overlapping with a first extension pattern of the fin portions; a first doped epitaxial layer filled within the first groove, and being used as a source; a second groove in the substrate and overlapping with a second extension pattern of the fin portions; and a second doped epitaxial layer filled within the second groove, and being used as a drain. | 2018-03-01 |
20180061825 | ELECTROSTATIC PROTECTION CIRCUIT, DISPLAY PANEL, AND DISPLAY APPARATUS - An electrostatic protection circuit, a display panel, and a display apparatus are disclosed. The electrostatic protection circuit comprises a switch control unit, a first electrostatic storage unit configured to store charges, and a second electrostatic storage unit configured to store charges, wherein the first electrostatic storage unit has a first terminal connected to a driving line and a second terminal connected to the switch control unit, and the second electrostatic storage unit has a first terminal connected to the switch control unit and a second terminal connected to a common electrode trace. With the first electrostatic storage unit connected to the driving line and the second electrostatic storage unit connected to the common electrode trace, the electrostatic protection circuit, the display panel, and the display apparatus according to the present disclosure can prevent leakage current on the driving line from flowing into the common electrode trace or prevent leakage current on the common electrode trace from flowing into the driving line after the switch control unit is switched off, which otherwise causes voltage fluctuation on the driving line or the common electrode trace thereby affecting the display quality. | 2018-03-01 |
20180061826 | SEMICONDUCTOR DEVICE, LIQUID-DISCHARGE HEAD SUBSTRATE, LIQUID-DISCHARGE HEAD, AND LIQUID-DISCHARGE DEVICE - A semiconductor device includes a transistor connected to a terminal having a first potential, an anti-fuse element connected between the transistor and a terminal having a second potential different from the first potential, and a resistor element connected in parallel with the anti-fuse element. An electric path between the transistor and the anti-fuse element has a length smaller than a length of an electric path between the transistor and the resistor element. | 2018-03-01 |
20180061827 | SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR MODULE - A semiconductor integrated circuit includes a semiconductor substrate of a first conductivity type, a first well region of a second conductivity type formed in an upper portion of the semiconductor substrate, a second well region of the first conductivity type formed in an upper portion of the first well region, an insulating layer formed separated from the first well region on a bottom portion of the semiconductor substrate that is directly beneath the first well region, and a rear surface electrode layer formed on a bottom of the insulating layer. | 2018-03-01 |
20180061828 | HIGH QUALITY DEEP TRENCH OXIDE - An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C. | 2018-03-01 |
20180061829 | VERTICAL FIELD EFFECT TRANSISTOR WITH UNIFORM GATE LENGTH - Fabrication of a semiconductor structure includes forming a set of two or more fins on a source/drain region formed on a substrate. A first mask layer and a second mask layer are formed on each fin. A spacer layer is formed on the source/drain region and between each fin, and a dielectric layer is formed on the spacer layer and along an exterior of each fin. A plurality of gate metal portions is created each having a thickness about equal to a target thickness. The first mask layer and an exposed portion of the dielectric layer are removed from each fin. An interlayer dielectric is deposited on the semiconductor structure. Portions of the interlayer dielectric and the gate metal are removed to a top of the second mask layer. The gate metal portions are each recessed to substantially the same depth. | 2018-03-01 |
20180061830 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication method includes providing a semiconductor substrate having a first region, a second region and an isolation region between the first region and the second region; forming a plurality of first fins on the semiconductor substrate in the first region and a plurality of second fins on the semiconductor substrate in the second region; forming an isolation structure, covering portions of side surfaces of the first fins and the second fins and with a top surface below the top surfaces of the first fins and the second fins, over the semiconductor substrate; and forming an isolation layer over the isolation structure in the isolation region and with a top surface coplanar or above the top surfaces of the first fins and the second fins. | 2018-03-01 |
20180061831 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source/drain structure, a conductor, and a contact etch stop layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure, in which the first spacer has a top portion and a bottom portion between the top portion and the substrate. The source/drain structure is present adjacent to the bottom portion of the first spacer. The conductor is electrically connected to the source/drain structure. The protection layer is present at least between the conductor and the top portion of the first spacer. The contact etch stop layer is present at least partially between the conductor and the bottom portion of the first spacer while absent between the protection layer and the top portion of the first spacer. | 2018-03-01 |
20180061832 | METHODS, APPARATUS AND SYSTEM FOR STI RECESS CONTROL FOR HIGHLY SCALED FINFET DEVICES - At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess level in a field region adjacent to a fin array region comprising a plurality of fins in a finFET device. The first oxide process comprises depositing an oxide layer over the field region and the fin array region and performing an oxide recess process to bring the oxide layer to the first oxide recess level in the field region. A second oxide process is performed for controlling a second oxide recess level in the fin array region. The second oxide process comprises isolating the fin array region, depositing oxide material, and performing an oxide recess process to bring the oxide level in the fin array region to the second oxide recess level. The first oxide recess level is within a predetermined height differential of the second oxide recess level. | 2018-03-01 |
20180061833 | SUBSTRATE CONTACT LAND FOR AN MOS TRANSISTOR IN AN SOI SUBSTRATE, IN PARTICULAR AN FDSOI SUBSTRATE - A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land. | 2018-03-01 |
20180061834 | Memory Cells and Memory Arrays - Some embodiments include a memory cell having first and second transistors and first and second capacitors. The first capacitor is vertically displaced relative to the first transistor. The first capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a common plate structure, and a first capacitor dielectric material between the first and second nodes. The second capacitor is vertically displaced relative to the second transistor. The second capacitor has a third node electrically coupled with a source/drain region of the second transistor, a fourth node electrically coupled with the common plate structure, and a second capacitor dielectric material between the first and second nodes. Some embodiments include memory arrays having 2T-2C memory cells. | 2018-03-01 |
20180061835 | Memory Cells and Memory Arrays - Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. | 2018-03-01 |
20180061836 | Memory Cells and Memory Arrays - Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor. | 2018-03-01 |
20180061837 | Memory Cells and Memory Arrays - Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor. | 2018-03-01 |
20180061838 | MEMORY CELL - A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion. | 2018-03-01 |
20180061839 | SEMICONDUCTOR DEVICE STRUCTURE WITH SELF-ALIGNED CAPACITOR DEVICE - A semiconductor device structure is disclosed including a semiconductor-on-insulator (SOI) substrate, the SOI substrate comprising a semiconductor layer, a substrate material and a buried insulating material layer positioned between the semiconductor layer and the substrate material, a trench isolation structure positioned in at least a portion of the SOI substrate, the trench isolation structure defining a first region in the SOI substrate, and a capacitor device formed in the first region, the capacitor device comprising a first electrode formed by a conductive layer portion formed in the first region on the buried insulating material layer, the conductive layer portion at least partially replacing the semiconductor layer in the first region, a second electrode formed over the first electrode, and an insulating material formed between the first electrode and the second electrode. | 2018-03-01 |
20180061840 | Memory Cells, Methods Of Forming An Array Of Two Transistor-One Capacitor Memory Cells, And Methods Used In Fabricating Integrated Circuitry - A memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and second transistors. The capacitor comprises a container-shape conductive first capacitor node electrically coupled with a first current node of the first transistor, a conductive second capacitor node electrically coupled with a first current node of the second transistor, and a capacitor dielectric material between the first capacitor node and the second capacitor node. The capacitor dielectric material extends across a top of the container-shape first capacitor node. Additional embodiments and aspects, including method, are disclosed. | 2018-03-01 |
20180061841 | MEMORY METAL SCHEME - A method of fabricating a memory array includes designing first layout sections in a row direction, each first layout section including first and second control lines in a first metal layer, and an upper conductive line in a third metal layer. A lower conductive line in a second metal layer is coupled to the first control line and the first control line is isolated from the second control line. A second layout section is inserted at every N-th first layout section, N being a positive integer equal to or greater than 2. The second layout section includes the first control line, the second control line and a lower conductive line in the second metal layer coupled to the second control line and to an upper conductive line in the third metal layer. The lower conductive lines in the first and second layout sections are isolated from each other. | 2018-03-01 |
20180061842 | DEVICES WITH CONTACT-TO-GATE SHORTING THROUGH CONDUCTIVE PATHS BETWEEN FINS AND FABRICATION METHODS - Semiconductor devices and methods of fabricating the semiconductor devices for forming conductive paths between fins for contact-to-gate shorting. One method includes, for instance: obtaining wafer with a substrate, at least one fin, at least one hard mask, and an oxide layer; etching the oxide layer to reveal at least one of a portion of the hard masks; forming sacrificial pillars over the substrate; forming sacrificial gates, wherein at least one sacrificial gate contacts at least one sacrificial pillar; growing an epitaxial layer between the at least one sacrificial gate and the at least one sacrificial pillar; starting a RMG process on the sacrificial gates; etching to remove the sacrificial pillars and form pillar openings; and completing the RMG process to fill the pillar openings and the gate openings with a metal. | 2018-03-01 |
20180061843 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions. | 2018-03-01 |
20180061844 | VERTICAL FIELD EFFECT TRANSISTOR INCLUDING INTEGRATED ANTIFUSE - A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate. | 2018-03-01 |
20180061845 | VERTICAL FIELD EFFECT TRANSISTOR INCLUDING INTEGRATED ANTIFUSE - A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate. | 2018-03-01 |
20180061846 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - Semiconductor devices and fabrication methods thereof are provided. An exemplary semiconductor device includes at least one FinFET device. The FinFET device includes a substrate, a plurality of fins protruding from the substrate, at least one gate structure on the substrate and across the plurality of fins by covering portions of side and top surfaces of the plurality of fins, and source/drain regions formed in the plurality of fins at two sides of the gate structure. The semiconductor device also includes a Fuse device formed above the FinFET device. The Fuse device includes a positive terminal and a negative terminal. The negative terminal is electrically connected to at least one source region of the FinFET device and the positive terminal is electrically connected to an external pad. Further, the semiconductor device also includes a dielectric layer formed between the FinFET device and the Fuse device. | 2018-03-01 |
20180061847 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A memory device includes a substrate. An insulation layer is disposed in a recess in the substrate. A first gate structure is disposed over the substrate and the insulation layer. A first etch stop layer is disposed over the first gate structure. A first oxide layer is disposed over the first etch stop layer. A second etch stop layer is disposed over the first oxide layer. A first contact material is surrounded by and in contact with the first gate structure, first etch stop layer, second etch stop layer, and first oxide layer. | 2018-03-01 |
20180061848 | METHOD FOR FABRICATING MEMORY DEVICE - A method for fabricating a memory device is provided. In the method, a first gate dielectric layer is formed on a substrate in a first region. A second gate dielectric layer is formed on the substrate in a second region and a third region. A first conductive layer is formed on the substrate. A first dielectric layer is directly formed on the first conductive layer. One portion of the first dielectric layer, one portion of the first conductive layer, and one portion of the second gate dielectric layer in the second region are removed. A third gate dielectric layer and a second conductive layer are formed sequentially on the substrate in the second region. A third conductive layer and a second dielectric layer are formed sequentially on the substrate. Isolation structures are formed in the substrate. Here, the isolation structures penetrate the second dielectric layer and extend into the substrate. | 2018-03-01 |
20180061849 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Performance and reliability of a semiconductor device are improved. An insulating film is formed such that a control gate electrode, a memory gate electrode, and a gate electrode are embedded, and then tops of the control gate electrode, the memory gate electrode, and the gate electrode are exposed by first polishing. Subsequently, a trench is formed by removing the gate electrode and filled with a metal film, and second polishing is performed to form a gate electrode including the metal film. The insulating film is an O | 2018-03-01 |
20180061850 | THREE-DIMENSIONAL MEMORY DEVICE WITH ANGLED WORD LINES AND METHOD OF MAKING THEREOF - A mesa structure is formed over peripheral devices on a substrate. An alternating stack of insulating layers and spacer material layers is formed over the substrate and the mesa structure. A region of the alternating stack overlying the mesa structure is removed to provide a region in which the layers in the alternating stack extend along a non-horizontal direction that is parallel to the dielectric sidewall of the mesa structure. Memory stack structures and backside contact via structures are formed through another region of the alternating stack that includes horizontally-extending portions of the layers within the alternating stack. The spacer material layers are provided as, or are replaced with, electrically conductive layers. Top surfaces of portions of the electrically conductive layers that extend parallel to the dielectric sidewall of the mesa structure can be contacted by word line contact via structures. | 2018-03-01 |
20180061851 | 3D STACKED MULTILAYER SEMICONDUCTOR MEMORY USING DOPED SELECT TRANSISTOR CHANNEL - In 3D stacked multilayer semiconductor memories including NAND and NOR flash memories, a lightly boron-doped layer is formed on top of a heavily boron-doped layer to form a select transistor, wherein the former serves as a channel of the select transistor and the latter serves as an isolation region which isolates the select transistor from a memory transistor. | 2018-03-01 |
20180061852 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of pillar portions, and an interconnection portion. The stacked body is provided on the substrate. The stacked body includes a plurality of electrode layers stacked separately from each other. The plurality of pillar portions are provided in the stacked body. The plurality of pillar portions extend in a stacking direction of the stacked body. The interconnection portion is provided in the stacked body. The interconnection portion extends in a first direction. The neighboring pillar portions are not arranged along the first direction. | 2018-03-01 |
20180061853 | STACKED SOI LATERAL BIPOLAR TRANSISTOR RF POWER AMPLIFIER AND DRIVER - An amplifier circuit including a substrate layer and a plurality of lateral bipolar junction transistors positioned entirely above the substrate. The lateral bipolar junction transistors include a plurality of monolithic emitter-collector regions coplanar to each other. Each of the emitter-collector regions is both an emitter region of a first bipolar junction transistor a collector region of a second bipolar junction transistor from the lateral bipolar junction transistors. Accordingly, the lateral bipolar junction transistors are electrically coupled in series circuit at the emitter-collector regions. | 2018-03-01 |
20180061854 | HIGH SNR PIXEL DESIGN - Display panels including mirror pixel layouts and power rail bridges are described. In an embodiment, a display panel includes a plurality of power rail bridges joining together a subset of power rails for a plurality of adjacent mirror pixels within a row of mirror pixels. | 2018-03-01 |
20180061855 | DISPLAY DEVICE - A display device can include a substrate including a display area, on which an input image is displayed, and a pad part including a convex portion and a concave portion that are alternately positioned outside the display area and have a height difference between them, and a circuit element attached to the pad part and including a bump inserted into the concave portion of the pad part. The pad part can further include a lower pad electrode electrically connected to a signal line extended from the display area, a first insulating layer disposed on the lower pad electrode in the convex portion, and an upper pad electrode disposed on the first insulating layer, connected to the lower pad electrode through a first contact hole penetrating the first insulating layer and extending into at least a portion of the concave portion. | 2018-03-01 |
20180061856 | HOLE STRUCTURE AND ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, DETECTION DEVICE AND DISPLAY DEVICE - A hole structure and a fabrication method thereof, an array substrate and a fabrication method thereof, a detection device and a display device are provided. The fabrication method of the hole structure includes: performing a first photolithography process on a first initial thin film with a pattern region of a mask to form a first thin film and a first hole located therein, and performing a second photolithography process on a second initial thin film covering the first thin film with the pattern region of the mask to form a second thin film and a second hole running through the second thin film and communicating with the first hole; a dimension of a second opening of the second hole away from a base substrate is larger than a dimension of a first opening of the second hole close to the base substrate. | 2018-03-01 |
20180061857 | DISPLAY DEVICE - According to one embodiment, a display device includes an insulating substrate, a first transistor including a first semiconductor layer of silicon and a first electrode, a first insulating layer provided above the first semiconductor layer, a second transistor including a second semiconductor layer of an oxide semiconductor, a second electrode and a conductive layer electrically connected to the second semiconductor layer, and a second insulating layer provided above the first insulating layer and the second semiconductor layer, the first electrode being electrically connected to the first semiconductor layer in a first hole, and the second electrode being in contact with the conductive layer in a second hole. | 2018-03-01 |
20180061858 | DISPLAY PANEL AND DISPLAY DEVICE INCLUDING THE SAME - Disclosed are a display panel and a display device including the same, in which each of non-display area lines, provided in an outer side among a plurality of non-display area lines connecting a driving driver to a plurality of display area lines provided in a display area, includes two electrodes electrically connected to each other with an insulation layer therebetween. | 2018-03-01 |
20180061859 | DISPLAY PANEL, METHOD FOR DRIVING THE SAME, AND DISPLAY DEVICE - The disclosure discloses a display panel, a method for driving the same, and a display device, where a control electrode is arranged on the side of an active layer of a thin film transistor away from a gate electrode, and the thickness of a buffer layer between the control electrode and the active layer is controlled so that the buffer layer is thicker than a gate insulation layer between the gate electrode and the active layer, to adjust the distance between the control electrode and the active layer to be larger than the distance between the gate electrode and the active layer; and at least when a gate off voltage is applied to the gate electrode so that the thin film transistor is switched off, a first control voltage is applied to the control electrode to vary a voltage Vg of the thin film transistor. | 2018-03-01 |
20180061860 | THIN FILM TRANSISTOR AND ORGANIC LIGHT EMITTING DIODE DISPLAY INCLUDING THE SAME - A thin film transistor includes a substrate, a semiconductor layer on the substrate, a first insulating layer covering the substrate and the semiconductor layer, a first gate electrode on the first insulating layer and overlapping the semiconductor layer, a second insulating layer covering the first gate electrode and the first insulating layer, a second gate electrode on the second insulating layer and overlapping the semiconductor layer and the first gate electrode, a third insulating layer covering the second gate electrode, a first contact hole defined in the first insulating layer, the second insulating layer and the third insulating layer, and through which a portion of the semiconductor layer is exposed, and a source electrode and a drain electrode connected to the semiconductor layer through the first contact hole. | 2018-03-01 |
20180061861 | MANUFACTURING METHOD OF DISPLAY DEVICE - A manufacturing method of a display device comprises steps: a lining layer is formed on an array substrate; a conduction layer is formed on the array substrate, wherein the conduction layer partially covers a surface of said lining layer, wherein said conduction layer refers to a second metal layer, a surface of said array substrate is also provided with a first metal layer connected with a common electrode of said array substrate and an indium tin oxide layer connected with said first metal layer, and said second metal layer is indirectly connected with said common electrode through connecting with said indium tin oxide layer; and a color filter substrate is enabled to abut pat of the conduction layer covering the surface of said lining layer, so that said conduction layer being conductive with said array substrate and said color filter substrate. | 2018-03-01 |
20180061862 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device are provided. The display panel includes a first substrate, and a second substrate. The first substrate includes active switches and conductive wires coupled with the active switches; and in a same direction, the active switch corresponding to an Nth conductive wire and the active switch corresponding to an (N−1)th conductive wire are adjacent. The active switches above are disposed in a back-to-back manner; the active switch corresponding to the Nth conductive wire and the active switch corresponding to an (N+1)th conductive wire are disposed in a face-to-face manner; a distance between the Nth conductive wire and the (N−1)th conductive wire is smaller than a distance between the Nth conductive wire and the (N+1)th conductive wire. The second substrate is disposed with a light shading layer at positions corresponding to the Nth conductive wire and the (N−1)th conductive wire. | 2018-03-01 |
20180061863 | DISPLAY DEVICE - Even when a light shielding film is provided between a transistor and a substrate, a threshold voltage of the transistor can be prevented or suppressed from being shifted. A display device includes light shielding films provided between a substrate and a semiconductor layer of a transistor including a gate electrode and the semiconductor layer. The semiconductor layer includes a source region and a drain region. Both of the light shielding films overlap the semiconductor layer when seen in a plan view, and are spaced apart from each other in a direction. | 2018-03-01 |
20180061864 | FIN-TYPE FIELD-EFFECT TRANSISTOR - This invention relates to a fin field-effect transistor semiconductor structure. The method of forming the semiconductor structure can include patterning a plurality of precursor fins on a semiconductor layer having a layer portion A and a layer portion B. The semiconductor layer can be located on a substrate. The layer portion B can be selectively etched to form B fins and a top half of precursor fins. The layer portion A can be selectively etched to form A fins and the substrate can be etched to form a bottom half of the decoupling fins. The precursor fins can be removed to expose the A fins, the decoupling fins, and the B fins. One of the A fins and the B fins can form n-type fins and the other can form p-type fins. | 2018-03-01 |
20180061865 | THIN FILM TRANSISTOR ARRAY PANEL - A thin film transistor array panel includes a substrate, a gate insulating layer, an interface layer, and a semiconductor layer. The gate insulating layer is disposed on the substrate. The interface layer is disposed on the gate insulating layer. The semiconductor layer is disposed on the interface layer. The interface layer includes a fluorinated silicon oxide. The semiconductor layer includes a p-type oxide semiconductor material. | 2018-03-01 |
20180061866 | SHIFT REGISTER AND DISPLAY DEVICE AND DRIVING METHOD THEREOF - The power consumption of a shift register or a display device including the shift register is reduced. A clock signal is supplied to a shift register by a plurality of wirings, not by one wiring. Any one of the plurality of wirings supplies a clock signal in only part of the operation period of the shift register, not during the whole operation period of the shift register. Therefore, the capacity load caused with the supply of clock signals can be reduced, leading to reduction in power consumption of the shift register. | 2018-03-01 |
20180061867 | METHODS OF PROTECTING SEMICONDUCTOR OXIDE CHANNEL IN HYBRID TFT PROCESS FLOW - Hybrid silicon TFT and oxide TFT structures and methods of formation are described. In an embodiment, a protection layer is formed over a semiconductor oxide channel layer of the oxide TFT to protect the semiconductor oxide channel layer during a cleaning operation of the silicon TFT. | 2018-03-01 |
20180061868 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE COMPRISING MULTIPLE TYPES OF THIN-FILM TRANSISTORS AND METHOD OF FABRICATING THE SAME - An OLED device includes a low-temperature poly-silicon (LTPS) thin-film transistor having a first channel layer, a first gate electrode, a first source electrode and a first drain electrode; an oxide semiconductor thin-film transistor having a second channel layer, a second gate electrode, a second source electrode and a second drain electrode; and a functional layer between the first channel layer and the first gate electrode. The second channel layer is in contact with an upper surface of the functional layer. | 2018-03-01 |
20180061869 | ELECTRONIC DEVICE AND DISPLAY DEVICE - According to one embodiment, an electronic device includes a first substrate including a first conductive layer, and a second substrate including a second conductive layer which is connected to the first conductive layer and which has a thickness larger than a thickness of the first conductive layer, a bridge line which has a thickness larger than the thickness of the first conductive layer and which is connected to the second conductive layer, and an insulating layer which is located between the second conductive layer and the bridge line. The first conductive layer, the second conductive layer and the bridge line form a coil. | 2018-03-01 |
20180061870 | THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME, ARRAY SUBSTRATE AND DISPLAY APPARATUS - A method of fabricating a TFT includes a step of forming a gate electrode, a gate insulation layer, an active layer, a source electrode, a drain electrode, a passivation layer and a connection electrode, wherein a pattern including the gate electrode, the source electrode and the drain electrode, the active layer and the gale insulation layer is formed by one patterning process, a pattern including the passivation layer and a via hole through the passivation layer is formed by one patterning process, and a pattern of the connection electrode is formed by one patterning process to electrically connect the source electrode and the drain electrode with the active layer. | 2018-03-01 |