09th week of 2018 patent applcation highlights part 70 |
Patent application number | Title | Published |
20180061871 | LIGHT-RECEIVING DEVICE HAVING AVALANCHE PHOTODIODES OF DIFFERENT TYPES - A light-receiving device includes a silicon semiconductor substrate, a plurality of first serial connections each of which includes a first avalanche photodiode (APD) and a first resistor connected in series, and a plurality of second serial connections each of which includes a second avalanche photodiode (APD) and a second resistor connected in series. The first APDs and the first resistors are formed on the silicon semiconductor substrate, and the first APDs is formed of silicon. The second APDs and the second resistors are formed on the silicon semiconductor substrate, and the second APDs is formed of a material having a smaller band gap than silicon. The plurality of first and second serial connections is connected in parallel between an anode terminal and a cathode terminal. | 2018-03-01 |
20180061872 | PHOTOELECTRIC CONVERSION DEVICE AND IMAGING SYSTEM - A photoelectric conversion device includes a photoelectric conversion portion in a silicon layer having a light-receiving surface. The silicon layer includes a P-type impurity region including a base portion having an atomic boron concentration Ba that is the highest of the portions opposite the light-receiving surface with respect to a charge accumulation region and an atomic oxygen concentration Oa, and a deep portion located opposite the charge accumulation region in the depth direction with respect to the base portion and having an atomic boron concentration Bb and an atomic oxygen concentration Ob. The impurity region satisfies Ba×Oa | 2018-03-01 |
20180061873 | SEMICONDUCTOR DEVICES - Semiconductor devices are provided. The semiconductor devices may include a substrate, a device isolation pattern in the substrate to electrically isolate a first pixel and a second pixel from each other, a conductive pattern in the device isolation pattern, and a doping layer on a side surface of the device isolation pattern. The doping layer may have a conductivity type different from a conductivity type of the substrate. | 2018-03-01 |
20180061874 | DISPLAY DEVICE WITH SEPARATION MEMBER INCLUDING STEPS - A display device includes: a substrate; a plurality of light-emission elements arranged, on the substrate, in a first direction and a second direction intersecting each other, each of the light-emission elements having a first electrode layer, an organic layer including a luminous layer, and a second electrode layer which are laminated in that order; and a separation section disposed, on the substrate, between the light-emission elements adjacent to each other in the first direction, the separation section having two or more pairs of steps. The first electrode layers in the light-emission elements are separated from each other, and the organic layers as well as the second electrode layers in the light-emission elements adjacent to each other in the first direction are separated from each other by the steps included in the separation section. | 2018-03-01 |
20180061875 | VERTICAL TRANSFER GATE TRANSISTOR AND ACTIVE CMOS IMAGE SENSOR PIXEL INCLUDING A VERTICAL TRANSFER GATE TRANSISTOR - A transfer gate transistor includes a semiconductor substrate including a charge collection source region, a portion forming a channel region and a top region forming a drain region. A trench in the substrate surrounds the top region and the portion of the substrate. A vertical insulated gate structure for the transistor is formed in the trench. The vertical insulated gate structure includes an insulating liner on sidewalls and a bottom of said trench and an electrode including an upper conductive part and a lower conductive part. A width of the upper conductive part parallel to an upper surface of the substrate increases as depth from the upper surface of the substrate increases. A thickness of the insulating liner adjacent the upper conductive part decreases as depth from the upper surface of the substrate increases. A thickness of the insulating liner adjacent the lower conductive part is substantially constant. | 2018-03-01 |
20180061876 | PHOTOSENSOR SUBSTRATE - A photosensor substrate achieves TFT property stabilization and further improvement in sensor performance. The photosensor substrate includes a substrate | 2018-03-01 |
20180061877 | PHOTODIODE GATE DIELECTRIC PROTECTION LAYER - In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method is performed by forming a gate dielectric layer over a substrate, and selectively forming a gate material over the gate dielectric layer. A gate dielectric protection layer is formed over the gate dielectric layer, and a first sidewall spacer is formed over the gate dielectric protection layer and flanking a side of the gate material. The gate dielectric protection layer continuously extends from between the first sidewall spacer and the gate dielectric layer to outside of the first sidewall spacer. | 2018-03-01 |
20180061878 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - A solid-state imaging device includes a plurality of pixels each of which includes a photoelectric conversion unit that generates charges by photoelectrically converting light, and a transistor that reads a pixel signal of a level corresponding to the charges generated in the photoelectric conversion unit. A phase difference pixel which is at least a part of the plurality of pixels is configured in such a manner that the photoelectric conversion unit is divided into a plurality of photoelectric conversion units and an insulated light shielding film is embedded in a region for separating the plurality of photoelectric conversion units, which are divided, from each other. | 2018-03-01 |
20180061879 | PHOTOELECTRIC CONVERSION APPARATUS AND CAMERA - A photoelectric conversion apparatus includes a photoelectric conversion substrate having photoelectric conversion units and a microlens array arranged above the conversion units, a light transmissive plate, a first member arranged between the photoelectric conversion substrate and the light transmissive plate, and that bonds the photoelectric conversion substrate and the light transmissive plate, and a second member arranged between the first member and the microlens array. The second member has at least one of a refractive index lower than the microlens array or a porosity higher than the microlens array. A surface on a side of the photoelectric conversion substrate of the first member has a plurality of steps from a portion over the plurality of photoelectric conversion units to a side surface of the photoelectric conversion apparatus. | 2018-03-01 |
20180061880 | Structure and Method for 3D Image Sensor - An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors. | 2018-03-01 |
20180061881 | SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER, CMOS IMAGE SENSOR INCLUDING THE SAME AND OPERATING METHOD THEREOF - A complementary metal oxide semiconductor (CMOS) image sensor includes a pixel array suitable for outputting a pixel signal corresponding to incident light; a row decoder suitable for selecting and controlling pixels in the pixel array by row lines; a tracking voltage generator suitable for generating a tracking voltage; a plurality of successive approximation register (SAR) analog-to-digital converters suitable for analog-to-digital converting a pixel signal by repeatedly performing N times (where N is a natural number representing desired resolution) a process of comparing the pixel signal generated by the pixel array with the tracking voltage generated by the tracking voltage generator and modulating the pixel signal; and a control unit suitable for controlling operations of the row decoder, the tracking voltage generator, and the plurality of SAR analog-to-digital converters. | 2018-03-01 |
20180061882 | IMAGE SENSOR - An image sensor includes a first semiconductor layer having a first semiconductor region and a first insulating region, and a second semiconductor layer under the first semiconductor layer including a second semiconductor region and a second insulating region. The first semiconductor layer includes a first transistor having first source or drain regions in the first semiconductor region and a first gate electrode in the first insulating region, a contact wiring, a first wiring layer electrically connecting the contact wiring and the first transistor, and a first junction region electrically connected to the first wiring layer. The second semiconductor layer includes a second transistor having second source or drain regions in the second semiconductor region and a second gate electrode in the second insulating region, a second wiring layer electrically connecting the contact wiring and the second transistor, and a second junction region electrically connected to the second wiring layer. | 2018-03-01 |
20180061883 | WIDE SPECTRUM OPTICAL SENSOR - An optical sensor including a semiconductor substrate; a first light absorption region formed in the semiconductor substrate, the first light absorption region configured to absorb photons at a first wavelength range and to generate photo-carriers from the absorbed photons; a second light absorption region formed on the first light absorption region, the second light absorption region configured to absorb photons at a second wavelength range and to generate photo-carriers from the absorbed photons; and a sensor control signal coupled to the second light absorption region, the sensor control signal configured to provide at least a first control level and a second control level. | 2018-03-01 |
20180061884 | X-RAY DETECTION PANEL OF X-RAY DETECTOR AND METHOD OF MANUFACTURING THE SAME - An X-ray detection panel for X-ray detectors and a method of manufacturing the same are disclosed. The X-ray detection panel includes a substrate, a photodiode disposed on the substrate and generating an electrical signal in response to light illuminating the photodiode, a first thin-film transistor disposed on the substrate and processing the electrical signal generated by the photodiode, and a second thin-film transistor disposed on the substrate and removing a residual current component accumulated in the photodiode and the first thin-film transistor. The X-ray detection panel can improve actual sensitivity and signal-to-noise ratio (SNR). | 2018-03-01 |
20180061885 | ACTUATOR DEVICE - An actuator device (AV) including a main body ( | 2018-03-01 |
20180061886 | METHODS OF FORMING MAGNETIC MEMORY CELLS, AND METHODS OF FORMING ARRAYS OF MAGNETIC MEMORY CELLS - Methods of forming a magnetic memory cell are disclosed. The method comprises forming a magnetic cell core material over a substrate, wherein forming the magnetic cell core comprises forming a first magnetic region over the substrate, forming a tunnel barrier material over the first magnetic region, and forming a second magnetic region over the tunnel barrier material. A temperature of at least one of the substrate or a wafer stage underlying the substrate is maintained at a temperature below about 0° C. and the magnetic cell core material is exposed to at least a first beam comprising one of an ion beam or a neutral beam comprising ions or elements of at least one noble gas to remove portions of the magnetic cell core material. Related magnetic memory cells and methods of forming an array of memory cells are also disclosed. | 2018-03-01 |
20180061887 | MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) WITH AN INTERCONNECT THAT GENERATES A SPIN CURRENT AND A MAGNETIC FIELD EFFECT - An MRAM cell having an MTJ stack with a free layer and an interconnect configured to generate a spin current and a magnetic field effect that is used to affect the magnetic moment of the free layer. The interconnect may comprise a Spin Hall lead. The interconnect may comprise an antiferromagnetic material. An MRAM cell array may include a plurality of bit elements each configured to store at least one bit, an interconnect coupled to the plurality of bit elements, and a transistor formed at a periphery of the MRAM cell array and configured to supply a current to the plurality of bit elements via the interconnect. The interconnect may be configured to generate a spin current and a magnetic field effect that is used to affect the magnetic moment of the free layer of each of the plurality of bit elements. | 2018-03-01 |
20180061888 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - The nonvolatile memory device includes a semiconductor substrate, a first and a second diffusion regions formed under a surface of the semiconductor substrate, a storage layer formed on the semiconductor substrate, a gate stacked on the storage layer, wherein the first diffusion region may at least one of active regions being separated by a part of the semiconductor substrate forming a channel region., wherein the second diffusion region may include an active region intersecting the gate insulating layer, wherein the storage layer may include an insulating layer or a variable resistor, and may service as a data storage layer to store data, and may be selected by a structure including the first and the second diffusion regions. | 2018-03-01 |
20180061889 | SWITCHING DEVICE, AND RESISTIVE RANDOM ACCESS MEMORY INCLUDING THE SAME AS A SELECTION DEVICE - A switching device includes a first electrode, a switching layer having a non-memory characteristic, and a second electrode that are disposed over a substrate. The switching layer includes an oxide of a first atom or a nitride of the first atom, and a second atom is doped in the oxide or the nitride. The second atom forms a trap site trapping a conductive carrier in the switching layer when a voltage having an absolute value that is smaller than an absolute value of a predetermined threshold voltage is applied between the first and the second electrodes. The second atom forms a moving path through which the conductive carrier moves between the first electrode and the second electrode when a voltage having an absolute value that is greater than an absolute value of a predetermined threshold voltage is applied between the first and the second electrodes. | 2018-03-01 |
20180061890 | SWITCHING ELEMENT, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In the cases of performing programming by forming a two-terminal-type variable resistance element on a semiconductor device, it has been difficult to control the programming, and malfunctions have often occurred. This switching element includes at least a first variable resistance element, a second variable resistance element, a first rectifying element, and a second rectifying element, one end of the first variable resistance element and one end of the second variable resistance element are respectively connected to one end of the first rectifying element and one end of the second rectifying element, and each of the rectifying elements has two terminals. | 2018-03-01 |
20180061891 | VARIABLE RESISTIVE MEMORY DEVICE - A variable resistive memory device may include a semiconductor substrate, a device layer, an upper metal interconnect, a plurality of memory cells, and an uppermost metal interconnect. The device layer may be formed on the semiconductor substrate including memory cell array regions, and may include a plurality of lower metal interconnect layers. The upper metal interconnect may be arranged on the device layer, and may include a plurality of metal patterns. The plurality of memory may be arranged over the device layer in which the upper metal interconnect is formed and are in contact with certain metal patterns selected from the metal patterns constituting the upper metal interconnect. The uppermost metal interconnect may be located over the plurality of memory cells, and may be in contact with other portion of the metal patterns constituting the upper metal interconnect. | 2018-03-01 |
20180061892 | THIN FILM TRANSISTOR ARRAY FORMED SUBSTRATE, IMAGE DISPLAY DEVICE SUBSTRATE AND MANUFACTURING METHOD OF THIN FILM TRANSISTOR ARRAY FORMED SUBSTRATE - A thin film transistor array formed substrate including a gate electrode, a gate insulation layer, a source wiring structure including a source wiring and a source electrode, a drain electrode, a pixel electrode connected to the drain electrode, a semiconductor layer formed in a stripe shape having a longitudinal side extending in a direction that the source wiring extends, and a protection layer formed to cover an entire portion of the semiconductor layer. The source wiring structure has notch portions positioned in the direction that the source wiring extends such that the notch portions overlap with the gate electrode, the source wiring has a first portion having a first width where the notch portions are formed and a second portion having a second width larger than the first width where no notch portions are formed, and the source wiring has an opening in the second portion. | 2018-03-01 |
20180061893 | FOLDABLE DISPLAY DESIGN WITH GENERALIZED LAYER MECHANICAL COMPATIBILITY - A flexible OLED display device that includes an upper module having a cover window film, a lower module, and a display module between the upper and lower modules. The display module includes an OLED and an OLED substrate. The stiffnesses of components in the display device are controlled to satisfy a particular relationship such that the bending stiffnesses of the upper and lower modules are tuned in order to position the neutral bending plane below the display module, which places the display into a state of compressive strain as opposed to zero strain. This design is suitable for a bifold flexible display in which the upper module can be folded to face itself. | 2018-03-01 |
20180061894 | Display Device and Method of Manufacturing the Same - Disclosed are a display device and a method of manufacturing the same, which prevent a reduction in an aperture ratio and occurrence of color mixing caused by a process error of a black matrix and a color filter. The display device includes a plurality of color filters, an inorganic layer covering the plurality of color filters, and a black matrix disposed on the inorganic layer between the plurality of color filters. | 2018-03-01 |
20180061895 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An OLED display device includes a substrate including a display region and a pad region, a display structure in the display region on the substrate, and a pad electrode structure in the pad region on the substrate, the pad electrode structure having a first pad electrode on the substrate, a first insulation layer covering opposite lateral portions of the first pad electrode and exposing a portion of an upper surface of the first pad electrode, a second pad electrode on the first pad electrode and on the first insulation layer, the second pad electrode having a step portion where the first pad electrode and the first insulation layer are overlapped, and a third pad electrode on the second pad electrode and on the first insulation layer, the third electrode covering the second pad electrode. | 2018-03-01 |
20180061896 | ORGANIC LIGHT-EMITTING DISPLAY PANEL AND MANUFACTURING METHOD THEREOF, AND ORGANIC LIGHT-EMITTING DISPLAY DEVICE - The present application discloses an organic light-emitting display panel and a manufacturing method thereof, and an organic light-emitting display device. The organic light-emitting display panel comprises a substrate, a first electrode layer, a second electrode layer, an organic light-emitting functional layer formed between the first electrode layer and the second electrode layer and comprising a plurality of first optical adjustment units, a plurality of second optical adjustment units and at least one light emitting layer covering a display area of the organic light-emitting display panel, and a pixel definition layer partitioning the organic light-emitting functional layer to form a pixel array comprising a first color pixel, a second color pixel and a third color pixel in an array arrangement. | 2018-03-01 |
20180061897 | Organic Light Emitting Display Having Touch Sensors and Method of Fabricating the Same, and Display Device - Disclosed is a display device comprising: a substrate comprising an active region and a non-active region; a light emitting device that emits light in the active area of the substrate; a touch sensor in the active area of the substrate that senses touch of the display device, the touch sensor including a plurality of conductive layers arranged in a stacking sequence; and a plurality of routing lines in the non-active region of the substrate that are connected to the touch sensor, each of the plurality of routing lines including a plurality of routing layers, each of the plurality of routing layers made of a same material as a corresponding one of the plurality of conductive layers included in the touch sensor, and the plurality of routing layers arranged in a same stacking sequence as the stacking sequence of the plurality of conductive layers of the touch sensor. | 2018-03-01 |
20180061898 | Organic Light Emitting Display Having Touch Sensor and Method of Fabricating the Same - Disclosed are an organic light emitting display having touch sensors, which may achieve process simplification and cost reduction, and a method of fabricating the same. The organic light emitting display includes a plurality of touch electrodes disposed on an encapsulation unit disposed so as to cover light emitting elements, the touch electrodes are formed through a low-temperature deposition process and may thus have amorphous characteristics so as to prevent damage to an organic light emitting layer during formation of the touch electrodes, and the touch electrodes are disposed on the encapsulation unit without a separate attachment process and may thus simplify the overall process and reduce manufacturing costs. | 2018-03-01 |
20180061899 | Organic Light Emitting Display Having Touch Sensor and Method of Fabricating the Same - Disclosed are an organic light emitting display having a touch sensor, which may achieve process simplification and cost reduction, and a method of fabricating the same. The organic light emitting display includes a compensation film having a flat surface and formed to cover dams forming a boundary with an organic encapsulation layer and the compensation film has a planarized surface between a region above the dams and a boundary region between the dams and the organic encapsulation layer ( | 2018-03-01 |
20180061900 | DISPLAY DEVICE - A display device in an embodiment according to the present invention includes a substrate, a plurality of wirings above the insulation surface, an interlayer insulation layer covering the plurality of wirings, a light emitting element above the interlayer insulation layer, a first inorganic insulation layer covering the light emitting element, a first detection electrode extending in a first direction above the first inorganic insulation layer, an organic insulation layer above the first inorganic insulation layer covering the first detection electrode, a second detection electrode extending in a second direction intersecting the first direction above the organic insulation layer, a second inorganic insulation layer above the organic insulation layer covering the second detection electrode, a first connection wiring electrically connecting the first detection electrode and one of the plurality of wirings, and a second connection wiring electrically connecting the second detection electrode and another one of the plurality of wirings. | 2018-03-01 |
20180061901 | ORGANIC LIGHT-EMITTING DEVICE AND DISPLAY DEVICE - The present application discloses an organic light-emitting device and a display device. The organic light-emitting device comprises an anode, a cathode, and a first blue light emitting layer, a second blue light emitting layer and a yellow light emitting layer laminated between the anode and the cathode, wherein the yellow light emitting layer is arranged between the cathode and the first blue light emitting layer, and the first blue light emitting layer is arranged between the yellow light emitting layer and the second blue light emitting layer; and the yellow light emitting layer comprises a phosphorescent material, one of the first blue light emitting layer and the second blue light emitting layer comprises a blue fluorescent material, and the other one comprises a blue thermally-activated delayed fluorescent material used as an auxiliary material between a host and a guest. | 2018-03-01 |
20180061902 | ORGANIC LIGHT-EMITTING ELEMENT AND ORGANIC LIGHT-EMITTING DISPLAY DEVICE - The present invention provides an organic light-emitting element comprising a first sub-pixel, a second sub-pixel, and a third sub-pixel, which have different colors, the organic light-emitting element comprising: a substrate; a first electrode arranged on the substrate; a second electrode arranged on the first electrode so as to face the first electrode; an organic light-emitting layer arranged between the first electrode and the second electrode, the organic light-emitting layer comprising a first organic light-emitting layer arranged on the first sub-pixel, a second organic light-emitting layer arranged on the second sub-pixel, and a third organic light-emitting layer arranged on the third sub-pixel; a hole transport layer arranged between the first electrode and the organic light-emitting layer; and a light-emitting supplement layer arranged between the hole transport layer and the organic light-emitting layer, the light-emitting supplement layer comprising a first light-emitting supplement layer, which is commonly arranged on the first sub-pixel, the second sub-pixel, and the third sub-pixel, a second light-emitting supplement layer, which is arranged on the second sub-pixel between the first light-emitting supplement layer and the second organic light-emitting layer, and a third light-emitting supplement layer, which is arranged on the third sub-pixel between the first light-emitting supplement layer and the third organic light-emitting layer. | 2018-03-01 |
20180061903 | FLEXIBLE DISPLAY APPARATUS AND METHOD OF MANUFACTURING FLEXIBLE DISPLAY APPARATUS - A flexible display apparatus and a method of manufacturing the flexible display apparatus that includes a first cover, a display panel configured to be disposed on a surface of the first cover and include a first panel configured to be divided into a first pixel part and a first driving part so as to enable the first pixel part and the first driving part to be folded on a first folding line and a second panel configured to be divided into a second pixel part and a second driving part so as to enable the second pixel part and the second driving part to be folded based on a second folding line, and a second cover configured to cover a back surface of the display panel. The first panel and the second panel are respectively folded by or on the first folding line and the second folding line to be disposed adjacent to each other so as to provide one image. | 2018-03-01 |
20180061904 | ORGANIC LIGHT-EMITTING ARRAY AND ORGANIC LIGHT-EMITTING DISPLAY DEVICE USING THE SAME - Disclosed are an organic light-emitting array and an organic light-emitting display device using the organic light-emitting array. The organic light-emitting array includes a substrate having a plurality of sub-pixels, each sub-pixel including an emission portion and a non-emission portion adjacent the emission portion; a first electrode provided on at least the emission portion and provided on a portion of the non-emission portion for each sub-pixel; a bank provided in the non-emission portion and having a positively tapered portion configured to overlap a portion of the first electrode and a negatively tapered portion configured so as not to overlap the first electrode; an organic layer provided on the first electrode and the bank; and a second electrode disposed on the organic layer over the plurality of sub-pixels. | 2018-03-01 |
20180061905 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display device that has a modified structure capable of preventing degradation of the aperture ratio and light leakage due to alignment tolerance between upper and lower substrates and a method of manufacturing the same are disclosed. The organic light-emitting display device includes a substrate including a plurality of sub-pixels, an insulation film disposed on the substrate and including recesses each having a bottom surface of a selected area and electrically isolating regions are positioned adjacent to a corresponding one of the recesses such that a pair comprising a recess and an isolation region corresponds to each of the sub-pixels. A first electrode is disposed on the bottom surface of each of the recesses in each of the sub-pixels. | 2018-03-01 |
20180061906 | DISPLAY DEVICE - Display devices are disclosed herein. In one embodiment, the display device includes a plastic substrate comprising a display area and a non-display area, and a data pad portion disposed on one side of the non-display area, with a flexible circuit board bonded thereto, the display area including a plurality of subpixels positioned on the display area, each subpixel including an organic light-emitting diode that includes an organic layer, wherein the organic layer extends continuously from one side of the display area to the other side of the display area and is arranged in a plurality of lines that are spaced apart from one another and disposed parallel to the data pad portion. | 2018-03-01 |
20180061907 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed is an organic light emitting display device including a thin film transistor on a substrate, a planarization layer on the thin film transistor, a contact hole passing through the planarization layer to expose a source or drain electrode of the thin film transistor, a first electrode on the planarization layer, the first electrode being connected to the source or drain electrode of the thin film transistor through the contact hole, a hole between the first electrode and another first electrode adjacent thereto, the hole being a recessed portion of the planarization layer, a pixel defining layer covering the first electrode passing through the contact hole and the planarization layer disposed in the hole, a light emitting layer on the first electrode and the pixel defining layer, and a second electrode on the light emitting layer. | 2018-03-01 |
20180061908 | DISPLAY DEVICE - A display device includes a substrate, a light shielding layer on the substrate, first to fourth subpixels sequentially arranged on the substrate including the light shielding layer in a horizontal direction, a first power line disposed on one side of the first subpixel and shared by the first and second subpixels, a sensing line disposed between the second subpixel and the third subpixel and shared by the first to fourth subpixels, a second power line disposed on one side of the fourth subpixel and shared by the third and fourth subpixels, first and second data lines between the first and second subpixels and third and fourth data lines between the third and fourth subpixels; and a scan line extended on the first to fourth subpixels in the horizontal direction. | 2018-03-01 |
20180061909 | DISPLAY DEVICE - An organic EL display device provided with a display portion includes a flexible base material (substrate) in which the display portion is provided, an inorganic film provided on the base material, a display element portion that is provided on the inorganic film and is provided to form the display portion, and a suppression portion that is provided outside the display portion and suppresses progression of cracking that has occurred in a peripheral portion of the base material. | 2018-03-01 |
20180061910 | Organic Light-Emitting Display Panel, Device And Method For Manufacturing The Same - Disclosed is an organic light-emitting display panel, which comprises a substrate, the substrate comprises a display region and a non-display region, wherein, the non-display region comprises: an insulating layer, which is provided on the same side as the array layer and provided with at least one groove by which the substrate is exposed; a metal layer, which comprises a first part and a second part, the first part covers the groove and contacts the substrate at the bottom of the groove, and the second part covers an outside of the groove and contacts the insulating layer; and at least one bank, contacting the second part, and wherein the bank comprises an organic material. | 2018-03-01 |
20180061911 | LIGHT-EMITTING APPARATUS, METHOD FOR FORMING LIGHT-EMITTING APPARATUS, AND DISPLAY APPARATUS - The present invention provides a light-emitting apparatus, a method for forming a light-emitting apparatus, and a display apparatus. The light-emitting apparatus comprises at least one OLED light-emitting unit and at least one quantum dot light-emitting unit, wherein the at least one quantum dot light-emitting unit and the at least one OLED light-emitting unit are arranged in series. | 2018-03-01 |
20180061912 | PACKAGE METHOD OF SUBSTRATE AND PACKAGE STURCTURE - A package structure includes a substrate and a package plate. A frame is formed of a seal glue arranged between the substrate and the package plate. An underfill is positioned inboard of the frame. The package plate has a spreading surface, and at least one groove is formed in a spreading path of the frame on the spreading surface of the package plate. | 2018-03-01 |
20180061913 | ORGANIC LIGHT EMITTING DISPLAY AND DEGRADATION SENSING METHOD THEREOF - A display and degradation sensing method, includes a display panel having a plurality of pixels that each comprise an Organic Light Emitting Diode (OLED) and Thin Film Transistor (TFT). The pixels are divided into multiple pixel groups of two or more pixels, each connected to different data lines but to the same gate and sensing lines. A gate driving circuit supplies a scan control signal to the gate line. A data driving circuit selectively supplies turn-on driving data voltage and turn-off data voltage to the data lines in sync with the scan control signal; a sensing circuit outputs (i) a first sensing value based upon an OLED threshold voltage of a sensing pixel, and (ii) a second sensing value based upon a kickback current. A sensing value correction circuit determines a final sensing value for the OLED threshold voltage based on the first sensing value and the second sensing value. | 2018-03-01 |
20180061914 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes a folding part configured to be folded, and a flat part adjacent to the folding part. The folding part includes a first pixel. The flat part includes a second pixel. The first pixel includes a first organic light emitting diode, a first driving transistor and a first control transistor. The first driving transistor includes a first semiconductor pattern. The first control transistor includes a second semiconductor pattern. The second pixel includes a second organic light emitting diode, a second driving transistor and second control transistor. The second driving transistor includes a third semiconductor pattern. The second control transistor includes a fourth semiconductor pattern. At least one of the first or second semiconductor patterns includes an oxide semiconductor or a polycrystalline silicon, and each of the third and fourth semiconductor patterns includes the other of the oxide semiconductor and the polycrystalline silicon. | 2018-03-01 |
20180061915 | ORGANIC LIGHT EMITTING DISPLAY - An organic light emitting display is disclosed. In the disclosure, only one switching TFT among TFTs constituting a pixel is implemented as an NMOS type TFT, and at least some of a driving TFT and the remaining switching TFTs are implemented as a PMOS type TFT. Therefore, the disclosure simplifies TFT process steps and provides an organic light emitting display suitable for realizing a high resolution pixel implementation. | 2018-03-01 |
20180061916 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY PANEL USING SAME - A TFT substrate for a display panel includes a substrate, a plurality of first scanning lines and a plurality of data lines thereon. A conductive layer is applied above the first scanning lines and at least one electrically insulating layer between the plurality of first scanning lines and the conductive layer. A touch sensing layer is placed above the conductive layer. The conductive layer forms a plurality of second scanning lines and a plurality of touch traces. Each touch trace is electrically coupled to the touch sensing layer. Each second scanning line is electrically coupled to one first scanning line by extending through the at least one electrically insulating layer. | 2018-03-01 |
20180061917 | DISPLAY APPARATUS HAVING REDUCED DEFECTS - Provided is a display apparatus capable of reducing generation of defects during manufacturing processes or while in use after being manufactured. The display apparatus includes a substrate including a first area including a display area, a second area spaced apart from the first area, and a bent area between the first area and the second area and connecting the first area and the second area to each other, wherein the substrate is bent about a bending axis; an inorganic insulating layer over the substrate, wherein the inorganic insulating layer includes a first opening or a first groove corresponding to the bent area and a second opening or a second groove at outside the display area to extend along at least a part of the display area; and an organic material layer at least partially filling the first opening or the first groove and the second opening or the second groove. | 2018-03-01 |
20180061918 | Organic Light Emitting Display Device - An organic light emitting display device is provided according to the present disclosure. An organic light emitting display device comprising a first planarization layer configured to planarize an upper portion of a circuit element on a substrate, an inorganic layer comprising a first out-gassing pattern on the first planarization layer, a second planarization layer configured to planarize an upper portion of the inorganic layer and a metal layer comprising a second out-gassing pattern on the second planarization layer. | 2018-03-01 |
20180061919 | DISPLAY DEVICE, DISPLAY MODULE, AND ELECTRONIC DEVICE - A display device with high luminance and excellent white balance is provided. The display device includes a first display element, a second display element, a first transistor, and a second transistor. The first display element includes a light-emitting layer and is electrically connected to the first transistor. The first transistor includes a first semiconductor film, a first gate electrode and a second gate electrode facing each other with the first semiconductor film provided therebetween, and a first source electrode and a first drain electrode over and in contact with the first semiconductor film. The second gate electrode is electrically connected to the first source electrode or the first drain electrode. The second display element includes a light-emitting layer and is electrically connected to the second transistor. The second transistor includes a second semiconductor film, and a third gate electrode and a fourth gate electrode facing each other with the second semiconductor film provided therebetween. The fourth gate electrode is electrically connected to the third gate electrode. | 2018-03-01 |
20180061920 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device. A pre first semiconductor pattern having a crystalline semiconductor material is formed on a base substrate. A pre first insulation layer is formed on the pre first semiconductor pattern. A first semiconductor pattern is formed by defining a channel region in the pre first semiconductor pattern. A pre protection layer is formed on the pre first insulation layer. A pre second semiconductor pattern including an oxide semiconductor material is formed on the pre protection layer. A pre second insulation layer is formed on the pre second semiconductor pattern. The pre second insulation layer is patterned using an etching gas such that at least a portion of the pre second semiconductor pattern is exposed. A second semiconductor pattern is formed by defining a channel region in the pre second semiconductor pattern. The pre protection layer has a material with a first etch selectivity that is different from a second etch selectivity of the second insulation layer with respect to the etching gas. | 2018-03-01 |
20180061921 | SEMICONDUCTOR DEVICE INCLUDING AN OXIDE THIN FILM TRANSISTOR - A semiconductor device includes a base substrate, a first transistor disposed on the base substrate, the first transistor including a first input electrode, a first output electrode, a first control electrode, and a first semiconductor pattern including a crystalline semiconductor, a second transistor disposed on the base substrate, the second transistor including a second input electrode, a second output electrode, a second control electrode, and a second semiconductor pattern including an oxide semiconductor, a plurality of insulating layers disposed on the base substrate, and an upper electrode disposed on the first control electrode with at least one insulating layer of the plurality of insulating layers interposed between the upper electrode and the first control electrode. The upper electrode overlaps the first control electrode and forms a capacitor with the first control electrode. | 2018-03-01 |
20180061922 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND A METHOD OF MANUFACTURING THE SAME - An organic light emitting device includes an organic light emitting diode including an anode and a cathode, a driving transistor including a first semiconductor layer, wherein the driving transistor is electrically connected to the anode of the organic light emitting diode, and a control transistor including a second semiconductor layer including a different material from the first semiconductor layer and configured to control the driving transistor. The first semiconductor layer includes a first channel part, and first and second contact parts, and the second semiconductor layer includes a second channel part, and third and fourth contact parts. One of the first and second contact parts directly contacts one of the third and fourth contact parts. | 2018-03-01 |
20180061923 | DUAL-SIDED OLED DISPLAY AND PACKAGE METHOD THEREOF - A dual-sided OLED display includes a package shell includes n transparent square box and a package cavity formed inside the package shell. An open terminal, arranged on both opposite sides of the package shell The first light-emitting display portion and the second light-emitting display portion arranged in the package cavity firmly. The dual-sided OLED display package structure includes a shell with fewer sealed opens which is produced in advance. Such a design effectively reduces the area of the package adhesive for the OLED display to further lessen the water vapor. It takes shorter time to package the OLED display so the yield increases owing to simple package. | 2018-03-01 |
20180061924 | ORGANIC EL DISPLAY DEVICE - An organic EL display device according to an embodiment of the present invention includes: an ITO layer divided and disposed in a region where a pixel opening is formed; a capacitance insulating film disposed on the ITO layer; a lower electrode disposed on the capacitance insulating film; an organic layer disposed on the lower electrode; an upper electrode disposed on the organic layer; and a planarizing member disposed so as to soften a step of a step part of the lower electrode. | 2018-03-01 |
20180061925 | DISPLAY DEVICE - A display device having a display region and a peripheral region in contact with the display region above a substrate is provided. The display region has a plurality of pixels each including a transistor, an insulating film above the transistor, a pixel electrode arranged above the insulating film and electrically connected to the transistor, and a common electrode above the insulating film, a video signal line and a gate signal line electrically connected to the transistor, and liquid crystal layer above the plurality of pixels. The peripheral region has a terminal electrically connected to the video signal line, a wiring arranged parallel to the gate wiring between the display region and the terminal, and a plurality of first electrodes above the wiring. The insulating film covers the wiring, and the wiring is electrically connected to the plurality of first electrodes via an opening in the insulating film. | 2018-03-01 |
20180061926 | ORGANIC ELECTROLUMINESCENT DEVICE AND ELECTRONIC APPARATUS - An organic electroluminescent device includes a first transistor, a power supply line layer connected to one current terminal of the first transistor, a capacitive element including a first capacitive electrode connected to a gate of the first transistor, and a second capacitive electrode, a signal line, and a pixel electrode connected to the other current terminal of the first transistor, the first capacitive electrode is provided on a layer over the gate of the first transistor, and the power supply line layer is provided on a layer between the first capacitive electrode and the signal line. | 2018-03-01 |
20180061927 | THIN FILM TRANSISTOR SUBSTRATE FOR FLAT PANEL DISPLAY - The present disclosure relates to a thin film transistor substrate for flat panel display including an organic light emitting diode display. The present disclosure provides a device comprising: a substrate; a scan line extending in a first direction on the substrate; a buffer layer on the scan line; a semiconductor layer extending in a second direction and crossing the scan line on the buffer layer; a gate insulating layer on the semiconductor layer; a gate electrode connected to the scan line, and extending in the first direction and crossing the semiconductor layer on the gate insulating layer; an intermediate insulating layer on the gate electrode; a data line crossing the scan line on the intermediate insulating layer; a source electrode branching from the data line and contacting a first side of the semiconductor layer; and a drain electrode facing the source electrode and contacting a second side of the semiconductor layer. | 2018-03-01 |
20180061928 | OLED DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - An OLED display panel is provided which can control the problem of shedding even in high definition panels. Metal wiring | 2018-03-01 |
20180061929 | TUNABLE ON-CHIP NANOSHEET RESISTOR - A method of forming an integrated circuit device having a nanosheet resistor includes forming a nanosheet structure having alternating sheets of silicon and silicon germanium. An ion implantation is performed on the nanosheet structure. A thermal anneal is performed on the nanosheet structure. A dielectric oxide is placed around the nanosheet structure. A first contact and a second contact are coupled to the nanosheet structure to form a resistor between the first contact and the second contact. Other embodiments are also described herein. | 2018-03-01 |
20180061930 | Semiconductor Device and Method for Forming Same - A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors. | 2018-03-01 |
20180061931 | MICROSTRUCTURAL ARCHITECTURE TO ENABLE STRAIN RELIEVED NON-LINEAR COMPLEX OXIDE THIN FILMS - An integrated non-linear complex oxide thin film heterostructure with a tailored microstructure architecture design and a method of fabrication thereof, inclusive, is provided. The tailored microstructure architecture design mitigates the undesirable effects of thermal strain, hence provides strain relief, which enables the desirable simultaneously achievement of a high permittivity and high dielectric Q/low dielectric loss in concert with one another. The material design and fabrication method thereof; enables enhanced performance, low cost NLCO-based tunable devices which possess desirable attributes including, but are not limited to, tunable device miniaturization, wide tunability, minimization of signal attenuation, reduced device operational power and enhanced operational range. Furthermore, the materials and related process science protocols are complementary metal oxide semiconductor compatible, scalable and affordable. | 2018-03-01 |
20180061932 | Method for Forming Trench Isolated Capacitor and Substrate Contact - An integrated trench capacitor and method for making the trench capacitor is disclosed. The method includes forming a trench in a silicon layer, forming a first dielectric on the exposed surface of the trench, performing an anisotropic etch of the first dielectric to expose silicon at the bottom of the trench, implanting a dopant into exposed silicon at the bottom of the trench, forming a first polysilicon layer over the first dielectric, forming a second dielectric over the first polysilicon layer, and forming a second polysilicon layer over the second dielectric to fill the trench. | 2018-03-01 |
20180061933 | BEOL Capacitor Through Airgap Metallization - A backend-of-the-line (BEOL) semiconductor capacitor made by method, apparatus, or computer program product, through an airgap metallization process, patterning a first electrode by removing a portion of inter-layer dielectric for a desired capacitor area, depositing a dielectric for a capacitor insulator, filling the desired capacitor area to form a second electrode, polishing and capping the second electrode, and interconnecting the first electrode and the second electrode. The manufactured product has a bottom electrode, composed of a conductor, electrically connected to upward conductive prominences; a low-K layer, above and conjoined to the bottom layer and surrounding the prominences, composed of a low-K dielectric; an isolation layer, above the low-K layer and surrounding the prominences, composed of a high-K insulator material, where modulating its material and thickness controls the capacitance; and a top electrode, composed of a conductor and electrically connected to downward prominences, where the bottom and top electrodes are interconnected. | 2018-03-01 |
20180061934 | VERTICAL MOSFET - A vertical MOSFET having a compound semiconductor layer is provided, the vertical MOSFET comprising a gate electrode, a gate insulating film provided between the gate electrode and the compound semiconductor layer, a drift region provided directly in contact with at least a part of the gate insulating film and being a part of the compound semiconductor layer, and a high resistance region provided at least in the drift region, is positioned below at least a part of the gate insulating film, and has a higher resistance value per unit length than that of the drift region. | 2018-03-01 |
20180061935 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - To prevent an intermediate region from contacting a cathode electrode even if a cathode region is partially defective. There is provided a semiconductor device with a semiconductor substrate that has a field stop region where first impurities of a first conduction type are implanted, an intermediate region that is formed on a back surface side of the field stop region and where second impurities of a second conduction type are implanted, and a cathode region of the first conduction type that is formed on a back surface side of the intermediate region. In a back surface of the semiconductor substrate, a concentration of the first impurities is higher than a concentration of the second impurities. | 2018-03-01 |
20180061936 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device, including a semiconductor layer of a first conductivity type, and a parallel pn layer formed on a surface of the semiconductor layer. The parallel pn layer includes a plurality of first semiconductor regions of the first conductivity type, and a plurality of second semiconductor regions of a second conductivity type. The first and second semiconductor regions are alternatingly arranged in a direction parallel to the surface of the semiconductor layer. Each second semiconductor region has at least one first region that is a region having a group 18 element introduced therein. | 2018-03-01 |
20180061937 | Charge Compensation Semiconductor Devices - A field-effect semiconductor device includes a semiconductor body having a first semiconductor region of a first conductivity type, a first side, an edge delimiting the semiconductor body in a direction substantially parallel to the first side, an active area, and a peripheral area arranged between the active area and the edge. A first metallization is arranged on the first side, and a second metallization is arranged opposite the first metallization and in Ohmic connection with the first semiconductor region. In the active area, the semiconductor body further includes: a plurality of drift portions of the first conductivity type alternating with compensation regions of a second conductivity type, the drift portions being in Ohmic connection with the first semiconductor region, the compensation regions being in Ohmic connection with the first metallization and having in a vertical direction perpendicular to the first side a vertical extension. | 2018-03-01 |
20180061938 | Transistor Device with High Avalanche Robustness - A transistor device includes drain, source and gate nodes, a plurality of drift and compensation cells each including a drift region of a first doping type and a compensation region of a second doping type complementary to the first doping type, and a control structure connected between the drift region of each of the drift and compensation cells and the source node. Each drift region is coupled to the drain node and each compensation region cells is coupled to the source node. A first type doping concentration N | 2018-03-01 |
20180061939 | Semiconductor Device Including Super Junction Structure - A semiconductor device of an embodiment includes transistor cells in a transistor cell area of a semiconductor body. A super junction structure in the semiconductor body includes a plurality of drift sub-regions and compensation sub-regions of opposite first and second conductivity types, respectively, and alternately arranged along a lateral direction. A termination area outside the transistor cell area between an edge of the semiconductor body and the transistor cell area includes first and third termination sub-regions of the first conductivity type, respectively. A second termination sub-region of the second conductivity type is sandwiched between the first and the third termination sub-regions along a vertical direction perpendicular to a first surface of the semiconductor body. | 2018-03-01 |
20180061940 | HIGH THERMAL BUDGET COMPATIBLE PUNCH THROUGH STOP INTEGRATION USING DOPED GLASS - A method of forming a punch through stop region in a fin structure is disclosed. The method may include forming a doped glass layer on a fin structure and forming a masking layer on the doped glass layer. The method may further include removing a portion of the masking layer from an active portion of the fin structure, and removing an exposed portion the doped glass layer that is present on the active portion of the fin structure. A remaining portion of the doped glass layer is present on the isolation portion of the fin structure. Dopant from the doped glass layer may then be diffused into the isolation portion of the fin structure to form the punch through stop region between the active portion of the fin structure and a supporting substrate. | 2018-03-01 |
20180061941 | STRUCTURE AND PROCESS TO TUCK FIN TIPS SELF-ALIGNED TO GATES - A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion. | 2018-03-01 |
20180061942 | STRUCTURE AND PROCESS TO TUCK FIN TIPS SELF-ALIGNED TO GATES - A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion. | 2018-03-01 |
20180061943 | FIELD-EFFECT TRANSISTOR (FET) DEVICES EMPLOYING ADJACENT ASYMMETRIC ACTIVE GATE / DUMMY GATE WIDTH LAYOUT - Field-Effect Transistor (FET) devices employing an adjacent asymmetric active gate/dummy gate width layout are disclosed. In an exemplary aspect, a FET cell is provided that includes a FET device having an active gate, a source region, and a drain region. The FET cell also includes an isolation structure comprising a dummy gate over a diffusion break located adjacent to one of the source region and the drain region. The FET cell has an asymmetric active gate/dummy gate width layout in that a width of the active gate is larger than a width of the adjacent dummy gate. The increased width of the active gate provides increased gate control and the decreased width of the dummy gate increases isolation from the dummy gate, thus reducing sub-threshold leakage through the dummy gate. | 2018-03-01 |
20180061944 | FORMING NANOSHEET TRANSISTORS WITH DIFFERING CHARACTERISTICS - A method of forming a transistor in an integrated circuit device can include forming a first and second nanosheet structure with alternating sheets of silicon and silicon germanium. A first and second transistor structure are constructed using the first and second nanosheet structures as first and second channels. The sheets of silicon germanium are removed from the first and second nanosheet structures. A mask is placed over the first transistor structure, leaving the second transistor structure exposed. The second channel is thinned while the first transistor is protected by the mask. Thereafter, semiconductor processing continues, with the first transistor having a thicker channel than the second transistor. | 2018-03-01 |
20180061945 | VERTICALLY ALIGNED NANOWIRE CHANNELS WITH SOURCE/DRAIN INTERCONNECTS FOR NANOSHEET TRANSISTORS - A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region. | 2018-03-01 |
20180061946 | VERTICALLY ALIGNED NANOWIRE CHANNELS WITH SOURCE/DRAIN INTERCONNECTS FOR NANOSHEET TRANSISTORS - A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region. | 2018-03-01 |
20180061947 | High Voltage Vertical Semiconductor Device with Multiple Silicon Pillars in a Racetrack Arrangement - A semiconductor device including a dummy pillar and a plurality of racetrack pillars. The dummy pillar of semiconductor material extends in a first lateral direction. The plurality of racetrack pillars, including the semiconducting material, surrounds the dummy pillar. Each of the plurality of racetrack pillars has a first linear section, which extends in the first lateral direction, and a first rounded section to form a racetrack shape. The plurality of racetrack pillars includes a first racetrack pillar and a second racetrack pillar. The first racetrack pillar is disposed proximate to the dummy pillar and the second racetrack pillar surrounds the first racetrack pillar. The first racetrack pillar is disposed between the dummy pillar and the second racetrack pillar. The semiconductor device includes a plurality of spacing regions including a first spacing region that surrounds the dummy pillar and is disposed between the first racetrack pillar and the dummy pillar. | 2018-03-01 |
20180061948 | EPITAXIAL WAFER FOR HETERO-JUNCTION BIPOLAR TRANSISTOR AND HETERO-JUNCTION BIPOLAR TRANSISTOR - An epitaxial wafer for a heterojunction bipolar transistor and a heterojunction bipolar transistor capable of reducing the resistance of the sub-collector layer without reducing the current amplification factor are provided. In an epitaxial wafer for a heterojunction bipolar transistor including a sub-collector layer made of n-type GaAs, the sub-collector layer contains n-type impurities having a covalent radius that is smaller than the covalent radius of the substitution site and n-type impurities having a covalent radius that is larger than the covalent radius of the substitution site. | 2018-03-01 |
20180061949 | COMMON CONTACT OF N++ AND P++ TRANSISTOR DRAIN REGIONS IN CMOS - Implementations of the present disclosure relate to semiconductor devices such as transistors used for amplifying or switching electronic signals. In one implementation, an integrated circuit is provided. The integrated circuit comprises a first transistor having a first conductivity type, the first transistor comprising a first gate, an first source region and a first drain region disposed on opposite sides of the first gate, and a second transistor having a second conductivity type opposite from the first conductivity type of the first transistor, the second transistor comprising a second gate, a second source region and a second drain region disposed on opposite sides of the second gate, wherein the second drain region of the second transistor is abutted against the first drain region of the first transistor. | 2018-03-01 |
20180061950 | TRANSISTOR DEVICE WITH THRESHOLD VOLTAGE ADJUSTED BY BODY EFFECT - A transistor device including a substrate, a gate structure, a first doped region, a second doped region and a body region is provided. The gate structure is disposed on the substrate. The first doped region and the second doped region are respectively disposed in the substrate at one side and another side of the gate structure. The first doped region and the second doped region have a first conductive type. The body region is disposed in the substrate at one side of the first doped region away from the gate structure. The body region has a second conductive type. The body region and the first doped region are separated by a distance, and no isolation structure exists between the body region and the first doped region. | 2018-03-01 |
20180061951 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes a first semiconductor layer of a first conductivity type provided on a front surface of a silicon carbide semiconductor substrate of the first conductivity type; a first semiconductor region of a second conductivity type; a second semiconductor region of the second conductivity type, connected with the first semiconductor region; a first electrode forming a Schottky contact with a first semiconductor layer and a first semiconductor region; and a second electrode forming an ohmic contact with the second semiconductor region. A density of the second electrode is lower at a center portion of the silicon carbide semiconductor substrate and increases toward an outer peripheral side. | 2018-03-01 |
20180061952 | CRYSTALLINE OXIDE SEMICONDUCTOR FILM, CRYSTALLINE OXIDE SEMICONDUCTOR DEVICE, AND CRYSTALLINE OXIDE SEMICONDUCTOR SYSTEM - In a first aspect of a present inventive subject matter, a crystalline oxide semiconductor film includes a crystalline oxide semiconductor that contains a corundum structure as a major component, a dopant, and an electron mobility that is 30 cm | 2018-03-01 |
20180061953 | High Voltage Laterally Diffused MOSFET with Buried Field Shield and Method to Fabricate Same - A structure includes a laterally diffused (LD) MOSFET with an n-type drift region disposed on a surface of a substrate and a p-type body region contained in the drift region. The structure further includes an n-type source region contained in the p-type body region; an n-type drain region contained in the n-type drift region; a gate electrode disposed on a gate dielectric overlying a portion of the p-type body region and the n-type drift region and an electrically conductive field shield member disposed within the n-type drift region at least partially beneath the p-type body region and generally parallel to the gate electrode. The electrically conductive buried field shield member is contained within and surrounded by a layer of buried field shield oxide and is common to both a first LD MOSFET and a second LD MOSFET that are connected in parallel. Methods to fabricate the structure are also disclosed. | 2018-03-01 |
20180061954 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device ( | 2018-03-01 |
20180061955 | ALL-AROUND GATE FIELD-EFFECT TRANSISTOR - An all-around gate field-effect transistor includes two drain-source areas supported by a semiconductor substrate. At least one channel region, surrounded with a gate insulated by a gate insulator, extends between the two drain-source areas. The at least one channel region is located above an insulating layer resting on the substrate and positioned between the two drain-source areas. This insulating layer has a thickness-to-permittivity ratio at least 2 times greater than that of the gate insulator. An extension of the insulating layer is positioned to insulate at least one of the channel regions from the semiconductor substrate. | 2018-03-01 |
20180061956 | MASKLESS METHOD TO REDUCE SOURCE-DRAIN CONTACT RESISTANCE IN CMOS DEVICES - Various methods and semiconductor structures for fabricating an FET device having Nickel atoms implanted in a silicide metal film on a source-drain contact region of the FET device thereby reducing resistance of the source-drain contact region of the FET device. An example fabrication method includes maskless blanket implantation of Nickel atoms across a semiconductor wafer. Nickel atoms can be implanted into silicide metal film of a source-drain contact region of nFET devices, pFET devices, or both, on a semiconductor wafer. Nickel atoms can be implanted into silicide metal film on a source-drain contact region of nFET devices and pFET devices. The silicide metal film on the source-drain contact region of the nFET device being a different material than the silicide metal film on the source-drain contact region of the pFET device. | 2018-03-01 |
20180061957 | ATOMIC LAYER DEPOSITION METHODS AND STRUCTURES THEREOF - A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate and a work-function metal layer is deposited over the gate dielectric layer. Thereafter, a fluorine-based treatment of the work-function metal layer is performed, where the fluorine-based treatment removes an oxidized layer from a top surface of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the fluorine-based treatment, another metal layer is deposited over the treated work-function metal layer. | 2018-03-01 |
20180061958 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES - A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction. | 2018-03-01 |
20180061959 | Purging Deposition Tools to Reduce Oxygen and Moisture in Wafers - A method includes placing a wafer in a wafer holder, placing the wafer holder on a loadport of a deposition tool, connecting the wafer holder to a front-end interface unit of the deposition tool, purging the front-end interface unit with nitrogen, and depositing a metal layer on the wafer in the deposition tool. | 2018-03-01 |
20180061960 | SILICON CARBIDE SEMICONDUCTOR BASE, METHOD OF CRYSTAL AXIS ALIGNMENT IN SILICON CARBIDE SEMICONDUCTOR BASE, AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - On a first epitaxial layer of a first conductivity type or a second conductivity type provided on a front surface of a silicon carbide substrate, a mark indicating a crystal axis direction of the silicon carbide substrate within a margin of error of one degree is provided. The mark is created on the silicon carbide substrate by forming the first epitaxial layer of the first conductivity type or the second conductivity type on the front surface of the silicon carbide substrate, detecting a stacking fault from the first epitaxial layer, and confirming the crystal axis direction of the silicon carbide substrate from the detected stacking fault. | 2018-03-01 |
20180061961 | METHOD FOR MANUFACTURING A BIPOLAR JUNCTION TRANSISTOR - Embodiments provide a method for manufacturing a bipolar junction transistor. The method comprises a step of providing a layer stack, the layer stack comprising a semiconductor substrate having a trench isolation, a base contact layer stack, wherein the base contact layer stack comprises a recess forming an emitter window, lateral spacers arranged on sidewalls of the emitter window, the lateral spacers isolating a base contact layer of the base contact layer stack; and a base layer arranged in the emitter window on the semiconductor substrate, wherein the base layer at least partially protrudes under the lateral spacers. The method further comprises a step of providing an isolation layer on the base layer. | 2018-03-01 |
20180061962 | Method for Producing a Doped Semiconductor Layer - A semiconductor device is produced by providing a semiconductor substrate, forming an epitaxial layer on the semiconductor substrate, and introducing dopant atoms of a first doping type and dopant atoms of a second doping type into the epitaxial layer. | 2018-03-01 |
20180061963 | FABRICATING METHOD OF SEMICONDUCTOR STRUCTURE - A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly. | 2018-03-01 |
20180061964 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - The reliability of a semiconductor device having a nonvolatile memory is improved. The memory cell of the nonvolatile memory is of a split gate type, and has first and second n type semiconductor regions in a semiconductor substrate, a control electrode formed over the substrate between the semiconductor regions via a first insulation film, and a memory gate electrode formed over the substrate between the semiconductor regions via a second insulation film having a charge accumulation part. The SSI method is used for write to the memory cell. During the read operation of the memory cell, the first and second semiconductor regions function as source and drain regions, respectively. The first width of the first sidewall spacer formed adjacent to the side surface of the memory gate electrode is larger than the second width of the second sidewall spacer formed adjacent to the side surface of the control gate electrode. | 2018-03-01 |
20180061965 | REPLACEMENT METAL GATE STRUCTURES - Replacement metal gate structures with improved chamfered workfunction metal and self-aligned contact and methods of manufacture are provided. The method includes forming a replacement metal gate structure in a dielectric material. The replacement metal gate structure is formed with a lower spacer and an upper spacer above the lower spacer. The upper spacer having material is different than material of the lower spacer. The method further includes forming a self-aligned contact adjacent to the replacement metal gate structure by patterning an opening within the dielectric material and filling the opening with contact material. The upper spacer prevents shorting with the contact material. | 2018-03-01 |
20180061966 | COMPOSITE SPACER ENABLING UNIFORM DOPING IN RECESSED FIN DEVICES - A semiconductor device that includes at least one fin structure and a gate structure present on a channel portion of the fin structure. An epitaxial semiconductor material is present on at least one of a source region portion and a drain region portion on the fin structure. The epitaxial semiconductor material includes a first portion having a substantially conformal thickness on a lower portion of the fin structure sidewall and a second portion having a substantially diamond shape that is present on an upper surface of the source portion and drain portion of the fin structure. A spacer present on first portion of the epitaxial semiconductor material. | 2018-03-01 |
20180061967 | CLOSELY PACKED VERTICAL TRANSISTORS WITH REDUCED CONTACT RESISTANCE - A method of forming a semiconductor device and resulting structures having closely packed vertical transistors with reduced contact resistance by forming a semiconductor structure on a doped region of a substrate, the semiconductor structure including a gate formed over a channel region of a semiconductor fin. A liner is formed on the gate and the semiconductor fin, and a dielectric layer is formed on the liner. Portions of the liner are removed to expose a top surface and sidewalls of the semiconductor fin and a sidewall of the dielectric layer. A recessed opening is formed by recessing portions of the liner from the exposed sidewall of the dielectric layer. A top epitaxy region is formed on the exposed portions of the semiconductor fin and dielectric layer such that an extension of the top epitaxy region fills the recessed opening. The top epitaxy region is confined between portions of the liner. | 2018-03-01 |
20180061968 | CONTACT STRUCTURE AND EXTENSION FORMATION FOR III-V NFET - FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions. | 2018-03-01 |
20180061969 | INTEGRATED CIRCUIT FABRICATION WITH BORON ETCH-STOP LAYER - Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer. | 2018-03-01 |
20180061970 | MAGNETIC MAJORITY GATE DEVICE - The disclosed technology relates generally to spintronics, and more particularly to a magnetic majority gate device. In one aspect, a magnetic majority gate device includes a magnetic propagation layer and at least one input transducer. The magnetic propagation layer includes a plurality of magnetic buses configured to guide propagating magnetic domain walls along longitudinal directions corresponding to elongated directions of the magnetic buses. The plurality of magnetic buses includes a plurality of input magnetic buses, where each of the input magnetic buses has a corresponding input site configured to receive a corresponding input magnetic domain wall. At least one input transducer at a corresponding input site is configured to convert a digital input electrical signal into an input magnetic domain wall, such that a magnetization state of the input magnetic domain wall corresponds to a digital logic state of the digital input electrical signal. The at least one input transducer is configured to inject an in-plane electrical current into the corresponding input magnetic bus if the digital logic state is a predetermined digital logic state. The magnetic propagation layer includes a central region at which the magnetic buses converge and are joined together, such that the central region is configured for an interaction of input magnetic domain walls guided by two or more magnetic buses. The central region includes at least one magnetic constriction configured to locally restrict propagation of propagating magnetic domain walls. | 2018-03-01 |