10th week of 2009 patent applcation highlights part 18 |
Patent application number | Title | Published |
20090057689 | LIGHT-EMITTING DEVICE - A light-emitting device includes an active region, an n-type region, a p-type region, an n-electrode and a p-electrode. The active region is formed from a semiconductor material. The semiconductor material has a tetrahedral structure and includes an impurity. The impurity creates at least two energy levels connected with the allowed transition within a band gap of the semiconductor material. The n-type and p-type regions in contact with the active region are disposed between the n-type and p-type regions. An excitation element is configured to inject an electron from the n-type region and inject a hole from the p-type region so as to generate an electron-hole pair in the active region. The active region has a thickness no less than an atomic distance of the semiconductor and no more than 5 nm. | 2009-03-05 |
20090057690 | Wafer level phosphor coating technique for warm light emitting diodes - Methods for wafer level fabricating of light emitting diode (LED) chips are disclosed with one embodiment of a method according to the present invention comprising providing a plurality of LEDs and then coating of the LEDs with a layer of first conversion material so that at least some light from the LEDs passes through the first conversion material. The light is converted to different wavelengths of light having a first conversion material emission spectrum. The LEDs are then coated with a layer of second conversion material arranged on the first layer of conversion. The second conversion material has a wavelength excitation spectrum, and at least some light from the LEDs passes through the second conversion material and is converted. The first conversion material emission spectrum does not substantially overlap with the second conversion material excitation spectrum. Methods according to the present invention can also be used in wafer level fabrication of LED chips and LED packages with pedestals for electrically contacting the LEDs through the conversion coatings. | 2009-03-05 |
20090057691 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor light emitting device and a method of manufacturing the same. The semiconductor light emitting layer comprises a first conductive type semiconductor layer, an active layer on the first conductive type semiconductor layer, and a second conductive type semiconductor layer on the active layer. The active layer comprises a quantum well layer, a quantum barrier layer, and a dual barrier layer. | 2009-03-05 |
20090057692 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided is a semiconductor light emitting device and a method for manufacturing the same. The semiconductor light emitting device comprises: a first semiconductor layer; a light emitting structure on one sided portion of the first semiconductor layer; a protection device structure on the other sided portion of the first semiconductor layer; and a first electrode layer on the protection device structure. | 2009-03-05 |
20090057693 | LIGHT-EMITTING ELEMENT ARRAY AND IMAGE FORMING APPARATUS - A light-emitting element array can be manufactured without the separation of a metal reflection layer. The light-emitting element array includes a plurality of light-emitting element portions provided on a substrate, at least one space of the spaces between adjacent light-emitting element portions being electrically separated from each other, wherein the metal reflection layer is provided on the substrate and under the plurality of light-emitting element portions, and a resistive layer for electrical separation between the light-emitting element portions is provided between the plurality of light-emitting element portions and the metal reflection layer. The plurality of light-emitting element portions are divided into a plurality of blocks. Each of the blocks includes a plurality of light-emitting portions. The electrical separation between the light-emitting portions can be made as electrical separation between adjacent light-emitting element portions in adjacent and different blocks. | 2009-03-05 |
20090057694 | LIGHT OPTOELECTRONIC DEVICE AND FORMING METHOD THEREOF - The present invention provides an optoelectronic device with an epi-stacked structure, which includes a substrate, a buffer layer that is formed on the substrate, in which the buffer layer includes a first nitrogen-containing compound layer, an II/V group compound layer is provided on the first nitrogen-containing compound layer, a second nitrogen-containing compound layer is provided on the II/V group compound layer, and a third nitrogen-containing compound layer is provided on the second nitrogen-containing compound layer, an epi-stacked stricture with a multi-layer structure is formed on the buffer layer, which includes a first semiconductor conductive layer is formed on the buffer layer, an active layer is formed on the first semiconductor conductive layer, a multi-layer structure is formed between the first semiconductor conductive layer and the active layer, and a second semiconductor conductive layer is formed on the active layer. | 2009-03-05 |
20090057695 | Nitride Semiconductor Device - A nitride semiconductor device according to the present invention sequentially includes at least an n-electrode, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The n-type semiconductor layer includes: an n-type GaN contact layer including n-type impurity-doped GaN having an electron concentration ranging from 5×10 | 2009-03-05 |
20090057696 | Light emitting diode device and manufacturing method therof - A light-emitting diode device (LED) device and manufacturing methods thereof are provided, wherein the LED device comprises a substrate, a first n-type semiconductor layer, an n-type three-dimensional electron cloud structure, a second n-type semiconductor layer, an active layer and a p-type semiconductor layer. The first n-type semiconductor layer, the n-type three-dimensional electron cloud structure, the second n-type semiconductor layer, the active layer and the p-type semiconductor layer are subsequently grown on the substrate. | 2009-03-05 |
20090057697 | LED ASSEMBLY WITH LED-REFLECTOR INTERCONNECT - The present invention provides a high output LED assembly including a heat sink ( | 2009-03-05 |
20090057698 | LIGHT EMISSION DEVICE - A light emitting apparatus | 2009-03-05 |
20090057699 | LED with Particles in Encapsulant for Increased Light Extraction and Non-Yellow Off-State Color - In one embodiment, sub-micron size granules of TiO | 2009-03-05 |
20090057700 | Light emitting element and a manufacturing method thereof - A light emitting element and a method for manufacturing the same are disclosed. In accordance with the element and the method, the dielectric thin film including the embossed pattern partially covering the sapphire substrate prevents damage of a sapphire substrate that occurs during a texturing of the sapphire substrate and a defect of an epitaxial thin film formed in a subsequent process. | 2009-03-05 |
20090057701 | Phosphor coating method for fabricating light emmitting semiconductor device and applications thereof - A phosphor coating method for fabricating a light-emitting semiconductor is provided. The phosphor coating method comprises the steps as follows: First a light emitting semiconductor wafer having a plurality of die units formed thereon is provided, and a photoresist is then formed on the light emitting semiconductor wafer to cover the die units. A pattern process is conducted to form a plurality of openings associated with the die units, whereby each die can be exposed via one of the openings. Subsequently, a compound mixed with phosphor is filled into the openings. | 2009-03-05 |
20090057702 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - The invention discloses a semiconductor light-emitting device. The semiconductor light-emitting device according to the invention includes a substrate, a multi-layer structure, at least one electrode structure, and a light reflector. The substrate has an upper surface. The multi-layer structure is formed on the upper surface of the substrate. The multi-layer structure includes a light-emitting region and at least one semiconductor material layer. The multi-layer structure also has a top surface. The at least one electrode structure is formed on the top surface of the multi-layer structure. The light reflector is formed on the top surface of the multi-layer structure. | 2009-03-05 |
20090057703 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THEREOF - A semiconductor light emitting device and a method of fabricating thereof are provided. The semiconductor light emitting device comprises: a first conductive semiconductor layer having an uneven pattern side; an active layer on the first conductive semiconductor layer; and a second conductive semiconductor layer on the active layer. | 2009-03-05 |
20090057704 | LIGHT EMITTING DIODE PACKAGE HAVING HEAT DISSIPATING SLUGS - A light emitting diode package having heat dissipating slugs is provided. The light emitting diode package comprises first and second heat dissipating slugs formed of a conductive material and spaced apart from each other; a package main body coupled to the first and second heat dissipating slugs to support the first and second heat dissipating slugs; and a light emitting diode die electrically connected to the first and second heat dissipating slugs, wherein the respective first and second heat dissipating slugs are exposed to the outside through lower and side surfaces of the package main body. As such, the first and second heat dissipating slugs can be used as external leads. | 2009-03-05 |
20090057705 | Semiconductor Element Mounting Substrate, Semiconductor Device Using the Same, and Method for Manufacturing Semiconductor Element Mounting Substrate - The invention provides a semiconductor element mounting substrate that, by virtue of an improvement in thermal conduction efficiency between the substrate and another member, can reliably prevent, for example, a light emitting element such as a semiconductor laser from causing a defective operation by heat generation of itself, by taking full advantage of high thermal conductivity of a diamond composite material. In the semiconductor element mounting substrate, a connecting surface to be connected with the light emitting element or the like is finished such that the number, per unit area, of at least either recesses or protrusions having a depth or height of 10 μm to 40 μm and a surface-direction diametrical size of 10 μm to 3 mm is 50/cm | 2009-03-05 |
20090057706 | SET OF OHMIC CONTACT ELECTRODES ON BOTH P-TYPE AND N-TYPE LAYERS FOR GAN-BASED LED AND METHOD FOR FABRICATING THE SAME - The present disclosure relates to set of a ohmic contact electrodes on both P-type and N-type layers of a GaN-based light emitting diode (LED) and a fabricating method thereof. The materials of ohmic contact electrodes on both P-type and N-type layers of a GaN-based LED are a metal combination of Cr/Pd/Au. In one embodiment, the fabricating method comprises etching out an N-type GaN layer on an epitaxial structure on a sapphire substrate, and evaporating a P-type transparent electrode layer on the P-type GaN layer, then positioning patterns of the ohmic contact electrodes on both P-type and N-type layers, and then evaporating a metal combination of a Cr layer 50 Å to 500 Å thick, a Pd layer 300 Å to 1000 Å thick and an Au layer 3000 Å to 20000 Å thick in turn on the P-type transparent electrode layer and N-type GaN layer respectively, and then annealing electrodes of the chip, on which the Cr, Pd and Au layers are evaporated in nitrogen atmosphere for 5 minutes to 20 minutes at a temperature from 200 degrees to 450 degrees. Excellent ohmic contact characteristics and better thermal stability are obtained as well as higher oxidation resistance, thus improving the reliability of diode. | 2009-03-05 |
20090057707 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor light emitting device includes: a laminated body including a first semiconductor layer, a second semiconductor layer, and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer; a first electrode provided on a first major surface of the laminated body and connected to the first semiconductor layer; and a second electrode provided on the first major surface of the laminated body and connected to the second semiconductor layer. The first electrode includes: a first region provided on the first semiconductor layer and including a first metal film; and a second region provided on the first semiconductor layer and including a second metal film, the second metal film having a higher reflectivity for light emitted from the light emitting layer than the first metal film and having a higher contact resistance with respect to the first semiconductor layer than the first metal film. | 2009-03-05 |
20090057708 | LED Light Source Having Improved Resistance to Thermal Cycling - A light source and method for making the same are disclosed. The light source includes a substrate, a die, and a cup. The substrate has a plurality of electrical traces thereon and the die includes an LED that is connected to two of the traces. The cup overlies the substrate and is filled with an encapsulant material. The die is located within the cup and is encapsulated by the substrate and the encapsulant material. The cup and encapsulant material have substantially the same coefficient of thermal expansion. The cup can include reflective sidewalls positioned to reflect light leaving the die. The cup, encapsulant and substrate can be constructed from the same material. | 2009-03-05 |
20090057709 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DIODE - A nitride semiconductor light emitting diode (LED) comprises an n-type nitride semiconductor layer; an electron emitting layer formed on the n-type nitride semiconductor layer, the electron emitting layer being composed of a nitride semiconductor layer including a transition element of group III; an active layer formed on the electron emitting layer; and a p-type nitride semiconductor layer formed on the active layer. | 2009-03-05 |
20090057710 | Insulated Gate Bipolar Transistor and Method for Manufacturing the Same - An insulated gate bipolar transistor according to an embodiment includes a first conductive type collector ion implantation area in a substrate; a second conductive type buffer layer, including a first segment buffer layer and a second segment buffer layer, on the first conductive collector ion implantation area; a first conductive type base area on the second conductive type buffer layer; a gate on the substrate at a side of the first conductive type base area; a second conductive type emitter ion implantation area in the first conductive type base area; an insulating layer on the gate; an emitter electrode electrically connected to the second conductive type emitter ion implantation area; and a collector electrode electrically connected to the first conductive collector ion implantation area. The first segment buffer layer can be aligned below a portion of the base area and can have a lower density of second conductive type ions than that of the second segment buffer layer adjacent the first segment buffer layer. | 2009-03-05 |
20090057711 | SEMICONDUCTOR DEVICE WITH A U-SHAPE DRIFT REGION - A semiconductor device with a U-shape drift region comprises a semiconductor substrate of a first conductivity type, a trench filled with an insulator material formed in a portion of a first main surface of the substrate, a cell of the device including the trench and semiconductor region surrounding the trench. The semiconductor device has at least one cell. Two device-feature regions are formed beneath the first main surface of the substrate, the first one is located at one side and the second one is located at the other side of the trench. At least a region of a second conductivity type and/or a region of metal is formed in the first device feature region and is connected to a first electrode. At least a region of a first conductivity type and/or a region of metal is formed in the second device feature region and is connected to a second electrode. Based on this invention, semiconductor devices, especially, an IGBT without tail during turning-off can be fabricated with a simple process at a low cost. | 2009-03-05 |
20090057712 | SEMICONDUCTOR DEVICE - The relationship between a distance Ls between a base layer and an n type buffer layer formed on the surface of a drift layer and the thickness t of a semiconductor substrate in contact with the drift layer is set to Ls≦t≦2×Ls. A loss upon turn-off of a high breakdown voltage semiconductor device can be reduced without deteriorating breakdown voltage characteristics. | 2009-03-05 |
20090057713 | SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR BODY - A semiconductor body includes a drift zone of a first conduction type. A body zone of a second conduction type complementary to the first conduction type is located near the surface in the semiconductor body. The semiconductor body includes a near-surface field stop zone of the second complementary conduction type and doped more lightly than the body zone. | 2009-03-05 |
20090057714 | THYRISTOR AND METHODS FOR PRODUCING A THYRISTOR - A thyristor having a semiconductor body in which a p-doped emitter, an n-doped base, a p-doped base and an n-doped main emitter are arranged successively in a vertical direction starting from a rear face toward a front face. For buffering of the transient heating, a metallization is applied to the front face and/or to the rear face and includes at least one first section which has an area-specific heat capacity of more than 50 J·K | 2009-03-05 |
20090057715 | SCR CONTROLLED BY THE POWER BIAS - A composite dual SCR circuit that acts to protect the Vcc node as well as an I/O node or pin. The dual SCR uses the Vcc to control or program the triggering point of the SCR connected to an I/O node. When Vcc is low, the SCR protecting an I/O node triggers a few volts above ground, but when Vcc is high the trigger point of the SCR protecting the I/O node is much higher. The dual SCR incorporates added diffusions to an existing first SCR structure between the power node and the ground node thereby forming a second SCR. The first and second SCRs share a common cathode transistor. In one illustrative embodiment, only one SCR is constructed incorporating the Vcc to control the triggering of the SCR. | 2009-03-05 |
20090057716 | Epitaxial surge protection device - A surge protection device with small-area buried regions ( | 2009-03-05 |
20090057717 | Low capacitance semiconductor device - A surge protection device with small-area buried regions ( | 2009-03-05 |
20090057718 | High Temperature Ion Implantation of Nitride Based HEMTS - A method is disclosed for forming a high electron mobility transistor. The method includes the steps of implanting a Group III nitride layer at a defined position with ions that when implanted produce an improved ohmic contact between the layer and contact metals, with the implantation being carried out at a temperature higher than room temperature and hot enough to reduce the amount of damage done to the Group III nitride layer, but below a temperature at which surface problems causing leakage at the gate or epitaxial layer dissociation would occur. An ohmic contact selected from the group consisting of titanium, aluminum, nickel and alloys thereof is added to the implanted defined position on the Group III nitride layer. | 2009-03-05 |
20090057719 | COMPOUND SEMICONDUCTOR DEVICE WITH MESA STRUCTURE - A compound semiconductor device having mesa-shaped element region, and excellent characteristics are provided. The compound semiconductor device has: an InP substrate; an epitaxial lamination mesa formed above the InP substrate and including a channel layer, a carrier supply layer above the channel layer and a contact cap layer above the carrier supply layer; ohmic source electrode and drain electrode formed on the cap layer; a recess formed by removing the cap layer between the source and drain electrodes, and exposing the carrier supply layer; an insulating film formed on the cap layer and retracted from an edge of the cap layer away from the recess; a gate electrode extending from the carrier supply layer in the recess to outside of the mesa; and air gap formed by removing side portion of the channel layer facing the gate electrode outside the mesa. | 2009-03-05 |
20090057720 | Field-Effect Semiconductor Device, and Method of Fabrication - A HEMT-type field-effect semiconductor device has a main semiconductor region comprising two layers of dissimilar materials such that a two-dimensional electron gas layer is generated along the heterojunction between the two layers. A source and a drain electrode are placed in spaced positions on a major surface of the main semiconductor region. Between these electrodes, a gate electrode is received in a recess in the major surface of the main semiconductor region via a p-type metal oxide semiconductor film whereby a depletion zone is normally created in the electron gas layer, with a minimum of turn-on resistance and gate leak current. | 2009-03-05 |
20090057721 | SEMICONDUCTOR DEVICE, EPITAXIAL WAFER, AND METHOD OF MANUFACTURING THE SAME - A manufacturing method and a semiconductor device produced by the method are provided, in which the semiconductor device can easily be manufactured while the hydrogen concentration is decreased. An N-containing InGaAs layer | 2009-03-05 |
20090057722 | Semiconductor device - There is provided a semiconductor device formed of a highly integrated high-speed CMOS inverter coupling circuit using SGTs provided on at least two stages. A semiconductor device according to the present invention is formed of a CMOS inverter coupling circuit in which n (n is two or above) CMOS inverters are coupled with each other, each of the n inverters has: a pMOS SGT; an nMOS SGT, an input terminal arranged so as to connect a gate of the pMOS SGT with a gate of the nMOS SGT; an output terminal arranged to connect a drain diffusion layer of the pMOS SGT with a drain diffusion layer of the nMOS SGT in an island-shaped semiconductor lower layer; a pMOS SGT power supply wiring line arranged on a source diffusion layer of the pMOS SGT; and an nMOS SGT power supply wiring line arranged on a source diffusion layer of the NMOS SGT, and an n−1th output terminal is connected with an nth input terminal. | 2009-03-05 |
20090057723 | SEMICONDUCTOR DEVICE - A semiconductor device including a plurality of semiconductor elements, a substrate on which the plurality of semiconductor elements are mounted, the substrate also having a plurality of terminals for connecting to external equipment, a fuse mounted on the outside of a mounting area of the plurality of semiconductor elements and mounted on a surface of the substrate near a power supply terminal among the plurality of terminals, and the power supply terminal and the plurality of semiconductor elements are connected via the fuse. | 2009-03-05 |
20090057724 | IMAGE SENSOR AND SENSOR UNIT - An image sensor includes a charge storage portion for storing and transferring signal charges, a first electrode for forming an electric field storing the signal charges in the charge storage portion, a charge increasing portion for increasing the signal charges stored in the charge storage portion and a second electrode for forming another electric field increasing the signal charges in the charge increasing portion, wherein the quantity of the signal charges storable in the charge storage portion is not less than the quantity of the signal charges storable in the charge increasing portion. | 2009-03-05 |
20090057725 | Image Sensor and Manufacturing Method Thereof - Disclosed is an image sensor. The image sensor includes a semiconductor substrate including a lower interconnection, a plurality of upper interconnection sections protruding upward from the semiconductor substrate, a first trench disposed between the upper interconnection sections such that the upper interconnection sections are spaced apart from each other, a bottom electrode disposed on an outer peripheral surfaces of the upper interconnection sections, a first conductive layer disposed on an outer peripheral surface of the bottom electrode, an intrinsic layer disposed on the semiconductor substrate including the first conductive layer and the first trench, and having a second trench on the first trench, a second conductive layer disposed on the intrinsic layer and having a third trench on the second trench, a light blocking part disposed in the third trench, and a top electrode disposed on the light blocking part and the second conductive layer. | 2009-03-05 |
20090057726 | Manufacturing method of semiconductor device, semiconductor device, and electronic device - An embrittlement layer is formed in a single crystal semiconductor substrate having a (110) plane as a main surface by irradiation of the main surface with ions, and an insulating layer is formed over the main surface of the single crystal semiconductor substrate. The insulating layer and a substrate having an insulating surface are bonded, and the single crystal semiconductor substrate is separated along the embrittlement layer to provide a single crystal semiconductor layer having the (110) plane as a main surface over the substrate having the insulating surface. Then, an n-channel transistor and a p-channel transistor are formed so as to each have a <110> axis of the single crystal semiconductor layer in a channel length direction. | 2009-03-05 |
20090057727 | Integrated Circuit Using Complementary Junction Field Effect Transistor and MOS Transistor in Silicon and Silicon Alloys - This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices. | 2009-03-05 |
20090057728 | DYNAMIC RANDOM ACCESS MEMORY HAVING JUNCTION FIELD EFFECT TRANSISTOR CELL ACCESS DEVICE - A dynamic random access memory (DRAM) device can include a plurality of memory cells. Each memory cell can include a charge storing structure and an access device comprising an enhancement mode junction field effect transistor (JFET). The DRAM device can further include a plurality of sense amplifiers that each generates an output value in response to a signal received at respective sense amplifier inputs, and a plurality of bit lines, each bit line coupling a plurality of memory cells to at least one input of at least one of the sense amplifiers. A method can fabricate such DRAM devices. | 2009-03-05 |
20090057729 | SEMICONDUCTOR DEVICE AND METHODS FOR FABRICATING SAME - A semiconductor device is provided which includes a substrate including an inactive region and an active region, a gate electrode structure having portions overlying the active region, a compressive layer overlying the active region, and a tensile layer overlying the inactive region and located outside the active region. The active region has a lateral edge which defines a width of the active region, and a transverse edge which defines a length of the active region. The gate electrode structure includes: a common portion spaced apart from the active region; a plurality of gate electrode finger portions integral with the common portion, and a plurality of fillet portions integral with the common portion and the gate electrode finger portions. A portion of each gate electrode finger portion overlies the active region. The fillet portions are disposed between the common portion and the gate electrode finger portions, and do not overlie the active region. The compressive layer also overlies the gate electrode finger portions, and the tensile layer is disposed adjacent the transverse edge of the active region. | 2009-03-05 |
20090057730 | METHODS FOR FORMING SELF-ALIGNED BORDERLESS CONTACTS FOR STRAIN ENGINEERED LOGIC DEVICES AND STRUCTURE THEREOF - A method for forming a borderless contact for a semiconductor FET (Field Effect Transistor) device, the method comprising, forming a gate conductor stack on a substrate, forming spacers on the substrate, such that the spacers and the gate conductor stack partially define a volume above the gate conductor stack, wherein the spacers are sized to define the volume such that a stress liner layer deposited on the gate conductor stack substantially fills the volume, depositing a liner layer on the substrate, the spacers, and the gate conductor stack, depositing a dielectric layer on the liner layer, etching to form a contact hole in the dielectric layer, etching to form the contact hole in the liner layer, such that a portion of a source/drain diffusion area formed in the substrate is exposed and depositing contact metal in the contact hole. | 2009-03-05 |
20090057731 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a MOS transistor, a structure of trenches or fins arranged in parallel to a gate length direction is formed in a stepwise manner along a gate width direction to thereby reduce a step height of each step. Even if the MOS transistor includes a deep trench or a high fin in order to increase driving performance per unit area, a uniform impurity concentration in a channel region, a source diffusion layer, and a drain diffusion layer can be made by an ion implantation method. Accordingly, there can be obtained a stable characteristic that variation in the characteristic due to a surface on which the channel is formed does not appear, and a lateral MOS transistor with high driving performance having a reduced on-resistance per unit area can be provided. | 2009-03-05 |
20090057732 | CMOS IMAGE SENSOR AND FABRICATING METHOD THEREOF - A CMOS image sensor and a fabricating method for a semiconductor device are disclosed. Embodiments provide a CMOS image sensor having an improved structure using a light reflection system, with a fabricating method thereof to simplify the fabrication process and maximize a light receiving area. Embodiments may be applied to a semiconductor device having a lamination structure. | 2009-03-05 |
20090057733 | Image Sensor and a Method for Manufacturing the Same - An image sensor and manufacturing method thereof are provided. A semiconductor substrate can include a light blocking region and a light receiving region. A photodiode can be formed in the light blocking region and in the light receiving region. A gate can be disposed at a side of the photodiode in the light receiving region, and a light blocking gate can be disposed on the photodiode in the light blocking region. A salicide layer can be formed on the light blocking gate. | 2009-03-05 |
20090057734 | IMAGE SENSOR - An image sensor includes a photoelectric conversion portion generating signal charges, a first electrode for forming an electric field transferring the signal charges generated by the photoelectric conversion portion, formed to be adjacent to the photoelectric conversion portion; and a second electrode for forming an electric field transferring the signal charges, provided on a side opposite to the photoelectric conversion portion with respect to the first electrode and formed to partially extend on the first electrode. | 2009-03-05 |
20090057735 | Image sensor having reduced dark current - An image sensor includes a light receiving device, a field effect transistor, a stress layer pattern, and a surface passivation material. The light receiving device is formed in a first region of a substrate. The field effect transistor is formed in a second region of the substrate. The stress layer pattern is formed over the field effect transistor for creating stress therein to improve transistor performance. The surface passivation material is formed on the first region of the substrate for passivating dangling bonds at the surface of the light receiving device. | 2009-03-05 |
20090057736 | Semiconductor Device Having Reduced Single Bit Fails and a Method of Manufacture Thereof - One aspect of the invention provides a method of manufacturing a FeRAM semiconductor device having reduce single bit fails. This aspect includes forming an electrical contact within a dielectric layer located over a semiconductor substrate and forming a first barrier layer over the dielectric layer and the electrical contact. The first barrier layer is formed by depositing multiple barrier layers and densifying each of the barrier layers after its deposition. This forms a stack of multiple barrier layers of a same elemental composition. The method further includes forming a second barrier layer over the first barrier layer and forming a lower capacitor electrode, a ferroelectric dielectric layer over the lower capacitor, and forming an upper capacitor electrode over the ferroelectric dielectric layer. A device made by this method is also provided herein. | 2009-03-05 |
20090057737 | INTEGRATED CIRCUIT WITH DIELECTRIC LAYER - A method of fabricating an integrated circuit with a dielectric layer on a substrate is disclosed. One embodiment provides forming the dielectric layer in an amorphous state on the substrate, the dielectric layer having a crystallization temperature; a doping the dielectric layer; a forming of a covering layer on the dielectric layer at a temperature being equal to or below the crystallization temperature; and a heating of the dielectric layer to a temperature being equal to or greater than the crystallization temperature. | 2009-03-05 |
20090057738 | CAPACITOR FOR SEMICONDUCTOR DEVICE - A capacitor for a semiconductor device having a dielectric film between an upper electrode and a lower electrode is featured in that the dielectric film includes an alternately laminated film of hafnium oxide and titanium oxide at an atomic layer level. | 2009-03-05 |
20090057739 | Ge channel device and method for fabricating ge channel device - The Ge channel device comprises: a Ge channel layer ( | 2009-03-05 |
20090057740 | Memory with surface strap - A memory with a surface strap. The memory comprises a trench capacitor, a self-aligned surface strap and a MOS transistor. The trench capacitor is formed in a semiconductor substrate. The self-aligned surface strap covers an opening of the trench capacitor and a active region in the periphery thereof. One of the source/drain regions of the MOS transistor is connected to the surface strap and the other is connected to a bit line. | 2009-03-05 |
20090057741 | Dram cell with enhanced capacitor area and the method of manufacturing the same - A dynamic random access memory (DRAM) cell and the method of manufacturing the same are provided. The DRAM cell includes a cell transistor and a cell capacitor. The cell capacitor includes a first, second and third dielectric layer, and a first, second and third capacitor electrode. The first dielectric layer is located on a first capacitor electrode. The second capacitor electrode is located on top of the first dielectric layer. The second dielectric layer is located on the second capacitor electrode. The third capacitor electrode is located on the second dielectric layer and is electrically connected with the drain. The third dielectric layer is located between the third capacitor electrode and the gate for isolating the gate from the third capacitor electrode. | 2009-03-05 |
20090057742 | CMOS VARACTOR - A varactor and method of fabricating the varactor. The varactor includes a silicon body in a silicon layer of an SOI substrate; a polysilicon electrode comprising a gate region and a plate region separated from the body by a gate dielectric layer, the gate and plate regions contiguous, the electrode electrically connected to a first pad; and a source formed in the body on a first side of the gate region, a drain formed in the body on a second and opposite side of the gate region, and a body contact formed in the body on a side of the plate region away from the gate region, the source, drain and body contact, separated from each other by regions of the body under the electrode, the source, drain and body contact electrically connected to each other and to a second pad. | 2009-03-05 |
20090057743 | Integrated Circuit Including Structures Arranged at Different Densities and Method of Forming the Same - A method of forming an integrated circuit includes forming first structures in a first portion of the integrated circuit and forming second structures, which are arranged more densely than the first structures, in a second portion. The first and second structures are defined by lithography processes using photomasks. At least one of the photomasks includes both openings in a first region for supporting the definition of the first structures and openings in a second region for supporting the definition of the second structures. | 2009-03-05 |
20090057744 | THICKENED SIDEWALL DIELECTRIC FOR MEMORY CELL - Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area. | 2009-03-05 |
20090057745 | Inverted nonvolatile memory device, stack module, and method of fabricating the same - Example embodiments provide a nonvolatile memory device that may be integrated through stacking, a stack module, and a method of fabricating the nonvolatile memory device. In the nonvolatile memory device according to example embodiments, at least one bottom gate electrode may be formed on a substrate. At least one charge storage layer may be formed on the at least one bottom gate electrode, and at least one semiconductor channel layer may be formed on the at least one charge storage layer. | 2009-03-05 |
20090057746 | SEMICONDUCTOR DEVICE - A semiconductor device having a passive element whose characteristic is adjustable even after manufacture by applying back bias voltage is provided. Formed on a main surface of a SOI substrate comprising a supporting substrate, a BOX layer, and an SOI layer is a MOS varactor comprising a gate dielectric formed on a surface of the SOI layer, a gate electrode formed on the gate dielectric, and a n | 2009-03-05 |
20090057747 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device including a floating gate formed on a tunnel oxide layer that is formed on a semiconductor substrate. The device also includes a drain region formed in the substrate adjacent to one side of the floating gate, a source region formed in the substrate adjacent to another side of the floating gate, where the source region is apart from the floating gate, and an inter-gate insulating layer formed on a portion of an active region between the source region and the floating gate and on a sidewall of the floating gate directing toward the source region, as well as on a sidewall of the floating gate directing toward the drain region. The device includes a word line formed over the floating gate and being across the substrate in one direction, and a field oxide layer interposing between the word line and the source region and between the word line and the drain region, and intersecting the word line. | 2009-03-05 |
20090057748 | Memory and manufacturing method thereof - A memory and a manufacturing method thereof are provided. The memory includes a dielectric layer, a polysilicon layer, a first buried diffusion, a second buried diffusion, a charge storage structure and a gate. The polysilicon layer is disposed on the dielectric layer and electrically connected to at least a voltage. The first buried diffusion and the second buried diffusion are separately disposed in the surface of the polysilicon layer. The charge storage structure is disposed on the polysilicon layer and positioned between the first buried diffusion and the second buried diffusion. The gate is disposed on the charge storage structure. | 2009-03-05 |
20090057749 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory cell includes a floating gate electrode, a first inter-electrode insulating film and a control gate electrode. A peripheral transistor includes a lower electrode, a second inter-electrode insulating film and an upper electrode. The lower electrode and the upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film. The first and second inter-electrode insulating films include a high-permittivity material, the first inter-electrode insulating film has a first structure, and the second inter-electrode insulating film has a second structure different from the first structure. | 2009-03-05 |
20090057750 | NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory element includes a semiconductor substrate, a source region and a drain region which are provided separately in the semiconductor substrate, a tunnel insulating layer which is provided between the source region and the drain region on the semiconductor substrate, a charge storage layer which is provided on the tunnel insulating layer, a block insulating layer which is provided on the charge storage layer and includes a crystallized lanthanum aluminate layer, and a control gate electrode which is provided on the block insulating layer. | 2009-03-05 |
20090057751 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an example of the present invention includes a semiconductor region, source/drain areas arranged separately in the semiconductor region, a tunnel insulating film arranged on a channel region between the source/drain areas, a floating gate electrode arranged on the tunnel insulating film, an inter-electrode insulating film arranged on the floating gate electrode, and a control gate electrode arranged on the inter-electrode insulating film. The inter-electrode insulating film includes La, Al and Si. | 2009-03-05 |
20090057752 | NON-VOLATILE MEMORY AND METHOD FOR MANUFACTURING THE SAME - A non-volatile memory located on a substrate is provided. The non-volatile memory includes a tunnel layer, a charge trapping composite layer, a gate and a source/drain region. The tunnel layer is located on the substrate, the charge trapping composite layer is located on the tunnel layer and the gate is located over the charge trapping composite layer. The source/drain region is located in the substrate on both sides of the tunnel layer. With the charge trapping composite layer, the non-volatile memory has relatively better programming and erasing performance and higher data retention ability. Furthermore, since there is no need to perform a thermal process in the formation of the charge trapping composite layer, thermal budget of the manufacturing process is low. | 2009-03-05 |
20090057753 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a source region and a drain region spaced from each other in a surface of a semiconductor layer, a tunnel insulating film provided on the semiconductor layer between the source region and the drain region, a charge storage film provided on the tunnel insulating film, a block insulating film provided on the charge storage film, and a control gate electrode provided on the block insulating film. The block insulating film is made of (Rm | 2009-03-05 |
20090057754 | Shielded Gate Trench FET with the Shield and Gate Electrodes Connected Together in Non-active Region - A field effect transistor (FET) includes a plurality of trenches extending into a semiconductor region. Each trench includes a gate electrode and a shield electrode with an inter-electrode dielectric therebetween. A body region extends between each pair of adjacent trenches, and source regions extend in each body region adjacent to the trenches. A first interconnect layer contacts the source and body regions. The plurality of trenches extend in an active region of the FET, and the shield electrode and gate electrode extend out of each trench and into a non-active region of the FET where the shield electrodes and gate electrodes are electrically connected together by a second interconnect layer. The electrical connection between the shield and gate electrodes is made through periodic contact openings formed in a gate runner region of the non-active region. | 2009-03-05 |
20090057755 | SPACER UNDERCUT FILLER, METHOD OF MANUFACTURE THEREOF AND ARTICLES COMPRISING THE SAME - Disclosed herein is a semiconducting device comprising a gate stack formed on a surface of a semiconductor substrate; a vertical nitride spacer element formed on each vertical sidewall of the gate stack; a portion of the vertical nitride spacer overlying the semiconductor substrate; a silicide contact formed on the semiconductor substrate adjacent the gate stack, the silicide contact being in operative communication with drain and source regions formed in the semiconductor substrate; and an oxide spacer disposed between the vertical nitride spacer element and the silicide contact; the oxide spacer operating to minimize an undercut adjacent the vertical nitride spacer during an etching process. | 2009-03-05 |
20090057756 | Trench MOSFET with Trench Termination and manufacture thereof - A trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) with a trench termination, including a substrate including a drain region which is strongly doped and a doping epi layer region, which is weekly doped the same type as the drain region, on the drain region; a plurality of source and body regions formed in the epi layer; a metal layer including a plurality of metal layer regions which are connected to respective source and body, and gate regions forming metal connections of the MOSFET; a plurality of metal contact plugs connected to respective metal layer regions; a plurality of gate trenches filled with polysilicon to form a plurality of trenched gates on top of epi layer; an insulating layer deposited on the epi layer formed underneath the metal layer with a plurality of metal contact holes therein for contacting respective source and body regions; a margin terminating gate trench which is around the gate trenches; and a margin terminating active region which is formed underneath the margin terminating gate trench. | 2009-03-05 |
20090057757 | TRENCH GATE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a trench gate semiconductor device including: a semiconductor layer having a first conductivity type; a first diffusion region having a second conductivity type having a planar structure on the semiconductor layer; a second diffusion region having the first conductivity type positioned selectively on the first diffusion region; a gate electrode provided via a gate insulation film in each first trench facing the second diffusion region and penetrating through the first diffusion region to reach the semiconductor layer; a first semiconductor region of the second conductivity type provided at a position, in the semiconductor layer, apart in a lateral direction from the first diffusion region; a second semiconductor region of the second conductivity type provided at a position, in the first diffusion region, between the adjacent first trenches; and a main electrode in contact with the semiconductor layer and the second diffusion region. | 2009-03-05 |
20090057758 | Thin silicon-on-insulator high voltage transistor with body ground - A silicon (Si)-on-insulator (SOI) high voltage transistor with a body ground is provided with an associated fabrication process. The method provides a SOI substrate with a buried oxide (BOX) layer and a Si top layer having a first thickness and a second thickness, greater than the first thickness. A body ground is formed in the second thickness of Si top layer overlying the BOX layer. A control channel is formed in the first thickness of the Si top layer. A control gate is formed overlying the control channel. An auxiliary channel is formed in the second thickness of Si top layer partially overlying the body ground and extending into the first thickness of the Si top layer. An auxiliary gate is formed overlying the auxiliary channel. A pn junction is formed in the second thickness of Si top layer between the auxiliary channel and the body ground. | 2009-03-05 |
20090057759 | MOS DEVICE AND PROCESS HAVING LOW RESISTANCE SILICIDE INTERFACE USING ADDITIONAL SOURCE/DRAIN IMPLANT - An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5×10 | 2009-03-05 |
20090057760 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device and fabricating method thereof are disclosed, by which channel mobility is enhanced and by which effect of flicker noise can be minimized. Embodiments relate to a method of fabricating a semiconductor device which includes forming a first epi-layer over a substrate, forming a second epi-layer over the first epi-layer, forming a gate electrode over the second epi-layer, forming a spacer over both sides of the gate electrode, etching an area adjacent both sides of the spacer to a depth of the substrate, forming an LDD region in a region under the spacer, and forming a third epi-layer for a source/drain region over the etched area adjacent both of the sides of the spacer. | 2009-03-05 |
20090057761 | Fin field effect transistor and method of manufacturing the same - Provided are a FinFET and a method of manufacturing the same. A FinFET may include at least one active fin, at least one gate insulating layer pattern, a first electrode pattern, a second electrode pattern and at least one pair of source/drain expansion regions. The at least one active fin may be formed on a substrate. The at least one gate insulating layer pattern may be formed on the at least one active fin. The first electrode pattern may be formed on the at least one gate insulating layer pattern. Further, the first electrode pattern may be intersected with the at least one active fin. The second electrode pattern may be formed on the first electrode pattern. Further, the second electrode pattern may have a width greater than that of the first electrode pattern. The at least one pair of source/drain expansion regions may be formed on a surface of the at least one active fin on both sides of the first electrode pattern. Thus, the FinFET may have improved capacity and reduced GIDL current. | 2009-03-05 |
20090057762 | Nanowire Field-Effect Transistors - Field-effect transistors (FETs) having nanowire channels are provided. In one aspect, a FET is provided. The FET comprises a substrate having a silicon-on-insulator (SOI) layer which is divided into at least two sections electrically isolated from one another, one section included in a source region and the other section included in a drain region; a channel region connecting the source region and the drain region and including at least one nanowire; an epitaxial semiconductor material, grown from the SOI layer, covering the nanowire and attaching the nanowire to each section of the SOI layer; and a gate over the channel region. | 2009-03-05 |
20090057763 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - This disclosure concerns a semiconductor memory device including an insulating film; a semiconductor layer provided on the insulating film; a source provided in the semiconductor layer; a drain provided in the semiconductor layer; a floating body provided between the source and the drain and being in an electrically floating state, carriers being accumulated in or emitted from the floating body to store data; a gate dielectric film provided on the floating body; a gate electrode provided on the gate dielectric film; a source and drain insulating film provided on the source and the drain, the source and drain insulating film being thinner than the gate dielectric film; and a silicide layer provided on the source and drain insulating film. | 2009-03-05 |
20090057764 | THIN FILM TRANSISTOR AND DISPLAY APPARATUS - A thin film transistor includes a crystal growth region in which a crystal is two-dimensionally grown on a plane, a source region and a drain region formed in the crystal growth region, and a gate electrode which is formed on a channel region between the source region and the drain region through a gate insulator film. The thin film transistor is characterized in that a side end portion on the channel region of the source region or drain region is aligned with a position located within a range of 1 μm to 3.5 μm away from a crystal growth start position. | 2009-03-05 |
20090057765 | FINFET STRUCTURE USING DIFFERING GATE DIELECTRIC MATERIALS AND GATE ELECTRODE MATERIALS - A semiconductor structure includes a first finFET and a second finFET. The first finFET and the second finFET may comprise an n-finFET and a p-finFET to provide a CMOS finFET structure. Within the semiconductor structure, at least one of: (1) a first gate dielectric within the first finFET and a second gate dielectric within the second finFET comprise different gate dielectric materials; and/or (2) a first gate electrode within the first finFET and a second gate electrode within the second finFET comprise different gate electrode materials. | 2009-03-05 |
20090057766 | INTEGRATION OF SILICON BORON NITRIDE IN HIGH VOLTAGE AND SMALL PITCH SEMICONDUCTORS - Integration of silicon boron nitride in high voltage semiconductors is generally described. In one example, a microelectronic apparatus includes a semiconductor substrate upon which transistors of an integrated circuit are formed, a plurality of transistor gates formed upon the semiconductor substrate, a gate spacer dielectric disposed between the gates, and a contact etch stop dielectric disposed upon the gates and gate spacer dielectric, the contact etch stop dielectric comprising silicon boron nitride (SiBN) to reduce breakdown of the contact etch stop dielectric in high voltage applications. | 2009-03-05 |
20090057767 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR DRIVING THE SAME - A semiconductor device includes a protected device formed on a semiconductor substrate, a first protection transistor formed in a second well of a second conductivity type, and a second protection transistor formed in a first well of a first conductivity type. A fourth source/drain diffusion layer of the second protection transistor is in contact with a second diffusion layer, and a third source/drain diffusion layer is in contact with a second source/drain diffusion layer of the first protection transistor in the second well. A first source/drain diffusion layer of the first protection transistor is in contact with a first diffusion layer, which is in contact with a protected device electrode. | 2009-03-05 |
20090057768 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - Disclosed is an ESD protection circuit, which includes: an ESD protection element, coupled to a pad; a transmitting gate circuit; an N MOSFET, for providing a first biasing voltage to the transmitting gate circuit according to the second voltage level; a first P MOSFET, for providing a second biasing voltage to the transmitting gate circuit according to the first voltage level; a delay circuit for determining the turning on and turning off time of the transmitting gate circuit; a first inversing logic circuit, for generating a first control signal according to the output of the delay circuit; and a second inversing logic circuit, for generating a second control signal according to the output of the first inversing logic circuit, wherein the transmitting gate circuit turns on or turns off according to the first control signal and the second control signal. | 2009-03-05 |
20090057769 | CMOS DEVICE HAVING GATE INSULATION LAYERS OF DIFFERENT TYPE AND THICKNESS AND A METHOD OF FORMING THE SAME - In the process sequence for replacing conventional gate electrode structures by high-k metal gate structures, the number of additional masking steps may be maintained at a low level, for instance by using highly selective etch steps, thereby maintaining a high degree of compatibility with conventional CMOS techniques. Furthermore, the techniques disclosed herein enable compatibility to front-end process techniques and back-end process techniques, thereby allowing the integration of well-established strain-inducing mechanisms in the transistor level as well as in the contact level. | 2009-03-05 |
20090057770 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device capable of preventing malfunction of a Schottky diode to reduce a failure ratio of the semiconductor device and a method for fabricating the same are disclosed. The semiconductor device includes first and second CMOS switching devices formed over a silicon substrate, a Schottky diode formed in a Schottky diode region, and a Schottky diode isolation film surrounding the Schottky diode region and isolating the Schottky diode from the silicon substrate. | 2009-03-05 |
20090057771 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a semiconductor device including a semiconductor substrate provided with an N-type FET and P-type FET, with a gate electrode of the N-type FET and a gate electrode of the P-type FET having undergone full-silicidation, wherein the gate electrode of the P-type FET has such a sectional shape in the gate length direction that the gate length decreases as one goes upwards from a surface of the semiconductor substrate, and the gate electrode of the N-type FET has such a sectional shape in the gate length direction that the gate length increases as one goes upwards from the surface of the semiconductor substrate. | 2009-03-05 |
20090057772 | Replacement gates to enhance transistor strain - Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain. | 2009-03-05 |
20090057773 | Semiconductor device and method of manufacturing the same - A method of manufacturing a semiconductor device including a complementary metal oxide semiconductor (CMOS) and a bipolar junction transistor (BJT), the method comprising the steps of: forming a gate oxide layer on a substrate having a p-type and an n-type well; removing the gate oxide layer on the p-type well; forming bases on the p-type well; forming a first photosensitive layer pattern that exposes the bases on the substrate; implanting p-type impurity ions into the bases through the first photosensitive layer pattern; removing the first photosensitive layer pattern; forming a second photosensitive layer pattern that exposes the p-type and the n-type wells; and implanting n-type impurity ions into the p-type and the n-type wells through the second photosensitive layer pattern to form an emitter and a collector, respectively, to form the BJT. Therefore, CMOS manufacturing processes are used to form a high frequency BJT having improved frequency and noise characteristics. | 2009-03-05 |
20090057774 | Methods of forming bipolar transistors by silicide through contact and structures formed thereby - Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming an opening in a masking layer, implanting an amorphizing species into a silicon region disposed within the opening, wherein the silicon region comprises a portion of an emitter of a bipolar transistor; and forming a silicide layer on the silicon region. | 2009-03-05 |
20090057775 | Semiconductor Device and Method for Manufacturing Semiconductor Device - A method for manufacturing a semiconductor device, including etching exposed areas of a substrate using patterned nitride and insulating layers as an etch mask to form a trench in the substrate; forming a buffer layer in the trench; forming a stress-inducing layer by implanting ions into a region of the substrate around the trench using the patterned nitride and insulating layers as an ion implant mask; forming a device isolation region by filling the trench with an trench insulating layer; and removing the patterned nitride and insulating layers. | 2009-03-05 |
20090057776 | METHOD OF FORMING FULLY SILICIDED NMOS AND PMOS SEMICONDUCTOR DEVICES HAVING INDEPENDENT POLYSILICON GATE THICKNESSES, AND RELATED DEVICE - A method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device. At least some of the illustrative embodiments are methods comprising forming an N-type gate over a semiconductor substrate (the N-type gate having a first thickness), forming a P-type gate over the semiconductor substrate (the P-type gate having a second thickness different than the first thickness), and performing a simultaneous silicidation of the N-type gate and the P-type gate. | 2009-03-05 |
20090057777 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a semiconductor substrate, a plurality of transistors provided in the semiconductor substrate, and an isolation region for isolating the plurality of transistors to one another, the isolation region being comprised of an isolating insulation film, wherein a crystal structure of at least a part of the isolating insulation film is broken. | 2009-03-05 |
20090057778 | INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT - An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type. | 2009-03-05 |
20090057779 | Semiconductor Device and Method of Fabricating the Same - A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a semiconductor substrate having a first area implanted with first conductive type impurities; an isolating film defining a first active area and a second active area in the first area; first LDD areas spaced from each other on the first active area at a first interval and implanted with second conductive type impurities; and second LDD areas spaced from each other on the second active area at a second interval narrower than the first interval and implanted with the second conductive type impurities. | 2009-03-05 |
20090057780 | FINFET STRUCTURE INCLUDING MULTIPLE SEMICONDUCTOR FIN CHANNEL HEIGHTS - A semiconductor structure and a method for fabricating the semiconductor structure include a first semiconductor fin and a second semiconductor fin of the same overall height over a substrate. Due to the presence of a channel stop layer at the base of one of the first semiconductor fin and the second semiconductor fin, but not the other of the first semiconductor fin and the second semiconductor fin, the first semiconductor fin and the second semiconductor fin have different channel heights. The semiconductor fins may be used to fabricating a corresponding first finFET and a corresponding second finFET with differing performance characteristics due to the different channel heights of the first semiconductor fin and the second semiconductor fin. | 2009-03-05 |
20090057781 | MUGFET WITH OPTIMIZED FILL STRUCTURES - A semiconductor structure includes active multi-gate fin-type field effect transistor (MUGFET) structures and inactive MUGFET fill structures between the active MUGFET structures. The active MUGFET structures comprise transistors that change conductivity depending upon voltages within gates of the active MUGFET structures. Conversely, the inactive MUGFET fill structures comprise passive devices that do not change conductivity irrespective of voltages within gates of the inactive MUGFET fill structures. The gates of the active MUGFET structures are parallel to the gates of the inactive MUGFET fill structures, and the fins of the active MUGFET structures are the same size as the fins of the inactive MUGFET fill structures. The active MUGFET structures have the same pitch as the gates of the inactive MUGFET fill structures. The gates of the active MUGFET structures comprise active doping agents, but the inactive MUGFET fill structures do not contain the active doping agents. | 2009-03-05 |
20090057782 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. Embodiments relate to a semiconductor device which includes an active region including a source region, a drain region, and a channel region. A gate electrode, source electrodes, and a drain electrode are formed around the active region. A plurality of gate fingers diverge from the gate electrode into the channel region. A plurality of source fingers diverge from the source electrodes into the source region, the source fingers being disposed between the gate fingers in a predetermined pattern, the source fingers having at least two finger lines connected to each other via at least one grid line. A plurality of drain fingers diverge from the drain electrode into the drain region, the drain fingers being disposed between the gate fingers where the source fingers are not disposed. | 2009-03-05 |
20090057783 | Semiconductor device and method of fabricating metal gate of the same - Provided is a semiconductor device and a method of fabricating a metal gate in the semiconductor device. The semiconductor device includes a metal gate formed on a gate insulating film, the metal gate is formed of a mixture of a metal nitride and a metal carbide, and a work function of the metal gate is determined according to ratios of the metal nitride with respect to the metal carbide. | 2009-03-05 |
20090057784 | Extension tailored device - The present invention discloses a semiconductor device with tailored extension structure comprising a semiconductor substrate. A gate dielectric is formed on the semiconductor substrate. A gate is formed on the gate dielectric. A first isolation layer is formed over the sidewall of the gate. Dielectric spacers are formed on the sidewall of the first isolation layer. And at least one of the p-n junctions of source and drain regions is formed under the dielectric spacers and therefore forming the fringing field induced extension region. Silicide layer is formed on the gate or the doped regions. The first dielectric layer is formed over the silicide layer, dielectric spacer and portion of semiconductor substrate. The second dielectric layer is formed over the first dielectric layer. A metal plug or interconnecting structure is formed in the first dielectric layer and second dielectric layer to electrically connect to at least one of doped regions. | 2009-03-05 |
20090057785 | METHOD OF FABRICATING EXTENDED DRAIN MOS TRANSISTOR - A method of fabricating an extended drain MOS transistor which reduces a design rule and prevents the generation of leakage current. The method includes sequentially forming a diffusion film, a first conductive epitaxial layer, a gate oxide layer and a hard mask layer over a semiconductor substrate, forming a first hard mask pattern having a first thickness by performing a first etching process on the hard mask layer, forming a second hard mask pattern having a second thickness by performing a second etching process on the first hard mask layer, and then forming a thin gate oxide layer by performing a third etching process on the gate oxide layer using the second hard mask pattern as a mask. | 2009-03-05 |
20090057786 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a high dielectric constant gate insulator film provided on a Si substrate which is a semiconductor substrate, a gate electrode formed on the high dielectric constant gate insulator film, a protective film provided on side surfaces of the high dielectric constant gate insulator film and the gate insulator, and a side wall film provided on the outside of the protective film. The protective film includes a high dielectric constant material having, in its composition, at least one metal selected from the group consisting of Hf, Zr, Al, La, Pr, Y, Ti, Ta and W, whereby it is possible to suppress the causes of such troubles as dispersions of characteristics and deterioration of short channel characteristic. | 2009-03-05 |
20090057787 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device which can control a reaction caused between a gate electrode and a high-k gate dielectric film, and which has an element structure suitable for higher integration and speed-up. The semiconductor device has an insulated-gate field-effect transistor, wherein the insulated-gate field-effect transistor has: a gate insulating film including a high-k dielectric film; and a gate electrode with a laminated structure including a first conductive layer, and a second conductive layer which has a resistivity lower than that of the first conductive layer, and the first conductive layer is provided on and in contact with the high-k dielectric film, and includes titanium nitride with a density of 5 g/cm | 2009-03-05 |
20090057788 | Angled implantation for removal of thin film layers - Embodiments of the invention provide a device with a reverse-tapered gate electrode and a gate dielectric layer with a length close to that of the gate length. In an embodiment, this may be done by altering portions of a blanket dielectric layer with one or more angled ion implants, then removing the altered portions of the blanket dielectric layer. | 2009-03-05 |