10th week of 2014 patent applcation highlights part 29 |
Patent application number | Title | Published |
20140062532 | NANO-ELECTRO-MECHANICAL-SWITCH ADIABATIC DYNAMIC LOGIC CIRCUITS - A dynamic logic gate includes a nano-electro-mechanical-switch, preferably a four-terminal-nano-electro-mechanical-switch. The invention further refers to dynamic logic cascade circuits comprising such a dynamic logic gate. In particular, embodiments of the invention concern dynamic logic cascade circuits comprising single or dual rail dynamic logic gates. | 2014-03-06 |
20140062533 | Adaptive Voltage Adjustment based on Temperature Value - Various embodiments of a method and apparatus for performing adaptive voltage adjustment based on temperature value are disclosed. In one embodiment, and integrated circuit (IC) includes logic circuitry having at least one temperature sensor therein. The IC also includes a power management circuit coupled to receive temperature readings from the temperature sensor. The power management circuit is configured to determine a temperature of the IC based on a temperature reading received from the temperature sensor. The power management circuit may compare the determined temperature to a temperature threshold. If the temperature exceeds a temperature threshold value, the power management circuit may cause the operating voltage to be reduced by an amount equivalent to a voltage guard band. | 2014-03-06 |
20140062534 | INTEGRATED CIRCUIT - An integrated circuit includes a plurality of semiconductor devices. Each of the semiconductor devices includes an internal voltage generation unit configured to generate a plurality of internal voltages, a voltage select output unit configured to output a default voltage of a plurality of internal voltages to a preset pad in response to an initial value of a select code, and selectively output the other voltages of the plurality of internal voltages to the pad in response to variations of the select code, and a stack operation control unit configured to control the voltage select output unit to output the default voltage to the pad in response to a stack signal and a predetermined value of the select code, instead of the initial value of the select code, and whether or not to activate the stack signal is determined according to whether or not the plurality of semiconductor devices are stacked. | 2014-03-06 |
20140062535 | Power-on Reset Circuit - A power-on reset circuit is disclosed. The power-on reset circuit includes a first resistor; a first transistor, including a first terminal coupled to a second terminal of the first resistor, and a control terminal for receiving a reference voltage; a second resistor, including a first terminal coupled to a second terminal of the first transistor; a second transistor, including a first terminal coupled to a second terminal of the first resistor, and a control terminal coupled to a second terminal of the second transistor and utilized for receiving an input voltage; and a comparator, including a first input terminal for receiving a comparison voltage, and a second input terminal for receiving the reference voltage, for generating a power-on reset signal according to the comparison voltage and the reference voltage. | 2014-03-06 |
20140062536 | OUTPUT MODULE AND METHOD FOR OPERATING THE OUTPUT MODULE - A method for operating an output module having an output circuit by which a voltage resulting in a current is connected to a load connected to an output, wherein a first driver module is operated and activated via a first control input to connect a voltage to the output, a second driver module is operated in parallel with the first driver module and activated via a second control input to also connect a voltage to the output, at a start time a control circuit receives a switching command for switching the voltage to the output, and wherein the control circuit initially starts by reciprocally activating the first and second control inputs respectively for a first time period, and wherein during this reciprocal activation, the first and second driver modules conduct the current for each respective duration of first and second activation periods. | 2014-03-06 |
20140062537 | FREQUENCY SYNTHESIZER - Disclosed is a frequency synthesizer including first and second shift register circuits | 2014-03-06 |
20140062538 | Systems and Methods for De-Emphasis Level Calibration in Voltage Mode Drivers - A voltage mode driver circuit includes a plurality of VMD cells and a calibration component. The plurality of VMD cells are configured to generate a calibrated emphasis level according to a calibration signal. The calibration component is configured to determine a voltage dependence effect. Additionally, the calibration component is configured to generate the calibration signal according to the determined voltage dependence effect. | 2014-03-06 |
20140062539 | CURRENT CONTROLLED ACTUATOR DRIVER WITH IMPROVED ACCURACY AT LOW CURRENT - Various exemplary embodiments relate to a current driver for controlling a current source controlled by an alternating current (AC) signal, including: a current sensor configured to measure an output current from the current source; a threshold detector configured to detect when the measured current is below a threshold value; and a controller configured to control the current source using a duty cycle of the AC signal when the measured current is below the threshold. | 2014-03-06 |
20140062540 | OUTPUT SUBASSEMBLY AND METHOD OF OPERATING THE OUTPUT SUBASSEMBLY - A method for operating an output subassembly in which a first driver module is operated between a power supply connection on the output subassembly, and an output and is actuated via a first control input to connect the voltage to the output, wherein a second driver module is operated in parallel with the first driver module and is actuated, via a second control input, to connect a voltage to an output, where at an initial time a control circuit receives a command to switch the voltage to the output and the control circuit thereupon initially actuates the second control input for a predefined first length of time, so that the second driver module is operated with current limitation up to a maximum current and, after a predefined second length of time, measured from the initial time, the control circuit actuates the first control input when the command is in effect. | 2014-03-06 |
20140062541 | DRIVE UNIT FOR DRIVING VOLTAGE-DRIVEN ELEMENT - A controller of a drive unit is configured so as to control a voltage supplied to a gate resistor of a voltage-driven element by using of a voltage of a feedback connector when an electrical connection between the feedback connector and the gate resistor of the voltage-driven element is ensured. Further, the controller of the drive unit is configured so as to control the voltage supplied to the gate resistor of the voltage-driven element by using of a voltage of an output connector when the electrical connection between the feedback connector and the gate resistor of the voltage-driven element is not ensured. | 2014-03-06 |
20140062542 | GATE DRIVER CIRCUIT AND METHOD - A driver circuit includes first switch, configured to selectively couple a first driving node to a power supply node, and a second switch, configured to selectively couple a second driving node to a ground node. The first driving node is coupled to each transistor in a first set of PMOS transistor(s) and the second driving node is coupled to each transistor in a second set of NMOS transistor(s). The driver circuit is configured to propagate a first drive signal in a first direction along an electrical path for biasing the first and second sets of transistors when the transistors in the first set, before receiving the first drive signal, are in a first state. The driver circuit is configured to propagate a second drive signal in a second direction along the path when the transistors in the first set, before receiving the second drive signal, are in a second state. | 2014-03-06 |
20140062543 | DYNAMIC DRIVER CIRCUIT - A circuit usable as a word line driver includes a driver that switches in response to a voltage on a control node, and a circuit supplying a voltage to the control node. The circuit that applies a voltage to control node provides a first static current tending to pull the control node up to a first source voltage, and provides a fighting current pulse in response to a signal selecting the driver to pull the control node down to a second source voltage, overcoming the first static current. In addition, a circuit provides a pull-up boost current on a transition of the signal selecting the driver that turns off the fighting current, and applies a boosting current pulse to the control node to assist pulling the control node quickly to the first source voltage. | 2014-03-06 |
20140062544 | Semiconductor Device Arrangement with a First Semiconductor Device and with a Plurality of Second Semiconductor Devices - Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device. | 2014-03-06 |
20140062545 | Method and Apparatus for Reducing the Clock Kick-Back of ADC Comparators While Maintaining Transistor Matching Behavior - The core concept of this ADC is the high-speed fully-differential comparators which are clocked at 2.64 GHz and used in a 60 GHz transceiver. The comparator consists of a pre-amplifier stage, a capture stage, a regeneration cell and an output latch. The pre-amplifier stage is not clocked; therefore, the pre-amplifier stage does not suffer initialization and transient behavior effects when the clock signal switches state. The transient response of being enabled and disabled is eliminated. Instead, a capture stage transfers the contents of the pre-amplifier stage into a memory regeneration stage. The capture stage is clocked by pulses that are timed to minimize the clock kick-back generated by the memory regeneration stage. The clock kick-back is reduced even when many comparators are coupled to the PGA. The comparators, instead of having extra dummy fingers, are also aligned right next to each other to minimize the mismatching layout effect. | 2014-03-06 |
20140062546 | SEMICONDUCTOR DEVICE AND METHOD OF DRIVING THE SAME - A semiconductor device includes a division unit configured to divide an oscillation signal and to generate a plurality of divided signals having different division ratios each other, a delay amount determination unit configured to combine an source signal, the oscillation signal, and the plurality of divided signals and to generate a delay amount information signal with information on a given delay amount, and an edge-delayed signal output unit configured to generate at least one edge-delayed signal corresponding to the given delay amount in response to the source signal and the delay amount information signal. | 2014-03-06 |
20140062547 | CORE VOLTAGE RESET SYSTEMS AND METHODS WITH WIDE NOISE MARGIN - Presented systems and methods facilitate efficient reset operation. In one embodiment, a system comprises a core domain portion an I/O domain portion and a core reset I/O by-pass component. The core domain portion is configured to operate at a nominal core domain voltage level. The I/O domain portion configured to operate at a nominal I/O domain voltage level. The core reset I/O by-pass component configured to forward a reset indication to the core domain independent of the I/O domain. In one exemplary implementation the core reset I/O by-pass component is operable to receive an input reset indication at a high domain voltage level and to convert the input reset indication to a core reset signal that is less than or substantially equal to the nominal core domain voltage, wherein the high domain is voltage higher than the core domain voltage level. | 2014-03-06 |
20140062548 | WIDE-RANGE GLITCH-FREE ASYNCHRONOUS CLOCK SWITCH - Embodiments include systems and methods for asynchronous, glitch-free clock switching across a wide range of clock frequencies with minimal clock down time. Embodiments effectively provide two stages of synchronization across two independent clock domains. In a first synchronization stage, a received, asynchronous clock select signal is translated into a synchronized clock select signal that is effectively synchronous with respect to a first clock domain and is still effectively asynchronous with respect to a second clock domain. In a second synchronization stage, the synchronized clock select signal is resynchronized so as to be effectively synchronous with respect to the second clock domain. The synchronized select signal can be used to disable the clock of the first clock domain, and the resynchronized clock select signal can be used to enable the clock of the second clock domain. | 2014-03-06 |
20140062549 | DIGITAL PLL WITH DYNAMIC LOOP GAIN CONTROL - The disclosed embodiments relate to a digital phase-locked loop (PLL) with dynamic gain control. This digital PLL includes a phase detector which receives a reference signal and a feedback signal as inputs and produces an output signal comprising up/down values. It also includes a digital loop filter which receives the phase-detector output signal as an input and produces an M-bit output signal. This digital loop filter is associated with a loop-parameter control unit (LPCU) which dynamically generates loop-filter parameters for the digital loop filter based on an observed pattern of up/down values from the phase-detector output over a specified period of time. A digitally controlled oscillator (DCO) receives the loop-filter output signal and produces a PLL output signal. Finally, a feedback path returns the PLL output signal to the phase detector. | 2014-03-06 |
20140062550 | PHASE LOCKED LOOP - A phase locked loop comprises a loop filter and a charge pump circuit. The loop filter comprises a parallel capacitor, a serial resistor and a serial capacitor. A first terminal of the serial resistor is electrically connected to a first terminal of the parallel capacitor. A first terminal of the serial capacitor is electrically connected to the second terminal of the serial resistor, and a second terminal of the serial capacitor is electrically connected to a second terminal of the parallel capacitor. The charge pump circuit comprises a first charge pump and a second charge pump. The first charge pump is electrically connected to the first terminal of the serial resistor, and the second charge pump is electrically connected to the second terminal of the serial resistor. The phase lock loop can reduce output jitter and therefore increases the performance of the phase lock loop. | 2014-03-06 |
20140062551 | METHOD AND SYSTEMS FOR HIGH-PRECISION PULSE-WIDTH MODULATION - In various embodiments, systems and methods for generating high-precision pulse-width modulation include a delay-locked loop comprising multiple delay units having time-variable delays, control logic for selecting a subset S of the multiple delay units to thereby generate a time-invariant shift amount having a precision finer than that of a system clock and circuitry for applying the shift amount to rising and falling edges of a pulse-width modulation waveform to thereby generate a high-precision pulse-width modulation waveform. | 2014-03-06 |
20140062552 | DLL CIRCUIT AND DELAY-LOCKED METHOD USING THE SAME - A delay-locked loop (DLL) circuit having improved phase correction performance includes a variable delay unit configured to generate a DLL clock signal by delaying an input clock signal by a varied delay time in response to a delay control signal at timing corresponding to an update cycle signal, a delay model configured to generate a feedback clock signal by delaying the DLL clock signal for a predetermined delay time, a phase detection unit configured to output a result of the detection of the phase of the feedback clock signal based on a reference clock signal as the delay control signal, and an update cycle control unit configured to determine whether a cycle has been shifted or not in response to an external clock signal and the delay control signal and shift a cycle where the update cycle signal is generated based on a result of the determination. | 2014-03-06 |
20140062553 | SEMICONDUCTOR DEVICE INCLUDING DELAY LOCKED LOOP CIRCUIT AND METHOD - A semiconductor device includes a delay locked loop unit configured to compare a phase of an internal clock with a phase of a feedback clock to delay the internal clock by a delay amount corresponding to a comparison result, and to output a delay locked clock, a delay replica modeling unit configured to output the feedback clock by reflecting a transfer delay amount of the internal clock used in an internal circuit into the delay locked clock, and to adjust the transfer delay amount in response to a delay replica adjustment signal, and a delay replica adjustment signal generation unit configured to compare the phase of the feedback clock with a phase of the delay locked clock, and to set a value of the delay replica adjustment signal in response to a comparison result. | 2014-03-06 |
20140062554 | DELAY TIME CONTROL CIRCUIT AND CONTROL METHOD THEREOF - A delay time control circuit is provided which includes a delay locked loop generating a second clock signal delayed by a predetermined time in response to a first clock signal; a plurality of delay circuits each receiving the first and second clock signals and outputting third and fourth clock signals in response to first and second digital clock signals; and a feedback control unit receiving the third and fourth clock signals to detect a delay time and generating the first and second digital control signals for compensating the detected delay time. | 2014-03-06 |
20140062555 | PROPAGATION SIMULATION BUFFER - Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay. | 2014-03-06 |
20140062556 | MULTIPHASE CLOCK DIVIDER - A multiphase clock divider includes: a reference clock generator for generating a plurality of reference clocks; and at least one output clock generator including a first multiplexer for selecting to output a selected reference clock, a second multiplexer for selecting to output a first selected input clock, a third multiplexer for selecting to output a second selected input clock, a first flip-flop for outputting a first sampling clock according to the selected reference clock and the first selected input clock, a second flip-flop for outputting a second sampling clock according to the first sampling clock and the second selected input clock, and a fourth multiplexer for selecting to output the first sampling clock or the second sampling clock to generate an output clock. | 2014-03-06 |
20140062557 | METHOD FOR REDUCING OUTPUT DATA NOISE OF SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS IMPLEMENTING THE SAME - Provided is a method for reducing output data noise of a semiconductor apparatus which includes a plurality of output buffers to output data. The method includes the steps of: driving low data to a specific output buffer among the plurality of output buffers, and driving data transiting from a high level to a low level to the other output buffers; and measuring the magnitude of data noise occurring in output data of the specific output buffer, and deciding slew rates of the plurality of output buffers based on the measurement result. | 2014-03-06 |
20140062558 | CURRENT MODE CONTROLLED POWER CONVERTER - A current mode controlled power converter controllable in a digitally processing current mode even during an on time. In the power converter, each control period based on a reference signal includes a slope calculation period in which a slope compensation signal for the control period is calculated by a slope compensation unit. During each slope calculation period, the slope compensation unit negates the slope compensation signal calculated previous to the control period including the slope calculation period, and a reset signal generation unit compares a current detection signal detected by a current detection unit with a current instruction set to an error signal generated by an error signal generation unit to generate a reset signal. | 2014-03-06 |
20140062559 | SYSTEM AND METHOD OF ADJUSTING A CLOCK SIGNAL - A method includes receiving an input clock signal at a programmable buffer. The method further includes filtering an output signal from the programmable buffer to generate a filtered signal having a voltage level, where the voltage level indicates a duty cycle of the output signal. The method further includes comparing the voltage level to a reference voltage. The method further includes modifying at least one operating parameter of the programmable buffer to adjust the duty cycle of the output signal. | 2014-03-06 |
20140062560 | RECONFIGURABLE FLIP-FLOP | 2014-03-06 |
20140062561 | SCHMITT RECEIVER SYSTEMS AND METHODS FOR HIGH-VOLTAGE INPUT SIGNALS - Presented systems and methods facilitate efficient switching operations for components operating at different voltage level than a received signal voltage level. In one embodiment, the components of a presented system are operable to perform switching operations for signals with a voltage level swing larger than the power rail of the circuit receiving the signals. In one embodiment a system includes an input component, a transition component, a transition point feedback component and an output component. The input component is operable to receive an input signal. The transition component is operable to transition the input signal. The transition point feedback component is operable to adjust a point at which a transition in the input signal occurs in the transition component. The output component is operable to forward an output signal from the transition point feedback component. | 2014-03-06 |
20140062562 | CONSTRAINING CLOCK SKEW IN A RESONANT CLOCKED SYSTEM - An integrated circuit includes a plurality of resonant clock domains of a resonant clock network. Each resonant clock domain has at least one clock driver that supplies a portion of clock signal to an associated resonant clock domain. The resonant clock network operates in a resonant mode with inductors connected to pairs of resonant clock domains at boundaries between the resonant clock domains. Each inductor forms an LC circuit with clock load capacitance in the pair of resonant clock domains to which the inductor is connected. | 2014-03-06 |
20140062563 | CONTROLLING IMPEDANCE OF A SWITCH USING HIGH IMPEDANCE VOLTAGE SOURCES TO PROVIDE MORE EFFICIENT CLOCKING - A clock system of an integrated circuit includes first and second transistors forming a switch that is used when switching the clock system between a resonant mode of operation and a non-resonant mode of operation. An inductor forms a resonant circuit with capacitance of the clock system in resonant mode. The switch receives a clock signal and supplies the clock signal to the inductor when the switch is closed and disconnects the inductor from the clock system when the switch is open. First and second high impedance voltage sources supply respective first and second voltages to the switch and a gate voltage of the first transistor transitions with the clock signal around the first voltage and a gate voltage of the second transistor transitions with the clock signal around the second voltage such that near constant overdrive voltages are maintained for the first and second transistors. | 2014-03-06 |
20140062564 | PROGRAMMABLE CLOCK DRIVER - A clock driver circuit supplies a clock signal with a drive strength determined according to one or more control signals supplied to the clock driver that vary during run-time. The clock driver is operated with a first drive strength in a non-resonant mode of operation of an associated clock network and with a second drive strength in a resonant mode of operation of the associated clock network, the first drive strength being higher than the second drive strength. | 2014-03-06 |
20140062565 | CLOCK DRIVER FOR FREQUENCY-SCALABLE SYSTEMS - A clock driver for a resonant clock network includes a delay circuit that receives and supplies a delayed clock signal. A first transistor is coupled to receive a first pulse control signal and supply an output clock node of the clock driver. An asserted edge of the first control signal is responsive to the falling edge of the delayed clock signal. A second transistor is coupled to receive a second control signal and to supply the output clock node of the clock driver. An asserted edge of the second control signal is responsive to a rising edge of the delayed clock signal. | 2014-03-06 |
20140062566 | TRANSITIONING BETWEEN RESONANT CLOCKING MODE AND CONVENTIONAL CLOCKING MODE - A resonant clock network includes an inductor coupled to the clock network through a plurality of switches. When the clock network enters resonant mode, the turn-on of the switches to couple the inductor to the clock network is staggered. The clock network may be formed of multiple regions, each with its own inductor and switches. The turn-on of switches of each region may be staggered with respect to the turn-on off the switches of the other regions as well as to the turn-on of switches within a region. In addition to staggering the turn-on of the switches when entering the resonant mode, the switches may be turned off in a staggered manner when exiting the resonant mode of operation. | 2014-03-06 |
20140062567 | Auto-Ranging for Time Domain Extraction of Perturbations to Sinusoidal Oscillation - A method for increasing the accuracy of a time-domain apparatus comprising the following steps: initiating a periodic oscillation with the time-domain apparatus; measuring time intervals between trigger events during each oscillation, wherein the trigger events correspond to the oscillation passing known values; detecting a perturbation to the oscillation by monitoring changes in the time intervals between trigger events; and adjusting a parameter of the oscillation based on the perturbation such that measurement error is reduced. | 2014-03-06 |
20140062568 | OUTPUT BUFFER CIRCUIT - A differential output buffer includes first and third switches and second and fourth switches which are connected in series respectively between a first voltage source and a current source, and a replica circuit includes a second voltage source which is equivalent to a first voltage source. A current control circuit controls a current flowing to the current source in such a manner that a voltage of a third node between two resistive elements connected in series between a first node between the first and third switches and a second node between the second and fourth switches and having an equal resistance value is equal to a reference voltage, for example, and a voltage control circuit generates a control signal in such a manner that a voltage of any node excluding an output terminal of the second voltage source in the current path is equal to a second reference voltage. | 2014-03-06 |
20140062569 | CONTINUOUSLY SELF-CALIBRATED LATCHED COMPARATOR - A comparator apparatus includes an amplifier and one or more latched comparators connected to the amplifier that compares input voltage signals to predefined reference voltage signals. The comparator apparatus includes an offset that limits the minimum input differential voltage signal with respect to the predefined voltage signals. A calibration component is electrically connected to the latched comparator and assists in continuously measuring and compensating the offset. | 2014-03-06 |
20140062570 | Overdrive Circuits and Related Method - An overdrive circuit includes a pull-up circuit and a pull-down circuit. The pull-down circuit includes first, second and third transistors electrically connected in cascode between an output node and a low voltage supply node. A capacitor is electrically connected from a gate electrode of the third transistor to a gate electrode of the first transistor. A first mono-directional bias device is electrically connected from a drain electrode of the first transistor to a gate electrode of the first transistor. A second mono-directional bias device is electrically connected from the gate electrode of the first transistor to a source electrode of the first transistor. | 2014-03-06 |
20140062571 | INVERSE LEVEL SHIFT CIRCUIT - A voltage conversion mask signal generation circuit generates a first main signal and a first mask signal by converting an output signal of the first transistor to a low-side voltage, and generating a second main signal and a second mask signal by converting an output signal of the second transistor to a low-side voltage. A mask signal generation circuit generating a third mask signal with higher sensitivity than the first and second mask signals with respect to a fluctuation in the high-side reference potential. A mask logical circuit generating a fourth mask signal by performing a AND operation between the first mask signal and the second mask signal, and masking the first and second main signals with the third and fourth mask signals; and a SR flip flop circuit generating the output signal from the masked first and second main signals. | 2014-03-06 |
20140062572 | SINGLE INPUT LEVEL SHIFTER - Provided is a single input level shifter. The single input level shifter includes: an input unit applying a power voltage to a first node in response to an input signal and applying the input signal to a second node in response to a reference signal; a bootstrapping unit applying the power voltage to the second node according to a voltage level of the first node; and an output unit applying the input signal to an output terminal in response to the reference signal and applying the power voltage to the output terminal according to the voltage level of the first node, wherein the bootstrapping unit includes a capacitor between the first and second nodes, and when the input signal is shifted from a first voltage level to a second voltage level, the bootstrapping unit raises the voltage level of the first node to a level higher than the power voltage. | 2014-03-06 |
20140062573 | LEVEL SHIFT DEVICE - Disclosed is a level shift device. The level shift device to convert an input signal having a low-voltage level into an output signal having a high-voltage level includes a latch-type level shifter and a voltage generator. The latch-type level shifter includes two upper pull-up P channel transistors and two lower P channel transistors to prevent the gate-source voltage breakdown of the two upper pull-up P channel transistors. The two upper pull-up P channel transistors and the two lower P channel transistors form a latch structure. The voltage generator generates a voltage to prevent the gate-source voltage brake down of the two upper pull-up P channel transistors and provides the voltage to the gate electrodes of the two lower P channel transistors. | 2014-03-06 |
20140062574 | CONTROLLING OUTPUT POWER OF MULTIPLE-INPUT SINGLE-OUTPUT (MISO) DEVICE - Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal. In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of constant envelope constituent signals. The constituent signals are amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal. Embodiments also perform frequency up-conversion. | 2014-03-06 |
20140062575 | RF Switch Branch Having Improved Linearity - Disclosed is a radio frequency (RF) switch branch having a reduced nonlinearity and an associated method for reducing nonlinearity in a RF switch branch. The RF switch branch includes a primary transistor, a first transistor having power terminals electrically connected between a drain node and a body node of the primary transistor, and a second transistor having power terminals electrically connected between the body node and a source node of the primary transistor. The RF switch may further include a body resistor electrically connected between the body node of the primary transistor and ground, and a gate resistor electrically connected between a gate of the primary transistor and a gate voltage source. A gate of each of the first transistor and the second transistor is electrically connected to the gate voltage source such that the first transistor and the second transistor are ON only when the primary transistor is ON. | 2014-03-06 |
20140062576 | SEMICONDUCTOR DEVICE - The semiconductor device includes first and second output terminals each coupled to one end side and another end side of an inductive or capacitive load, a first MOS transistor coupled between a first voltage and the first output terminal, a second MOS transistor coupled between a second voltage and the first output terminal, a third MOS transistor coupled between the first voltage and the second output terminal, a fourth MOS transistor coupled between the second voltage and the second output terminal, and a drive circuit driving the first to fourth MOS transistors for controlling the inductive or capacitive load, and further includes first and second bypass transistors for bypassing a forward current of a parasitic diode of a PN-junction formed in the MOS transistor in the dead-off period. | 2014-03-06 |
20140062577 | RF Switch with Adaptive Drain and Source Voltage - A radio frequency (RF) switch includes a common port, a first port, and a second port, a first semiconductor switching element disposed in a first RF pathway between the common port and the first port, a second semiconductor switching element disposed in a second RF pathway between the common port and the second port, a first pair of direct current (DC) blocking capacitors disposed to isolate the first semiconductor switching element in the first RF pathway, and a second pair of DC blocking capacitors disposed to isolate the second semiconductor switching element in the second RF pathway. The respective pairs of DC blocking capacitors allow for different bias voltages to be applied to the respective RF pathways. A charge-discharge circuit may also be employed to decrease transient switching time of the RF switch. | 2014-03-06 |
20140062578 | SEMICONDUCTOR STRUCTURE HAVING AN ACTIVE DEVICE AND METHOD FOR MANUFACTURING AND MANIPULATING THE SAME - A semiconductor structure comprising a substrate, an active device, a field oxide layer and a poly-silicon resistor is disclosed. The active device is formed in a surface area of the substrate. The active device has a first doped area, a second doped area and a third doped area. The second doped area is disposed on the first doped area. The first doped area is between the second and the third doped areas. The first doped area has a first type conductivity. The third doped area has a second type conductivity. The first and the second type conductivities are different. The field oxide layer is disposed on a part of the third doped area. The poly-silicon resistor is disposed on the field oxide layer and is electrically connected to the third doped area. | 2014-03-06 |
20140062579 | APPARATUS FOR FLUID CONTROL DEVICE MONITORING - Apparatus for fluid control device monitoring are disclosed. An example apparatus includes a body through which a shaft extends. The shaft is to be coupled to an actuator. An angular position of the shaft is based on a position of the actuator. The apparatus includes a target coupled to the shaft and a circuit including a user configurable switch and a proximity switch. The user configurable switch is configurable to a first state or a second state. When the user configurable switch is in the first state and the target is distant from the proximity switch, the circuit is to output a first signal. When the user configurable switch is in the second state and the target is distant from the proximity switch, the circuit is to output a second signal different than the first signal. | 2014-03-06 |
20140062580 | Diode Formed of PMOSFET and Schottky Diodes - A P-type Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) includes a gate, a first source/drain region connected to the gate, and a second source/drain region on an opposite side of the gate than the first source/drain region. A first Schottky diode includes a first anode connected to the first source/drain region, and a first cathode connected to a body of the PMOSFET. A second Schottky diode includes a second anode connected to the second source/drain region, and a second cathode connected to the body of the PMOSFET. | 2014-03-06 |
20140062581 | RADIATION HARDENED CHARGE PUMP - This invention relates to radiation hardened charge pumps for electronic circuitry. | 2014-03-06 |
20140062582 | SENSOR CURRENT INTERFACE TRANSCEIVER WITH ADAPTIVE LINEARIZATION - Some embodiments of the present disclosure relate to a sensor interface module having a linearization module that increase a size of a linear region of a current output from a high-side current source. The disclosed sensor interface module has a reference voltage source configured to generate a reference signal. An output driver stage having a high-side current source and a low-side current source is connected in series at an output node of the sensor interface module. A closed control loop configured to receive the reference signal and to generate a digital control signal that drives the high-side current source. A linearization module configured to operate the low-side current source to approximate a nonlinearity of the high-side current source and to use the approximated nonlinearity to generate a compensation function that mitigates nonlinearities in the high side current source. | 2014-03-06 |
20140062583 | INTEGRATED CIRCUIT AND METHOD OF OPERATING THE SAME - An integrated circuit includes a first internal voltage generation unit configured to generate a first voltage and output the first voltage through an internal voltage terminal in an active operation period, a second internal voltage generation unit configured to generate a second voltage and output the second voltage through the internal voltage terminal in an initial section of a standby operation period, and a third internal voltage generation unit configured to generate a third voltage and output the third voltage through the internal voltage terminal in the remaining section of the standby operation period. | 2014-03-06 |
20140062584 | Semiconductor Integrated Circuit - A semiconductor integrated circuit includes a first internal voltage generator including a PMOS and a first comparator, and a second internal voltage generator including an NMOS, a second comparator, and a voltage pump generator configured to provide a pumping power voltage to the second comparator. A power control circuit switchably enables an output from the first internal voltage generator during a power-on of the semiconductor integrated circuit and enables an output from the second internal voltage generator after the power-on. | 2014-03-06 |
20140062585 | Circuit Arrangement with a First Semiconductor Device and with a Plurality of Second Semiconductor Devices - A circuit arrangement includes a first semiconductor device having a load path and a number of second semiconductor devices. Each second semiconductor device has a control terminal and a load path between a first load terminal and a second load terminal. The second semiconductor devices have their load paths connected in series and connected in series with the load path of the first semiconductor device. Each of the second semiconductor devices has a load terminal of one of the first semiconductor device and of one of the second semiconductor devices associated thereto and a voltage limiting element coupled between the control terminal of one of the second semiconductor devices and the load terminal associated with that one of the second semiconductor devices. | 2014-03-06 |
20140062586 | DOUBLE THROUGH SILICON VIA STRUCTURE - This invention discloses a double Through Silicon Via (TSV) structure, including a first die unit, a first signal path, a second signal path, a receiving unit and a second die unit. The first and the second signal paths respectively include a driving unit and a TSV unit. Each driving unit includes a first end, a second end and a third end. The invention divides the signal paths of the conventional double TSV into two different signal paths by two driving units and the receiving unit having OR gate or NOR gate, to avoid generating the problem of signal degradation from the TSV unit with short defect. The invention further disposes a first switch unit, a second switch unit, a first exchange unit, a second exchange unit, a first VDD keeper and a second VDD keeper, to avoid generating the problems of open defect and leakage current. | 2014-03-06 |
20140062587 | SEMICONDUCTOR DEVICE HAVING STACKED CHIPS - According to one embodiment, a semiconductor device includes chips and a first selection circuit. Each of the chips has at least first and second vias for transmitting at least first and second address signals, these chips are stacked to be electrically connected via the first and second vias. The first selection circuit is provided in each chip, includes a logic circuit that selects a chip based on at least the first and second address signals, and supplies a result of operating the first and second address signals to the subsequent chip. | 2014-03-06 |
20140062588 | SYSTEM AND METHOD TO DEMODULATE A LOAD MODULATED SIGNAL - A method includes demodulating a load modulated signal at an initiator device based at least partially on a phase adjusted comparison value corresponding to the load modulated signal. | 2014-03-06 |
20140062589 | QUASI-BROADBAND DOHERTY AMPLIFIER WITH ASSOCIATED CAPACITOR CIRCUIT - An amplifier provides a first amplifier circuit ( | 2014-03-06 |
20140062590 | MULTIPLE POWER SUPPLY INPUT PARALLEL AMPLIFIER BASED ENVELOPE TRACKING - A switch mode power supply converter and a parallel amplifier are disclosed. The switch mode power supply converter is coupled to a modulated power supply output and the parallel amplifier has a parallel amplifier output coupled to the modulated power supply output. Further, the parallel amplifier has a group of output stages, such that each output stage is directly coupled to the parallel amplifier output and each output stage receives a separate supply voltage. | 2014-03-06 |
20140062591 | POWER AMPLIFIER WITH VARIABLE OUTPUT IMPEDANCE - A power amplifier circuit, comprising: an amplifier for receiving an input signal to be amplified; a power input for coupling the amplifier to a power supply; and a transformer for providing the amplified signal from the amplifier to a load, comprising a primary inductor and a secondary inductor. The power amplifier circuit is characterized by: a first capacitor coupled in parallel with the primary inductor; and a second capacitor coupled in parallel with the secondary inductor; wherein at least one of the first and second capacitors has a variable capacitance. | 2014-03-06 |
20140062592 | POP-FREE SINGLE-ENDED OUTPUT CLASS-D AMPLIFIER - A pop-free single-ended output class-D amplifier includes: an input signal generator for generating an input signal; a power supply for supplying input power; a reference voltage generator for generating a reference voltage; a gain-adjustable stage for generating an amplified signal according to the reference voltage and adjusting a gain of the single-ended output class-D amplifier; a pulse width modulation module for outputting a pulse width modulation signal according to the reference voltage, the amplified signal, and the input power; a low-pass filter for low-pass filtering the pulse width modulation signal to generate an output voltage; and a logic controller for generating at least one control signal to control the reference voltage generator, the gain-adjustable stage, and the pulse width modulation module according to the input power, the reference voltage, and the pulse width modulation signal. | 2014-03-06 |
20140062593 | CLASS RESONANT-H ELECTROSURGICAL GENERATORS - A generator for use with an electrosurgical device is provided. The generator has a gain stage electrically disposed between a first voltage rail and a second voltage rail, wherein the gain stage includes an input and an output. A voltage source operably coupled to the gain stage input and configured to provide an input signal thereto responsive to a drive control signal is also provided. The generator also has one or more sensors configured to sense an operational parameter of the amplifier and to provide a sensor signal corresponding thereto and a controller adapted to receive the sensor signal(s) and in response thereto provide a drive control signal to the voltage source. The generator has an amplifier output configured to supply an output voltage corresponding to the first voltage rail and the second voltage rail when the output of the gain stage falls between a voltage of the first voltage rail and a voltage of the second voltage rail and is configured to supply a peak voltage output when the voltage output is falls greater than the voltage of the first voltage rail or less than the voltage of the second voltage rail. | 2014-03-06 |
20140062594 | CHIP CARD - According to an embodiment, a chip card is provided comprising a signal source configured to generate a signal to be transmitted via radio, a p-channel field effect transistor and being coupled with its source terminal to an upper supply potential and with its drain terminal to a common node; an n-channel field effect transistor and being coupled with its drain terminal to the common node and with its source terminal to a lower supply potential; an operational amplifier having a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal is coupled to the common node, the negative input terminal is coupled to the signal source and the output terminal is coupled to the gate terminal of the p-channel field effect transistor and to the gate terminal of the n-channel field effect transistor; and an antenna coupled to the common node. | 2014-03-06 |
20140062595 | DIFFERENTIAL OUTPUT CIRCUIT AND SEMICONDUCTOR DEVICE - A highly reliable circuit is realized using the transistors having a lower withstand voltage. There are provided a differential pair including a first and a second transistor which respectively receive input signals having mutually reversed phases; a third and a fourth transistor respectively cascode-coupled to the first and the second transistor, and having the same conductivity type as the first and the second transistor; a first and a second output terminal coupled to respective drains of the third and the fourth transistor; and a voltage divider circuit which divides an intermediate potential between respective potentials of the first and the second output terminal and supplies the divided potential to gates of the third and the fourth transistor. | 2014-03-06 |
20140062596 | CHOPPED OSCILLATOR - Embodiments of the present disclosure may provide a relaxation oscillator with improved performance against phase noise error. The phase noise error may be reduced from sources whose power is greater at lower frequencies. To reduce the noise error, the relaxation oscillator may include chopping in the charging current driver; chopping in the trigger level generator; and/or chopping in the currents that feed the cells. A chopped amplifier may be provided to perform chopping of the input signals. | 2014-03-06 |
20140062597 | EXTERNAL PROGRAMMABLE DFE STRENGTH - A decision feedback equalizer is disclosed. The decision feedback equalizer comprises an amplifier circuit and a latch. The amplifier circuit is configured to receive an input signal, a decision feedback signal and a control signal, and is configured to adjust its driving capability according to the decision feedback signal and the control signal to provide an amplified signal of the input signal. The latch is configured to latch the amplified signal as an output signal. | 2014-03-06 |
20140062598 | INPUT/OUTPUT SENSE AMPLIFIER - An input/output sense amplifier includes: a data input unit configured to amplify data using a driving voltage and to output the amplified data, and a latch unit configured to latch and output an output signal of the data input unit to an output terminal. | 2014-03-06 |
20140062599 | SELECTIVE GAIN CONTROL CIRCUIT - A circuit for providing signal amplification with reduced fixed pattern noise. In an embodiment, the circuit includes an amplifier and a plurality of legs coupled in parallel with one another between a first node for an input of the amplifier and a second node for an output of the amplifier. Control logic selects a first combination of the plurality of legs for a first configuration of the circuit to provide a first loop gain with the amplifier. In another embodiment, the control logic further selects a second combination of the plurality of legs for a second configuration of the circuit to provide a second loop gain with the amplifier, wherein the first loop gain is substantially equal to the second loop gain. | 2014-03-06 |
20140062600 | Temperature Compensation Circuit and Electronic Device With Temperature Compensation - A temperature compensation circuit is adapted to be used in an electronic device including a processing circuit. The temperature compensation circuit includes a thermistor, a compensation capacitor and a compensation diode. The thermistor has two ends, one of which is adapted to be electrically connected to the processing circuit. The compensation capacitor has two ends, one of which is electrically connected to the other one of the two ends of the thermistor. The compensation diode has an anode electrically connected to the other one of the two ends of the compensation capacitor, and a cathode to be grounded. The impedance of the thermistor varies with temperature so as to compensate and stabilize an output of the electronic device. | 2014-03-06 |
20140062601 | DOHERTY AMPLIFIER HAVING COMPACT OUTPUT MATCHING AND COMBINING NETWORKS - A Doherty amplifier having a main amplifier branch and one or more peak amplifier branches, where the functionality and structure of the cascade of the main output matching network, the main offset line, and the quarter-wave transformer of the main amplifier branch of a conventional Doherty amplifier are subsumed into the main output matching network of the main amplifier branch, and the functionality and structure of each cascade of the peak output matching network and the peak offset line of each peak amplifier branch of a conventional Doherty amplifier are subsumed into the peak output matching network of the corresponding peak amplifier branch. Furthermore, the output quarter-wave transformer can be replaced by a wideband node matching network that does not have to perform frequency inversion. | 2014-03-06 |
20140062602 | READ OUT INTEGRATED CIRCUIT - According to one embodiment, a circuit comprises a Capacitive Trans-Impedance Amplifier (CTIA) configured to receive a current pulse at an input and convert the current pulse to a voltage step. The voltage step is directed to a first signal path and a second signal path. When the voltage step exceeds a first threshold, the first signal path directs an enable pulse to the second signal path. The second signal path generates an output pulse when the voltage step exceeds a second threshold and the enable pulse is enabled. The second signal path comprises a first, a second, and a third amplifier to increase detection of the voltage step by the second signal path. | 2014-03-06 |
20140062603 | SYSTEM AND METHOD FOR OPERATING A POWER AMPLIFIER AND A LOAD MODULATION NETWORK - A system and method for operating a power amplifier comprising the steps of determining a first impedance generated by a first amplifier component of the power amplifier, determining a second impedance generated by a second amplifier component of the power amplifier, and, adjusting the first impedance or the second impedance to an optimal impedance condition by altering a current ratio of a current delivered by the first amplifier component and a current delivered by the second amplifier component. | 2014-03-06 |
20140062604 | System and Method for a Power Amplifier - In accordance with an embodiment, a system includes a first amplifier and a first bandpass filter having an input coupled in series with an output of the first amplifier, and an output configured to be coupled to a load. The bandpass filter has a lower input impedance at an in-band center frequency than at out-of-band frequencies, and the first amplifier is configured to receive a pulse width modulated waveform filtered according to a first transfer function that attenuates sidebands of the pulse width modulated waveform. | 2014-03-06 |
20140062605 | METHOD AND APPARATUS FOR A SYNTHESIZER ARCHITECTURE - A synthesizer architecture, responsive to a low noise reference signal from a discrete oscillator, provides a continuous periodic output with a period that is a fractional multiple of the low noise reference signal. One exemplary embodiment includes a phase detector providing a control signal to a selected one of a plurality of integrated voltage controlled oscillators (VCO), wherein the phase detector is a sub-harmonic continuous time sampling phase detector. Another exemplary embodiment includes a continuous fractional divider input to the phase detector in response to an output of the selected VCO. Yet another exemplary embodiment comprises an injection locked ring oscillator responsive to the low noise narrow band variable reference signal with a fractional output period. | 2014-03-06 |
20140062606 | TEST SOLUTION FOR RING OSCILLATORS - A method and apparatus is disclosed herein for testing of multiple ring oscillators. In one embodiment, the apparatus comprises at least one ring oscillator structure having a ring oscillator having an inverter chain with an odd number of inverters connected back-to-back and operable to produce an oscillatory output, and a test structure coupled to provide either an observability chain input or a test input to the ring oscillator and to receive the oscillatory output as a feedback from the ring oscillator. | 2014-03-06 |
20140062607 | ULTRA SLIM RF PACKAGE FOR ULTRABOOKS AND SMART PHONES - A semiconductor device package having reduced form factor and a method for forming said semiconductor device are disclosed. In an embodiment, an active die is embedded within a cavity in the core layer of the package substrate, wherein an in-situ electromagnetic shield is formed on the sidewalls of the cavity. In another embodiment, a crystal oscillator is at least partially embedded within the core layer of the package substrate. In another embodiment, a package having a component embedded in the core layer is mounted on a PCB, and a crystal oscillator generating a clock frequency for the package is mounted on the PCB. By embedding components within the core or removing components from the package to be mounted directly on the PCB, the x, y, and z dimensions of a package may be reduced. In addition, in-situ electromagnetic shield may reduce EM noise emitted from the active die. | 2014-03-06 |
20140062608 | VAPOR CELL ATOMIC CLOCK PHYSICS PACKAGE - In an example, a chip-scale atomic clock physics package is provided. The physics package includes a body defining a cavity having a base surface and one or more side walls. The cavity includes a first step surface and a second step surface defined in the one or more side walls. A first scaffold mounted to the base surface in the cavity. One or more spacers defining an aperture therethrough are mounted to the second step surface in the cavity. A second scaffold is mounted to a first surface of the one or more spacers spans across the aperture of the one or more spacers. A third scaffold is mounted to a second surface of the one or more spacers in the cavity and spans across the aperture of the one or more spacers. Other components of the physics package are mounted to the first, second, and third scaffold. | 2014-03-06 |
20140062609 | XTAL oscillator - Resistor bias circuitry is included in components of an XTAL oscillator system to reduce 1/f noise. An XTAL oscillator includes a resistor bias circuit attached to the XTAL core. A common mode feedback OP amp connected to the XTAL core also includes a resistor bias circuit. An XTAL oscillator chain includes an XTAL core, common mode feedback OP amp, common mode logic buffer (CML BF), and differential to CMOS converter (D2C) each with resistor bias circuitry. | 2014-03-06 |
20140062610 | OSCILLATION CIRCUIT, REAL-TIME CLOCK, AND INFORMATION PROCESSING DEVICE - According to one embodiment, a switching unit switches between a first state in which the current source is connected to a first capacitance element and a ground electric potential is connected to a second capacitance element and a second state in which a current source is connected to the second capacitance element and the ground electric potential is connected to the first capacitance element. A comparison unit compares a voltage charged in the first capacitance element and a reference voltage with each other in the first state and compares a voltage charged in the second capacitance element and the reference voltage with each other in the second state. A generation unit generates a periodical pulse based on a comparison result acquired by the comparison unit. The switching unit alternately switches between the first state and the second state based on the comparison result acquired by the comparison unit. | 2014-03-06 |
20140062611 | FILTERING DEVICE WITH SLOTTED GROUND STRUCTURE - The present invention is related to a filtering device with slotted ground structure, comprising a first substrate, a second substrate and a pair of differential signal lines, in which a ground plane having slotted ground structure is provided between the first substrate and the second substrate. Each of the two differential signal lines is symmetric to each other and comprises a first line segment being horizontally provided on the top surface of the first substrate and a second line segment being horizontally provided on the bottom surface of the second substrate, respectively. The first line segment is connected to the second line segment through a vertically disposed conductive via. Thereby, a common-mode noise within a specific frequency band may be suppressed effectively, so as to avoid interference a differential-mode signal transmitted on the differential signal lines, due to the slotted ground structure etched on the ground plane. | 2014-03-06 |
20140062612 | SIGNAL TRANSMISSION CIRCUIT HAVING CROSSTALK CANCELLATION UNIT - A signal transmission circuit may include a main driving unit configured to drive a first signal transmission line with given driving force in response to a first input signal, and a crosstalk cancellation unit configured to differentiate a signal transferred through a second signal transmission line, which is adjacent to the first signal transmission line, and incorporate a differentiated value into the first signal transmission line. | 2014-03-06 |
20140062613 | SYSTEMS AND METHODS FOR HIGH POWER RF CHANNEL SELECTION - A switch is disclosed for selecting a port. The switch includes a dielectric layer, a first circuit, and a second circuit. The first and second circuits are disposed on the dielectric layer and electrically coupled to each other through the dielectric layer. The first circuit includes a set of ports. The switch further includes a control port for receiving a control signal and a plurality of switching elements. The control signal selects at least one of the set of ports to be connected to the second circuit by setting operational states of the plurality of switching elements. | 2014-03-06 |
20140062614 | APPARATUS AND METHOD FOR SELECTING FREQUENCY BAND - A switching circuit is provided. The switching circuit includes at least one Surface Acoustic Wave (SAW) filter, a Single-Pole n Throw (SPnT) switch connected to an input port of each of the at least one SAW filter, and a Dual-Pole n Throw (DPnT) switch connected to an output port of each of the at least one SAW filter. | 2014-03-06 |
20140062615 | THIN FILM TYPE COMMON MODE FILTER - Disclosed herein is a thin film type common mode filter including: a base substrate made of an insulating material; a first insulating layer formed on the base substrate; a coil-shaped internal electrode formed on the first insulating layer; a second insulating layer formed on the internal electrode; an external electrode terminal having a vertical section connected to a side surface of the internal electrode and a horizontal section extended from an upper end of the vertical section toward a horizontal direction to thereby form a parallel surface spaced apart from the internal electrode by a predetermined distance; and a ferrite resin layer formed between the horizontal section of the external electrode terminal and the internal electrode. | 2014-03-06 |
20140062616 | FILTER - In a filter, a plurality of coils include a plurality of line conductor layers that are each provided on an insulator layer, a plurality of via hole conductors that extend from one end of the line conductor layers in the y-axis direction to the negative direction side of the z-axis direction, and are electrically connected to a plurality of capacitor conductor layers, and a plurality of via hole conductors that extend from the other end of the line conductor layers in the y-axis direction to the negative direction side of the z-axis direction, and are electrically connected to a ground conductor layer. The distance between the via hole conductor layers connected to the ground conductor layer differs from the distance between the via hole conductor layers connected to the capacitor conductor layers. | 2014-03-06 |
20140062617 | FILTER ASSEMBLY - A filter assembly is provided. The filter assembly includes a printed circuit board (PCB) including a plurality of electronic components, a base disposed under the PCB, and an inductor coupled to the base, the inductor including a core and a coil to which current is applied, wherein the PCB has a through-hole through which at least one portion of the coil pass. | 2014-03-06 |
20140062618 | ELECTROMAGNETIC INTERFERENCE FILTER FOR IMPLANTED ELECTRONICS - An electromagnetic interference filter for various electronic devices such as implantable medical devices is provided. A plurality of signal electrodes can be configured in an array, where each signal electrode extends vertically from a top surface to a bottom surface of the filter such that the signal electrodes are flush with the top and bottom surface. Ground or common electrodes can have a parallel arrangement and be interposed between the signal electrodes. The ground electrodes can be grounded internally, externally, or both internally and externally. Dielectric material can be disposed between signal electrodes and ground electrodes to act as an insulator between adjacent electrodes. | 2014-03-06 |
20140062619 | METHODS AND SYSTEMS FOR MEMS CMOS-BASED RADIO FREQUENCY FILTERS HAVING ARRAYS OF ELEMENTS - Systems and methods for manufacturing a chip comprising a MEMS-based radio frequency filter arranged in an integrated circuit are provided. In one aspect, the systems and methods provide for a chip including electronic elements formed on a semiconductor material substrate. The chip further includes a stack of interconnection layers including layers of conductor material separated by layers of dielectric material. A radio frequency filter is formed within the stack of interconnection layers by applying gaseous HF to the interconnection layers. The radio frequency filter includes a plurality of mechanically decoupled resonator elements. | 2014-03-06 |
20140062620 | VOLTAGE TUNABLE FILTERS - A suspended line resonator and a tunable filter comprising multiple suspended line resonators. A microstrip resonator and a tunable filter comprising multiple microstrip resonators. A suspended substrate resonator and a tunable filter comprising multiple suspended substrate resonators. | 2014-03-06 |
20140062621 | Method and Apparatus for an Active Negative-Capacitor Circuit to Cancel the Input Capacitance of Comparators - The differential output of a Programmable Gain Amplifier (PGA) is loaded by the input differential gate capacitance of a plurality of Analog to Digital converters (ADC) comparators and the differential metal layer traces to interconnect these comparators to the PGA. The differential capacitive load presented to the PGA is quite large and reduces the bandwidth of this interconnect between the PGA and ADC. To overcome the performance degradation due to the differential capacitive load, an active negative-capacitor circuit cancels the effect of the large input capacitance of the ADC comparators. This cancellation extends the gain characteristics of the interconnect between the PGA's output and the inputs of the first stage of the comparators. The active negative-capacitance is comprised of a cross pair NMOS with a capacitor connecting their sources where each NMOS is biased by a current source. | 2014-03-06 |
20140062622 | LOW-FREQUENCY EQUALIZER CIRCUIT FOR A HIGH-SPEED BROADBAND SIGNAL - A method of compensating for loss of a high-speed broadband signal may include receiving a high-speed broadband signal. The method may also include at least partially compensating for a low-frequency loss associated with a low-frequency component of the high-speed broadband signal. The compensation for the low-frequency loss may be based on a transfer function that may include a pole with a pole-frequency associated with the low-frequency component of the high-speed broadband signal. | 2014-03-06 |
20140062623 | REMOTE OPERATED CIRCUIT BREAKER - A circuit breaker having a movable contact arm for opening and closing the circuit which is controlled separately by a circuit breaker mechanism for circuit protection and by a switch lever mechanism which does not require actuation of the circuit breaker mechanism to function. The switch lever may be activated by a solenoid or other suitable means, and various interlocking mechanical states exist among the elements that provide added safety features. | 2014-03-06 |
20140062624 | RELAY HAVING A MODIFIED FORCE-DISPLACEMENT CHARACTERISTIC - An electromagnetic relay including at least one contact-set support in which a plurality of contact springs are fixed at the base end and, in pairs, form normally open and/or normally closed contacts, wherein at least one actuator acts on each active contact spring, the actuator being movably driven in the longitudinal direction thereof by a magnet system and having actuating surfaces for acting on the respective contact spring to be actuated, the actuating surfaces assigned to each of the active contact springs forming an angle with the direction of actuation of the actuator. | 2014-03-06 |
20140062625 | ELECTROMAGNETIC CONTACTOR - An electromagnetic contactor has a pair of fixed contacts disposed maintaining a predetermined interval and a movable contact disposed to be capable of connecting to and separating from the pair of fixed contacts; and an electromagnet unit that drives the movable contact. The electromagnet unit includes a magnetic yoke enclosing a plunger drive portion; a movable plunger in which a leading end is protruding through an aperture formed in the magnetic yoke, and urged by a return spring; and an annular permanent magnet enclosing a peripheral flange portion formed on a protruding end side of the movable plunger, and magnetized in a moving direction of the movable plunger. | 2014-03-06 |
20140062626 | ELECTROMAGNETIC RELAY - An electromagnetic relay including an electromagnet, a movable contact actuated by the electromagnet, and a fixed contact disposed opposite to the movable contact and capable of contacting and separating from the movable contact. The electromagnetic relay further includes a backstop for stopping movement of the movable contact in a direction separating from the fixed contact, and a backstop positioner for setting the backstop at a position for defining a predetermined contact gap between the fixed contact and the movable contact. In a state where movement of the movable contact is stopped by the backstop, different-sized contact gaps are defined between the fixed contact and the movable contact, depending on the position of the backstop set by the backstop positioner. | 2014-03-06 |
20140062627 | ELECTROMAGNETIC CONTACTOR - An electromagnetic contactor has a contact device including a pair of fixed contacts disposed maintaining a predetermined distance and a movable contact disposed to be capable of contacting to and separating from the pair of fixed contacts. The pair of fixed contacts each includes a support conductor portion supported by an upper plate of a contact housing case, and a contact conductor portion connected to an end portion of the support conductor portion. The contact conductor portion includes a contact plate portion formed with a contact portion, and a connecting plate portion formed on an outer end portion of the contact plate portion and extending to the upper plate side. The movable contact is mounted onto a connecting shaft connected to a drive portion through a contact spring on an end portion on the upper plate side, and disposed to face the contact portion of the pair of fixed contacts. | 2014-03-06 |
20140062628 | ELECTROMAGNETIC ACTUATOR DEVICE - An electromagnetic actuator device has a coil unit ( | 2014-03-06 |
20140062629 | MAGNETIC ASSEMBLY - A magnetic assembly for use in a housing of an electronic device can include a first and a second magnet and a magnetic shield. The magnetic shield can reduce magnetic flux density from the first and the second magnets that can appear on the outside of the housing. A magnetic hinge assembly can include magnets configured to correlate with the first and second magnets. The magnetic hinge can magnetically attach to the housing by cooperating with the first and second magnets with magnets that can be included in the magnetic hinge. | 2014-03-06 |
20140062630 | PERMANENT MAGNET AND METHOD FOR MANUFACTURING THE SAME, AND MOTOR AND POWER GENERATOR USING THE SAME - According to one embodiment, a permanent magnet is provided with a sintered body having a composition represented by R(Fe | 2014-03-06 |
20140062631 | NdFeB SYSTEM SINTERED MAGNET - A NdFeB system sintered magnet produced by the grain boundary diffusion method and has a high coercive force and squareness ratio with only a small decrease in the maximum energy product. A NdFeB system sintered magnet having a base material produced by orienting powder of a NdFeB system alloy and sintering the powder, with Dy and/or Tb (the “Dy and/or Tb” is hereinafter called R | 2014-03-06 |