10th week of 2014 patent applcation highlights part 42 |
Patent application number | Title | Published |
20140063832 | LED LAMP FOR CAR USE - An LED lamp for car use can be mounted in a long strip-shaped installation position, comprises a case, a light-reflecting base, a light source series and a lens base. The case is mounted corresponding to the installation position and the case has an opening and a first fixing part mounted opposite to the opening for being connected securely to the light-reflecting base. The light-reflecting base has a plurality of reflectors. Each of the reflectors has a second fixing part for being connected securely to the light source series. The light source series has a plurality of first LED lights and a plurality of second LED lights. The lens base located at the opening wraps the opening. The LED lamp for car use of the present invention can be used as a fog light or a daytime running light, and save space for installation of lamps in a car. | 2014-03-06 |
20140063833 | LAMP FOR VEHICLE - A lamp for a vehicle, and more particularly, a lamp for a vehicle capable of forming a suitable light irradiation pattern and improving chromatic aberration so as to prevent light blindness is provided. In particular, the lamp includes a light source unit including at least one light source, a shield unit configured to block a part of the light irradiated from the light source unit by one or more light blocking portions formed to have an outer circumferential end (curved end) toward an optical axis of the light source unit, and a lens unit configured to irradiate the light passing through the shield unit to the outside. | 2014-03-06 |
20140063834 | HEAD LAMP FOR VEHICLE AND METHOD OF CONTROLLING THE SAME - Disclosed are a head lamp for a vehicle and a method of controlling the same. The head lamp for a vehicle according to an exemplary embodiment of the present invention includes: a first lamp module; and a second lamp module disposed at a front side of the first lamp module, in which a mode of the second lamp module is set to one of a first mode in which a portion of the second lamp module is overlapped with the first lamp module on a light proceeding path, and a second mode in which the second lamp module is not overlapped with the first lamp module. | 2014-03-06 |
20140063835 | BULB FIXING INTO SLEEVE FOR A VEHICLE HEADLAMP - A headlamp for an automobile is provided with one or more features that improve the positioning of the headlamp during installation and the securing of the headlamp during use. More particularly, the bulb is provided with one or more raised features that are matched by complementary features on a sleeve into which the bulb is inserted. Such features can be provided along one side or opposing sides of the bulb. | 2014-03-06 |
20140063836 | Laser Lighting Device - A laser lighting device, including a laser light source and a light pipe, is disclosed. The laser light source can produce a laser beam with a diffusion angle not larger than 30 degrees. The light pipe is disposed in a light path of the laser beam, and has a light incident surface, a light exiting surface and several cut planes. The light incident surface is opposite to the laser light source, and the cut planes are located between the light incident and light exiting surfaces. Each of the cut planes is normal to the longitudinal direction of the light pipe, and has an area smaller than that of the light exiting surface but larger than that of the light incident surface. The areas of the cut planes increase sequentially along the longitudinal direction. The laser beam will be effectively collimated by the light pipe after passing through the light pipe. | 2014-03-06 |
20140063837 | LED BASED LIGHTING SYSTEM - An LED lighting system comprises an LED assembly for emitting light. A bulb comprises an enclosure and an optic element in the enclosure for receiving the light from the LED assembly and transmitting the light from the enclosure. An Edison-style or other traditional-style base is provided on the bulb for connecting the bulb to an Edison-style or other traditional-style socket. | 2014-03-06 |
20140063838 | FLAME RETARDANT LIGHT DIFFUSING FIBER - This disclosure is directed to lighting diffusing fibers (LDFs) having a flame retardant coating thereon. The LDFs comprise a glass RAL fiber core having a primary polymer coating of a clear, colorless polymeric material having an index of refraction less than that of the glass fiber core and a flame retardant coating applied over the primary coating. The flame retardant coating consist of approximately 35-85 wt. % UV curable polymer forming monomers and 15-65 wt. % of an inorganic, halogen free filler, along with at least one photoinitiator and an antioxidant. In an embodiment phosphor-containing polymer layer can be applied between the primary coating and the flame retardant coating. In another embodiment the phosphor can be added to the flame retardant coating. | 2014-03-06 |
20140063839 | SIDE EMITTING OPTICAL APPARATUS AND METHOD FOR POSSIBLE USE IN AN AIRCRAFT - Side emitting optical apparatuses and methods. In some embodiments, a transparent optical element includes a plurality of diffusive side areas that are configured to disrupt the travel path of a light ray traversing along a longitudinal axis of the optical element to re-direct the light ray out of the side of the optical element. In some embodiments, the diffusive side areas are configured such that the light is emitted more uniformly along a length of the optical element. | 2014-03-06 |
20140063840 | LIGHT SOURCE STRUCTURE FOR OPTICAL FIBER DISPLAY DEVICE AND OPTICAL FIBER DISPLAY DEVICE - Embodiments of the present invention provide a light source structure for optical fiber display device and an optical fiber display device. The light source structure for optical fiber display device comprises a light source. The light source structure for optical fiber display device is of a hollow truncated cone structure, a upper surface, a side surface and a lower surface of the hollow truncated cone structure are constituted by the light source, a reflection cover and an optical fiber connection surface, respectively, a light emitting surface of the light source is disposed to face the optical fiber connection surface, a reflection surface of the reflection cover is provided inside the hollow truncated cone structure, and the optical fiber connection surface has an optical fiber connection region that corresponds to the position of the light source and has a same size as the light source. | 2014-03-06 |
20140063841 | FRONT LIGHT MODULE - A front light module is installed in front of a panel, and the front light module includes a light source, a light guide plate and an intermediate layer disposed on an external side of the panel, and the light guide plate is provided for receiving a light emitted from the light source and reflecting and refracting the light onto the panel, and the light guide plate has a plurality of microstructures disposed on at least one side parallel to the panel, and the intermediate layer is filled and distributed in the microstructures, so as to avoid glare and enhance the brightness and uniformity of the panel. | 2014-03-06 |
20140063842 | LIGHT-EMITTING DEVICE AND IMAGE DISPLAY APPARATUS - A light-emitting device includes: a light guiding member; a plurality of light-emitting elements; and a reflection member. A light reflection/exit surface of the light guiding member has a concave-convex pattern including a plurality of convex portions reflecting light emitted from the light-emitting elements inward. On the assumption that L is a distance between the light-emitting elements, t is a thickness of the light guiding member, an incident angle φ of the light on the light reflection/exit surface is an angle between a line segment obtained by projecting a light path from the light-emitting element to the light reflection/exit surface and a line segment extending from a central point of the light-emitting element to the light reflection/exit surface, and θ is a maximum angle range of reflected light, a value of the angle range θ decreases as a value of the incident angle φ increases in a range of 0<φ2014-03-06 | |
20140063843 | DISPLAY DEVICE - Provided is a display device, which includes a light source, a light guide plate, a light conversion member, and a display panel. Light is incident to the light guide plate from the light source. The light conversion member is between the light source and the light guide plate. The display panel is on the light guide plate. The light guide plate includes a central region corresponding to an available display region of the display panel for displaying an image, an outer region around the central region, and a total reflection surface inclined from an optical axis of the light source, and disposed in the outer region. | 2014-03-06 |
20140063844 | BACKLIGHT MODULE AND LIQUID DISPLAY DEVICES WITH THE SAME - A backlight module and a liquid crystal device are disclosed. The backlight module includes a plastic frame, an aluminum extrusion, and a light guiding plate. The plastic frame and the aluminum extrusion prohibit the light guiding plate from moving in an up and down direction. Wherein the light guiding plate is disposed on the aluminum extrusion. The light guiding plate includes a body, and a first position portion extends along the body towards the aluminum extrusion. The aluminum extrusion includes a position slot corresponding to the first position portion, and the first position portion closely engages with the first position slot. The backlight module and the liquid crystal device fix the light guiding plate by engaging the light guiding plate, the aluminum extrusion, and the plastic frame so that the light guiding plate is stably fixed and the light coupling is stable. | 2014-03-06 |
20140063845 | LIGHT-GUIDING PLATE AND PLANE ILLUMINATION APPARATUS THEREWITH - A light-guiding plate and a plane illumination apparatus therewith are disclosed. The plane illumination apparatus includes the light-guiding plate and at least one light-emitting source. The light-guiding plate includes a light incident surface, a first surface opposite to the light incident surface, a second surface between the light incident surface and the first surface, and a light emitting surface opposite to the second surface. The second surface is coated with diffuse reflection layer. The first surface gradually extends substantially toward the light incident surface from its one side near to the second surface to the other side near to the light emitting surface. The light-emitting source is disposed corresponding to the light incident surface for providing a light beam. | 2014-03-06 |
20140063846 | SURFACE LIGHT SOURCE DEVICE AND EDGE-LIT TYPE BACKLIGHT MODULE - The invention provides a surface light source device and an edge-lit type backlight module. The surface light source device comprises: a luminant, a bottom reflector plate, a light leaking plate and a plurality of side reflector plates, wherein the bottom reflector plate and the plurality of side reflector plates form a light guide box with an upper opening, the luminant is disposed on at least one of the plurality of side reflector plates, the light leaking plate is disposed in the upper opening of the light guide box, such that light from the luminant is transformed into an exiting surface light via the light leaking plate. | 2014-03-06 |
20140063847 | LIGHT EMITTING APPARATUS - A light emitting apparatus in which light of different colors can be irradiated depending on the locations of a light guide member used in the light emitting apparatus and in accordance with the environment of a facility or a user's demand, a light source member includes a plurality of light source members each with one or more light sources, and adjacent light source parts emitting light of different colors with each other. The light guide member includes a recess which is formed between the respective input surfaces through which the light from the corresponding light source parts is input and which has a recess side surface that reflects at least some of the light input through the input surfaces; a plurality of extension parts that respectively guide mainly the light input from the corresponding light source parts through the input surfaces; and a cutout portion formed between the extension parts. | 2014-03-06 |
20140063848 | BACKLIGHT MODULE AND DISPLAY DEVICE - According to the present disclosure, there are provided a backlight module and a display device. With the backlight module, a heat dissipating device can be saved, and a light guide plate is prevented from being warped and deformed due to heat generation of a light source. The backlight module comprises a light source, a light guide plate and a side-glowing optical fiber. The side-glowing optical fiber includes: a light emitting section which is fixed to at least one side of the light guide plate; and a light guide section, which extends from the light emitting section to the outside of the light guide plate, and a terminal of which is connected to the light source. | 2014-03-06 |
20140063849 | BACKLIGHT MODULE WITH LIGHT-GUIDING PORTIONS - A backlight module includes a substrate, a plurality of LED packages mounted on the substrate and a light diffusion board located above the LED packages. The light diffusion board includes a light incident surface facing toward the LED packages and a light output surface. A plurality of light-guiding portions is configured extending from the incident surface of the light diffusion board toward the LED package. Each light-guiding portion comprises a concave surface at an outer periphery thereof. A diameter of each light-guiding portion decreases gradually from light diffusion board toward the LED packages. The concave surface of each light-guiding portion is recessed inwardly from the outer periphery of the light-guiding portion. Light from the LED packages and emitting into the light-guiding potions is divergently and uniformly adjusted into the light diffusion board by the concave surfaces of the light-guiding portions. | 2014-03-06 |
20140063850 | Backlight And Liquid Crystal Module - A backlight and a liquid crystal module having the same are provided. The backlight comprises: a light guide plate, a light-guide-plate fixing element for fixing the light guide plate, and at least one light source disposed adjacent to the light guide plate, wherein the light-guide-plate fixing element is made of thermal-contractive material. As the light-guide-plate fixing element is made of thermal-contractive material, in a test environment of high temperature and high humidity, it is possible to ensure that the light guide plate can expand and contract freely without resistance; meanwhile; while at normal temperatures, as the tight-guide-plate fixing element is in contact with the light guide plate without gap therebetween. | 2014-03-06 |
20140063851 | DISPLAY DEVICE - A brightness distribution of light emitted from one specific light source and outputted from the light outputting part of a light-guide part has a characteristic of having a mountain-shaped distribution increasing from a position of the specific light source, then reaching a maximum value, and then decreasing with distance from a specific light source, and a light source adjacent to the specific light source is disposed at a position where a brightness distribution decreases from the maximum value of the brightness distribution. | 2014-03-06 |
20140063852 | LIGHT GUIDE PLATE, PLANAR LIGHTING DEVICE AND METHOD OF MANUFACTURING LIGHT GUIDE PLATE - A light guide plate is provided which is high in light use efficiency, and is capable of emitting light with reduced luminance unevenness and obtaining a convex distribution. The light guide plate includes two or more layers which change in thickness in a direction substantially perpendicular to a light exit surface. A combined particle concentration changes so as to have a first local maximum value on a side closer to each of one or more light incidence surfaces and a second local maximum value which is larger than the first local maximum value. Each of the one or more light incidence surfaces is a roughened surface obtained by forming a cut and polished surface having a given periodic structure in a direction parallel to a longitudinal direction of each of the one or more light incidence surfaces. | 2014-03-06 |
20140063853 | FILM-BASED LIGHTGUIDE INCLUDING A WRAPPED STACK OF INPUT COUPLERS AND LIGHT EMITTING DEVICE INCLUDING THE SAME - A lightguide includes a plurality of coupling lightguides extending from a body of film. The plurality of coupling lightguides are folded and arranged in a stack, wherein a region of the film is wrapped around at least one side of the stack of the plurality of coupling lightguides. | 2014-03-06 |
20140063854 | APPARATUS AND METHOD FOR MANUFACTURING LIGHT GUIDING PLATE - Provided is an apparatus for manufacturing a light guiding plate. The apparatus for manufacturing a light guiding plate includes an unwinding unit unwinding a film formed of a flexible material and wound in a roll shape, a winding unit winding the film provided from the unwinding unit in a roll shape, a surface treatment unit disposed between the unwinding unit and the winding unit to treat a surface of the film transferred into the winding part into a hydrophobic surface, a pattern formation unit disposed between the surface treatment unit and the winding unit to form a micro lens pattern on the surface of the film of which the surface is treated, and a pattern curing unit disposed between the pattern formation unit and the winding unit to cure the pattern. | 2014-03-06 |
20140063855 | BACKPLATE, BACKLIGHT MODULE AND DISPLAY DEVICE - The embodiments of the invention provided a backplate, a backlight module and a display device. The backplate comprises a bottom plate; an outer surface of the backplate is coated with a heat dissipation paint. The backlight module comprises the afore-mentioned backplate and a light source directly disposed on the backplate. The display device comprises the afore-mentioned backlight module. The backplate dissipates heat from the light source without a heat dissipation unit, thereby reducing the cost. | 2014-03-06 |
20140063856 | VOLATGE CONVERTING APPARATUS AND SUB-HARMONIC DETECTOR THEREOF - A voltage converting apparatus and a sub-harmonic detector are disclosed. The sub-harmonic detector includes a pulse eliminating circuit, a counter, and a comparator. The pulse eliminating circuit receives a pulse width modulation (PWM) signal and a reference PWM signal having a same period. The PWM signal and reference PWM signal has a plurality of pulses and reference pulses respectively. The pulse eliminating circuit eliminates at least one part of the pulses which overlap with the reference pulses for generating a processed signal. The counter counts the processed signal and the PWM signal during a time period to obtain first and second counting values. The comparator compares the first and second counting values for detecting whether a sub-harmonic condition happens or not in the PWM signal. | 2014-03-06 |
20140063857 | METHOD AND APPARATUS FOR CONTROLLING A LIGHTING DEVICE - Aspects of the disclosure provide a method. The method includes determining a power adjustment to a load, determining whether a switching frequency of a pulse width modulation (PWM) signal is within a specific range, and adjusting the switching frequency of the PWM signal based on the power adjustment to control power transfer to the load. The switching frequency is adjusted to remain in the specific range. | 2014-03-06 |
20140063858 | Supply voltage control - A disconnect device for a switched-mode power supply, including an activation device for a first transistor for generating a transformable voltage. The device includes a second transistor of the PNP type and a third transistor of the NPN type, the base of the second transistor being connected to the collector of the third transistor and the base of the third transistor being connected to the collector of the second transistor. The emitter of the third transistor is connected to ground. The emitter of the second transistor is connected to a control voltage terminal of the activation device, the control voltage terminal being configured for suppressing the generation of the voltage by the first transistor, if the control voltage terminal is connected to ground, so that the generation of the voltage is suppressed if the base of the third transistor is acted upon by a voltage exceeding a predetermined threshold value. | 2014-03-06 |
20140063859 | POWER SUPPLY DEVICE - A power supply device is provided. The power supply device includes: a transformer configured to include first and second windings; a half bridge circuit configured to be connected to first and second nodes and both ends of the first wiring; and a full bridge circuit configured to be connected to third and fourth nodes and both ends of the second winding. Since the leakage inductance of the transformer and the bridge capacitor of the half bridge circuit form a direct current (DC) resonant tank, switching loss that may occur during the turning on or off of switches can be reduced. | 2014-03-06 |
20140063860 | DC POWER SOURCE DEVICE AND POWER CONVERSION METHOD - FETs disposed in a DC/DC converter are each driven by a drive transformer. A voltage from a single drive power supply disposed in common for the FETs is divided into positive and negative biases to be applied to the FETs, and an operational state of the FETs is detected based on voltage signals. A sequence circuit turns on an input from a three-phase AC power supply by driving a relay circuit at a time point when it is confirmed that the FETs have normally started stable ON/OFF operation, and drives a power factor improvement circuit, which converts AC voltage from the three-phase AC power supply into a DC voltage by simultaneously performing full-wave rectification and power factor improvement. | 2014-03-06 |
20140063861 | AC-DC VOLTAGE CONVERTER WITH LOW STANDBY POWER CONSUMPTION AND CONTROL METHOD THEREOF - Disclosed are AC-DC voltage converter circuits and methods for low standby power consumption. In one embodiment, a method can include: (i) detecting operating states of an input power supply, where the input power supply is received by a safety capacitor and provided to a switching power supply circuit after being rectified and filtered; (ii) removing a phantom load when the input power supply operates in a normal operating state; (iii) loading the phantom load when the input power supply operates in an under voltage lock out state; and (iv) when the input power supply operates in the under voltage lock out state, using energy stored in the safety capacitor to supply power to a load of the switching power supply circuit and the phantom load, and disabling a power stage circuit until a voltage of the safety capacitor is reduced to less than a safety threshold value. | 2014-03-06 |
20140063862 | VARYING SWITCHING FREQUENCY AND PERIOD OF A POWER SUPPLY CONTROLLER - A controller includes a PWM circuit and a timing circuit. The PWM circuit controls a switch in response to a clock signal. A switching period of the clock signal is based on a charging and discharging time of a capacitor included in the timing circuit. Both first and second current sinks discharge the capacitor while the timing circuit is in a normal discharging mode that is when an on time of the switch is less than a threshold time. The second current sink is prevented from discharging the capacitor such that the capacitor is discharged with the first current sink and not the second current sink while the timing circuit is in an alternative discharging mode that is when the on time of the switch exceeds the threshold time. The discharging of the capacitor in the alternative discharging mode increases the switching period of the clock signal. | 2014-03-06 |
20140063863 | ENERGY TRANSFER ASSEMBLY WITH TUNED LEAKAGE INDUCTANCE AND COMMON MODE NOISE COMPENSATION - An energy transfer assembly includes first and second windings wound around a bobbin. The first winding has a first number of layers proximate to a first end and a second number of layers proximate to a second end of the bobbin. The second winding has a third number of layers proximate to the first end and a fourth number of layers proximate to the second end. At least a portion of one of the first and second windings overlaps at least a portion of the other one of the first and second windings. A degree of overlap between the first and second windings is non-uniform. An isolation barrier is between the first and second windings and around the bobbin. A distance between the isolation barrier and an axis of the bobbin varies along the length of the bobbin. | 2014-03-06 |
20140063864 | ELECTRONIC DEVICE - An electronic device includes a magnetic element, a first circuit module and a second circuit module. The magnetic component includes a magnetic core set and a winding, and the winding includes a first winding and a second winding, and the winding is assembled on the magnetic core set. The first circuit module is connected to the first winding of the magnetic element. The second circuit module is connected to the second winding of the magnetic element. The first circuit module or/and the second circuit module has/have an overlap portion with the winding on a vertical projection area of a first plane, and the first plane is the first plane is a horizontal plane at which the winding is located. | 2014-03-06 |
20140063865 | DC/DC CONVERTER - A pulse modulator generates a pulse modulation signal S | 2014-03-06 |
20140063866 | METHOD AND APPARATUS FOR A CONTROL CIRCUIT RESPONSIVE TO AN IMPEDANCE COUPLED TO A CONTROL CIRCUIT TERMINAL - A controller includes a current sense circuit and a voltage regulation circuit. The current sense circuit generates a first signal that indicates whether a current through a sense terminal exceeds a first threshold current level, which indicates a fault condition of a power converter. The voltage regulation circuit regulates the sense terminal to a first voltage level when the current through the terminal is less than the first threshold current level and regulates the sense terminal to a second voltage level when the current exceeds the first threshold current level. The current sense circuit generates a second signal that indicates whether the current through the sense terminal exceeds a second threshold current level while the sense terminal is regulated to the second voltage level. The response circuit generates an output signal that determines a response of the controller to the fault condition based on the second signal. | 2014-03-06 |
20140063867 | APPARATUS AND METHOD FOR SENSING OF ISOLATED OUTPUT - A switched-mode power supply includes an energy transfer element coupled between a primary side and a secondary side. A first main terminal of a switch is coupled to the energy transfer element and a second main terminal of the switch is coupled to an input of the primary side. A driver circuit is coupled to drive the switch to be open at a first one of a plurality of levels and closed at a second one of the plurality of levels. The driver circuit is coupled to drive the switch to be substantially independent of a voltage between the first and second main terminals at a third one of the plurality of levels. A current conducted between the first and second main terminals at the third one of the plurality of levels is sufficient to only partially discharge a capacitance that is coupled to the first main terminal. | 2014-03-06 |
20140063868 | POWER SUPPLY APPARATUS WITH POWER FACTOR CORRECTION AND PULSE WIDTH MODULATION MECHANISM AND METHOD THEREOF - A power supply apparatus that includes a pulse width modulation (PWM) based power conversion unit and a power factor correction (PFC) conversion unit is provided. The PWM-based power conversion unit is configured to receive a direct current (DC) input voltage and perform pulse width modulation on the received DC input voltage in response to a power supply request of a load, so as to generate a DC output voltage to the load. The PFC conversion unit is coupled to the PWM-based power conversion unit and configured to perform power factor correction on a rectification voltage associated with an alternating current (AC) input voltage, so as to generate the DC input voltage. The PFC conversion unit is further configured to adjust the generated DC input voltage in response to a variation of the load. | 2014-03-06 |
20140063869 | METHODS OF BALANCING REACTIVE POWER IN MULTI-LEVEL MOTOR DRIVES WITH ACTIVE FRONT ENDS - A method of balancing reactive power at a power delivery system is disclosed. The method may include operating a power delivery system that may have a plurality of power cells that are electrically connected to a first transformer comprising one or more primary windings and a plurality of secondary windings such that each cell is electrically connected to one of the secondary windings and a plurality of the secondary windings are phase-shifted with respect to the primary windings. The method may further include controlling the reactive current flow at each power cell by calculating, at a first controller, a reactive current flow adjustment for at least one power cell so that reactive current flow is balanced among each of the plurality of power cells. Each cell may include a plurality of switching devices. | 2014-03-06 |
20140063870 | APPARATUS AND METHODS FOR RESTORING POWER CELL FUNCTIONALITY IN MULTI-CELL POWER SUPPLIES - A method is provided for operating a multi-cell power supply that includes multiple series-connected power cells in each of multiple legs. Each power cell includes a bypass device that may be used to selectively bypass and de-bypass the power cell. After a first power cell faults and is bypassed as a result of the fault, the method includes de-bypassing the first power cell without stopping the multi-cell power supply if the first power cell fault was caused by a predetermined operating condition. Numerous other aspects are provided. | 2014-03-06 |
20140063871 | POWER DELIVERY SYSTEMS AND METHODS FOR OFFSHORE APPLICATIONS - A system for delivering power to an offshore load is disclosed. The system may include an on-land source of three-phase power, an on-land AC-to-DC power conversion module, a DC transmission line, and an offshore DC-to-AC power inverter. The on-land AC-to-DC power conversion module may be configured to convert the three-phase power to DC power. The DC transmission line may have a source end and a load end, where the source end is configured to receive DC power from the on-land AC-to-DC power conversion module. The offshore DC-to-AC power inverter may be configured to receive DC power from the DC transmission line, convert the DC power to three-phase AC power, and deliver the three-phase AC power to an offshore load. | 2014-03-06 |
20140063872 | Digital EMI Filter - The invention provides a digital active EMI filter that removes, minimizes, or reduces unwanted interference (i.e., EMI noise) generated by a power circuit such as, for example, a power converter. Digital active filtering includes digital sampling of the incident noise signal amplitude and frequency, discrete time conversion of the EMI noise source, processing (e.g., inverting) the digital signal, and then constructing an analog output signal (i.e., an EMI compensation signal) which is injected to the input of the power circuit. A digital EMI filter as described herein may be used in both differential-mode and common-mode configurations, and overcomes limitations of passive and active analog EMI filters. | 2014-03-06 |
20140063873 | METHOD AND APPARATUS FOR INVERTER OUTPUT CURRENT HARMONIC REDUCTION - Method and apparatus for reducing harmonic distortion. In one embodiment, the method comprises determining an inverter output current waveform; determining a plurality of harmonic components of the inverter output current waveform; determining, based on the plurality of harmonic components, a plurality of harmonic compensation components; and generating a compensating current comprising the plurality of harmonic compensation components | 2014-03-06 |
20140063874 | HIGH-FREQUENCY-LINK POWER-CONVERSION SYSTEM HAVING DIRECT DOUBLE-FREQUENCY RIPPLE CURRENT CONTROL AND METHOD OF USE - A direct double-frequency ripple current control in a two-stage high-frequency-link (HFL) based fuel cell converter that can achieve low-frequency ripple free input current without using large electrolytic capacitors is provided. To eliminate the double-frequency ripple current disturbance introduced by the single-phase inverter load, a proportional-resonant (PR) controller is developed to achieve an extra high control gain at designed resonant frequency. This high gain can be viewed as the virtual high impedance for blocking the double-frequency ripple energy propagation from inverter load to fuel cell stack. More particularly, the proposed control system can realize the utilization of all capacitive ripple energy sources in the system by regulating all the capacitors to have large voltage swing and the voltage swing is synchronized to keep real-time balancing of the transformer primary-side and secondary-side voltages. As a result, the zero-voltage-switching (ZVS) operation for all switching devices in the dc-dc stage can be guaranteed. | 2014-03-06 |
20140063875 | START-UP CIRCUIT AND METHOD FOR AC-DC CONVERTERS - An AC-DC power converter includes a rectifying unit for generating a rectified voltage, an output stage for converting the rectified voltage into a DC voltage for a load, a controller for controlling the output stage, and a start-up circuit. The start-up circuit includes a first power section coupled to the rectifying unit and configured to generate a first voltage from the rectified voltage and to output the first voltage to the controller to enable the controller before the output stage starts outputting power. The first power section includes a depletion mode transistor having a first terminal configured to receive the rectified voltage and a second terminal configured to output the first voltage. | 2014-03-06 |
20140063876 | APPARATUS AND METHODS FOR INPUT PROTECTION FOR POWER CONVERTERS - Systems and methods in accordance with this invention provide a power converter including an input signal terminal, a first output signal at a first output signal terminal, and a controller. The controller is adapted to switch the first output signal from a first value to a second value, measure a voltage at the input signal terminal as a function of time, set a flag to a first flag value if the measured voltage falls below a predetermined value within a first predetermined time interval after the first output signal has been switched from the first value to the second value, otherwise set the flag to a second flag value, and save the flag in a memory. Numerous other aspects are also provided. | 2014-03-06 |
20140063877 | POWER CONVERSION APPARATUS - A power conversion apparatus according to the present invention includes a plurality of PWM converters ( | 2014-03-06 |
20140063878 | PARALLEL POWER SUPPLY AND POWER DETECTION METHOD FOR PARALLEL POWER SUPPLY - A parallel power supply includes a built-in test switch and a control and determination unit. The built-in test switch is arranged to generate a first detection signal. The control and determination unit is coupled to the built-in test switch. When receiving the first detection signal, the control and determination unit is operative for enabling a detection mechanism according to the first detection signal in order to detect an operation of the parallel power supply, and accordingly generating a detection result. A power detection method for a parallel power supply includes: disposing a built-in test switch inside the parallel power supply; and when receiving a first detection signal generated from the built-in test switch, enabling a detection mechanism according to the first detection signal in order to detect an operation of the parallel power supply, and accordingly generating a detection result. | 2014-03-06 |
20140063879 | RECTIFIER CIRCUIT AND ELECTRONIC DEVICE USING SAME - A rectifier circuit includes a three-phase alternating current (AC) voltage, a first rectifier unit, a second rectifier unit, a third rectifier unit, a first voltage output terminal, a second voltage output terminal, a first energy storing circuit and a second energy storing circuit. The three-phase AC voltage generates a first AC voltage, a second AC voltage, and a third AC voltage, and outputs them to the first rectifier circuit, a second rectifier circuit, and a third rectifier circuit correspondingly. The first energy storing circuit and the second storing circuit are connected in series and are coupled between the first voltage output terminal and the second voltage output terminal, to drive a load. In a positive period of each AC voltage, the second energy storing circuit is charged by each rectifier unit. In a negative period of each AC voltage, the first energy storing circuit is charged by each rectifier unit. | 2014-03-06 |
20140063880 | RECTIFIER CIRCUIT AND ELECTRONIC DEVICE USING SAME - A rectifier circuit includes a first alternating current (AC) voltage input terminal, a second AC voltage input terminal, a signal generating circuit, a first energy generating circuit, a second energy generating circuit, a third energy generating circuit, a first output terminal, and a second output terminal The first and second AC voltage input terminals receive an AC voltage. The signal generating circuit generates control signals. The first energy storing circuit is charged by the AC voltage. In a positive period of the AC voltage, the first energy storing circuit discharges to the second energy storing circuit. In a negative period of the AC voltage, the first energy storing circuit discharges to the third energy storing circuit The second energy storing circuit and the third energy storing circuit discharge to a load via the first output terminal | 2014-03-06 |
20140063881 | INVERTER AND DRIVING METHOD THEREOF - An inverter according to an embodiment of the present disclosure may include a converter having a switch, configured to convert a DC voltage into a half-wave rectified sine waveform voltage; a switching device unit having a switch, configured to convert the half-wave rectified sine waveform voltage into a sine waveform voltage; and a controller configured to control the on/off of the switch of the converter and the switch of the switching device unit. | 2014-03-06 |
20140063882 | Circuit Arrangement with Two Transistor Devices - A circuit arrangement includes a first transistor device and a second transistor device. Each transistor device includes a first load terminal, a second load terminal, a gate terminal, and a control terminal. The first load terminals are electrically connected, and the control terminals are electrically connected. A capacitive storage element is connected between the first load terminals and the control terminals. | 2014-03-06 |
20140063883 | SYSTEM FOR OPTIMIZING SWITCHING DEAD-TIME AND METHOD OF MAKING SAME - A system for optimizing switching dead-time includes a power converter that includes a half-bridge circuit comprising a first switch coupled in series with a second switch, first and second state detection circuits respectively coupled to the first and second switches and configured to respectively detect an activation state of the first and second switches. First and second switch control circuits coupled respectively to the first and second switches are configured to respectively toggle the first and second switches between an activate state and a deactivated state. The first switch control circuit includes a first input configured to receive an activation signal from the second state detection circuit indicative of the activation state of the second switch, and the second switch control circuit includes a first input configured to receive an activation signal from the first state detection circuit indicative of the activation state of the first switch. | 2014-03-06 |
20140063884 | INVERTER DEVICE - In an inverter device, a first three-level circuit includes first to fourth preceding-stage switch elements connected in series between a first input end and a ground and a first charging and discharging capacitor. A second three-level circuit includes fifth to eighth preceding-stage switch elements connected in series between a second input end and the ground and a second charging and discharging capacitor. The first and second two three-level circuits define a five-level circuit that is subjected to switching with the carrier frequency of PWM modulation. The output polarity of a subsequent-stage bridge clamping circuit is inverted between the anterior half cycle and the posterior half cycle of a power supply frequency. | 2014-03-06 |
20140063885 | POWER-SYSTEM-INTERCONNECTED INVERTER DEVICE - In a power-system-interconnected inverter device, PI control circuits obtain voltage correction values in directions reducing the current errors on the basis of current errors serving as differences between target current values and detection values. Multiplexers provide modulation circuits with voltage target values corrected by the voltage correction values being added to voltage detection values. The modulation circuits provide gate signals for switch elements in multilevel circuits. In addition, a sign circuit provides gate signals for switch elements in a bridge clamping circuit. | 2014-03-06 |
20140063886 | TECHNIQUES FOR SUPPRESSING MATCH INDICATIONS AT A CONTENT ADDRESSABLE MEMORY - A content addressable memory (CAM) suppresses an indication of a match in response to determining that the entry that stores data matching received compare data is the subject of a write operation. To suppress the indication, an address decoder decodes a write address associated with the write operation to determine the entry of the CAM that is the subject of the write operation, and provides control signaling indicative of the determined entry. The CAM uses the control signaling to suppress any match indications for the entry being written, thereby preventing erroneous match indications. | 2014-03-06 |
20140063887 | STACKED DRAM DEVICE AND METHOD OF MANUFACTURE - A memory stack includes a number of memory dies including a master die and one or more slave dies. The slave die can be converted to a master die by further processing. The slave die includes a memory core having memory cell arrays. The slave die also includes first and second metal layers that form first and second distribution lines in the memory core, respectively. An interface circuit in the slave die is decoupled from the first and second metal layers. | 2014-03-06 |
20140063888 | MEMORY ARRAY PLANE SELECT AND METHODS - Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged in a matrix and a plurality of plane selection devices. Groups of the plurality of memory cells are communicatively coupled to a respective one of a plurality of plane selection devices. A decode logic having elements is formed in a substrate material and communicatively coupled to the plurality of plane selection devices. The plurality of memory cells and the plurality of plane selection devices are not formed in the substrate material. | 2014-03-06 |
20140063889 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including first lines, second lines, and memory cells provided at each of intersections of the first lines and the second lines; and a control unit including a row control circuit, a first column control circuit provided on a side of one ends of the second lines, and a second column control circuit provided on a side of the other ends of the second lines, the control unit, during an access operation, controlling a potential of the first lines and the second lines such that a bias, which is lower than that applied to a certain unselected memory cell, is applied to those of unselected memory cells that are located more toward a center of the memory cell array in the column direction than the certain unselected memory cell. | 2014-03-06 |
20140063890 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including gate structures provided on a substrate, a separation insulating layer interposed between the gate structures, and a plurality of cell pillars connected to the substrate through each gate structure. Each gate structure may include horizontal electrodes vertically stacked on the substrate, and an interval between adjacent ones of the cell pillars is non-uniform. | 2014-03-06 |
20140063891 | SEMICONDUCTOR MEMORY DEVICE - According to one or more embodiments of the present invention, the semiconductor memory device of this disclosure includes the first bit line and the second bit line. Each of the multiple memory cells includes a memory element and a transistor, which are connected in series between the first and the second bit lines. Multiple memory cells are connected in parallel between the first and the second bit lines. In the first memory cell, its memory element is connected to the first bit line, and its transistor is connected to the second bit line. In the second memory cell, its memory element is connected to the second bit line, and its transistor is connected to the first bit line. | 2014-03-06 |
20140063892 | DIODE SEGMENTATION IN MEMORY - Memory devices, memory arrays, and methods of operation of memory arrays with segmentation. Segmentation elements can scale with the memory cells, and may be uni-directional or bi-directional diodes. Biasing lines in the array allow biasing of selected and unselected select devices and segmentation elements with any desired bias, and may use biasing devices of the same construction as the segmentation elements. | 2014-03-06 |
20140063893 | SHIFT REGISTER TYPE MAGNETIC MEMORY - A shift register type magnetic memory according to an embodiment includes: a magnetic nanowire; a magnetic material chain provided in close vicinity to the magnetic nanowire, the magnetic material chain including a plurality of disk-shaped ferromagnetic films arranged along a direction in which the magnetic nanowire extends; a magnetization rotation drive unit configured to rotate and drive magnetization of the plurality of ferromagnetic films; a writing unit configured to write magnetic information into the magnetic nanowire; and a reading unit configured to read magnetic information from the magnetic nanowire. | 2014-03-06 |
20140063894 | E-FUSE ARRAY CIRCUIT AND PROGRAMMING METHOD OF THE SAME - A program method for an e-fuse array circuit includes receiving an address and a multi-bit program data, programming the multi-bit program data in e-fuses designated by the address, reading a multi-bit read data from the e-fuses, and comparing bits of the multi-bit program data with bits of the multi-bit read data, wherein if the bits of the multi-bit program data are identical to the bits of the multi-bit read data, a program operation is terminated; and if the bits of the multi-bit read data are not identical to the bits of the multi-bit program data, then the programming of the multi-bit program data, the reading of the multi-bit read data, and the comparing of the bits are performed again. | 2014-03-06 |
20140063895 | LOW COST PROGRAMMABLE MULTI-STATE DEVICE - A one time programmable (OPT) and multiple time programmable (MTP) structure is constructed in a back end of line (BEOL) process using only one, two or three masks. The OTP/MTP structure can be programmed in one of three states, a pre-programmed high resistance state, and a programmable low resistance state and a programmable very high resistance state. In the programmable low resistance state, a barrier layer is broken down during an anti-fuse programming so that the OTP/MTP structure exhibits resistance in the hundred ohm order of magnitude. In the very high resistance state a conductive fuse is blown open during programming so that the OTP/MTP structure exhibits resistance in the mega-ohm order of magnitude. The OTP/MTP structure may include a magnetic tunnel junction (MTJ) structure or a metal-insulator-metal (MIM) capacitor structure. | 2014-03-06 |
20140063896 | NONVOLATILE MEMORY APPARATUS AND METHOD FOR DRIVING THE SAME - A method for driving a nonvolatile memory apparatus includes: a data storage preparation step of setting a write control voltage to a first level of voltage; a data storage step of driving a driving transistor through the write control voltage to generate a write current, and storing an external data in a memory cell through the write current; a data detection step of varying the write control voltage by a predetermined level from a preset voltage level, and reading the data stored in the memory cell; and a data verification step of determining whether the stored data coincides with the external data or not, and repeating the data storage step and the data detection step according to a result of the determining. | 2014-03-06 |
20140063897 | NON-VOLATILE MEMORY INCLUDING REFERENCE SIGNAL PATH - Some embodiments include apparatuses and methods having a first memory element and a first select component coupled to the first memory element, a second memory element and a second select component coupled to the second memory element, and an access line shared by the first and second select components. At least one of the embodiments can include a circuit to generate a signal indicating a state of the second memory element based on a first signal developed from a first signal path through the first memory element and a second signal developed from a second signal path through the second memory element. | 2014-03-06 |
20140063898 | SYSTEMS, METHODS AND DEVICES FOR PROGRAMMING A MULTILEVEL RESISTIVE MEMORY CELL - Embodiments disclosed herein may relate to programming a multi-level memory cell with programming pulse sequences that comprise forward-biased and reverse-biased programming pulses. | 2014-03-06 |
20140063899 | METHODS, DEVICES AND SYSTEMS USING OVER-RESET STATE IN A MEMORY CELL - Memory cells, devices and methods are disclosed, including those that involve applying a waveform to a resistive memory cell to program the memory cell to an over-reset state representing a logic value. | 2014-03-06 |
20140063900 | APPARATUS AND METHOD FOR DETECTING REFLOW PROCESS - Circuitry and method for detecting occurrence of a reflow process to an embedded storage device are disclosed. A temperature sensing device includes a resistor, a temperature sensor, and a comparator. The first terminal of the resistor is coupled to a voltage source, and the second terminal of the resistor is coupled to both the first terminal of the temperature sensor and the first input of the comparator. The second terminal of the temperature sensor is grounded and the second input of the comparator is coupled to a reference voltage. The resistance state of the temperature sensor changes from a first resistance state to a second resistance state when the temperature surrounding the temperature sensor reaches a threshold. The comparator generates an output based on the resistance changes of the temperature sensor. The generated output may indicate whether a reflow process has occurred to the embedded storage device. | 2014-03-06 |
20140063901 | MEMORY DEVICES, CIRCUITS AND, METHODS THAT APPLY DIFFERENT ELECTRICAL CONDITIONS IN ACCESS OPERATIONS - A memory device can include a plurality of memory elements programmable between different impedance states; and circuits configured to apply first electrical conditions to one group of memory elements and second electrical conditions, different from the first electrical conditions, to another group of memory elements to vary a speed of an access operation to the different groups of memory elements. | 2014-03-06 |
20140063902 | MEMORY DEVICES, CIRCUITS AND, METHODS THAT APPLY DIFFERENT ELECTRICAL CONDITIONS IN ACCESS OPERATIONS - A memory device can include a plurality of physical blocks that each include a number of memory elements programmable between at least two different impedance states, the memory elements being subject to degradation in performance; and bias circuits configured to applying healing electrical conditions to at least one spare physical block that does not contain valid data; wherein the healing electrical conditions are different from write operation electrical conditions, and reverse degradation of the memory elements of the at least one spare physical block. | 2014-03-06 |
20140063903 | RESISTIVE RANDOM ACCESS MEMORY, CONTROLLING METHOD AND MANUFACTURING METHOD THEREFOR - A resistive random access memory (RRAM), a controlling method for the RRAM, and a manufacturing method therefor are provided. The RRAM includes a first electrode layer; a resistance switching layer disposed on the first electrode layer; a diffusion metal layer disposed on the resistance switching layer; and a second electrode layer disposed on the diffusion metal layer, wherein at least one extension electrode is disposed in the resistance switching layer. | 2014-03-06 |
20140063904 | VARIABLE RESISTANCE MEMORY DEVICE AND OPERATING METHOD THEREOF - An operating method of a variable resistance memory device including a pre-read step which may include the steps of: reading a first reference cell using a first reference voltage; reading a second reference cell using a second reference voltage; and setting a third reference voltage based on the first and second reference voltages; and a main read step of reading a selected memory cell using the third reference voltage. | 2014-03-06 |
20140063905 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF MEASURING WRITE CURRENT AND METHOD FOR MEASURING WRITE CURRENT - A method for measuring a write current of a semiconductor memory device includes the steps of: programming initial data into memory cells which are to be programmed substantially at the same time; determining whether the memory cells are programmed into the same state or not; inputting test data when the memory cells are programmed into the same state; setting write current paths of the memory cells by comparing the initial data and the test data; and measuring a write current consumed when the test data are programmed into the memory cells. | 2014-03-06 |
20140063906 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory cells provided at each of intersections of a plurality of first lines and a plurality of second lines; | 2014-03-06 |
20140063907 | SEMICONDUCTOR MEMORY DEVICE - This semiconductor memory device comprises: a memory cell array configured as an arrangement of memory cells disposed at intersections of a plurality of first lines disposed substantially in parallel and a plurality of second lines disposed to intersect the first lines, each of the memory cells including a variable resistance element; and a control circuit configured to control the memory cell array. The control circuit is configured to change a voltage value of a resetting verify voltage applied for confirming completion of the resetting operation according to a degree of change of resistance of the memory cell when performing the resetting operation to change the memory cell from a low-resistance state to a high-resistance state. | 2014-03-06 |
20140063908 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment comprises: a memory cell array including memory cells, each of the memory cells disposed at each of intersections of first lines and second lines and including a variable resistor; and a control circuit configured to apply a first voltage to a selected first line and to apply a second voltage having a voltage value which is smaller than that of the first voltage to a selected second line, such that a selected memory cell is applied with a first potential difference required in an operation of the selected memory cell. The control circuit is configured such that when the first potential difference is applied a plurality of times to a plurality of the selected memory cells to execute the operation, the number of selected memory cells simultaneously applied with the first potential difference can be changed. | 2014-03-06 |
20140063909 | NONVOLATILE MEMORY ELEMENT, NONVOLATILE MEMORY DEVICE, AND WRITING METHOD FOR USE IN NONVOLATILE MEMORY ELEMENT - In a nonvolatile memory element, when a voltage value of an electric pulse has a relationship of V2>V1>0 V>V3>V4 and a resistance value of a variable resistance layer has a relationship of R3>R2>R4>R1, the resistance value of the variable resistance layer becomes: R2, when the electric pulse having a voltage value of V2 or greater is applied between electrodes; R4, when the electric pulse having a voltage value of V4 or smaller is applied between the electrodes; R3, when the resistance value of the variable resistance layer is R2 and the electric pulse having a voltage value of V3 is applied between the electrodes; and R1, when the resistance value of the variable resistance layer is R4 and the electric pulse having a voltage value of V1 is applied between the electrodes. | 2014-03-06 |
20140063910 | DATA VERIFICATION DEVICE AND A SEMICONDUCTOR DEVICE INCLUDING THE SAME - A semiconductor device includes a data verification device. The data verification device includes a data storage unit for storing data to be input to a memory region in response to a first or second control signal, an input data verifier for deactivating an output of a sense amplifier in response to the first control signal and transmitting the input data stored in the data storage unit to an external pad, and a sense-amplifier verifier for transmitting the input data stored in the data storage unit to the sense amplifier upon in response to the second control signal. | 2014-03-06 |
20140063911 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING SAME - A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory layers; and a control unit configured to control a voltage applied to the memory cell array. Each of the memory layers comprises a first line and a second line, and further includes a memory cell disposed between the first line and the second line and including a variable resistance element. The control unit is configured to, when executing a forming operation on the memory cell array, execute the forming operation sequentially on the plurality of memory layers. The forming operation is executed sequentially on the memory layers in ascending order of a magnitude of a non-selected current flowing in a non-selected memory cell during the forming operation. | 2014-03-06 |
20140063912 | NON-VOLATILE MEMORY DEVICE - According to an embodiment, a non-volatile memory device includes a first conductive layer, a second conductive layer, and a resistance change layer provided between the first conductive layer and the second conductive layer. The resistance change layer is capable of making a transition between a low-resistance state and a high-resistance state, and includes an oxide containing at least one of hafnium (Hf) and zirconium (Zr), at least one selected from the group consisting of barium (Ba), lanthanum (La), gadolinium (Gd) and lutetium (Lu), and nitrogen (N). | 2014-03-06 |
20140063913 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A non-volatile memory device includes: a memory cell array including a plurality of memory cells each including a variable resistance element and a first current steering element; and a current steering element parameter generation circuit. The current steering element parameter generation circuit includes: a third line placed between a substrate and a second interlayer dielectric; a fourth line placed above the second interlayer dielectric; and a second current steering element which is connected between the third line and the fourth line without the variable resistance element being interposed therebetween when the variable resistance element is removed between the third line and the fourth line and has the same non-linear current steering characteristics as the first current steering element. | 2014-03-06 |
20140063914 | VARIABLE RESISTANCE MEMORY DEVICES AND ERASE VERIFYING METHODS THEREOF - An erase verifying method includes applying a first voltage to a plurality of word lines connected to a memory cell block, and applying a second voltage less than the first voltage to a plurality of bit lines connected to the memory cell block. The method includes sensing bit line currents flowing through the plurality of bit lines, and comparing the sensed bit line currents with a reference current. The method also includes determining that the memory cell block has been sufficiently erased by a first erase operation if each of the sensed bit line currents is less than the reference current. | 2014-03-06 |
20140063915 | DIFFERENTIAL VECTOR STORAGE FOR DYNAMIC RANDOM ACCESS MEMORY - A storage device stores data in groups of memory cells using vectors corresponding to voltage code codewords, each codeword having k entries. Entries have values selected from a set of at least three entry values and 2 | 2014-03-06 |
20140063916 | SRAM LOCAL EVALUATION LOGIC FOR COLUMN SELECTION - An SRAM includes a first SRAM column having first SRAM cells and a first local evaluation logic coupled to a global bit line and a second SRAM column having second SRAM cells and a second local evaluation logic coupled to the same global bit line. The first SRAM column is selected with a first column select line and the second SRAM column is selected with a second column select line. | 2014-03-06 |
20140063917 | READ SELF-TIME TECHNIQUE WITH FINE GRAINED PROGRAMMABLE LOGIC DELAY ELEMENT - A sense amplifier enable signal delay circuit for the programmable control of the delay of the generation of a sense amplifier enable signal is described. Further, stacked transistors and a pulse-width control block, which are programmed by external test pins to control the delay of the generation of a sense amplifier enable signal are described. Methods associated with the use of the sense amplifier enable signal delay circuit and for the sense amplifier enable signal generation delay are also described. | 2014-03-06 |
20140063918 | CONTROL CIRCUIT OF SRAM AND OPERATING METHOD THEREOF - A control circuit of SRAM and an operating method thereof are provided. The control circuit includes a memory array, a word-line driver, a boost circuit and a voltage level detecting circuit. The memory array includes a plurality of memory cells. Each memory cell includes a plurality of transistors. The word-line driver is to activate the word-line of the memory array for cell storage data access. The boost circuit is to provide the higher voltage source for the word-line driver and a first operating voltage for boosting the first operating voltage to a second operating voltage. The voltage level detecting circuit is detecting if the first operation voltage needed boosted with boost-operation and a detecting-trigger signal and controls the operating of the boost circuit based on the detecting-trigger signal, the first operating voltage and a predetermined voltage. | 2014-03-06 |
20140063919 | MULTIPLE-PORT SRAM DEVICE - A method for providing a SRAM cell having a dedicated read port separated from a write port includes providing a first and a second bit-line placed in parallel forming a complementary bit-line pair for the dedicated read port, and providing a third and a fourth bit-line placed in parallel forming a complementary bit-line pair for the write port. The method further includes providing a positive voltage supply line disposed between a first and a second ground line placed in parallel, providing a first and a second metal line adjacently flanking and in parallel to the first bit-line, and providing a third and a fourth metal line adjacently flanking and in parallel to the second bit-line to provide a new SRAM cell structure having a balanced read and write operation speed and an improved noise margin. | 2014-03-06 |
20140063920 | Static random access memory that initializes to pre-determined state - A static random access memory (SRAM) is provided for establishing an initialization state. The SRAM connects to a plurality of signal lines including a bit line and an inverse bit line. The SRAM includes first and second inverters, a voltage potential and a ground. The first inverter includes a first n-type metal oxide semiconductor (MOS) transistor having a first n-type threshold voltage and a first p-type MOS transistor having a first p-type threshold voltage. The second inverter includes a second n-type MOS transistor having a second n-type threshold voltage and a second p-type MOS transistor having a second p-type threshold voltage. The first transistors connect respectively first n-type and first p-type drains together at a first junction that connects to the bit line. The second transistors connect respectively a second n-type and second p-type drains together at a second junction that connects to the inverse bit line. The voltage potential connects to corresponding first and second p-type sources of the first and second p-type MOS transistors, and the ground potential connects to corresponding first and second n-type sources of the first and second n-type MOS transistors. The SRAM initializes the bit line to either logical high or low in response to differences in threshold voltages between either or both of the first and second n-type MOS transistors or the first and second p-type MOS transistors. | 2014-03-06 |
20140063921 | METHOD AND SYSTEM FOR PROVIDING INVERTED DUAL MAGNETIC TUNNELING JUNCTION ELEMENTS - A method and system for providing a magnetic junction residing on a substrate and usable in a magnetic device are described. The magnetic junction includes a first pinned layer, a first nonmagnetic spacer layer having a first thickness, a free layer, a second nonmagnetic spacer layer having a second thickness greater than the first thickness, and a second pinned layer. The first nonmagnetic spacer layer resides between the pinned layer and the free layer. The first pinned layer resides between the free layer and the substrate. The second nonmagnetic spacer layer is between the free layer and the second pinned layer. Further, the magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. | 2014-03-06 |
20140063922 | MRAM WORD LINE POWER CONTROL SCHEME - Systems, circuits and methods for controlling word line (WL) power levels at a WL of a Magnetoresistive Random Access Memory (MRAM). The disclosed power control scheme uses existing read/write commands and an existing power generation module associated, with the MRAM to supply and control WL power levels, thereby eliminating the cost and increased die-size of schemes that control WL power through relatively large and expensive power control switches and control circuitry on the MRAM macro. | 2014-03-06 |
20140063923 | Mismatch Error Reduction Method and System for STT MRAM - The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a method for reading a memory cell includes combining a cell current from a memory cell with a reference current from a reference source to create an average current, enabling the average current to flow through a first mirror transistor in a sense path and a second mirror transistor in a reference path, storing the current mismatch on a capacitor coupled to the gates of the first mirror transistor and the second mirror transistor, disconnecting the memory cell from the reference path and disconnecting the reference source from the sense path, enabling the cell current only to flow through the sense path, and determining the output level of the memory cell. | 2014-03-06 |
20140063924 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD OF THE SAME - According to one embodiment, a nonvolatile semiconductor memory device comprises a semiconductor substrate, and a memory cell which is arranged on the semiconductor substrate and comprises a variable resistance element. The variable resistance element comprises a laminated structure including a phase-change element which has at least two different crystalline resistance states by varying a crystalline state, and a magnetoresistive element which has at least two different magnetization resistance states by varying a magnetization state, and applies or does not apply a magnetic field to the phase-change element in accordance with the magnetization state. | 2014-03-06 |
20140063925 | PARALLEL PROGRAMMING MULTIPLE PHASE CHANGE MEMORY CELLS - Embodiments of the present invention provide a device comprising a plurality of phase change memory cells, a word line, and a plurality of bit lines. Each phase change memory cell is coupled to a corresponding transistor. Each transistor is coupled to the word line. Each bit line is coupled to a phase change memory cell of the device. The device further comprises a programming circuit configured to program at least one phase change memory cell to the SET state by selectively applying a two-stage waveform to the word line and the bit lines of the device. In a first stage, a first predetermined low voltage and a first predetermined high voltage are applied at the word line and the bit lines, respectively. In a second stage, a second predetermined high voltage and a predetermined voltage with decreasing amplitude are applied at the word line and the bit lines, respectively. | 2014-03-06 |
20140063926 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: a sense amplifier unit enabled for a predetermined time during a read operation in response to a first read enable signal, enabled before a write operation in response to a second read enable signal, and disabled when the write operation is started, and a switch unit configured to connect a write driver and a memory unit during the write operation in response to a first select signal, connect the sense amplifier unit and the memory unit for the predetermined time during the read operation in response to a control signal, and disconnect the sense amplifier and the memory unit when the write operation is started. | 2014-03-06 |
20140063927 | Cell-Generated Reference in Phase Change Memory - Phase-change memory arrays, subarrays and chips, and systems and devices in which phase change memory is used, in which two reference columns are added on to hold complementary states for each wordline of data. The outputs from the cells in the two reference columns are combined (e.g. as a plain or weighted average) to provide a reference value for read discrimination of cell states in the other columns. This provides reference values which closely track resistance changes in corresponding ones of said words resulting from, e.g., drift and other time- and phase change material-dependent factors. One of the columns of reference cells can hold a checksum. | 2014-03-06 |
20140063928 | Processors and Systems with Cell-Generated-Reference in Phase-Change Memory - Phase-change memory arrays, subarrays and chips, and systems and devices in which phase change memory is used, in which two reference columns are added on to hold complementary states for each wordline of data. The outputs from the cells in the two reference columns are combined (e.g. as a plain or weighted average) to provide a reference value for read discrimination of cell states in the other columns. This provides reference values which closely track resistance changes in corresponding ones of said words resulting from, e.g., drift and other time- and phase change material-dependent factors. One of the columns of reference cells can hold a checksum. | 2014-03-06 |
20140063929 | Complement Reference in Phase Change Memory - Phase change memory arrays, subarrays, modules, and chips, as well as systems and devices in which phase change memory is used, wherein a reference corresponding to a pair of adjacent logical states (e.g., 0 and 1) can be generated by averaging outputs from a designated data-storing cell and a designated reference cell storing the logical complement to the logical state stored by the data-storing cell. By writing designated cells contemporaneously with words of cells that are configured to be written together, resulting references can closely track resistance changes in said words resulting from, e.g., drift and other time- and phase change material-dependent factors. | 2014-03-06 |
20140063930 | Processors and Systems with Drift-Tolerant Phase-Change Memory Data Storage - Phase change memory arrays, subarrays, modules, and chips, as well as systems and devices in which phase change memory is used, wherein a reference corresponding to a pair of adjacent logical states (e.g., 0 and 1) can be generated by averaging outputs from a designated data-storing cell and a designated reference cell storing the logical complement to the logical state stored by the data-storing cell. By writing designated cells contemporaneously with words of cells that are configured to be written together, resulting references can closely track resistance changes in said words resulting from, e.g., drift and other time- and phase change material-dependent factors. | 2014-03-06 |
20140063931 | MULTIBIT PHASE-CHANGE MEMORY WITH MULTIPLE REFERENCE COLUMNS - Systems and devices in which multi-bit phase change memory is used, including memory systems and memories, as well as methods for operating such systems and devices. According to the present invention, a reference corresponding to a pair of adjacent logical states (e.g., 0 and 1) can be generated by averaging outputs from multiple phase change memory reference cells designated to store said adjacent logical states. By writing reference cells contemporaneously with words of cells that are configured to be written together, resulting references can closely track output changes in corresponding ones of said words resulting from, e.g., drift and other time- and phase change material-dependent factors. Ordering of states within said reference cells can be used to encode information such as checksums of corresponding words. | 2014-03-06 |