11th week of 2015 patent applcation highlights part 17 |
Patent application number | Title | Published |
20150069542 | MAGNETO-RESISTIVE ELEMENT AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a method of manufacturing a magneto-resistive element, includes forming a first ferromagnetic layer on a substrate, forming a tunnel barrier layer on the first ferromagnetic layer, forming a second ferromagnetic layer containing B on the tunnel barrier layer, exposing a laminate of the first ferromagnetic layer, the tunnel barrier layer, and the second ferromagnetic layer under a pressurized atmosphere, and annealing the laminate while being exposed to the pressurized atmosphere, thereby promoting the orientation of the second magnetic layer. | 2015-03-12 |
20150069543 | MAGNETORESISTIVE ELEMENT AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a method of manufacturing a magnetoresistive element includes forming a first ferromagnetic layer on a base substrate, forming a tunnel barrier layer on the first ferromagnetic layer, forming a second ferromagnetic layer containing B on the tunnel barrier layer, and performing annealing in a gas-phase atmosphere including a gas, after formation of the second ferromagnetic layer, the gas producing a reaction product with B, the reaction product having a melting point lower than a treatment temperature. | 2015-03-12 |
20150069544 | MAGNETO-RESISTIVE ELEMENT - According to one embodiment, magneto-resistive element, includes a first ferromagnetic layer formed on an underlying substrate, a tunnel barrier layer formed on the first ferromagnetic layer, a second ferromagnetic formed on the tunnel barrier layer and a cap layer formed on the second ferromagnetic layer, and a surface tension of the cap layer is equal to or less than that of the second ferromagnetic layer. | 2015-03-12 |
20150069545 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a MRAM chip including a semiconductor substrate and a memory cell array area includes magnetoresistive elements which are provided on the semiconductor substrate, and a magnetic shield layer separated from the MRAM chip, surrounding the memory cell array area in a circumferential direction of the MRAM chip, and having a closed magnetic path. | 2015-03-12 |
20150069546 | MAGNETIC MEMORY DEVICE - According to one embodiment, a magnetic memory device includes a semiconductor substrate, a memory cell array area on the semiconductor substrate, the memory cell array area including magnetoresistive elements, each of the magnetoresistive elements having a reference layer with an invariable magnetization, a storage layer with a variable magnetization, and a tunnel barrier layer therebetween, a magnetic field generating area which generates a first magnetic field cancelling a second magnetic field applying from the reference layer to the storage layer, and which is separated from the magnetoresistive elements, and a closed magnetic path area functioning as a closed magnetic path of the first magnetic field, and surrounding the memory cell array area and the magnetic field generating area. | 2015-03-12 |
20150069547 | MAGNETIC MEMORY AND MANUFACTURING METHOD THEREOF - According to one embodiment, a magnetic memory includes a magnetoresistive effect element provided in a memory cell, the magnetoresistive effect element including a multilayer structure including a first magnetic layer, a second magnetic layer, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer, a first electrode provided on an upper portion of the multilayer structure and including a first material, and a first film provided on a side surface of the first electrode and including a second material which is different from the first material of the first electrode. | 2015-03-12 |
20150069548 | MAGNETORESISTIVE ELEMENT - According to one embodiment, a magnetoresistive element includes a storage layer having a variable magnetization direction, a reference layer having an invariable magnetization direction, a tunnel barrier layer formed between the storage layer and the reference layer, and a heater layer formed on an opposite side to the tunnel barrier layer of the storage layer. The storage layer includes a first layer formed on a side of the heater layer, and a second layer formed on the side of the tunnel barrier layer and having a Curie temperature higher than that of the first layer. | 2015-03-12 |
20150069549 | MAGNETIC ELEMENT AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a first magnetic layer, a first nonmagnetic layer on the first magnetic layer, a second magnetic layer on the first nonmagnetic layer, a second nonmagnetic layer on the second magnetic layer, and a third magnetic layer on the second nonmagnetic layer, the third magnetic layer having a sidewall includes a material which is included in the second nonmagnetic layer. | 2015-03-12 |
20150069550 | MAGNETORESISTIVE ELEMENT AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a magnetoresistive element is disclosed. The element includes a lower electrode, a stacked body provided on the lower electrode and including a first magnetic layer, a tunnel barrier layer and a second magnetic layer. The first magnetic layer is under the tunnel barrier layer, the second magnetic layer is on the tunnel barrier layer. The first magnetic layer includes a first region and a second region outside the first region to surround the first region. The second region includes an element in the first region and other element being different from the element. | 2015-03-12 |
20150069551 | MAGNETORESISTIVE ELEMENT AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer. The reference layer includes a first region, and a second region provided outside the first region to surround the same. The second region contains an element contained in the first region and another element being different from the element. The magnetoresistive element further includes a storage layer, and a tunnel barrier layer provided between the reference layer and the storage layer. The storage layer is free from the another element. | 2015-03-12 |
20150069552 | MAGNETIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE MAGNETIC MEMORY DEVICE - According to one embodiment, a magnetic memory device includes a magnetoresistance effect element having a structure in which a first magnetic layer, a nonmagnetic layer, a second magnetic layer, and a third magnetic layer are stacked, wherein the third magnetic layer comprises a first region and a plurality of second regions, and each of the second regions is surrounded by the first region, has conductivity, and has a greater magnetic property than the first region. | 2015-03-12 |
20150069553 | MAGNETIC MEMORY AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a magnetic memory is disclosed. The magnetic memory includes a substrate, and a magnetoresistive element provided on the substrate. The magnetoresistive element includes a first magnetic layer, a tunnel barrier layer on the first magnetic layer, and a second magnetic layer on the tunnel barrier layer. The first magnetic layer or the second magnetic layer includes a first region, second region, and third region whose ratios of crystalline portion are higher in order closer to the tunneling barrier. | 2015-03-12 |
20150069554 | MAGNETIC MEMORY AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a magnetic memory is disclosed. The memory includes a conductive layer containing a first metallic material, a stacked body formed above the conductive layer and including a first magnetic layer containing a second metallic material, a second magnetic layer, and a tunnel barrier layer formed between the first magnetic layer and the second magnetic layer, and an insulating layer formed on a side face of the stacked body and containing an oxide of the first metallic material. A standard electrode potential of the first metallic material is lower than the standard electrode potential of the second metallic material. | 2015-03-12 |
20150069555 | MAGNETIC MEMORY - According to one embodiment, a magnetic memory includes first and second magnetoresistive effect elements neighboring in a first direction in a cell array of a substrate, each of the first and second magnetoresistive effect elements including a first magnetic layer with an invariable direction of magnetization, a second magnetic layer with a variable direction of magnetization, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer. Directions of magnetization of the first magnetic layers of the first and second magnetoresistive effect elements are different from each other. | 2015-03-12 |
20150069556 | MAGNETIC MEMORY AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a magnetic memory is disclosed. The magnetic memory includes a substrate, a first magnetoresistive element provided on the substrate. A second magnetoresistive element which is provided on the substrate and is arranged next to the first magnetoresistive element. Each of the first and second magnetoresistive elements includes a first magnetic layer, a tunnel barrier layer and a second magnetic layer. The tunnel barrier layer is provided on the first magnetic layer, the second magnetic layer is provided on the tunnel barrier layer. A first stress member having a tensile stress as an internal stress is provided on an area including a side face of the stacked body. | 2015-03-12 |
20150069557 | MAGNETORESISTIVE ELEMENT AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element. | 2015-03-12 |
20150069558 | MAGNETIC MEMORY AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a magnetic memory is disclosed. The memory includes a conductive layer containing a first metal material, a stacked body above the conductive layer, and including a first magnetization film containing a second metal material, a second magnetization film, and a tunnel barrier layer between the first magnetization film and the second magnetization film, and an insulating layer on a side face of the stacked body, and containing an oxide of the first metal material. The first magnetization film and/or the second magnetization film includes a first region positioned in a central portion, and a second region positioned in an edge portion and containing As, P, Ge, Ga, Sb, In, N, Ar, He, F, Cl, Br, I, Si, B, C, O, Zr, Tb, S, Se, or Ti. | 2015-03-12 |
20150069559 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a magnetoresistive element formed on a semiconductor substrate, a first contact plug which extends through an interlayer dielectric film formed on the semiconductor substrate and immediately below the magnetoresistive element, has a bottom surface in contact with an upper surface of the semiconductor substrate, and is adjacent to the magnetoresistive element, and an insulating film formed between the magnetoresistive element and the first contact plug and on the interlayer dielectric film, wherein the insulating film includes a first region positioned on a side of the interlayer dielectric film, and a second region positioned in the insulating film and on an upper surface of the first region, the insulating film is made of SiN, and the first region is a nitrogen rich film compared to the second region. | 2015-03-12 |
20150069560 | MAGNETIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Magnetic memory devices and methods of manufacturing the same are disclosed. A method may include forming a magnetic tunnel junction layer on a substrate, forming mask patterns on the magnetic tunnel junction layer, and sequentially performing a plurality of ion implantation processes using the mask patterns as ion implantation masks to form an isolation region in the magnetic tunnel junction layer. The isolation region may thereby define magnetic tunnel junction parts that are disposed under corresponding ones of the mask patterns. A magnetic memory device may include a plurality of magnetic tunnel junction parts electrically and magnetically isolated from each other through the isolation region. | 2015-03-12 |
20150069561 | LOGIC COMPATIBLE MEMORY - A device and a method of forming a device are presented. A substrate is provided. Front end of line processing is performed to form circuit component on the substrate and back end of line processing is performed to include the uppermost inter level dielectric (ILD) layer. The uppermost ILD layer includes first and second interconnects. A pad level is formed over the uppermost ILD layer. A storage unit of a memory cell is provided in the pad level. The storage unit is coupled to the first interconnect of the uppermost ILD layer. A cell interconnect and a pad interconnect are formed in the pad level. The cell interconnect is formed on top of and coupled to the storage unit and the pad interconnect is coupled to the second interconnect in the uppermost ILD layer. | 2015-03-12 |
20150069562 | Magnetic Tunnel Junctions And Methods Of Forming Magnetic Tunnel Junctions - A method of forming a line of magnetic tunnel junctions includes forming magnetic recording material over a substrate, non-magnetic material over the recording material, and magnetic reference material over the non-magnetic material. The substrate has alternating outer regions of reactant source material and insulator material along at least one cross-section. The reference material is patterned into a longitudinally elongated line passing over the alternating outer regions. The recording material is subjected to a set of temperature and pressure conditions to react with the reactant of the reactant source material to form regions of the dielectric material which longitudinally alternate with the recording material along the line and to form magnetic tunnel junctions along the line which individually comprise the recording material, the non-magnetic material, and the reference material that are longitudinally between the dielectric material regions. Other methods, and lines of magnetic tunnel junctions independent of method, are disclosed. | 2015-03-12 |
20150069563 | Low Offset and High Sensitivity Vertical Hall Effect Sensor - A vertical Hall Effect sensor is provided having a high degree of symmetry between its bias modes, can be adapted to exhibit a small pre-spinning systematic offset, and complies with the minimal spacing requirements allowed by the manufacturing technology (e.g., CMOS) between the inner contacts. These characteristics enable the vertical Hall Effect sensor to have optimal performance with regard to offset and sensitivity. | 2015-03-12 |
20150069564 | IMAGING DEVICE, APPARATUS AND METHOD FOR PRODUCING THE SAME AND ELECTRONIC APPARATUS - Solid-state imaging devices, methods to produce the solid-state imaging devices, and electronic apparatuses including the solid-state imaging devices, where the solid-state imaging devices include a semiconductor substrate including a light receiving surface; a plurality of photoelectric conversion parts provided within the semiconductor substrate; and a plurality of reflection portions provided in the semiconductor substrate on a side of the photoelectric conversion parts that is opposite from the light receiving surface; where each of the reflection portions includes a reflection plate and a plurality of metal wirings, and where the plurality of metal wirings are disposed in a same layer of the semiconductor substrate as the reflection plate. | 2015-03-12 |
20150069565 | Germanium Photodetector Having Absorption Enhanced under Slow-Light Mode - A novel germanium (Ge) photodetector is disclosed, containing a stripe layer including Ge, a substrate supporting the stripe layer, and P and N regions, which are located inside the substrate and near opposite sides of the stripe. The stripe layer containing Ge for light absorption is operated in a slow-light mode by adding combinations of a gradual taper indent structure and a periodic indent structure to reduce light scatterings and to control light group velocity inside the stripe. Due to the slower light traveling velocity inside the stripe, the absorption coefficient of the stripe containing Ge is upgraded to be 1 to 2 orders of magnitude larger than that of a traditional bulk Ge at L band, and so the absorption coefficient reaches more than 1 dB/μm at the wavelength of 1600 nm. | 2015-03-12 |
20150069566 | PHOTODIODE - According to one embodiment, a photodiode includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, and a film. The second semiconductor layer is provided in the first semiconductor layer. The third semiconductor layer is provided in the first semiconductor layer so as to surround the second semiconductor layer. Each of one ends of the second and third semiconductor layers is located at an upper surface of the first semiconductor layer. The first to third semiconductor layers include first to third impurity concentrations respectively. The second and third impurity concentrations are higher than the first impurity concentration. The film is provided above the third semiconductor layer, and blocks light to enter into a neighborhood of the third semiconductor layer. | 2015-03-12 |
20150069567 | SUPERJUNCTION STRUCTURES FOR POWER DEVICES AND METHODS OF MANUFACTURE - A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type. | 2015-03-12 |
20150069568 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a semiconductor substrate and a memory array. The semiconductor substrate has a first face. The memory array region is provided on the first face and includes a plurality of semiconductor pillars. The semiconductor pillars extend in a first direction perpendicular to the first face. Each of the semiconductor pillars includes a plurality of memory cells connected in series. Each of the semiconductor pillars is disposed at the nodes of a honeycomb shape when viewed in the first direction. When the semiconductor pillars are projected onto a first plane along the first and second directions perpendicular to the first direction, a component in the second direction of an interval between the semiconductor pillars has first and second intervals repeated alternately. The second interval is an integer multiple of the first interval greater than or equal to 2. | 2015-03-12 |
20150069569 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes: a first semiconductor region extending in a first direction; second semiconductor regions extending in a second direction crossing the first direction from the first semiconductor region and arranged in the first direction; and a first element isolation region provided between the second semiconductor regions. A width of the first semiconductor region in the second direction is wider than a width of the second semiconductor region in the first direction. | 2015-03-12 |
20150069570 | Integrated Circuit Structure with Active and Passive Devices in Different Tiers - An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a first substrate including a semiconductor material, an active device at a surface of the first substrate, and a first interconnect structure over the first substrate, wherein the first tier is free from passive devices therein. The second tier includes a second substrate bonded to and in contact with the first interconnect structure, and a second interconnect structure over the second substrate, wherein metal lines in the second interconnect structure are electrically coupled to the first interconnect structure. The second tier further includes a plurality of through-vias penetrating through the second substrate, wherein the plurality of through-vias lands on metal pads in a top metal layer of the first interconnect structure, and a passive device in the second interconnect structure. | 2015-03-12 |
20150069571 | HEAT DISSIPATION THROUGH DEVICE ISOLATION - According to a structure herein, a silicon substrate has an active device in the silicon substrate. A dielectric film is on the active device. An isolation trench is in the dielectric film surrounding the active device. The trench extends through the dielectric film and at least partially into the silicon substrate. A core is in the isolation trench. The core comprises material having thermal conductivity greater than silicon dioxide and electrical conductivity approximately equal to silicon dioxide. | 2015-03-12 |
20150069572 | Multilayer High Voltage Isolation Barrier in an Integrated Circuit - A semiconductor package is provided that has a transformer formed within a multilayer dielectric laminate substrate. The transformer has a first inductor coil formed in one or more dielectric laminate layers of the substrate, a second inductor coil formed in one or more dielectric laminate layers of the substrate, and an isolation barrier comprising two or more dielectric laminate layers of the multilayer substrate positioned between the first inductor coil and the second inductor coil. The transformer may be mounted on a lead frame along with one or more integrated circuits and molded into a packaged isolation device. | 2015-03-12 |
20150069573 | CAPACITOR STRUCTURE AND STACK-TYPE CAPACITOR STRUCTURE - A capacitor structure is provided, which includes a conductive substrate, a first dielectric layer, and a first metal layer. The conductive substrate includes a first surface and at least one first concave located on the first surface. The first dielectric layer covers the first surface and the first concave. The first metal layer covers the first dielectric layer, wherein the first dielectric layer and the first metal layer respectively have concave structures corresponding to the first concave. A stack-type capacitor structure is also provided. | 2015-03-12 |
20150069574 | INTEGRATED CIRCUIT AND MANUFACTURING AND METHOD THEREOF - A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above. | 2015-03-12 |
20150069575 | NITRIDE SEMICONDUCTOR GROWTH APPARATUS, AND EPITAXIAL WAFER FOR NITRIDE SEMICONDUCTOR POWER DEVICE - A nitride semiconductor growth apparatus of the present invention comprises a chamber into which a reactive gas containing nitrogen is to be introduced as a material gas and a reaction part which is placed in the chamber and in which the material gas is brought into reaction to grow a nitride semiconductor. In the nitride semiconductor growth apparatus, in a region which includes a reaction part and part of an upstream side from a reaction part with respect to a flow of a material gas, portions to be in contact with the material gas (a gas introducing part, a current introducing part and a view port part and the like) are made from non-copper material (i.e., material containing no copper). | 2015-03-12 |
20150069576 | Semiconductor Device and Method for Manufacturing a Semiconductor Device - A method includes providing a semiconductor wafer including multiple semiconductor chips, forming a first scribe line on a frontside of the semiconductor wafer, wherein the first scribe line has a first width and separates semiconductor chips of the semiconductor wafer, forming a second scribe line on the frontside of the semiconductor wafer, wherein the second scribe line has a second width and separates semiconductor chips of the semiconductor wafer, wherein the first scribe line and the second scribe line intersect in a crossing area which is greater than a product of the first width and the second width, and plasma etching the semiconductor wafer in the crossing area. | 2015-03-12 |
20150069577 | REMOVAL OF ELECTROSTATIC CHARGES FROM INTERPOSER FOR DIE ATTACHMENT - A wafer includes a first interposer having a first patterned metal layer and a second interposer having a second patterned metal layer. The wafer includes a metal connection in a scribe region of the wafer that electrically couples the first patterned metal layer of the first interposer with the second patterned metal layer of the second interposer forming a global wafer network. The wafer further includes a probe pad located in the scribe region that is electrically coupled to the global wafer network. | 2015-03-12 |
20150069578 | COMBINATION GRINDING AFTER LASER (GAL) AND LASER ON-OFF FUNCTION TO INCREASE DIE STRENGTH - Consistent with an example embodiment, there is a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side. The method comprises pre-grinding the backside of a wafer substrate to a thickness. The front-side of the wafer is mounted onto a protective foil. A laser is applied to the backside of the wafer, at first focus depth to define a secondary modification zone in saw lanes. To the backside of the wafer, a second laser process is applied, at a second focus depth shallower than that of the first focus depth, in the saw lanes to define a main modification zone, the secondary modification defined at a pre-determined location within active device boundaries, the active device boundaries defining an active device area. The backside of the wafer is ground down to a depth so as to remove the main modification zone. The IC device die are separated from one another by stretching the protective foil. | 2015-03-12 |
20150069579 | METHOD FOR FORMING AN AIR GAP AROUND A THROUGH-SILICON VIA - Semiconductor devices with air gaps around the through-silicon via are formed. Embodiments include forming a first cavity in a substrate, filling the first cavity with a sacrificial material, forming a second cavity in the substrate, through the sacrificial material, by removing a portion of the sacrificial material and a portion of the substrate below the sacrificial material, filling the second cavity with a conductive material, removing a remaining portion of the sacrificial material to form an air gap between the conductive material and the substrate, and forming a cap over the air gap. | 2015-03-12 |
20150069580 | Alignment Mark and Method of Formation - In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess. | 2015-03-12 |
20150069581 | NOBLE GAS BOMBARDMENT TO REDUCE SCALLOPS IN BOSCH ETCHING - A method of etching a trench in a substrate is provided. The method repeatedly alternates between using a fluorine-based plasma to etch a trench, which has trench sidewalls, into a selected region of the substrate; and using a fluorocarbon plasma to deposit a liner on the trench sidewalls. The liner, when formed and subsequently etched, has an exposed sidewall surface that includes scalloped recesses. The trench, which includes the scalloped recesses, is then bombarded with a molecular beam where the molecules are directed on an axis parallel to the trench sidewalls to reduce the scalloped recesses. | 2015-03-12 |
20150069582 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a plurality of pillars vertically extending from the semiconductor substrate, each pillar including a groove formed in an upper surface thereof, a salicide layer formed to cover the upper surface and a lateral circumference of an upper end of each pillar and a lower electrode formed to cover an upper surface and a lateral surface of the salicide layer. | 2015-03-12 |
20150069583 | III NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - Provided are a III nitride semiconductor device which can be operated at a lower voltage can be provided, in which device a good ohmic contact is achieved between the (000-1) plane side of the III nitride semiconductor layer and the electrode and a method of producing the III nitride semiconductor device. A III nitride semiconductor device of the present invention includes a plurality of protrusions rounded like domes in a predetermined region on the (000-1) plane side of the III nitride semiconductor layer; and an electrode on the upper surface of the predetermined region. | 2015-03-12 |
20150069584 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. A first extension line from a first bottom edge intersects with a second extension line from a second bottom edge to form a first base point. A first projection line is formed on the first surface, an extension line of the first projection line intersects with the second bottom edge to form a first intersection point, a second projection line is formed on the first surface, and an extension line of the second projection line intersects with the first bottom edge to form a second intersection point. A zone by connecting the first base point, the first intersection point and the second intersection point is the first anti-stress zone. | 2015-03-12 |
20150069585 | SEMICONDUCTOR DEVICE WITH AN ANGLED PASSIVATION LAYER - A semiconductor device includes a first passivation layer including a first passivation portion and a second passivation portion substantially diametrically opposite the first passivation portion. The semiconductor device includes a first corner of the first passivation portion separated a first distance from a second corner of the second passivation portion. A third corner of the first passivation portion is separated a second distance from a fourth corner of the second passivation portion. The first distance is not equal to the second distance | 2015-03-12 |
20150069586 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes: forming a first electrode on a first semiconductor substrate; coating the semiconductor substrate with an insulating material having a first viscosity at a first temperature, having a second viscosity lower than the first viscosity at a second temperature higher than the first temperature, and having a third viscosity higher than the second viscosity at a third temperature higher than the second temperature; and forming a first insulating film by curing the insulating material. In this method, the forming the first insulating film includes: bringing the insulating material to the second viscosity by heating the insulating material under a first condition; and bringing the insulating material to the third viscosity by heating the insulating material under a second condition. The first condition and the second condition are different in their temperature rising rate. | 2015-03-12 |
20150069587 | INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME - Presented is an integrated circuit packaged at the wafer level wafer (also referred to as a wafer level chip scale package, WLCSP), and a method of manufacturing the same. The WLCSP comprises a die having an electrically conductive redistribution layer, RDL, formed above the upper surface of the die, the RDL defining a signal routing circuit. The method comprises the steps of: depositing the electrically conductive RDL so as to form an electrically conductive ring surrounding the signal routing circuit; and coating the side and lower surfaces of the die with an electrically conductive shielding material. | 2015-03-12 |
20150069588 | RADIATION HARDENED MICROELECTRONIC CHIP PACKAGING TECHNOLOGY - A novel radiation hardened chip package technology protects microelectronic chips and systems in aviation/space or terrestrial devices against high energy radiation. The proposed technology of a radiation hardened chip package using rare earth elements and mulitlayered structure provides protection against radiation bombardment from alpha and beta particles to neutrons and high energy electromagnetic radiation. | 2015-03-12 |
20150069589 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element in a frame body. The semiconductor element includes a first electrode electrically connected to an electrode block provided on a first side of the semiconductor element. A connection element, which in some embodiments may be a portion of the electrode block, connects the electrode block to the frame body. The semiconductor element is sealed within an enclosure formed at least in part by the frame body, the connection element, and the electrode block. The connection element includes a fragile portion which has a resistance to increases in pressure or temperature that is less than other portions of the connection element. That is, in general, the fragile portion will fail before other portions of the connection element when pressure or temperature increases, which may occur when, for example, the semiconductor element breaks down. | 2015-03-12 |
20150069590 | Multi-Die Power Semiconductor Device Packaged On a Lead Frame Unit with Multiple Carrier Pins and a Metal Clip - A power semiconductor device comprises a lead frame unit, a control die, a first MOSFET die and a second MOSFET die, wherein the lead frame unit comprises at least a die paddle for mounting the first and second MOSFET dies, a first pin and a second pin for connecting to top electrodes of the first and second MOSFET dies, a first row of carrier pins and a second row of carrier pins disposed in-line with the first and second pins respectively for the control die to mount thereon. | 2015-03-12 |
20150069591 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage. | 2015-03-12 |
20150069592 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SAME, AND APPLICATION BOARD MOUNTED WITH SAME - In one embodiment, a semiconductor device includes a lead frame including an island portion and a terminal portion separated from the island portion. The device further includes a semiconductor chip mounted on the island portion and including an electrode. The device further includes an insulating layer disposed on the semiconductor chip and having an opening to expose at least a part of the electrode. The device further includes a connector covering the electrode exposed through the opening and electrically connecting the electrode and the terminal portion. | 2015-03-12 |
20150069593 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - In one embodiment, a semiconductor device includes a lead frame including a chip mounting portion and a lead portion separated from the chip mounting portion and having the same thickness as the chip mounting portion, a level of an upper face of the chip mounting portion being same as a level of an upper face of the lead portion. The device further includes a semiconductor chip mounted on the upper face of the chip mounting portion and electrically connected to the lead portion. The device further includes a molding resin which collectively seals up the lead frame and the semiconductor chip. The device further includes a metal film covering parts of rear faces of the chip mounting portion and the lead portion. | 2015-03-12 |
20150069594 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is inhibited from being degraded in reliability. The semiconductor device has a tab including a top surface, a bottom surface, and a plurality of side surfaces. Each of the side surfaces of the tab has a first portion continued to the bottom surface of the tab, a second portion located outwardly of the first portion and continued to the top surface of the tab, and a third portion located outwardly of the second portion and continued to the top surface of the tab to face the same direction as each of the first and second portions. In planar view, the outer edge of the semiconductor chip is located between the third portion and the second portion of the tab, and the outer edge of an adhesive material fixing the semiconductor chip to the tab is located between the semiconductor chip and the second portion. | 2015-03-12 |
20150069595 | Apparatus and Method for a Component Package - A component package and a method of forming are provided. A first component package may include a first semiconductor device having a pair of interposers attached thereto on opposing sides of the first semiconductor device. Each interposer may include conductive traces formed therein to provide electrical coupling to conductive features formed on the surfaces of the respective interposers. A plurality of through vias may provide for electrically connecting the interposers to one another. A first interposer may provide for electrical connections to a printed circuit board or subsequent semiconductor device. A second interposer may provide for electrical connections to a second semiconductor device and a second component package. The first and second component packages may be combined to form a Package-on-Package (“PoP”) structure. | 2015-03-12 |
20150069596 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a metal plate, a plurality of semiconductor chips, an insulation layer, a wiring layer, external connection terminals and a sealing resin portion. The metal plate includes a first surface and the plurality of semiconductor chips are laminated on a second surface of the metal plate. The insulation layer and the wiring layer are provided on the semiconductor chips. The external connection terminals are provided on the insulation layer and the wiring layer. The sealing resin portion seals the plurality of semiconductor chips while exposing the first surface of the metal plate. At least one pair of opposing outer peripheral surfaces of the metal plate are covered with the sealing resin portion. | 2015-03-12 |
20150069597 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor element, a mounting member including Cu, and a bonding layer provided between the semiconductor element and the mounting member. The bonding layer includes a first region including Ti and Cu, and a second region provided between the first region and the mounting member, and including Sn and Cu. A first position along the first direction is positioned between the semiconductor element and a second position along the first direction. The first position is where the composition ratio of Ti in the first region is 0.1 times a maximum value of the composition ratio of Ti. The second position is where the composition ratio of Sn in the second region is 0.1 times a maximum value of the composition ratio of Sn. A distance between the first position and the second position is not less than 0.1 micrometers. | 2015-03-12 |
20150069598 | HEAT DISSIPATION CONNECTOR AND METHOD OF MANUFACTURING SAME, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME, AND SEMICONDUCTOR MANUFACTURING APPARATUS - In one embodiment, a heat dissipation connector mounted on a semiconductor chip and sealed up with a molding resin along with the semiconductor chip and a lead frame includes a heat dissipation portion configured to have a block shape, and have an upper face exposed out of the molding resin. The connector further includes a connecting portion configured to extend from a first side face of the heat dissipation portion, and electrically connect an electrode arranged on the semiconductor chip to the lead frame. The heat dissipation portion and the connecting portion are integrally made of the same metal sheet. | 2015-03-12 |
20150069599 | Power electronic switching device and assembly - A switching device having a substrate, a power semiconductor component, a connecting device, load connection devices and a pressure device. Substrate has electrically insulated conductor tracks. A power semiconductor component is arranged on a conductor track. Connecting device is formed as a film composite having an electrically conductive film and an electrically insulating film, and has first and second main surfaces. Switching device is connected in an internally circuit-conforming manner by connecting device. The pressure device has a pressure body with a first recess, a pressure element being arranged so that it projects out of the recess, wherein the pressure element presses onto a section of the second main surface of film composite and, in this case, the section is arranged within the surface of the power semiconductor component in projection along the normal direction of the power semiconductor component. | 2015-03-12 |
20150069600 | Embedded Silver Nanomaterials into Die Backside to Enhance Package Performance and Reliability - A method and apparatus for enhancing the electrical and thermal performance of semiconductor packages effectively, especially for laminated packages, where sinterable materials cannot be used. The concept of this invention is to embed silver or silver-coated nanomaterials, which can be nanoparticles, nanoflakes, nanowires etc., into die backside to improve the interface between die and die attach materials, thus enhancing electrical and thermal performance through sintering and enhancing reliability by improving adhesion. | 2015-03-12 |
20150069601 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device and a semiconductor device that is manufactured by the method. In the method of manufacturing a semiconductor device, a releasing sheet is disposed in close contact with a hole of an aluminum plate having the recessed hole, and a skeleton structure of a semiconductor device is put into the recessed hole. Then, liquid epoxy resin is poured into the recessed hole. After hardening, the epoxy resin body | 2015-03-12 |
20150069602 | CHIP-ON-FILM DEVICE - A chip-on-film device including a flexible circuit film having a wire, a passivation layer having a hole, an adhesive layer, a first pad, a second pad, an interconnection, and a bump is provided. A part of the adhesive layer is disposed in the hole. The first pad and the second pad are disposed under the passivation layer. | 2015-03-12 |
20150069603 | COPPER PILLAR BUMP AND FLIP CHIP PACKAGE USING SAME - Electrically conductive pillars with a solder cap are formed on a substrate with an electroplating process. A flip-chip die having solder wettable pads is attached to the substrate with the conductive pillars contacting the solder wettable pads. | 2015-03-12 |
20150069604 | SEMICONDUCTOR DEVICE HAVING A BOUNDARY STRUCTURE, A PACKAGE ON PACKAGE STRUCTURE, AND A METHOD OF MAKING - A semiconductor device includes a substrate and a first conductive pad on a top surface of the substrate. The semiconductor device further includes a boundary structure on the top surface of the substrate around the conductive pad. | 2015-03-12 |
20150069605 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF AND SEMICONDUCTOR STRUCTURE - A semiconductor device is disclosed, which includes: a substrate having a plurality of connecting pads; a semiconductor component having a plurality of bonding pads formed on a surface thereof and corresponding to the connecting pads and a UBM layer formed on the bonding pads; a plurality of conductive elements each having a first conductive portion and a second conductive portion sequentially formed on the UBM layer, wherein the second conductive portion is less in width than the first conductive portion; and a plurality of solder balls formed between the second conductive portions and the connecting pads for connecting the semiconductor component and the substrate, thereby preventing solder bridging from occurring between the adjacent conductive elements and reducing stresses between the conductive elements and the UBM layer. | 2015-03-12 |
20150069606 | Methods and Apparatus for Package on Package Devices - Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors contained in the bottom package and not connected to any corresponding connector in the top package. | 2015-03-12 |
20150069607 | THROUGH VIA PACKAGE - An integrated circuit package includes an integrated circuit die in a reconstituted substrate. The active side is processed then covered in molding compound while the inactive side is processed. The molding compound on the active side is then partially removed and solder balls are placed on the active side. | 2015-03-12 |
20150069608 | THROUGH-SILICON VIA STRUCTURE AND METHOD FOR IMPROVING BEOL DIELECTRIC PERFORMANCE - An improved through-silicon via (TSV) and method of fabrication are disclosed. A back-end-of-line (BEOL) stack is formed on a semiconductor substrate. A TSV cavity is formed in the BEOL stack and semiconductor substrate. A conformal protective layer is disposed on the interior surface of the TSV cavity, along the BEOL stack and partway into the semiconductor substrate. The conformal protective layer serves to protect the dielectric layers within the BEOL stack during subsequent processing, improving the integrated circuit quality and product yield. | 2015-03-12 |
20150069609 | 3D CHIP CRACKSTOP - Embodiments of the present invention provide a crackstop and seal ring for 3D chip stacked wafers. A continuous through-silicon trench (TST) spans multiple wafers of a 3D chip stacked wafer, and forms a closed shape around a functional circuit or die, protecting the chip during subsequent fabrication such as dicing and packaging. | 2015-03-12 |
20150069610 | ELECTRODE CONTACT STRUCTURE FOR SEMICONDUCTOR DEVICE - In one embodiment, a method for forming a semiconductor device having a shield electrode includes forming first and second shield electrode contact portions within a contact trench. The first shield electrode contact portion can be formed recessed within the contact trench and includes a flat portion. The second shield electrode contact portion can be formed within the contact trench and makes contact to the first shield electrode contact portion along the flat portion. | 2015-03-12 |
20150069611 | METAL NANOPARTICLES GROWN ON AN INNER SURFACE OF OPEN VOLUME DEFECTS WITHIN A SUBSTRATE - The present invention provides a method for forming metal nanoparticle(s) onto an inner surface of one or more open volume defects within a substrate by providing the substrate containing the one or more open volume defects, depositing an immiscible metal on a surface of the substrate, and forming the metal nanoparticle(s) by diffusing the immiscible metal from the surface onto the inner surface of each open volume defect using a heat treatment. The method can be used to produce a substrate having at least one open volume defect with a metal nanoparticle formed onto an inner surface of the open volume defect, a solar cell, an optical switch, a radiation detector, or other similar device. | 2015-03-12 |
20150069612 | RELIABLE SURFACE MOUNT INTEGRATED POWER MODULE - A surface mount packaging structure that yields improved thermo-mechanical reliability and more robust second-level package interconnections is disclosed. The surface mount packaging structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level metal interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer on a side opposite the semiconductor devices, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to the first surface of a multi-layer substrate structure, with a dielectric material positioned between the dielectric layer and the multi-layer substrate structure to fill in gaps in the surface-mount structure and provide additional structural integrity thereto. | 2015-03-12 |
20150069613 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one exemplary embodiment, a semiconductor device includes a chip main body; a first layer that is provided on the chip main body and contains nickel and phosphorus; and a second layer that is provided on the first layer and contains nickel and phosphorus and has a higher phosphorus concentration than that of the first layer. | 2015-03-12 |
20150069614 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first metal layer disposed on a first surface of a semiconductor layer, or a portion thereof. The first metal layer is made of a first metal. At least a portion of the first metal layer is crystallized. A second metal layer is disposed on a second surface of the semiconductor layer. The second surface is opposite the first surface. The second metal layer is also made of the first metal and has at least a portion that is crystallized. In some embodiments, the first metal may be nickel. In some embodiments, the semiconductor device may be a power semiconductor device, such as an insulated gate bipolar transistor and a fast recovery diode. | 2015-03-12 |
20150069615 | SEMICONDUCTOR DEVICE - In one embodiment, a semiconductor device includes first and second semiconductor layers of a first conductivity type above a substrate via a first film, a first electrode above the second semiconductor layer, and a second electrode disposed on a side of the first electrode or an opposite side of the first electrode with respect to the second semiconductor layer. The device further includes a first pad layer connected to the first electrode, a second pad layer connected to the second electrode and including a first upper portion contacting the second electrode, a second upper portion disposed at a level between upper and lower portions of the substrate, and a third upper portion opposed to the lower portion of the substrate, and a third semiconductor layer of a second conductivity type between the second upper portion of the second pad layer and a lower portion of the first film. | 2015-03-12 |
20150069616 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate on which a plurality of contact regions are defined, a plurality of transistors formed in the plurality of contact regions, a support body formed over the plurality of transistors and including a top surface, portions of which have different heights in the plurality of contact regions, a plurality of stacked structures including a plurality of conductive layers stacked over the support body, slits located between the plurality of stacked structures, first lines coupled to first junctions of the plurality of transistors through the slits, and second lines coupled to second junctions of the plurality of transistors through the slits. | 2015-03-12 |
20150069617 | EXTREMELY STRETCHABLE ELECTRONICS - In embodiments, the present invention may attach at least two isolated electronic components to an elastomeric substrate, and arrange an electrical interconnection between the components in a boustrophedonic pattern interconnecting the two isolated electronic components with the electrical interconnection. The elastomeric substrate may then be stretched such that the components separate relative to one another, where the electrical interconnection maintains substantially identical electrical performance characteristics during stretching, and where the stretching may extend the separation distance between the electrical components to many times that of the un-stretched distance. | 2015-03-12 |
20150069618 | Method for forming through wafer vias - A method for forming through substrate vias (TSVs) in a non-conducting, glass substrate is disclosed. The method involves patterning a silicon template substrate with a plurality of lands and spaces, bonding a slab or wafer of glass to the template substrate, and melting the glass so that it flows into the spaces formed in the template substrate. The template substrate may then be removed to leave a plurality of TSVs in the glass slab or wafer. | 2015-03-12 |
20150069619 | 3DIC Interconnect Apparatus and Method - An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug. | 2015-03-12 |
20150069620 | Semiconductor Devices and Methods of Forming Same - Embodiments of the present disclosure include a semiconductor device and methods of forming the same. An embodiment is a method for of forming a semiconductor device, the method including forming a first conductive feature over a substrate, forming a dielectric layer over the conductive feature, and forming an opening through the dielectric layer to the first conductive feature. The method further includes selectively forming a first capping layer over the first conductive feature in the opening, and forming a second conductive feature on the first capping layer. | 2015-03-12 |
20150069621 | EMBEDDED ELECTRONIC PACKAGING AND ASSOCIATED METHODS - An electronic package includes a semiconductor die, conductive pillars extending outwardly from the semiconductor die, and a liquid crystal polymer (LCP) body surrounding the semiconductor die and having openings therein receiving respective ones of the conductive pillars. A first interconnect layer is on the LCP body and contacts the openings. Conductive bodies are in the openings to connect the conductive pillars to the first interconnect layer. | 2015-03-12 |
20150069622 | Via Definition Scheme - A method includes defining a metal pattern layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is grown over the metal pattern layer and the first dielectric layer. A metal trench is formed with a metal width in the first dielectric layer. A via hole is formed with a via width in the second dielectric layer. | 2015-03-12 |
20150069623 | Integrated Fan-Out Structure with Guiding Trenches in Buffer Layer - A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding compound. A device die is molded in the molding compound. A guiding trench extends from a top surface of the buffer layer into the buffer layer, wherein the guiding trench is misaligned with the device die. | 2015-03-12 |
20150069624 | RECESSED SEMICONDUCTOR DIE STACK - Recessed semiconductor die stacks. In some embodiments, a semiconductor device includes a first die including an active side and a back side, the back side including a non-recessed portion thicker than a recessed portion, the recessed portion including one or more through-die vias on a recessed surface; and a second die located in the recessed portion, the second die including an active side facing the recessed surface of the first die and coupled thereto through the one or more through-die vias. In another embodiment, a method includes creating a recess on a first die having a first thickness, the recess having a depth smaller than the first thickness; coupling a second die having a second thickness greater than the depth to the recess; and reducing the thickness of the second die by an amount equal to or greater than a difference between the second thickness and the depth. | 2015-03-12 |
20150069625 | ULTRA-THIN METAL WIRES FORMED THROUGH SELECTIVE DEPOSITION - The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a pair of ultra-thin metal wires in an opening using a selective deposition process. | 2015-03-12 |
20150069626 | CHIP PACKAGE, CHIP PACKAGE MODULE BASED ON THE CHIP PACKAGE, AND METHOD OF MANUFACTURING THE CHIP PACKAGE - A chip package is formed of a complex substrate and a chip. The complex substrate includes a core plate, a thermally-conductive insulated layer, and a through hole running through the core plate and the thermally-conductive insulated layer. The core plate is fixed to the core plate and buried into the thermally-conductive insulated layer. An upper electrode of the chip is connected with a first circuit layer. The first circuit layer is disposed on a top side of the thermally-conductive insulated layer, into the through hole, and on a lower surface of the core plate. A lower electrode of the chip is connected with a second circuit layer. The second circuit layer is disposed on the lower surface of the core plate. In light of the structure, the chip package has a simplified manufacturing process and reduces the production cost and the package size. | 2015-03-12 |
20150069627 | INTERPOSER WAFER AND METHOD OF MANUFACTURING SAME - In one embodiment, a method of manufacturing an interposer wafer includes forming a first hole having a first depth on a first main surface of a semiconductor wafer. The method further includes forming a second hole having a second depth on the first main surface of the semiconductor wafer before forming the first hole or after forming the first hole, the second depth being shallower than the first depth. The method further includes forming an electrode in the first hole. The method further includes forming an alignment mark in the second hole. | 2015-03-12 |
20150069628 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurance of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided. | 2015-03-12 |
20150069629 | HYBRID PACKAGE TRANSMISSION LINE CIRCUITS - “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels. | 2015-03-12 |
20150069630 | MEMORY CELL FORMED BY IMPROVED CMP PROCESS - Memory cell array architectures and methods of forming the same are provided. An example method for forming an array of memory cells can include forming a plurality of vertical structures each having a switch element in series with a memory element in series with a top electrode, and forming an interconnection conductive material between the respective top electrodes of the plurality of vertical structures. The interconnection conductive material is etched-back and chemical-mechanical polished (CMPed). A conductive line is formed over the interconnection conductive material after CMPing the interconnection conductive material. | 2015-03-12 |
20150069631 | ALLEVIATION OF THE CORROSION PITTING OF CHIP PADS - Methods for processing a metal pad of a chip and chip structures including a chip with a metal pad. A surface modification agent is applied to the metal pad on the chip. The surface modification agent is effective to increase the hydrophobicity of the metal pad and may involve silylation. | 2015-03-12 |
20150069632 | SEMICONDUCTOR PACKAGE - According to one embodiment, a semiconductor package includes a substrate with first and second pad, first semiconductor chip above the substrate, first wire, first mold member, second semiconductor chip above the first mold member, third semiconductor chip above the second semiconductor chip, second wire, and a second mold member. The first wire electrically connects the first pad and the first semiconductor chip. The first mold member seals the first wire and the first semiconductor chip. The second wire electrically connects the second pad and the second semiconductor chip. The second mold member seals the second wire, the second and the third semiconductor chips, and the first mold member. | 2015-03-12 |
20150069633 | SEMICONDUCTOR DEVICE AND MEMORY DEVICE - A semiconductor device includes a substrate, a controller chip, and memory chips. Wiring is formed on the substrate. The controller chip has a rectangular surface area, and is mounted on the substrate. The memory chips have quadrangular surface areas, and are superposed on the substrate on a first major side of the controller chip. The first major side defines a first direction and a first controller terminal block is formed along a first minor side thereof orthogonal to the first direction, and a second controller terminal block is formed along a second major side opposite to the first major side. | 2015-03-12 |
20150069634 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor chip having a first main surface and a second main surface which opposes the first main surface and on which a first electrode is mounted, a second semiconductor chip having a third main surface on which a second electrode connected to the first electrode is provided and a fourth main surface which opposes the third main surface, and a first spacer which is arranged in a region formed between the first and second electrodes and an outer peripheral surface of the first and second semiconductor chips, and ensures a gap between the first semiconductor chip and the second semiconductor chip. | 2015-03-12 |
20150069635 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Provided are semiconductor packages and methods of fabricating the same. The method may include mounting a first semiconductor chip including chip and heat-transfer regions and a lower heat-transfer pattern disposed on the heat-transfer region, on a substrate, mounting a second semiconductor chip on the chip region of the first semiconductor chip, forming a mold layer on the substrate to enclose the first and second semiconductor chips, forming an opening in the mold layer to expose at least a portion of the lower heat-transfer pattern, forming a heat-pathway pattern in the opening, and forming a heat-dissipating part on the second semiconductor chip and the mold layer to be connected to the heat-pathway pattern. | 2015-03-12 |
20150069636 | MULTIPLE ACCESS OVER PROXIMITY COMMUNICATION - A multiple access Proximity Communication system in which electrical elements on an integrated circuit chip provide the multiplexing of multiple signals to a single electrical receiving element on another chip. Multiple pads formed on one chip and receiving separate signals may be capacitively coupled to one large pad on the other chip. Multiple inductive coils on one chip may be magnetically coupled to one large coil on another chip or inductive coils on three or more chips may be used for either transmitting or receiving. The multiplexing may be based on time, frequency, or code. | 2015-03-12 |
20150069637 | INTERPOSER PACKAGE-ON-PACKAGE STRUCTURE - An integrated circuit (IC) package includes an IC die having a first surface and a second surface opposite of the first surface. The IC package includes first contact members coupled to the second surface of the IC die. The IC package includes a bottom substrate having a first surface and a second surface opposite of the first surface, where the first surface of the bottom substrate is coupled to the second surface of the IC die via the first contact members. The IC package includes an interposer substrate coupled to the first surface of the IC die via an adhesive material, where the adhesive material is disposed on at least a surface of the interposer substrate. The IC package includes second contact members coupled along a periphery of the interposer substrate, where the interposer substrate is coupled to the first surface of the bottom substrate via the second contact members. | 2015-03-12 |
20150069638 | METALLIC PARTICLE PASTE, CURED PRODUCT USING SAME, AND SEMICONDUCTOR DEVICE - According to one embodiment, a metallic particle paste includes a polar solvent and particles dispersed in the polar solvent and containing a first metal. A second metal different from the first metal is dissolved in the polar solvent. | 2015-03-12 |
20150069639 | Substrate-Less Stackable Package With Wire-Bond Interconnect - A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are uncovered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer. | 2015-03-12 |
20150069640 | FLEXIBLE CHIP SET ENCAPSULATION STRUCTURE - A flexible chip set encapsulation structure includes a chip set. The chip set comprises a plurality of spaced chips and a fixing film. The fixing film is adapted to wrap and fix the chips. The fixing film has at least one bending portion at a predetermined position for the fixing film to have flexibility in a predetermined direction. Thus, the flexible chip set encapsulation structure is flexible for bending. When the user wears the flexible chip set, the movement of the user won't be confined. Besides, the chip set is completely attached to the body to provide a comfortable wear, and the chips provide a better far infrared radiation effect. | 2015-03-12 |
20150069641 | CARBURETOR FOR AIR SCAVENGED ENGINE - A fuel and air supply device for an engine includes at least one carburetor body having a main bore and an air passage and an air valve operably associated with the air passage to control air flow through the air passage. In at least some implementations, the air passage has a portion with a reduced dimension compared to a different portion of the passage. This may facilitate, among other things, a varying external size of the device and facilitate its use within constrained spaces. | 2015-03-12 |