11th week of 2016 patent applcation highlights part 58 |
Patent application number | Title | Published |
20160079287 | METHOD FOR PRODUCING A VIA, A METHOD FOR PRODUCING AN ARRAY SUBSTRATE, AN ARRAY SUBSTRATE, AND A DISPLAY DEVICE - The invention relates to the field of display technologies, and discloses a method for producing a via, a method for producing an array substrate, an array substrate and a display device to prevent a chamfer from being formed in producing the via, to promote the product quality and improve the display effect of the display device. The method for producing a via comprises: employing a first etching process to partially etch a top film layer in an area that needs to form a via above an electrode, wherein the vertical etching amount achieved by employing the first etching process is less than the thickness of the top film layer; and employing a second etching process for which the vertical etching rate is larger than the lateral etching rate to etch the remaining part in the area that needs to form a via, until the electrode is exposed. | 2016-03-17 |
20160079288 | METHODS OF FORMING AN IMAGE SENSOR - Methods of forming an image sensor are provided. A method of forming an image sensor includes forming a trench in a substrate to define a unit pixel region of the substrate. The method includes forming an in-situ-doped passivation layer on an exposed surface of the trench. The method includes forming a capping pattern on the in-situ-doped passivation layer, in the trench. The method includes forming a photoelectric conversion region in the unit pixel region. Moreover, the method includes forming a floating diffusion region in the unit pixel region. | 2016-03-17 |
20160079289 | METHOD FOR MOUNTING CHIP ON PRINTED CIRCUIT BOARD - A method for mounting a chip on a printed circuit board (PCB) is disclosed. The method includes the steps of: providing a chip having a plurality of bonding pads and a PCB having a recess portion and a plurality of connectors; gluing the recess portion; placing the chip into the recess portion; and forming circuit patterns linking associated bonding pad and connector. A bottom of the recess portion is substantially flat and a shape of the recess portion is similar to that of the chip but large enough so that the chip can be fixed in the recess portion after being glued. | 2016-03-17 |
20160079290 | SOLID-STATE IMAGE PICKUP ELEMENT AND IMAGE PICKUP APPARATUS - Disclosed herein is a solid-state image pickup element, including: a photoelectric conversion region; a transistor; an isolation region of a first conductivity type configured to isolate the photoelectric conversion region and the transistor from each other; a well region of the first conductivity type having the photoelectric conversion region, the transistor, and the isolation region of the first conductivity type formed therein; a contact portion configured to supply an electric potential used to fix the well region to a given electric potential; and an impurity region of the first conductivity type formed so as to extend in a depth direction from a surface of the isolation region of the first conductivity type in the isolation region of the first conductivity type between the contact portion and the photoelectric conversion region, and having a sufficiently higher impurity concentration than that of the isolation region of the first conductivity type. | 2016-03-17 |
20160079291 | CMOS IMAGE SENSOR - A CMOS image sensor including: an array of M×N pixels, the pixels of a same column being connected to a same output track, each pixel including a photodiode, a sense node, a transfer transistor, a reset transistor, and a read circuit; and a test circuit including an assembly of N elementary reference cells respectively connected to the N output tracks of the sensor, each cell including a resistor, a sense node, a transfer transistor, a reset transistor, and a read circuit, the N resistors being series-connected between first and second nodes of application of a reference voltage. | 2016-03-17 |
20160079292 | IMAGE SENSOR INCLUDING MICRO-LENSES HAVING HIGH REFRACTIVE INDEX AND IMAGE PROCESSING SYSTEM INCLUDING THE SAME - Provided are an image sensor with micro-lenses having a high refractive index and an image processing system including the same. The image sensor includes: a semiconductor substrate in which a photoelectric conversion device is formed; at least one color filter formed on the semiconductor substrate; at least one color filter fence formed on the semiconductor substrate and between two neighboring color filters among the at least one color filter; and at least one micro-lens formed on the color filter, respectively. The micro-lens has a first refractive index equal to or greater than a first threshold. The filter fence has a second refractive index less than or equal to a second threshold. The second threshold is less than the first threshold. | 2016-03-17 |
20160079293 | INFRARED SENSOR - An infrared sensor according to an embodiment includes a housing, a detector, a lid, and a light shielding film. The detector is mounted on the bottom surface of the housing and includes a heat-sensitive pixel region and a reference pixel region. The lid seals the housing and includes a support member and a window member. The support member is bonded to the side surfaces of the housing and has an opening positioned above the heat-sensitive pixel region. The window member is bonded to a surface of the support member on a side of the detector so as to cover the opening. The light shielding film is formed on a surface of the window member on a side of the detector and arranged on an optical path of the infrared rays entering the reference pixel region. | 2016-03-17 |
20160079294 | IMAGE PICKUP DEVICE AND METHOD OF MANUFACTURING THE SAME - To prevent deterioration in the sensitivity of a pixel part caused by variation in the distance between a waveguide and a photo diode and by decay of light due to suppression of reflection of entering light. In a pixel region, there is formed a waveguide which penetrates through a fourth interlayer insulating film or the like and reaches a sidewall insulating film. The sidewall insulating film is configured to have a stacked structure of a silicon oxide film and a silicon nitride film. The waveguide is formed so as to penetrate through even the silicon nitride film of the sidewall insulating film and to reach the silicon oxide film of the sidewall insulating film, or so as to reach the silicon nitride film of the sidewall. | 2016-03-17 |
20160079295 | IMAGE PICKUP ELEMENT, IMAGE PICKUP APPARATUS, AND IMAGE PICKUP SYSTEM - An image pickup element includes a first pixel, a second pixel, and a third pixel that share one microlens, a first boundary that is provided between the first pixel and the second pixel, and a second boundary that is provided between the first pixel and the third pixel, and when a charge amount of the first pixel is saturated, a first charge amount from the first pixel to the second pixel via the first boundary is larger than a second charge amount from the first pixel to the third pixel via the second boundary. | 2016-03-17 |
20160079296 | SOLID-STATE IMAGE SENSOR AND ELECTRONIC DEVICE - There is provided a solid-state image sensor including a semiconductor substrate in which a plurality of pixels are arranged, and a wiring layer stacked on the semiconductor substrate and formed in such a manner that a plurality of conductor layers having a plurality of wirings are buried in an insulation film. In the wiring layer, wirings connected to the pixels are formed of two conductor layers. | 2016-03-17 |
20160079297 | IMAGING DEVICE - An imaging device including a unit pixel cell comprising: a semiconductor substrate including a first conductivity type region of a first conductivity type, a first and second impurity regions of a second conductivity type provided in the first conductivity type region; a photoelectric converter located above the semiconductor substrate; and a first transistor including a gate electrode and at least a part of the second impurity region as a source or a drain. The first impurity region is at least partially located in a surface of the semiconductor substrate and electrically connected to the photoelectric converter. The second impurity region is electrically connected to the photoelectric converter via the first impurity region and has an impurity concentration lower than that of the first impurity region. The second impurity region at least partially overlaps the gate electrode in a plan view. | 2016-03-17 |
20160079298 | IMAGE CAPTURING APPARATUS AND CONTROL METHOD THEREFOR - An image capturing apparatus having pixels is provided. Each pixel includes a photoelectric conversion unit including a charge accumulation region, an output unit configured to output a signal based on a potential of a node electrically connected to the charge accumulation region, and a connection unit configured to electrically connect a capacitance to the node. The charge accumulation region includes a first portion and a second portion. Charge is configured to be first accumulated in the first portion, and, after the first portion is saturated, be accumulated in the second portion. The output unit is configured to output a first signal based on the potential of the node before the capacitance is connected thereto, and, then a second signal based on the potential of the node after the capacitance is connected thereto. | 2016-03-17 |
20160079299 | SEMICONDUCTOR IMAGE PICKUP DEVICE - According to one embodiment, a semiconductor image pickup device includes a pixel area and a non-pixel area. The device includes a first photoelectric conversion element formed in the pixel area, a first transistor formed in the pixel area and connected to the first photoelectric conversion element, a second photoelectric conversion element formed in the non-pixel area, a second transistor formed in the non-pixel area and connected to the second photoelectric conversion element, a metal wire formed at least in the non-pixel area, a first cap layer formed on the metal wire to prevent diffusion of metal contained in the metal wire, and a dummy via wire formed in the non-pixel area and penetrating the first cap layer. | 2016-03-17 |
20160079300 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - A solid-state imaging device includes: a pixel region in which a plurality of pixels composed of a photoelectric conversion section and a pixel transistor is arranged; an on-chip color filter; an on-chip microlens; and a multilayer interconnection layer in which a plurality of layers of interconnections is formed through an interlayer insulating film. The solid-state imaging device further includes a light-shielding film formed through an insulating layer in a pixel boundary of a light receiving surface in which the photoelectric conversion section is arranged. | 2016-03-17 |
20160079301 | X-RAY DETECTOR - An X-ray detector has a layered structure that includes a substrate, a TFT array disposed on the substrate, a photodiode layer disposed on the TFT array, and a scintillator layer disposed on the photodiode layer. The scintillator layer comprises a particle-in-binder composite that contains a continuous parylene matrix having dispersed therein a plurality of particles that include a scintillator material that emits light in response to the absorption of X-rays. | 2016-03-17 |
20160079302 | METHOD OF MANUFACTURING IMAGING APPARATUS - Provided is a method of manufacturing an imaging apparatus. The imaging apparatus is formed on a substrate and includes a pixel region and a peripheral circuit region that is arranged on a periphery of the pixel region. The method includes: forming an insulating layer in the pixel region and the peripheral circuit region; etching the insulating layer formed in the pixel region in a state in which the peripheral circuit region is protected; planarizing a surface of the insulating layer; and forming a waveguide in the pixel region. After the forming an insulating layer and before the etching the insulating layer, an average value of heights of a top surface of the insulating layer in the pixel region is larger than an average value of heights of a top surface of the insulating layer in the peripheral circuit region. | 2016-03-17 |
20160079303 | MANUFACTURING METHOD OF ELECTRONIC DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of an electronic device processes a surface of a first wafer, bonds a surface of a second wafer to the processed surface of the first wafer, thins the first wafer by polishing a back surface of the first wafer, the back surface being located on an opposite side of the processed surface, forms a groove along a periphery of the back surface of the thinned first wafer by using a dicing blade, attaches a protective layer to the back surface of the first wafer having the groove, via a bonding layer, and polishes a back surface of the second wafer, the back surface being located on an opposite side of the surface attached to the protective layer. | 2016-03-17 |
20160079304 | METHOD FOR FABRICATING AN IMAGE SENSOR PACKAGE - An image sensor package and method for fabricating the same is provided. The image sensor package includes a first substrate comprising a via hole therein, a driving circuit and a first conductive pad thereon. A second substrate comprising a photosensitive device and a second conductive pad thereon is bonded to the first substrate, so that the driving circuit, formed on the first substrate, can electrically connect to and further control the photosensitive device, formed on the second substrate. A solder ball is formed on a backside of the first substrate and electrically connects to the via hole for transmitting a signal from the driving circuit. Because the photosensitive device and the driving circuit are fabricated individually on the different substrates, fabrication and design thereof is more flexible. Moreover, the image sensor package is relatively less thick, thus, the dimensions thereof are reduced. | 2016-03-17 |
20160079305 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To provide a semiconductor device having improved performance and reduce a production cost. | 2016-03-17 |
20160079306 | Surface Micro-Machined Infrared Sensor Using Highly Temperature Stable Interferometric Absorber - A method for manufacturing a surface machined infrared sensor package is disclosed. A semiconductor wafer is provided having a front side surface and a back side surface. A transistor is defined on the substrate front side. A thin film reflector is implanted in the substrate front side, and a sensor is formed on the semiconductor substrate front side adjacent to the reflector. A thin-film absorber is deposited upon the sensor, wherein the thin-film absorber is substantially parallel to the reflector. | 2016-03-17 |
20160079307 | SUB-LITHOGRAPHIC PATTERNING OF MAGNETIC TUNNELING JUNCTION DEVICES - A method for fabricating a magnetic tunnel junction (MTJ) device includes creating a recess within a second patterning layer, in which a first patterning layer overhangs the recessed second patterning layer. Such a method further includes depositing a film into the recess to create a keyhole pattern within the deposited film. The method further includes transferring the keyhole pattern through a hard mask layer to an MTJ stack. The method also includes depositing a conductive material into the transferred keyhole pattern and on an MTJ stack. The method also includes removing the hard mask layer to create a conductive hard mask pillar. | 2016-03-17 |
20160079308 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor memory device includes a magnetic tunnel junction (MTJ) element includes a first magnetic layer, a second magnetic layer and a non-magnetic layer between the first and second magnetic layers, a contact layer formed underneath the MTJ element, the contact layer being formed of a first material, and a first layer formed around the contact layer, wherein the first layer in contact with a side surface of the contact layer, has a first width extending parallel to a stacking direction of the MTJ element, and a second width extending perpendicularly to the direction of extension of the first width, the second width being less than the first width. | 2016-03-17 |
20160079309 | RESISTANCE CHANGE MEMORY, METHOD OF MANUFACTURING RESISTANCE CHANGE MEMORY, AND FET - According to one embodiment, a resistance change memory includes a first conductive line, a second conductive line provided above the first conductive line, and extending in a first direction, a third conductive line extending in a second direction intersecting the first direction, a select transistor provided between the first and third conductive lines, and a resistance change layer provided between the second and third conductive lines. | 2016-03-17 |
20160079310 | SELECTOR-RESISTIVE RANDOM ACCESS MEMORY CELL - Memory devices and manufacturing methods thereof are presented. A memory device a substrate and a memory cell having at least one selector and a storage element. | 2016-03-17 |
20160079311 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display apparatus includes: an organic light-emitting device including a plurality of sub-pixels respectively emitting lights of different colors; a color filter formed on the organic light-emitting device in a region corresponding to each of the sub-pixels; a spacer color filter formed in the color filter between red, green, and blue color filters at locations corresponding to non-emitting areas; and a substrate provided on the color filter to encapsulate the organic light-emitting device. | 2016-03-17 |
20160079312 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light emitting display device includes a substrate and a plurality of pixels defined in the substrate. A pixel includes red subpixel, green subpixel, blue subpixel, and white subpixel. The organic light emitting display device includes an anode electrode formed on the substrate, a cathode electrode opposing the anode electrode, and a red common emission layer, a green common emission layer, and a blue common emission layer formed across each of the red, green, blue and white subpixel areas. The blue common emission layer is disposed above and adjacent to the anode electrode, the green common emission layer is disposed above the blue common emission layer, and the red common emission layer is disposed above the green common emission layer and adjacent to the cathode electrode. | 2016-03-17 |
20160079313 | OLED LIGHTING DEVICE WITH SHORT TOLERANT STRUCTURE - A first device that may include a short tolerant structure, and methods for fabricating embodiments of the first device, are provided. A first device may include a substrate and a plurality of OLED circuit elements disposed on the substrate. Each OLED circuit element may include a fuse that is adapted to open an electrical connection in response to an electrical short in the pixel. Each OLED circuit element may comprise a pixel that may include a first electrode, a second electrode, and an organic electroluminescent (EL) material disposed between the first and the second electrodes. Each of the OLED circuit elements may not be electrically connected in series with any other of the OLED circuit elements. | 2016-03-17 |
20160079314 | Light-Emitting Device, Electronic Device, and Lighting Device - A light-emitting device, an electronic device, or a lighting device with low power consumption and high reliability is provided. The light-emitting device includes a first light-emitting element, a second light-emitting element, a third light-emitting element, and a fourth light-emitting element. The first to fourth light-emitting elements include the same EL layer between an anode and a cathode. The EL layer includes a first light-emitting layer and a second light-emitting layer. The first light-emitting layer contains a fluorescent substance. The peak wavelength of an emission spectrum of the fluorescent substance in a toluene solution of the fluorescent substance is 440 nm to 460 nm, preferably 440 nm to 455 nm. The second light-emitting layer contains a phosphorescent substance. The first light-emitting element exhibits blue emission. The second light-emitting element exhibits green emission. The third light-emitting element exhibits red emission. The fourth light-emitting element exhibits yellow emission. | 2016-03-17 |
20160079315 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display apparatus, including a substrate; a first reflective layer, a second reflective layer, and a third reflective layer that are separately disposed on the substrate; a first insulating layer on the first reflective layer, but not on the second reflective layer and the third reflective layer; a second insulating layer on the first insulating layer and the second reflective layer, but not on the third reflective layer; and a first pixel electrode for red emission on the second insulating layer and corresponding to the first reflective layer, a second pixel electrode for green emission on the second insulating layer and corresponding to the second reflective layer, and a third pixel electrode for blue emission on the third reflective layer. | 2016-03-17 |
20160079316 | LIGHT EMITTING DEVICE INCLUDING TANDEM STRUCTURE - A light emitting device comprising: a pair of electrodes; two or more light emitting elements disposed between the electrodes in a stacked arrangement, wherein a light emitting element comprises a layer comprising an emissive material; and a charge generation element disposed between adjacent light emitting elements in the stacked arrangement, the charge generation element comprising a first layer comprising an inorganic n-type semiconductor material, and a second layer comprising a hole injection material. A charge generation element is also disclosed. | 2016-03-17 |
20160079317 | PIXEL CIRCUIT AND DISPLAY APPARATUS INCLUDING THE SAME - A display apparatus including: a display unit including a plurality of pixels, each of the plurality of pixels including: a light-emitting circuit including a light-emitting device; and a heating circuit adjacent to the light-emitting circuit, the heating circuit including: a heating device; and a controller configured to generate and output an emission signal for controlling an operation of the light-emitting circuit; and generating and output a heating signal for controlling an operation of the heating circuit, wherein: a first end of the light-emitting circuit is connected to a first power supply voltage; a second end of the light-emitting circuit is connected to a second power supply voltage; a first end of the heating circuit is connected to a first heating power supply voltage; and a second end of the heating circuit is connected to a second heating power supply voltage. | 2016-03-17 |
20160079318 | DISPLAY DEVICE - A display device includes an accommodating member in which an inner space is defined, a display panel accommodated in the inner space in the accommodating member, and an energy generating module disposed between the accommodating member and the display panel and which produces a triboelectricity, where the energy generating module includes a first electrified substrate fixed to the accommodating member and a second electrified substrate disposed on the first electrified substrate, the second electrified substrate moves relative to the first electrified substrate by a frictional event, and the triboelectricity is produced by the relative movement between the first and second electrified substrates. | 2016-03-17 |
20160079319 | DUAL-MODE PIXELS INCLUDING EMISSIVE AND REFLECTIVE DEVICES, AND DUAL-MODE DISPLAY USING THE PIXELS - A dual-mode display including a substrate and a plurality of sub-pixels on the substrate, in which each sub-pixel includes, a reflective device having an optical filter function which reflects different color according to electrical signals applied from outside the display, and an emissive device disposed on the reflective device, wherein the emissive device includes a cathode and an anode, and the cathode and the anode include a carbon-based material including graphene sheets, graphene flakes, and graphene platelets, and a binary or ternary transparent conductive oxide including indium oxide, tin oxide, and zinc oxide. | 2016-03-17 |
20160079320 | FLEXIBLE DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - Provided is a method of manufacturing a flexible display apparatus, the method including forming a sacrificial layer on a support substrate; forming a first material layer having a higher hydrogen concentration than the sacrificial layer on the sacrificial layer; forming a second material layer, preventing hydrogen diffusion from the first material layer to a flexible substrate, on the first material layer; forming the flexible substrate on the second material layer; forming a display layer on the flexible substrate; and irradiating a laser onto the support substrate to delaminate the sacrificial layer from the first material layer. | 2016-03-17 |
20160079321 | DISPLAY DEVICE - A display device includes an element substrate including a display area where a plurality of self-light-emitting elements are formed, and a driver IC disposed outside the display area in the element substrate. A first metal layer is disposed on the reverse side of the element substrate at a position opposite to the display area . A second metal layer is disposed with a space between the first metal layer and the second metal layer on the reverse side of the element substrate at a position opposite to the driver IC. | 2016-03-17 |
20160079322 | ORGANIC LIGHT EMITTING DISPLAY DEVICE, ORGANIC LIGHT EMITTING DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME - An organic light emitting display panel and an organic light emitting display device according to the present invention may include a substrate, a pixel electrode positioned in each of a plurality of pixel areas on the substrate, a bank positioned in a non-emission area on the substrate, having a portion overlapping an edge of each pixel electrode and exposing a portion of each pixel electrode, and an organic layer positioned on each exposed pixel electrode. A plurality of grooves or holes may be positioned in the bank, and a material the same as that of the organic layer may be positioned in the groove or hole. | 2016-03-17 |
20160079323 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An OLED device is disclosed. The device includes a substrate defined to have a first active area and a dummy area. First electrodes are formed on the substrate, and a first bank pattern is formed to overlap with edges of each first electrode and to expose a part of an upper surface of each first electrode. A second bank pattern is formed on the first bank pattern within the first active area, and a third bank pattern is formed on the first bank pattern within the dummy area in the same layer as the second bank pattern. The second bank pattern is formed to have a larger width than that of the third bank pattern. As such, an organic emission layer can be evenly formed in the active area. | 2016-03-17 |
20160079324 | DISPLAY APPARATUS - A display apparatus includes a first substrate including an active area, a circuit area extending outwardly from the active area, and a cell seal area extending outwardly from the circuit area, a second substrate covering the first substrate, a sealing portion between the first substrate and the second substrate, the sealing portion covering at least a portion of the circuit area, a circuit line in the circuit area of the first substrate and electrically connected to a device in the active area of the first substrate, at least a portion of the sealing portion being on the circuit line, and a pixel definition layer between the sealing portion and the circuit line. | 2016-03-17 |
20160079325 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light emitting display device comprises a partition wall formed on a bank that covers a portion of an auxiliary electrode. The organic light emitting display device includes a first electrode, an auxiliary electrode, a first bank, and a partition wall. The first electrode may be connected to a driving transistor, and the auxiliary electrode may be disposed on the same layer as the first electrode. The first bank may cover a portion of the first electrode and a portion of the auxiliary electrode. A portion of a bottom surface of the partition wall may contact a top surface of the first bank, and the other portion except the portion of the bottom surface may be disposed on the auxiliary electrode. | 2016-03-17 |
20160079326 | PIXEL STRUCTURE OF ELECTROLUMINESCENT DISPLAY PANEL AND METHOD OF FABRICATING THE SAME - A pixel structure of electroluminescent display panel includes a substrate, a display driving structure, a planarization structure and an electroluminescent device. The display driving structure is disposed on the substrate. The display driving structure includes a driving device. The planarization structure is disposed on the substrate. The planarization structure covers the top surface and the sidewall of the driving device, and the planarization structure has a contact hole partially exposing the driving device. The electroluminescent device is disposed on the planarization structure. The electroluminescent device includes an anode, a light-emitting layer and a cathode. The anode covers the top surface of the planarization structure and surrounds the sidewall of the planarization structure, and the anode is filled into the contact hole and electrically connected to the driving device. The light-emitting layer is disposed on the anode. The cathode is disposed on the light-emitting layer. | 2016-03-17 |
20160079327 | ORGANIC EL DISPLAY UNIT - There is provided an organic EL display unit having superior light emission efficiency and superior display performance. This display unit includes two or more kinds of organic light-emitting devices, each of the organic light-emitting devices having a laminated configuration in which a first electrode layer, an organic layer, and a second electrode layer are laminated in order on a base, and the organic light-emitting devices configured to emit light of different colors. The organic layer includes a common light-emitting layer and an individual light-emitting layer, the common light-emitting layer shared by all of the kinds of organic light-emitting devices, and the individual light-emitting layer provided in only a kind configured to emit specific color light of the kinds of organic light-emitting devices. Some of the kinds of organic light-emitting devices each include a transparent conductive layer between the first electrode layer and the organic layer. | 2016-03-17 |
20160079328 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY APPARATUS - Provided is a thin film transistor substrate including a substrate; a source electrode and a drain electrode that are disposed on the substrate; an active layer that is formed on the source electrode and the drain electrode; a gate electrode that is formed on and is insulated from the active layer; and a pixel electrode that extends from one of the source electrode and the drain electrode. | 2016-03-17 |
20160079329 | ROLLABLE DISPLAY DEVICE - A rollable display device including a roll frame and a flexible display unit windable in the roll frame, the flexible display unit includes a flexible substrate, a display layer disposed on the flexible substrate, an encapsulation layer respectively disposed on and configured to seal the display layer, a polarization layer, a touch screen layer, and a protection layer sequentially disposed on the encapsulation layer, and adhesive layers disposed between the encapsulation layer and the polarization layer, the polarization layer and the touch screen layer, and the touch screen layer and the protection layer, in which each of the adhesive layers comprise first regions and second regions alternately disposed between a first end and a second end of the flexible display unit, and a modulus of the first regions is different from a modulus of the second regions. | 2016-03-17 |
20160079330 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - An organic light emitting display device includes: a substrate; a semiconductor on the substrate and including a switching channel of a switching transistor and a driving channel of a driving transistor, wherein the switching transistor and the driving transistor are spaced; a first insulating layer covering the semiconductor; a switching gate electrode on the first insulating layer and overlapped with the switching channel and a driving gate electrode on the first insulating layer and overlapped with the driving channel; a second insulating layer covering the switching gate electrode and the driving gate electrode; a data line on the second insulating layer and configured to transmit a data signal, a driving voltage line on the second insulating layer and configured to transmit a driving voltage; a passivation layer; a pixel electrode on the passivation layer; and a pixel connecting member on the passivation layer. | 2016-03-17 |
20160079331 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - An organic light emitting display device according to the present disclosure includes: a semiconductor on a substrate including a switching channel of a switching transistor and a driving channel of a driving transistor, the driving transistor being spaced from the switching transistor; a first insulating layer covering the semiconductor; a switching gate electrode on the first insulating layer and overlapping the switching channel and a driving gate electrode on the first gate insulating layer and overlapping the driving channel; a second insulating layer covering the switching gate electrode and the driving gate electrode; a data line on the second insulating layer comprising: an upper data line; and a lower data line; a driving voltage line on the second insulating layer; a passivation layer covering the data line and the driving voltage line; a pixel electrode on the passivation layer; and a first pixel connecting member on the passivation layer. | 2016-03-17 |
20160079332 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes a first substrate, a plurality of common lines, an optical member, and a second substrate. The first substrate includes a pixel region and a transparent region. The light emitting structure is disposed on the first substrate of the pixel region. The common lines are disposed adjacent to a boundary of the pixel region and the transparent region. The optical member prevents a light diffraction generated adjacent to the common lines. The second substrate is disposed on the light emitting structure and the optical member. | 2016-03-17 |
20160079333 | Display Device - Provided is a display device with high resolution, high display quality, or high aperture ratio. A pixel includes three subpixels and is electrically connected to two gate lines. One of the gate lines is electrically connected to a gate of a transistor included in each of the two subpixels, and the other gate line is electrically connected to a gate of a transistor included in the other subpixel. Display elements of the three subpixels are arranged in the same direction. Three pixel electrodes of the three subpixels are arranged in the same direction. | 2016-03-17 |
20160079334 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - Discussed is an organic light emitting display device in which an auxiliary electrode is disposed on an overcoating layer, and thus, an aperture ratio is enhanced. The organic light emitting display device can include a first overcoating layer disposed on a driving transistor and a supply electrode, a connection electrode disposed on the first overcoating layer and connected to the supply electrode through the second contact hole, a first electrode disposed on the first overcoating layer and connected to the driving transistor through the first contact hole, a second overcoating layer disposed on the first overcoating layer, and an auxiliary electrode disposed on the second overcoating layer and connected to the connection electrode. The first overcoating layer may include a first contact hole and a second contact hole. The second overcoating layer may cover the first and second contact holes and may not cover a portion of the first electrode. | 2016-03-17 |
20160079335 | DISPLAY MODULE - An organic display device includes a pixel driving circuit having a thin film transistor connected to a current supply line and a capacitor. A first insulation layer, with a first electrode thereon, covers a source electrode of the transistor. The first electrode is connected to the transistor through a contact hole in the insulation layer. A second insulation layer including an aperture is formed on the first insulation layer and electrode layers. An organic light emitting layer, with a second electrode thereon is formed in the aperture and connected to the first electrode. The second insulation layer includes an inner wall at the aperture, said inner wall having a surface of a convex plane on an edge of the recessed part of the first electrode. The convex plane is located between the organic light emitting layer and the edge of the first electrode, and the second electrode is formed over plurality of pixels. | 2016-03-17 |
20160079336 | FLEXIBLE DISPLAY SUBSTRATE, FLEXIBLE ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A flexible display substrate, a flexible organic light emitting display device, and a method of manufacturing the same are provided. The flexible display substrate comprises a flexible substrate including a display area and a non-display area extending from the display area, a first wire formed on the display area of the flexible substrate, and a second wire formed on the non-display area of the flexible substrate, wherein at least a part of the non-display area of the flexible substrate is curved in a bending direction, and the second wire formed on at least a part of the non-display area of the flexible substrate includes a first portion formed to extend in a first direction and a second portion formed to extend in a second direction. | 2016-03-17 |
20160079337 | NARROW BORDER ORGANIC LIGHT-EMITTING DIODE DISPLAY - An electronic device may be provided having an organic light-emitting diode display and control circuitry for operating the display. The display may include one or more display layers interposed between the control circuitry and a display layer having thin-film transistors. The electronic device may include a coupling structure interposed between the layer of thin-film transistors and the control circuitry that electrically couples the layer of thin-film transistors to the control circuitry. The coupling structure may include a dielectric member having a conductive via, a flexible printed circuit having a bent portion, or a conductive via formed in an encapsulation layer of the display. The display may include a layer of opaque masking material. The layer of opaque masking material may be formed on an encapsulation layer, an organic emissive layer, a thin-film transistor layer, or a glass layer of the organic light-emitting diode display. | 2016-03-17 |
20160079338 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode display includes: a substrate including a first and a second gate electrode formed over a first and a second region, respectively, a first and a second gate insulator formed on the first and the second gate electrode, respectively, a first and a second semiconductor layer formed on the first and the second gate insulator, respectively, the first semiconductor layer including a first channel region, the second semiconductor layer including a second channel region, an interlayer insulator formed over the substrate and over at least part of the first and second semiconductor layers, a first and a second etching stop layer formed over the first and second channel regions, respectively, and surrounded by the interlayer insulator, and a first and a second source electrode and a first and a second drain electrode contacting the first and the second semiconductor layer, respectively, through the interlayer insulator. | 2016-03-17 |
20160079339 | INDUCTOR HEAT DISSIPATION IN AN INTEGRATED CIRCUIT - The present invention relates generally to semiconductor structures and methods of manufacturing and, more particularly, to improving heat dissipation of devices, such as active devices like inductors, by filling portions of the semiconductor structure with thermally conductive and electrical isolating material that may serve as a heat sink to a base substrate. In an embodiment, an inductor may be formed above a cavity region in which the thermally conductive and electrical isolating material has been formed. Heat may then be dissipated from the inductor to the cavity, and eventually to the base substrate, through trenches filled with the thermally conductive and electrical isolating material. | 2016-03-17 |
20160079340 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to one embodiment includes a semiconductor substrate, an insulating member provided in a first region on the semiconductor substrate, an insulating film provided in a second region not provided with the insulating member on the semiconductor substrate, a conductive member provided on the insulating member and on the insulating film, and a first and a second vias connected to the conductive member. An upper surface of the insulating film is lower than an upper surface of the insulating member. An upper part of the conductive member is provided in both the first region and the second region, and a lower part is provided in the second region and not provided in the first region. The conductive member has at least one portion located on the first region between the first via and the second via. | 2016-03-17 |
20160079341 | INDUCTOR STRUCTURE WITH MAGNETIC MATERIAL AND METHOD FOR FORMING THE SAME - The methods for forming an inductor structure are provided. The method includes forming an oxide layer over a substrate, and the layer includes an opening. The method includes forming a magnetic material over the oxide layer and in the opening and forming a patterned photoresist layer over the magnetic material, wherein the patterned photoresist layer overlaps the opening. The method further includes performing an etching process on the magnetic material using the patterned photoresist as a mask. | 2016-03-17 |
20160079342 | METHOD AND DEVICE FOR AN INTEGRATED TRENCH CAPACITOR - A methodology for forming trench capacitors on an interposer wafer by an integrated process that provides high-capacitance, ultra-low profile capacitor structures and the resulting device are disclosed. Embodiments include forming a polymer block on a front side of an interposer wafer, patterning and etching the polymer block to form one or more trenches, and forming a capacitor on an upper surface of the polymer block and in the one or more trenches. | 2016-03-17 |
20160079343 | Multiple Depth Vias In an Integrated Circuit - An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with different depths without causing etch damage to the material being contacted by the vias. | 2016-03-17 |
20160079344 | Electronic Device Including An Isolation Structure - An electronic device can include a semiconductor layer having a primary surface, and an isolation structure. The isolation structure can include a first well region within the semiconductor layer and having a first conductivity, a second well region within the semiconductor layer and having a second conductivity type opposite the first conductivity type, and a third well region within the semiconductor layer having the first conductivity type. The second well region can be disposed between the first and third well regions. The first, second, and third well regions can be electrically connected to one another. The electronic device can help to allow more electrons during an electrostatic discharge or similar event to flow where the electrons will be less problematic. A process of forming the electronic device may be implemented with changes to existing masks without adding any processing operations. | 2016-03-17 |
20160079345 | Bipolar Transistor - A semiconductor device comprising a bipolar transistor and a method of making the same. A power amplifier including a bipolar transistor. The bipolar transistor includes a collector including a laterally extending drift region. The bipolar transistor also includes a base located above the collector. The bipolar transistor further includes an emitter located above the base. The bipolar transistor also includes a doped region having a conductivity type that is different to that of the collector. The doped region extends laterally beneath the collector to form a junction at a region of contact between the doped region and the collector. The doped region has a non-uniform lateral doping profile. A doping level of the doped region is highest in a part of the doped region closest to a collector-base junction of the bipolar transistor. | 2016-03-17 |
20160079346 | SEMICONDUCTOR STRUCTURE - A semiconductor structure comprising an improved ESD protection device is provided. The semiconductor structure comprises a substrate, a well formed in the substrate, a first heavily doped region formed in the well, a second heavily doped region formed in the well and separated apart from the first heavily doped region, a gate structure formed on the substrate between the first heavily doped region and the second heavily doped region, a field region formed in the well under the first heavily doped region and the gate structure, and a field oxide/shallow trench isolation structure formed adjacent to the first heavily doped region. The field region is not formed under the second heavily doped region. The well and the field region have a first type of doping. The first heavily doped region and the second heavily doped region have a second type of doping. | 2016-03-17 |
20160079347 | SEMICONDUCTOR DEVICE - It is an objective to improve reverse surge withstand capability of a semiconductor device, for example, a Schottky barrier diode. | 2016-03-17 |
20160079348 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a semiconductor layer, a first electrode, and a first insulating film. The semiconductor layer is provided on the semiconductor substrate. The semiconductor layer includes first-fifth regions. The first region includes a first portion and a second portion arranged with the first portion. The second region is provided in a surface of the first portion. The third region is provided between the second portion and the second region in the surface of the first portion. The fourth region is provided between the second portion and the third region in the surface of the first portion. The fifth region is provided in a surface of the fourth region. The first electrode is provided between the fifth region and the second portion on the semiconductor layer. The first insulating film is provided between the semiconductor layer and the first electrode. | 2016-03-17 |
20160079349 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes a silicon carbide layer, an element region including a semiconductor element portion formed in the silicon carbide layer, a JTE region (first electric field relaxing region), an insulating film disposed on a first main surface and covering the JTE region, and a pad electrode electrically connected to the JTE region. The pad electrode includes an extension portion extending from an end of the JTE region close to the element region in a peripheral direction from the element region toward the JTE region, the extension portion being disposed on the insulating film. The extension portion overlies at least a portion of the JTE region. | 2016-03-17 |
20160079350 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first semiconductor region of a first conductivity type, an element region, a terminal region, and a second electrode. The element region includes a second semiconductor region of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a gate electrode, and a first electrode. The terminal region includes a fifth semiconductor region of the second conductivity type, and a sixth semiconductor region of the second conductivity type. The terminal region surrounds the element region. The fifth semiconductor region is provided within the first semiconductor region. A plurality of the fifth semiconductor regions are provided along a second direction. The sixth semiconductor region is provided between the first semiconductor region and the fifth semiconductor region. A dopant of the sixth semiconductor region is higher than a dopant concentration of the fifth semiconductor region. | 2016-03-17 |
20160079351 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided in the first semiconductor region, an element region, and a termination region. The element region includes a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, and a gate electrode disposed on a gate insulating layer that extends adjacent the third semiconductor region and the fourth semiconductor region. The termination region surrounds the element region and includes a first electrode, which includes first portions extending in a first direction and second portions extending in a second direction. A plurality of first electrodes are provided on the first semiconductor region and the second semiconductor region. An interval between adjacent first portions in the second direction is less than an interval between adjacent second portions in the first direction. | 2016-03-17 |
20160079352 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To realize a semiconductor device having a power MOSFET satisfying both a low conduction resistance and a high junction breakdown voltage by a simple and easy manufacturing method. Over an n-type substrate, a p-type epitaxial layer of a low concentration is formed, and, in an active part, a plurality of active regions is defined by a plurality of trenches that is formed in the epitaxial layer and extends in a first direction with first intervals in a second direction orthogonal to the first direction. In the epitaxial layer between the adjacent trenches, an n-type diffusion region that functions as a drain offset layer is formed, and, in the epitaxial layer between a side wall of the trench and the n-type diffusion region, a p-type diffusion region connected with a channel region (the p-type diffusion region) is formed, to constitute a super junction structure. Further, by forming an n-type diffusion region in the epitaxial layer, having a prescribed width from a side wall of a trench lying in the end part of the active part toward an outer periphery part, to achieve the improvement of a drain breakdown voltage. | 2016-03-17 |
20160079353 | SEMICONDUCTOR STRUCTURE AND MANUFACUTING METHOD OF THE SAME - Present disclosure provides a semiconductor structure, including a substrate having a center portion and an edge portion, an isolation layer over the substrate; a semiconductor fin with a top surface and a sidewall surface, partially positioning in the isolation layer, a first gate covering a portion of the top surface and a portion of the sidewall surface of the semiconductor fin, positioning at an edge portion of the substrate, and a second gate covering a portion of the top surface and a portion of the sidewall surface of the semiconductor fin, positioning at a center portion of the substrate. A lower width of the first gate in proximity to the isolation layer is smaller than an upper width of the first gate in proximity to top surface of the semiconductor fin. | 2016-03-17 |
20160079354 | INTEGRATED CIRCUIT DEVICES AND METHODS OF MANUFACTURING THE SAME - An IC device includes a substrate including a device region having a fin-type active region and a deep trench region; a gate line that extends in a direction intersecting the fin-type active region; and an inter-device isolation layer that fills the deep trench region. The gate line includes a first gate portion that extends on the device region to cover the fin-type active region and has a flat upper surface at a first level and a second gate portion that extends on the deep trench region to cover the inter-device isolation layer while being integrally connected to the first gate portion and has an upper surface at a second level that is closer to the substrate than the first level. | 2016-03-17 |
20160079355 | SEMICONDUCTOR DEVICE AND FORMATION THEREOF - A semiconductor device and methods of formation are provided herein. A semiconductor device includes a conductor concentrically surrounding an insulator, and the insulator concentrically surrounding a column. The conductor, the insulator and the conductor are alternately configured to be a transistor, a resistor, or a capacitor. The column also functions as a via to send signals from a first layer to a second layer of the semiconductor device. The combination of via and at least one of a transistor, a capacitor, or a resistor in a semiconductor device decreases an area penalty as compared to a semiconductor device that has vias formed separately from at least one of a transistor, a capacitor, or resistor. | 2016-03-17 |
20160079356 | ELECTRONIC DEVICE OF VERTICAL MOS TYPE WITH TERMINATION TRENCHES HAVING VARIABLE DEPTH - An electronic device is integrated on a chip of semiconductor material having a main surface and a substrate region with a first type of conductivity. The electronic device has a vertical MOS transistor, formed in an active area having a body region with a second conductivity type. A set of one or more cells each one having a source region of the first conductivity, a gate region of electrically conductive material in a gate trench extending from the main surface in the body region and in the substrate region, and an insulating gate layer, and a termination structure with a plurality of termination rings surrounding at least part of the active area on the main surface, each termination ring having a floating element of electrically insulating material in the termination trench extending from the main surface in the chip and at least one bottom region of said semiconductor material of the second conductivity type extending from at least one deepest portion of a surface of the termination trench in the chip; the termination trenches have a depth from the main surface decreasing moving away from the active area. | 2016-03-17 |
20160079357 | ORIENTED BOTTOM-UP GROWTH OF ARMCHAIR GRAPHENE NANORIBBONS ON GERMANIUM - Graphene nanoribbon arrays, methods of growing graphene nanoribbon arrays and electronic and photonic devices incorporating the graphene nanoribbon arrays are provided. The graphene nanoribbons in the arrays are formed using a scalable, bottom-up, chemical vapor deposition (CVD) technique in which the (001) facet of the germanium is used to orient the graphene nanoribbon crystals along the [110] directions of the germanium. | 2016-03-17 |
20160079358 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor structure, and methods for forming the semiconductor device are provided. In various embodiments, the semiconductor device includes a substrate, source/drain regions over the substrate, a plurality of nanowires over the substrate and sandwiched by the source/drain regions, a gate dielectric layer surrounding the plurality of nanowires, and a gate layer surrounding the gate dielectric layer. | 2016-03-17 |
20160079359 | HIGH VOLTAGE FIELD EFFECT TRANSISTORS - Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions. | 2016-03-17 |
20160079360 | UNIAXIALLY STRAINED NANOWIRE STRUCTURE - Uniaxially strained nanowire structures are described. For example, a semiconductor device includes a plurality of vertically stacked uniaxially strained nanowires disposed above a substrate. Each of the uniaxially strained nanowires includes a discrete channel region disposed in the uniaxially strained nanowire. The discrete channel region has a current flow direction along the direction of the uniaxial strain. Source and drain regions are disposed in the nanowire, on either side of the discrete channel region. A gate electrode stack completely surrounds the discrete channel regions. | 2016-03-17 |
20160079361 | Silicide Region of Gate-All-Around Transistor - The disclosure relates to a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a nanowire structure protruding from the substrate comprising a channel region between a source region and a drain region; a pair of silicide regions extending into opposite sides of the source region, wherein each of the pair of silicide regions comprising a vertical portion adjacent to the source region and a horizontal portion adjacent to the substrate; and a metal gate surrounding a portion the channel region. | 2016-03-17 |
20160079362 | METHOD OF FORMING AN EPITAXIAL SEMICONDUCTOR LAYER IN A RECESS AND A SEMICONDUCTOR DEVICE HAVING THE SAME - A method of manufacturing a semiconductor device may include: etching a recess in a semiconductor substrate, where the etching produces a metal residue over a surface of the recess. The recess may thereafter be exposed to a cleaning process that causes the metal residue to etch at least one fissure in the semiconductor substrate. The at least one fissure may extend from the surface of the recess into the semiconductor substrate. The method may further include epitaxially forming a liner comprising a first semiconductor material having a first dopant concentration within the recess and over the at least one fissure. The method proceeds with epitaxially forming a semiconductor layer comprising a second semiconductor material having a second dopant concentration over the liner. | 2016-03-17 |
20160079363 | TRANSISTOR, ELECTRONIC DEVICE HAVING THE TRANSISTOR, AND METHOD FOR FABRICATING THE SAME - An electronic device includes a semiconductor memory unit that includes: a gate including at least a portion buried in a substrate; a junction portion formed in the substrate on both sides of the gate; and a memory element coupled with the junction portion on one side of the gate, wherein the junction portion includes: a recess having a bottom surface protruded in a pyramid shape; an impurity region formed in the substrate and under the recess; and a contact pad formed in the recess. | 2016-03-17 |
20160079364 | DEEP COLLECTOR VERTICAL BIPOLAR TRANSISTOR WITH ENHANCED GAIN - An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant. | 2016-03-17 |
20160079365 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According one embodiment, a memory device includes: a stacked body provided on a foundation layer, the stacked body including electrode layers stacked alternately with first insulating layers, at least one of the plurality of electrode layers including a first portion and a second portion, a first length between the first portion and the foundation layer being longer than a second length between the second portion and the foundation layer, difference between the first length and the second length increasing toward the foundation layer; a semiconductor member piercing the second portion, the semiconductor member extending in a direction of the stacking of the electrode layers and the first insulating layers, the semiconductor member including a region where maximum length of the semiconductor member cut perpendicularly to the direction decreases toward the foundation layer; and a memory film provided between the semiconductor member and each of the electrode layers. | 2016-03-17 |
20160079366 | Method of Tuning Doping Concentration in III-V Compound Semiconductor through Co-Doping Donor and Acceptor Impurities - A method includes epitaxially growing a first III-V compound semiconductor, wherein the first III-V compound semiconductor is of p-type. The first III-V compound semiconductor is grown using precursors including a first precursor comprising Cp2Mg, and a second precursor comprising a donor impurity. A second III-V compound semiconductor is grown overlying and contacting the first III-V compound semiconductor. The second III-V compound semiconductor is of n-type. | 2016-03-17 |
20160079367 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device may have a structure that prevents or reduces an etching amount of certain portions, such as a part of a source/drain region. Adjacent active fins may be merged with a blocking layer extending between adjacent the source/drain region. The blocking layer may be of a material that is relatively high-resistant to the etchant. | 2016-03-17 |
20160079368 | Metal-Oxide-Semiconductor Field-Effect Transistor with Extended Gate Dielectric Layer - A metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a source and a drain in the substrate, a gate electrode disposed over the substrate between the source and drain, and a gate dielectric layer disposed between the substrate and the gate electrode. At least a portion of the gate dielectric layer is extended beyond the gate electrode toward at least one of the source or the drain. | 2016-03-17 |
20160079369 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes first and second electrodes, and a first semiconductor region provided between the first and second electrodes. A first element region includes a second semiconductor region provided between the first semiconductor region and the first electrode, a third semiconductor region provided between the first semiconductor region and the second electrode, a fourth semiconductor region provided between the third semiconductor region and the second electrode, and a third electrode provided in the first, third and fourth semiconductor regions. A second element region includes a fifth semiconductor region provided between the first semiconductor region and the first electrode, and a sixth semiconductor region provided between the first semiconductor region and the second electrode. An isolation region includes a seventh semiconductor region provided between the first semiconductor region and the second electrode. The isolation region is positioned between the first and second element regions. | 2016-03-17 |
20160079370 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - According to one embodiment, a nitride semiconductor device including a first semiconductor layer and a second semiconductor layer is provided. The first semiconductor layer is provided on a base, and includes a nitride semiconductor. The first semiconductor layer includes a first region, and a second region which is provided on the first region, has a concentration of Si lower than a concentration of Si in the first region, and is thicker than the first region. The second semiconductor layer is provided on the first semiconductor layer. | 2016-03-17 |
20160079371 | SEMICONDUCTOR DEVICE - According to one embodiment, there is provided a semiconductor device including a first semiconductor layer, a second semiconductor layer, a first insulating film, a first electrode, and a second insulting film. The first semiconductor layer includes a compound semiconductor. The second semiconductor layer is provided on the first semiconductor layer and includes a compound semiconductor. The first insulating film is provided on the second semiconductor layer. The first electrode is provided on the first insulating film. The second insulting film covers at least a portion of the first electrode and has a higher hydrogen concentration than the hydrogen concentration of the first insulating film. | 2016-03-17 |
20160079372 | DEVICE CONTACT STRUCTURES INCLUDING HETEROJUNCTIONS FOR LOW CONTACT RESISTANCE - A semiconductor device can include a channel region with a first semiconductor material for a majority carrier in the channel region during operation (on state) of the device and a metal contact. A source/drain region can include a semiconductor material alloy including a second semiconductor material and at least one heterojunction located between the metal contact and the channel region, wherein the heterojunction forms a band-edge offset for the majority carrier that is less than or equal to about 0.2 eV. | 2016-03-17 |
20160079373 | SEMICONDUCTOR DEVICE - A semiconductor device includes a compound semiconductor layer, an insulating element, and a conductive element. The conductive element includes a plurality of conductive regions which are spaced from the compound semiconductor layer in a first direction. The insulating element is provided between the compound semiconductor layer and the conductive element. A length of each of the plurality of conductive regions in a second direction which intersects the first direction becomes longer the farther the individual one of the plurality of conductive regions is spaced from the compound semiconductor layer. | 2016-03-17 |
20160079374 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor device includes forming a first electrode on a lower portion of a trench that is formed on a semiconductor layer and having a first insulating film between the first electrode and the semiconductor layer; forming a second insulating film that covers an inner surface of an upper portion of the trench, forming a resist film that extends into the upper portion of the trench on the second insulating film, removing the second insulating film between the resist film and a side wall of the trench to leave a portion of the second insulating film on the first electrode, forming a third insulating film on a side wall of an upper portion of the trench, and forming a second electrode on the first electrode in an inner portion of the second insulating film. | 2016-03-17 |
20160079375 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, the electrodes are provided in the first semiconductor layer and extend in a first direction. The gate electrodes are provided on the electrodes and extend in the first direction. The interconnection is provided outside ends in the first direction of the gate electrodes, extends in a second direction crossing the first direction, and is commonly connected to the electrodes. The gate contacts are provided on the gate electrodes and connected to the gate electrodes. | 2016-03-17 |
20160079376 | Semiconductor Device with Field Electrode Structure - According to an embodiment a semiconductor device includes a semiconductor body with a mesa section that may include a rectifying structure and a first drift zone section. The mesa section surrounds a field electrode structure that includes a field electrode and a field dielectric sandwiched between the field electrode and the semiconductor body. A maximum horizontal extension of the field electrode in a measure plane parallel to a first surface of the semiconductor body is at most 500 nm. | 2016-03-17 |
20160079377 | Semiconductor Device with Current Sensor - A semiconductor device includes a semiconductor body. The semiconductor body includes a load transistor part and a sensor transistor part. A first source region of the load transistor part and a second source region of the sensor transistor part are electrically separated from each other. A common gate electrode in a common gate trench extends into the semiconductor body from a first surface. A first part of the common gate trench is in the load transistor part, and a second part of the common gate trench is in the sensor transistor part. A field electrode in a field electrode trench extends into the semiconductor body from the first surface. A maximum dimension of the field electrode trench parallel to the first surface is smaller than a depth of the field electrode trench. | 2016-03-17 |
20160079378 | TRANSISTOR DEVICES AND METHODS - The present disclosure includes transistor devices and methods. In one embodiment, a transistor includes a gate, a source, and a drain. According to one aspect of the disclosure, different resistive paths in the drain are compensated using different gate-to-drain capacitances. According to another aspect of the disclosure, current enters a drain at a center tap point and flows symmetrically outward under two adjacent gates to two adjacent sources. | 2016-03-17 |
20160079379 | SEMICONDUCTOR DEVICE INCLUDING FIRST AND SECOND MISFETS - In an n-channel HK/MG transistor including: a gate insulating film made of a first high dielectric film containing La and Hf; and a gate electrode which is formed of a stacked film of a metal film and a polycrystalline Si film and which is formed in an active region in a main surface of a semiconductor substrate and surrounded by an element separation portion formed of an insulating film containing oxygen atoms, a second high dielectric film which contains Hf but whose La content is smaller than a La content of the first high dielectric film is formed below the gate electrode which rides on the element separation portion, instead of the first high dielectric film. | 2016-03-17 |
20160079380 | SEMICONDUCTOR STRUCTURE AND A FABRICATING METHOD THEREOF - A gate structure is provided. The gate structure includes a substrate, a gate disposed on the substrate and a gate dielectric layer disposed between the substrate and the gate, wherein the gate dielectric layer is in the shape of a barbell. The barbell has a thin center connecting to two bulging ends. Part of the bulging ends extends into the gate and the substrate. | 2016-03-17 |
20160079381 | Semiconductor Chip Including Integrated Circuit Including At Least Five Gate Level Conductive Structures Having Particular Spatial and Electrical Relationship and Method for Manufacturing the Same - A semiconductor chip region includes a first conductive structure (CS) that forms a gate electrode (GE) of a first transistor of a first transistor type (TT) and a GE of a first transistor of a second TT, a second CS that forms a GE of a second transistor of the first TT, a third CS that forms a GE of a second transistor of the second TT, a fourth CS that forms a GE of a third transistor of the first TT, and a fifth CS that forms a GE of a third transistor of the second TT. Diffusion terminals of the first and second transistors of the first TT are electrically connected. Diffusion terminals of the first and second transistors of the second TT are electrically connected. Diffusion terminals of the second and third transistors of both the first TT and second TT are electrically connected. | 2016-03-17 |
20160079382 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer, a gate insulation film on the semiconductor layer, and a gate electrode on the gate insulation film. The gate electrode includes a first metal compound layer with a first element also contained in the gate insulation film. A first metal layer is on the first metal compound layer, wherein the diffusion coefficient thereof in gold is smaller than the diffusion coefficient thereof in nickel. The first metal layer includes a second element also contained in the first metal compound layer. A gold layer is on the first metal layer. A second metal layer is on the gold layer. Third metal layers are on side surfaces of the gold layer. A source and drain electrode are provided. An interlayer insulation film is on the gate electrode. | 2016-03-17 |
20160079383 | SEMICONDUCTOR DEVICE HAVING MODIFIED PROFILE METAL GATE - A semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer. | 2016-03-17 |
20160079384 | GATE STRUCTURE INTEGRATION SCHEME FOR FIN FIELD EFFECT TRANSISTORS - In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure includes a dielectric spacer contacting a sidewall of a gate dielectric and a gate conductor. Epitaxial source and drain regions are present on opposing sidewalls of the fin structure, wherein surfaces of the epitaxial source region and the epitaxial drain region that is in contact with the sidewalls of the fin structure are aligned with an outside surface of the dielectric spacer. In some embodiments, the dielectric spacer, the gate dielectric, and the gate conductor of the semiconductor device are formed using a single photoresist mask replacement gate sequence. | 2016-03-17 |
20160079385 | VERTICAL TFT WITH MULTILAYER PASSIVATION - A vertical transistor includes an electrically conductive gate structure having a reentrant profile in contact with a substrate. A conformal gate insulating layer is in contact with the gate structure in the reentrant profile. A conformal semiconductor layer is in contact with the conformal gate insulating layer. A first electrode is in contact with a first portion of the conformal semiconductor layer over the electrically conductive gate structure. A second electrode is in contact with a second portion of the conformal semiconductor layer and separated vertically from the first electrode. The vertical TFT has a multilayer insulating structure that is in contact with at least the conformal semiconductor layer in the reentrant profile. The multilayer insulating structure includes an inorganic dielectric layer and a polymer structure in contact with the conformal semiconductor layer in the reentrant profile. | 2016-03-17 |
20160079386 | SEMICONDUCTOR WAFER, METHOD OF PRODUCING SEMICONDUCTOR WAFER AND ELECTRONIC DEVICE - To provide a semiconductor wafer having a wafer, a compound semiconductor layer, a first insulating layer and a second insulating layer, wherein in the depth direction, oxygen atoms and nitrogen atoms are continuously distributed, the number of the nitrogen atoms along the depth direction shows its maximum in the first insulating layer, the total number of third atoms and fourth atoms along the depth direction becomes the largest in the compound semiconductor layer, the number of the oxygen atoms at the interface between the compound semiconductor layer and the first insulating layer is smaller than the number of the oxygen atoms at the interface between the first insulating layer and the second insulating layer. | 2016-03-17 |