11th week of 2021 patent applcation highlights part 60 |
Patent application number | Title | Published |
20210082466 | FABRICATION METHODS FOR MAGNETIC RECORDING TAPE HAVING RESILIENT SUBSTRATE - A method for making a magnetic recording tape, in accordance with one approach, includes coupling an underlayer to a substrate, the substrate comprising a poly ether ether ketone (PEEK). A method for making a magnetic recording tape in accordance with another approach includes coupling an underlayer to a substrate via radiation-induced grafting, the substrate comprising a poly ether ether ketone (PEEK). A recording layer is coupled to the underlayer. | 2021-03-18 |
20210082467 | DATA STORAGE SYSTEM INCLUDING MOVABLE CARRIAGE - An apparatus with a housing which stores a plurality of data storage magazines, where each data storage magazine includes a plurality of data storage devices. The housing includes a movable carriage, the movable carriage configured to selectively couple a set of data storage devices held by a particular data storage magazine to a host device. The housing also includes a motor configured to move the movable carriage within the housing to enable the movable carriage to communicatively couple the set of data storage devices held by the particular data storage magazine to the host device | 2021-03-18 |
20210082468 | DISK DEVICE AND READ PROCESSING METHOD - According to one embodiment, a disk device includes a disk, a head including a write head which writes data to the disk, a first read head which reads data from the disk, and is configured to detect a first value indicating a signal quality of read data during read processing, and a second read head which reads data from the disk, and is configured to detect a second value indicating a signal quality of read data during read processing, and a controller which determines whether there is a possibility that data cannot be read by the first read head and the second read head based on the first value and the second value. | 2021-03-18 |
20210082469 | AUTOMATIC DETECTION AND REMEDIATION OF VIDEO IRREGULARITIES - An embodiment includes receiving, by one or more processors, a scene reference that corresponds to a reference state of the scene. The embodiment also includes comparing, by one or more processors, the candidate portion and the scene reference such that the comparing provides an indication of an irregularity in the candidate portion. The embodiment also includes responsive to the indication of the irregularity in the candidate portion, automatically evaluating the irregularity, using one or more processors, such that the evaluating generates a severity value associated with the irregularity. The embodiment also includes, responsive to the generating of the severity value, automatically initiating, by one or more processors, a selected remedial action from among a plurality of remedial action options based at least in part on the severity value, wherein the automatic initiation of the selected remedial action includes automatic actuation of an element of video production equipment. | 2021-03-18 |
20210082470 | GENERATION AND DISTRIBUTION OF A DIGITAL MIXTAPE - A system for generating and distributing a digital mixtape. In one example, the system can receive a user command to generate a digital mixtape including a user-defined compilation of music. The user command identifies a recipient of the digital mixtape and identifies one or more media content items to be included in the music compilation for the recipient. The digital mixtape can also include audio recordings from the user to be added to the digital mixtape. | 2021-03-18 |
20210082471 | SYSTEMS AND METHODS FOR GENERATING MUSIC RECOMMENDATIONS - Systems, methods, and non-transitory computer-readable media can be configured to determine a video embedding for a video content item based at least in part on a first machine learning model. A set of music embeddings can be determined for a set of music content items based at least in part on a second machine learning model. The set of music content items can be ranked based at least in part on the video embedding and the set of music embeddings. | 2021-03-18 |
20210082472 | VIDEO-LOG PRODUCTION SYSTEM - Methods, computer-readable media, and apparatuses for composing a video in accordance with a user goal and an audience preference are described. For example, a processing system having at least one processor may obtain a plurality of video clips of a user, determine at least one goal of the user for a production of a video from the plurality of video clips, determine at least one audience preference of an audience, and compose the video comprising at least one video clip of the plurality of video clips of the user in accordance with the at least one goal of the user and the at least one audience preference. The processing system may then upload the video to a network-based publishing platform. | 2021-03-18 |
20210082473 | DISPLAY METHOD, COMPUTER-READABLE RECORDING MEDIUM RECORDING DISPLAY PROGRAM, AND INFORMATION PROCESSING APPARATUS - A display method includes: acquiring, by a computer, sensing data obtained by sensing a motion of a player by a three-dimension (3D) sensor; specifying predetermined timing of each joint from a change in a degree of bending of each joint of the player based on the sensing data; and displaying the predetermined timing of each joint in a graspable state in association with a slide bar for designating playback timing in a motion model of the player based on the sensing data or a video obtained by capturing the player. | 2021-03-18 |
20210082474 | MEMORY SYSTEM - A memory system includes a first substrate including a first signal terminal and a second signal terminal electrically connected to a bus, a first circuit in which a first switching element and a first resistor are connected in series between a first terminal and a second terminal, the first terminal connected to the first signal terminal, a second circuit in which a second switching element and a second resistor are connected in series between a third terminal and a fourth terminal, the third terminal connected to the second signal terminal, a first memory electrically connected to the second terminal, a second memory electrically connected to the fourth terminal, and a controller electrically connected to the bus and configured to control the first and second switching elements. | 2021-03-18 |
20210082475 | SRAM HAVING IRREGULARLY SHAPED METAL LINES - A semiconductor device includes a gate structure, a source/drain, a first via that is disposed over the gate structure and the source/drain, and a first metal line having a more elevated vertical position than the first via in a cross-sectional view. The first via is electrically coupled to both the gate structure and the source/drain. The first metal line and the first via each extends in a first direction. A first distance separates the metal line from the via in a second direction different from the first direction. The first metal line includes a protruding portion that protrudes outwardly in the second direction. | 2021-03-18 |
20210082476 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment includes: a substrate having a substrate plane extending in a first direction and a second direction intersecting with the first direction; a first wiring provided above the substrate, the first wiring being provided so that a longitudinal direction extends along the first direction; a second wiring provided above the substrate, the second wiring being separated from the first wiring in the first direction, the second wiring being passed by the same virtual line together with the first wiring, the second wiring being provided so that a longitudinal direction extends along the first direction; a third wiring provided between the first wiring and the second wiring, the third wiring being separated from the first wiring and the second wiring, the third wiring being passed by the same virtual line together with the first wiring and the second wiring, the third wiring being provided so that a longitudinal direction extends along the first direction; a fourth wiring provided above the first wiring, the fourth wiring overlapping with the first wiring when viewed from the above, the fourth wiring being provided so that a longitudinal direction extends along the first direction; a fifth wiring provided over the second wiring and the third wiring, the fifth wiring being separated from the fourth wiring in the first direction, the fifth wiring overlapping with the second wiring and the third wiring when viewed from the above, the fifth wiring being passed by the same virtual line together with the fourth wiring, the fifth wiring being provided so that a longitudinal direction extends along the first direction; a sixth wiring provided over the fourth wiring and the fifth wiring, the sixth wiring overlapping with the fourth wiring and the fifth wiring when viewed from the above, the sixth wiring being provided so that a longitudinal direction extends along the first direction; a plurality of seventh wirings provided between the first wiring and the fourth wiring, between the third wiring and the fifth wiring, and between the second wiring and the fifth wiring, the seventh wirings being provided so that a longitudinal direction extends along the second direction; a plurality of eighth wirings provided between the fourth wiring and the sixth wiring and between the fifth wiring and the sixth wiring, the eighth wirings being provided so that a longitudinal direction extends along the second direction; a plurality of first memory cells provided between the first wiring, the second wiring, and the third wiring and the seventh wirings; a plurality of second memory cells provided between the fourth wiring and the seventh wirings and between the fifth wiring and the seventh wirings, the second memory cells overlapping with the first memory cells when viewed from the above; a plurality of third memory cells provided between the fourth wiring and the eighth wirings and between the fifth wiring and the eighth wirings, the third memory cells overlapping with the second memory cells when viewed from the above; a plurality of fourth memory cells provided between the sixth wiring and the eighth wirings, the fourth memory cells overlapping with the third memory cells when viewed from the above; a first connection wiring provided above the substrate, the first connection wiring being provided at least partially under a portion where the first wiring and the third wiring are separated; a second connection wiring provided between the first wiring and the third wiring so that a longitudinal direction extends along a third direction intersecting with the first direction and the second direction, the second connection wiring connecting the sixth wiring and the first connection wiring; a third connection wiring configured to connect the first wiring and the first connection wiring; a fourth connection wiring configured to connect the third wiring and the first connection wiring; a fifth connection wiring provided above the substrate, the fifth connection wiring being provided at least partially under a portion where the second wiring and the third wiring are separated; and a sixth connection wiring provided between the second wiring and the third wiring so that a longitudinal direction extends along the third direction, the sixth connection wiring connecting the fifth wiring and the fifth connection wiring. | 2021-03-18 |
20210082477 | LEVEL SHIFTER - A voltage level shifter for an SRAM device includes a level shifter input and provides a second voltage level. A voltage input terminal receives a first signal at a first voltage level and an inverter having an input and an output with the voltage input terminal is connected to the inverter input. A first voltage selector selectively applies an intermediate voltage to the gate of a PMOS transistor in a first complementary pair when the voltage of a complementary level shift output voltage rises to a logical 1 and a second voltage selector applies the intermediate voltage to the gate of a PMOS transistor in a second complementary pair when the voltage of the level shift output voltage node rises to a logical 1. The PMOS transistor current is thereby reduced resulting in lower energy dissipation and supporting a larger voltage separation between the first and second voltage levels. | 2021-03-18 |
20210082478 | SEMICONDUCTOR MEMORY DEVICE AND A MEMORY SYSTEM HAVING THE SAME - A semiconductor memory device includes: a temperature sensor configured to sense an internal temperature of the semiconductor memory device and generate a temperature signal; and a temperature code storage unit configured to receive the temperature signal in response to a temperature code write control signal that is generated when an operation corresponding to a specific command is performed, generate an operating temperature code corresponding to the temperature signal, compare the operating temperature code with a previously stored temperature code, store a larger temperature code of the operating temperature code and the previously stored temperature code as a maximum temperature code, and output the maximum temperature code to an external source in response to a temperature code read control signal. | 2021-03-18 |
20210082479 | METHOD AND MEMORY SYSTEM FOR OPTIMIZING ON-DIE TERMINATION SETTINGS OF MULTI-RANKS IN A MULTI-RANK MEMORY DEVICE - A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal. | 2021-03-18 |
20210082480 | CELL MODULE EQUALIZATION AND PRECHARGE DEVICE AND METHOD - A device and a method for equalizing and precharging a cell module, which may form a circuit for performing a corresponding operation by a converter unit by selectively connecting the converter unit and one or more cell modules by controlling a conduction state of a switching unit based on an operation which the converter intends to perform. | 2021-03-18 |
20210082481 | DATA AND CLOCK SYNCHRONIZATION AND VARIATION COMPENSATION APPARATUS AND METHOD - An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data. | 2021-03-18 |
20210082482 | MAGNETORESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A magnetoresistive memory device includes a plurality of bottom conductive lines, a plurality of top conductive lines, a first memory cell, and a second memory cell. The top conductive lines are over the bottom conductive lines. The first memory cell is between the bottom conductive lines and the top conductive lines and includes a first magnetic tunnel junction (MTJ) stack. The second memory cell is adjacent the first memory cell and between the bottom conductive lines and the top conductive lines. The second memory cell includes a second MTJ stack, and a top surface of the second MTJ stack is higher than a top surface of the first MTJ stack. | 2021-03-18 |
20210082483 | MEMORY SYSTEM - According to one embodiment, a shift register memory includes blocks and a control circuit. The blocks each includes data storing shift strings. Each of the data storing shift strings includes layers. The control circuit performs storing and reading data by shifting one layer of the layers, in a direction along each of the data storing shift strings. The reading includes reading data from a first layer of the layers. The storing includes storing data to a second layer of the layers. The control circuit reads first data stored in one or more third layers of the layers, the one or more third layers being successive from the first layer, determines a shift parameter in accordance with the reading of the first data, and performs the reading using the determined shift parameter. | 2021-03-18 |
20210082484 | MAGNETIC MEMORY - A magnetic memory according to an embodiment includes: a first wiring; a second wiring; a first switching element disposed between the first wiring and the second wiring; a first magnetic member extending in a first direction and disposed between the first switching element and the second wiring; a third wiring disposed between the first magnetic member and the second wiring; a first magnetoresistive element disposed between the third wiring and the second wiring; and a second switching element disposed between the first magnetoresistive element and the second wiring. | 2021-03-18 |
20210082485 | ASYNCHRONOUS READ CIRCUIT USING DELAY SENSING IN MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) - Some embodiments of the present disclosure relate to a memory device. The memory device includes an active current path including a magnetic tunnel junction (MTJ); and a reference current path including a reference resistance element. The reference resistance element has a resistance that differs from a resistance of the MTJ. An asynchronous, delay-sensing element has a first input coupled to the active current path and a second input coupled to the reference current path. The asynchronous, delay-sensing element is configured to sense a timing delay between a first rising or falling edge voltage on the active current path and a second rising or falling edge voltage on the reference current path. The asynchronous, delay-sensing element is further configured to determine a data state stored in the MTJ based on the timing delay. | 2021-03-18 |
20210082486 | MEMORY DEVICE - According to one embodiment, a memory device includes a resistance change memory element to which one of a low-resistance state and a high-resistance state is allowed to be set in accordance with a write current, a first transistor including a first gate, and causing a current to flow through the resistance change memory element in a first write period, a voltage holding section holding a first voltage applied to the first gate in the first write period, and a second transistor including a second gate, in which the first voltage held in the voltage holding section is applied to the second gate, thereby causing a current to flow through the resistance change memory element in a second write period after the first write period. | 2021-03-18 |
20210082487 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR LOGIC DEVICE - The present invention relates to a semiconductor device. The semiconductor device based on the spin orbit torque (SOT) effect, according to an example of the present invention, comprises the first electrode; and the first cell and the second cell connected to the first electrode, wherein the first and the second cells are arranged on the first electrode separately; the magnetic tunnel junction (MTJ) having a free magnetic layer and a pinned magnetic layer with a dielectric layer in between them; the magnetization direction of the free magnetic layer is changed when the current applied on the first electrode exceeds critical current value of each cell; and the critical current value of the first cell is different from that of the second cell. | 2021-03-18 |
20210082488 | PACKAGED INTEGRATED CIRCUIT HAVING A PHOTODIODE AND A RESISTIVE MEMORY - A packaged integrated circuit includes a photodiode and a memory. The photodiode generates energy when radiation strikes a surface of the photodiode. The memory includes a plurality of non-volatile memory cells and memory control circuitry. The memory control circuitry is configured to perform an operation to change values stored in at least some of the memory cells of the plurality of non-volatile memory cells while being powered by energy generated by the photodiode. An encapsulant at least partially encapsulates the photodiode and the memory, in which the encapsulant blocks radiation from reaching the surface of the photodiode. | 2021-03-18 |
20210082489 | TIME TRACKING CIRCUIT FOR FRAM - Methods and apparatus for reading and/or writing FRAM memory are disclosed. An example memory circuit includes a controller to output a signal to an input of a driver; a transistor coupled an output of the driver; the driver to, in response to receiving the signal, output a first voltage to the transistor; and the transistor to, in response to receiving the first voltage, output a second voltage to a bit cell after a transistor delay, the transistor selected based on a size of the memory circuit. | 2021-03-18 |
20210082490 | Memory Device Having Variable Impedance Memory Cells and Time-To-Transition Sensing of Data Stored Therein - The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a memory array including a plurality of memory cells, each memory cell having an impedance that varies in accordance with a respective data value stored therein; and a tracking memory cell having an impedance based on a tracking data value stored therein; and a read circuit coupled to the memory array, the read circuit configured to determine an impedance of a selected memory cells with respect to the impedance of the tracking memory cell; read a data value stored within the selected memory cell based upon a voltage change of a signal node voltage corresponding to the impedance of the selected memory cell. | 2021-03-18 |
20210082491 | MEMORY DEVICE, MEMORY SYSTEM, AND METHOD FOR REFRESHING MEMORY DEVICE - A memory device applies different refresh rates to target data (or objective data) according to data characteristics (i.e., required reliability levels). The memory device includes a memory cell array provided with a plurality of memory cells, a row decoder configured to selectively activate word lines of the memory cell array in response to a row address signal, and a refresh controller configured to output the row address signal in response to the row address signal. The refresh controller controls a refresh ratio of a first storage region and a second storage region contained in the memory cell array in response to a changeable refresh control value. | 2021-03-18 |
20210082492 | SRAM Structure with Reduced Capacitance and Resistance - A structure includes an SRAM cell includes a first and a second pull-up MOS device, and a first and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device. A first metal layer is over the gate electrodes of the MOS devices in the SRAM cell. The structure further includes a first metal layer, and a CVss landing pad, wherein the CVss landing pad has a portion in the SRAM cell. The CVss landing pas is in a second metal layer over the first metal layer. A word-line is in the second metal layer. A CVss line is in a third metal layer over the second metal layer. The CVss line is electrically coupled to the CVss landing pad. | 2021-03-18 |
20210082493 | STRAP CELL DESIGN FOR STATIC RANDOM ACCESS MEMORY (SRAM) ARRAY - A SRAM array is provided. The SRAM array includes a first bit cell array and a second bit cell array arranged along a first direction, and a strap cell arranged along a second direction and positioned between the first bit cell array and the second bit cell array along the first direction. The strap cell includes a first P-type well region, two first N-type well regions, a second N-type well region. The two first N-type well regions are separated by the first P-type well region in the first direction, and the second N-type well region and one of the two first N-type well regions are separated by the first P-type well region in the second direction. The strap cell further includes a deep N-type well region underlying the two first N-type well regions and the second N-type well region. | 2021-03-18 |
20210082494 | CIRCUIT FOR REDUCING VOLTAGE DEGRADATION CAUSED BY PARASITIC RESISTANCE IN A MEMORY DEVICE - An array of memory cells is arranged into a plurality of columns and rows. A first signal line extends through a first column of the plurality of columns. The first signal line is electrically coupled to the memory cells in the first column. A first end portion of the first signal line is configured to receive a logic high signal from a first circuit during a first operational state of the memory device and a logic low signal from the first circuit during a second operational state of the memory device. A second circuit includes a plurality of transistors. The transistors are configured to be turned on or off to electrically couple a second end portion of the first signal line to a logic low source when the first end portion of the first signal line is configured to receive the logic low signal from the first circuit. | 2021-03-18 |
20210082495 | INTEGRATED CIRCUIT AND OPERATING METHOD THEREOF - An integrated circuit and an operating method thereof are provided. The integrated circuit includes memory cells, at least one first word line, second word lines, bit lines and write-assist bit lines. The at least one first word line is electrically connected to at least one row of the memory cells. The second word lines are electrically connected to other rows of the memory cells. Two bit lines are located between a column of the memory cells and two write-assist bit lines. The bit lines and the write-assist bit lines are configured to be electrically disconnected with each other when at least one of the memory cells electrically connected with the at least one first word line is configured to be written, and electrically connected with each other when at least one of the memory cells electrically connected to the second word lines is configured to be written. | 2021-03-18 |
20210082496 | Read Assist Circuitry for Memory Applications - Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. While activated, the read assist transistor may generate an adaptive underdrive on the wordline, the level of which depends on the process, temperature and voltage of operation of the memory, when the wordline is selected and driven by the wordline driver. | 2021-03-18 |
20210082497 | MEMORY SYSTEM - A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state. | 2021-03-18 |
20210082498 | MEMORY SYSTEM AND OPERATING METHOD OF MEMORY SYSTEM - A memory system includes: a memory device including a three dimensional (3D) cell array, in which memory cells having the same height are coupled to a component word line by units of rows and component word lines having the same height are coupled to a group word line; and a controller suitable for controlling the memory device to perform a program operation with a program data into memory cells coupled to a data component word line selected from a plurality of component word line included in a single group word line and to perform a dummy program operation with dummy data into memory cells coupled to remaining dummy component word lines among the plurality of component word lines. | 2021-03-18 |
20210082499 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes: a voltage generation circuit configured to generate a read voltage to be supplied to a selected word line to which a read-target memory cell transistor is connected and a read-pass voltage to be supplied to an adjacent word line; a word line driver configured to, when the read voltage transitions, apply the read voltage to the selected word line with a first kick voltage amount and apply the read-pass voltage to the adjacent word line with a second kick voltage amount; and a control circuit configured to set each of the first kick voltage amount and the second kick voltage amount to a voltage corresponding to an amount of the transition. | 2021-03-18 |
20210082500 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device of an embodiment has stacked semiconductor memories, each semiconductor memory including first lines intersecting with second lines, and resistive change elements each disposed between one of the first lines and one of the second lines. In two of the semiconductor memories adjacent to each other in the stacking direction, either two of the first lines or two of the second lines are disposed along and in contact with each other. A first contact electrically connected to the second line of the uppermost semiconductor memory passes through a region between the second lines of each of the semiconductor memories located below the uppermost semiconductor memory, and a second contact electrically connected to the second line of each of the semiconductor memories located at an intermediate level passes through a region between the second lines of each of the semiconductor memories located below the intermediate level. | 2021-03-18 |
20210082501 | MEMORY DEVICE INCLUDING DISCHARGE CIRCUIT - A memory device includes: first conductive lines extending in a first direction; second conductive lines extending in a second direction intersecting the first direction; a plurality of memory cells disposed at intersection portions of the first conductive lines and the second conductive lines; first selection transistors respectively connected to the first conductive lines, the first selection transistors constituting a plurality of groups; and first discharge circuits respectively connected to the plurality of groups of first selection transistors, each of the first discharge circuits discharging a group of first conductive lines corresponding thereto among the first conductive lines in response to a gate control signal. | 2021-03-18 |
20210082502 | RESISTIVE RANDOM-ACCESS MEMORY FOR EXCLUSIVE NOR (XNOR) NEURAL NETWORKS - A resistive random-access memory (RRAM) system includes an RRAM cell. The RRAM cell includes a first select line and a second select line, a word line, a bit line, a first resistive memory device, a first switching device, a second resistive memory device, a second switching device, and a comparator. The first resistive memory device is coupled between a first access node and the bit line. The first switching device is coupled between the first select line and the first access node. The second resistive memory device is coupled between a second access node and the bit line. The second switching device is coupled between the second select line and the second access node. The comparator includes a first input coupled to the bit line, a second input, and an output. | 2021-03-18 |
20210082503 | APPARATUSES, MEMORIES, AND METHODS FOR ADDRESS DECODING AND SELECTING AN ACCESS LINE - Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. The first select line is configured to provide a first voltage, the second select line is configured to provide a second voltage, and the polarity line is configured to provide a polarity signal. The address decoder circuit is configured to receive address information and further configured to couple the access line to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level. | 2021-03-18 |
20210082504 | VOLTAGE-MODE BIT LINE PRECHARGE FOR RANDOM-ACCESS MEMORY CELLS - Circuits and methods are disclosed for voltage-mode bit line precharge for random-access memory cells. A circuit includes an array of random access memory cells; a low-impedance voltage source configured to provide a precharge voltage; and a control circuit configured to precharge a bit line of one of the random access memory cells to the precharge voltage using the low-impedance voltage source prior to reading the one of the random access memory cells. | 2021-03-18 |
20210082505 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor device according to an embodiment includes first and second drain select transistors, first and second source select transistors, first and second memory cell transistors, third and fourth memory cell transistors, first and second bit lines, first to third select gate line, first and second word lines, and a controller. The controller is configured to execute, in the program loop, a program operation, a recovery operation and a verify operation in sequence. In the write operation of the first memory cell transistor, the controller is configured, at a first time of the recovery operation, to: apply a first voltage to the first select gate line; apply a second voltage to the third select gate line; and apply a third voltage to the first bit line. | 2021-03-18 |
20210082506 | SUB-BLOCK SIZE REDUCTION FOR 3D NON-VOLATILE MEMORY - Systems and methods for reducing the size of sub-blocks within a physical memory block for a three-dimensional non-volatile memory using buried source lines are described. The physical memory block may be fabricated using dual buried source lines such that sub-blocks within the physical memory block may be individually selected in both a horizontal word line direction and a vertical NAND string direction. The physical memory block may include a plurality of sub-blocks that are individually selectable and that share bit lines and/or source-side select gate lines. The plurality of sub-blocks that are individually selectable may correspond with different portions of the same NAND string in which a first sub-block of the plurality of sub-blocks connects to a drain-side select gate for the NAND string and a second sub-block of the plurality of sub-blocks connects to a source-side select gate for the NAND string. | 2021-03-18 |
20210082507 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes first signal lines divided into groups respectively including m (m is an integer equal to or larger than 2) of the first signal lines; and second signal lines. A memory cell array includes memory cells provided to correspond to respective intersections of the first signal lines and the second signal lines. A selection voltage is applied to any of the first signal lines through m global signal lines. First transistors are provided to respectively correspond to the first signal lines and connected between the first signal lines and the global signal lines. First selection signal lines are provided to respectively correspond to the groups and connected to gate electrodes of the first transistors included in a corresponding one of the groups in common. First dummy signal lines are arranged between adjacent ones of the groups, to which a non-selection voltage is applied. | 2021-03-18 |
20210082508 | MEMORY SYSTEM AND METHOD FOR CONTROLLING MEMORY SYSTEM - According to one embodiment, a memory system includes a memory device and a controller. The controller is configured to instruct to apply, to a first word line, a determination voltage that is based on a first value and a first difference value in a case where it is determined whether or not a first data value has been written in a first memory cell, to instruct to apply, to a second word line, a determination voltage that is based on the first value, the first difference value, and a second difference value in a case where it is determined whether or not the first data value has been written in the second memory cell, and to change the first difference value in a case where a first condition is satisfied. | 2021-03-18 |
20210082509 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes first, second, third, and fourth planes, a first address bus connected to the first and third planes, a second address bus connected to the second and fourth planes, and a control circuit configured to execute a synchronous process on at least two planes in response to a first command set including a first address and a second address. The control circuit is configured to transfer the first address to the first and third planes through the first address bus, and the second address to the second and fourth planes through the second address bus, and during the synchronous process, select a first block in one of the first and third planes, based on the transferred first address and select a second block in one of the second and fourth planes, based on the transferred second address. | 2021-03-18 |
20210082510 | MEMORY SYSTEM - In connection with a write operation, a memory controller transmits a first command sequence to a memory chip, thereby causing the memory chip to execute a first-stage program operation that includes a first operation and a first part of a second operation after the first operation, and a second command sequence to the memory chip after the first-stage program operation is executed, thereby causing the memory chip to execute a second-stage program operation that includes a second part of the second operation and no part of the first operation. During the first operation, a program voltage is applied a plurality of times while increasing the program voltage each of the times by a first step size. During the second operation, the program voltage is applied a plurality of times while increasing the program voltage each of the times by a second step size smaller than the first step size. | 2021-03-18 |
20210082511 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes: a memory cell array including a memory cell transistor that is an electrically rewritable non-volatile semiconductor storage element. The memory cell transistor includes a gate electrode and a channel region adjacent the gate electrode. The semiconductor storage device includes a circuit configured to write the memory cell transistor by applying a breakdown voltage to cause dielectric breakdown between the gate electrode and the channel region. | 2021-03-18 |
20210082512 | SEMICONDUCTOR MEMORY DEVICE - A memory device includes a first cell above a substrate, a first line connected to the first cell, a second cell above the first cell connected with the first cell, a second line connected to the second cell, a third cell above the second cell connected with the second cell, a third line connected to the third cell, a fourth cell above the third cell connected with the third cell, a fourth line connected to the fourth cell, and a driver applying voltages to the lines when data is written to a cell in a write operation. To write data to the second cell, the driver applies a write voltage to the second line, applies a first voltage lower than the write voltage to the first line, and applies a second voltage higher than the first voltage and lower than the write voltage to the third and fourth lines. | 2021-03-18 |
20210082513 | MEMORY SYSTEM AND CONTROL METHOD OF MEMORY SYSTEM - According to one embodiment, a memory system includes a semiconductor memory device including a first and second string each including cells coupled in series, and a memory controller configured to instruct the device to execute a write operation for writing data on any one of the cells in the first or second string. The first and second string are coupled in parallel between a bit line and a source line, and coupled to different word lines. The write operation includes a first write operation and a second write operation executed after the first write operation. The controller is configured to instruct the device to execute a first write operation on a second cell in the second string between a first write operation on a first cell in the first string and a second write operation on the first cell. | 2021-03-18 |
20210082514 | NON-VOLATILE MEMORY AND DATA WRITING METHOD THEREOF - A non-volatile memory and a data writing method are provided. The non-volatile memory includes a memory array and a memory controller. The memory array has a plurality of memory cells. The memory controller is configured to perform a data write operation on a plurality of selected memory cells. In the data write operation, the memory controller records a total number of times that a data write pulse is supplied, compares the total number of times of the data write pulse to a preset threshold value to obtain an indication value, and adjusts an absolute value of a voltage of the data write pulse according to the indication value. | 2021-03-18 |
20210082515 | MEMORY DEVICE WITH COMPENSATION FOR PROGRAM SPEED VARIATIONS DUE TO BLOCK OXIDE THINNING - Techniques are provided for optimizing a program operation in a memory device to compensate for program speed variations due to block oxide thinning. In one approach, during a program operation, a program voltage which indicates program speed is acquired from sub-blocks with the highest and lowest program speeds. An initial program voltage for intermediate sub-blocks can be determined based on the acquired program voltages and the positions of the intermediate sub-blocks. The technique can accommodate a loss of one or both acquired program voltages if the programming is interrupted. In another approach, a program voltage which indicates program speed is acquired from one sub-block, and for a later-programmed sub-block, an appropriate offset is located from a table and summed with the acquired program voltage to determine an optimum initial program voltage. | 2021-03-18 |
20210082516 | Programming Circuit and Method For Flash Memory Array - An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed. In one embodiment, a programming circuit comprises a switch configured to couple a current source to a capacitor during a first mode and to uncouple the current source from the capacitor during the second mode, wherein during the second mode the capacitor is coupled to the gate of a transistor used to program a memory cell. | 2021-03-18 |
20210082517 | Non-volatile Memory Device With Stored Index Information - A memory device that includes a memory array having pluralities of non-volatile memory cells, a plurality of index memory cells each associated with a different one of the pluralities of the non-volatile memory cells, and a controller. The controller is configured to erase the pluralities of non-volatile memory cells, set each of the index memory cells to a first state, and program first data into the memory array by reading the plurality of index memory cells and determining that a first one of the index memory cells is in the first state, programming the first data into the plurality of the non-volatile memory cells associated with the first one of the index memory cells, and setting the first one of the index memory cells to a second state different from the first state. | 2021-03-18 |
20210082518 | INTEGRATED CIRCUIT DEVICE - An integrated circuit device includes channel structures extending from a substrate in a vertical direction, memory cell strings disposed along the plurality of channel structures, gate lines spaced apart from one another in the vertical direction and including erase control lines and string selection lines, and driving transistors including erase control driving transistors connected to the erase control lines and string selection driving transistors connected to the string selection lines. | 2021-03-18 |
20210082519 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line. | 2021-03-18 |
20210082520 | PROCESSOR IN NON-VOLATILE STORAGE MEMORY - In one example, a computing system includes a device, the device including: a non-volatile memory divided into a plurality of selectable locations, each bit in the non-volatile memory configured to have corresponding data independently altered, wherein the selectable locations are grouped into a plurality of data lines; and one or more processing units coupled to the non-volatile memory, each of the processing units associated with a data line of the plurality of data lines, and each of the processing units configured to compute, based on data in an associated data line of the plurality of data lines, corresponding results, wherein the non-volatile memory is configured to selectively write, based on the corresponding results, data in selectable locations of the associated data line reserved to store results of the computation from the process unit associated with the associated data line. | 2021-03-18 |
20210082521 | LOW NOISE BIT LINE CIRCUITS - The disclosed technology teaches a memory device with memory cells, each with a sense circuit with an input node in current flow communication, a BLC transistor, a transfer transistor, a current source transistor, and an output circuit to generate data based on a voltage on the sensing node. Also disclosed is a sensing sequence in which control circuits apply BLC voltage to the BLC transistor, transfer voltage to the transfer transistor and current control voltage to the current source transistor to provide a charging current to the BL, and to adjust the current control voltage to provide a keeping current on the BL from the current source transistor, and to apply a read voltage to a selected memory cell on the bit line. Additionally included is applying a timing signal to the output circuit to generate the data based on a voltage on the sensing node. | 2021-03-18 |
20210082522 | VOLTAGE IDENTIFYING METHOD, MEMORY CONTROLLING CIRCUIT UNIT AND MEMORY STORAGE DEVICE - A voltage identifying method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a plurality of first memory cells according to a first read voltage group in a plurality of read voltage groups and performing a first decoding operation to generate first verification information; identifying a plurality of second read voltage groups in the plurality of read voltage groups corresponding to a first interval in a plurality of intervals according to the first interval in which the first verification information is located; and reading the plurality of first memory cells by using a third read voltage group in the plurality of second read voltage groups and performing the first decoding operation. | 2021-03-18 |
20210082523 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line. | 2021-03-18 |
20210082524 | MEMORY SYSTEM - A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors. | 2021-03-18 |
20210082525 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - A semiconductor device includes pads for inputting and outputting data, a plurality of control circuit groups connected to the pads, a first supply line for supplying a first electric potential to the control circuit groups, and a second supply line for supplying a second electric potential lower than the first electric potential to the control circuit groups. At least one of the first electric potential supply line or the second supply line is provided with a blocking region such that the blocking region prevents supply of the first electric potential, and the first electric potential is supplied to the plurality of control circuit groups from the first supply line divided by the blocking region, or the blocking region prevents supply of the second electric potential, and the second electric potential is supplied to the plurality of control circuit groups from the second supply line divided by the blocking region. | 2021-03-18 |
20210082526 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes first and second memory cell transistors between first and second select transistors, third and fourth memory cell transistors between third and fourth select transistors, a first word line for first and third memory cell transistors, a second word line for second and fourth memory cell transistors, first to fourth selection gate lines respectively for first through fourth select transistors, a bit line, and a source line. During a read operation, while a voltage applied to the second word line is boosted, voltages applied to the first word line and the third and fourth selection gate line are also boosted, after which the voltage applied to the first word line is lowered, and the third and fourth selection gate lines are discharged. After the time the third and fourth selection gate lines are discharged, voltages applied to the bit line and the source line are boosted. | 2021-03-18 |
20210082527 | MEMORIES HAVING MULTIPLE VOLTAGE GENERATION SYSTEMS CONNECTED TO A VOLTAGE REGULATOR - Memories having an array of memory cells might include a plurality of voltage generation systems each having a respective output selectively connected to a respective access line, and a voltage regulator having an input connected to the output of each of the voltage generation systems, and having an output selectively connected to the respective access line for each of the voltage generation systems. | 2021-03-18 |
20210082528 | MEMORY SYSTEM AND METHOD - According to one embodiment, a memory system includes a first memory and a memory controller. The first memory is nonvolatile and includes a plurality of memory cell transistors, each of which stores data corresponding to a threshold voltage. The memory controller causes the first memory to execute a read operation to acquire data corresponding to the threshold voltage from the plurality of memory cell transistors on the basis of a result of comparison between the threshold voltage and a read voltage. The memory controller selects a first candidate value from among a plurality of candidate values for the read voltage in accordance with a degree of stress that affects the threshold voltage; and causes the first memory to execute the read operation using the first candidate value as the read voltage. | 2021-03-18 |
20210082529 | METHODS FOR DETECTING AND MITIGATING MEMORY MEDIA DEGRADATION AND MEMORY DEVICES EMPLOYING THE SAME - Memory devices, system, and methods for operating the same are provided. The memory device can comprise a non-volatile memory array and control circuitry. The control circuitry can be configured to store a value corresponding to a number of activate commands received at the memory device, update the value in response to receiving an activate command received from a host device, and trigger, in response to the value exceeding a predetermined threshold, a remedial action performed by the memory device. The control circuitry can be further configured to store a second value corresponding to a number of refresh operations performed by the memory device, update the second value in response to performing a refresh operation, and trigger, in response to the value exceeding a second predetermined threshold, a second remedial action performed by the memory device. | 2021-03-18 |
20210082530 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A method of operating a semiconductor memory device includes dummy-programming selected memory cells representing all the memory cells to be programmed for a programming operation. The method also includes determining as a first group of memory cells those selected memory cells having threshold voltages less than or equal to a reference threshold voltage and determining as a second group of memory cells those selected memory cells having threshold voltages greater than the reference threshold voltage. The method further includes program ling the selected memory cells by applying a first bit line voltage to the memory cells of the first group, applying a second bit line voltage different from the first bit line voltage to the memory cells of the second group, and applying a same program pulse to the memory cells of the first and second groups. | 2021-03-18 |
20210082531 | SEMICONDUCTOR MEMORY DEVICE AND MEMORY STATE DETECTING METHOD - According to a certain embodiment, the semiconductor memory device includes a memory cell array, a control circuit, and a data register storing an erase verify fail flag. An erase target block is divided into word line groups. The control circuit includes: a counter configured to count the number of the erase verify fail flags to be output as a count value for each group; a plurality of counter registers configured to store the count value for each group; an arithmetic circuit configured to take a difference of the plurality of count values respectively stored in the plurality of counter registers and to output a result of the difference as a number of second fail flags; and a comparator configured to compare the number of criteria of the erase verify fail flag and the number of the second fail flags to be output as a memory state detected result. | 2021-03-18 |
20210082532 | SENSING CIRCUITS FOR CHARGE TRAP TRANSISTORS - The present disclosure relates to a structure including a first delay path circuit which is configured to receive an input signal and is connected to a complement transistor of a twin cell transistor pair through a complement bitline signal, a second delay path circuit which is configured to receive the input signal and is connected to a true transistor of the twin cell transistor pair through a true bitline signal, and a logic circuit which is configured to receive a first output of the first delay path circuit and a second output of the second delay path circuit and output a data output signal. | 2021-03-18 |
20210082533 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a MOS transistor and a drive circuit. The MOS transistor has a gate and a gate insulating film. The drive circuit is coupled to the gate and supplies a first voltage that destroys the gate insulating film or a second voltage lower than the first voltage. The drive circuit applies the first voltage to the gate in a first write to the MOS transistor, and applies the second voltage to the gate in a second write to the MOS transistor. | 2021-03-18 |
20210082534 | METHODS FOR MEMORY INTERFACE CALIBRATION - Integrated circuits with memory interface circuitry may be provided. Prior to calibration, a number of samples may be determined by computing probability density function curves as a function of timing window edge asymmetry for different degrees of oversampling. During calibration, duty cycle distortion in data strobe signals may be corrected by selectively delaying the data strobe rising or falling edges. A data clock signal that is used for generating data signals may also suffer from duty cycle distortion. The rising and falling edges of the data clock signal may be selectively delayed to correct for duty cycle distortion. The data path through which the data signals are routed may be adjusted to equalize rising and falling transitions to minimize data path duty cycle distortion. Multi-rank calibration may be performed by calibrating to an intersection of successful settings that allow each memory rank to pass memory operation tests. | 2021-03-18 |
20210082535 | VARIABLE ERROR CORRECTION CODEWORD PACKING TO SUPPORT BIT ERROR RATE TARGETS - Systems, apparatuses and methods may provide for technology that programs a first plurality of error correction codewords to a first set of pages in a block of non-volatile memory, wherein the first plurality of error correction codewords are programmed at a first density. The technology may also program a second plurality of error correction codewords to a second set of pages in the block, wherein the second plurality of error correction codewords are programmed at a second density. In one example, the first density and the second density are different from one another. | 2021-03-18 |
20210082536 | SEMICONDUCTOR MEMORY DEVICE AND STORAGE DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell array, a processing circuit, a timer, a command decoder, and a training circuit. The memory cell array includes a plurality of memory cells. The processing circuit writes data into the memory cell array. The timer sets a waiting time. The command decoder receives a command output from a memory controller. The training circuit waits until the waiting time has passed since a predetermined command is received by the command decoder and performs a process relating to determination of a correction value for a signal sent from the memory controller to the processing circuit based on reference data output from the memory controller after the waiting time has passed. | 2021-03-18 |
20210082537 | SELECTIVE PEPTIDE ANTAGONISTS - Methods and compositions related to the selective, specific disruption of multiple ligand-receptor signaling interactions, such as ligand-receptor interactions implicated in disease, are disclosed. These interactions may involve multiple cytokines in a single receptor family or multiple ligand receptor interactions from at least two distinct ligand-receptor families. The compositions may comprise polypeptides having composite sequences that comprise sequence fragments of two or more ligand binding sites. The methods and compositions may involve sequence fragments of two or more ligand binding sites that are arranged to conserve the secondary structure of each of the ligands from which the sequence fragments were taken. | 2021-03-18 |
20210082538 | NORMALIZING CHROMOSOMES FOR THE DETERMINATION AND VERIFICATION OF COMMON AND RARE CHROMOSOMAL ANEUPLOIDIES - The present invention provides a method capable of detecting single or multiple fetal chromosomal aneuploidies in a maternal sample comprising fetal and maternal nucleic acids, and verifying that the correct determination has been made. The method is applicable to determining copy number variations (CNV) of any sequence of interest in samples comprising mixtures of genomic nucleic acids derived from two different genomes, and which are known or are suspected to differ in the amount of one or more sequence of interest. The method is applicable at least to the practice of noninvasive prenatal diagnostics, and to the diagnosis and monitoring of conditions associated with a difference in sequence representation in healthy versus diseased individuals. | 2021-03-18 |
20210082539 | GENE MUTATION IDENTIFICATION METHOD AND APPARATUS, AND STORAGE MEDIUM - The present disclosure relates to a gene mutation identification method and apparatus, and a storage medium. The method includes: obtaining at least one gene sequencing read segment corresponding to a gene mutation candidate site; determining a sequence feature and a non-sequence feature of the gene mutation candidate site according to attribute information of the at least one gene sequencing read segment, where the sequence feature is a feature related to the position of the site; and identifying gene mutation of the gene mutation candidate site based on the sequence feature and the non-sequence feature. According to embodiments of the present disclosure, the sequence feature and the non-sequence feature of the gene can be combined, thereby more comprehensively analyzing the features of a gene mutation site and improving accuracy of gene mutation identification. | 2021-03-18 |
20210082540 | SYSTEMS AND METHODS FOR ASSESSING COLORECTAL CANCER MOLECULAR SUBTYPE AND RISK OF RECURRENCE AND FOR DETERMINING AND ADMINISTERING TREATMENT PROTOCOLS BASED THEREON - Products, systems, and methods for classifying human colorectal cancer into a consensus molecular subtype (CMS) and for assessing risk of recurrence based on CMS scores and based on risk scores derived from abbreviated gene expression profiles, for determining suitable treatment protocols for human colorectal cancer patients based on the determined CMS classification and based on the determined risk of recurrence, and for administering the suitable treatment protocols. | 2021-03-18 |
20210082541 | MEASURING ATTRIBUTES OF A VIRAL GENE DELIVERY VEHICLE SAMPLE VIA SEPARATION - The present disclosure describes an apparatus, method, and system of measuring attributes of a viral gene delivery vehicle sample via separation. In an embodiment, the method, system, and computer program product include executing a set of logical operations analyzing a viral gene delivery vehicle sample on a set of analytical instruments, where the set includes at least one separation instrument, at least one static light scattering instrument, and at least two concentration detectors, resulting in a capsid protein mass of the sample, m | 2021-03-18 |
20210082542 | SYSTEM AND METHOD FOR CREATING LEAD COMPOUNDS, AND COMPOSITIONS THEREOF - A method is provided to create lead compound(s) by discovering a general chemical structure, moieties, formula(s) to explore suitable compositions by computer simulation and/or robotic biological or biochemical experiments at least partially based upon employing said lead compound(s) discover method, which includes steps for inputting at least one chemical formula and at least one byproduct formula, steps for creating a list of dipeptides that might dissociate the byproduct from the input formula by way of catalysis, steps for using these dipeptides to fingerprint a protein from its peptide sequence, and searching a protein database or use experimental methods to search for such proteins. A composition creating means is provide by way of computer simulation and/or robotic biological or biochemical experiments at least partially based upon employing, as lead compound(s), the final chemical structure, moieties, formula(s) generated and communicated the above method. | 2021-03-18 |
20210082543 | Method for establishing chart for designing mechanical properties of cement stones in large-scale fracturing oil well - A method for establishing a chart for designing mechanical properties of cement stones in a large-scale fracturing oil well is provided, including steps of: establishing a stress distribution model of a cement sheath based on a theory of elasticity and thick-walled cylinder; establishing a cement sheath integrity prediction model based on the cement sheath failure criterion and the stress increment distribution state of the cement sheath; establishing a cement sheath integrity control method based on the cement sheath stress analysis model and the cement sheath integrity prediction model; establishing a functional relationship between cement stone mechanical parameters and strength parameters based on the cement sheath integrity control method; and establishing a cement stone performance index control chart based on the functional relationship between the cement stone mechanical parameters and strength parameters. | 2021-03-18 |
20210082544 | MAVIN ANALYSIS AND REPORTING SYSTEMS AND METHODS FOR SCALING AND RESPONSE INSIGHTS IN SURVEY RESEARCH - The Mavin systems and computer-implemented processes of the invention analyze, score, and report the results from Likert scale survey questions. The systems and methods address three weaknesses in traditional Likert scale analyses by providing: (1) a scoring procedure that is sensitive to all levels of response; (2) a determination and designation of a standard score used to determine whether the results meet that standard; and (3) a scoring process used to determine the degree to which a given score exceeds or fails to meet this standard. In addition, the Mavin systems and methods support recalculation and adjustment to the scoring model when available data support such adjustments. | 2021-03-18 |
20210082545 | MEDICAL EVALUATION SYSTEM AND METHOD FOR USE THEREWITH - A medical evaluation system operates by: receiving a set of medical scans of a medical scan protocol captured for a patient, the set of medical scans corresponding to a proper subset of a plurality of sequence types; generating abnormality data by performing an inference function on the set of medical scans, wherein the inference function utilizes a computer vision model trained on a plurality of medical scans corresponding to the proper subset of the plurality of sequence types; calculating a confidence score for the abnormality data; generating first additional sequence data, wherein when the confidence score compares unfavorably to a confidence score threshold, the first additional sequence data indicates at least one first additional medical scan of the patient, corresponding to a first at least one of the plurality of sequence types not included in the proper subset of the plurality of sequence types, and when the confidence score compares favorably to the confidence score threshold, the first additional sequence data indicates no further medical scans of the patient; and transmitting the first additional sequence data. | 2021-03-18 |
20210082546 | METHOD AND DEVICE FOR EXCHANGING INFORMATION REGARDING THE CLINICAL IMPLICATIONS OF GENOMIC VARIATIONS - A method and a device are for exchanging information regarding the clinical implications genomic variations. In an embodiment, the method includes receiving login-data of a user; evaluating the login-data received; establishing an encrypted data connection to the user after the evaluating indicates a positive evaluation of the login-data; saving, upon receiving a dataset in a context of a genomic variation, the dataset received in a memory, context-related with the genomic variation; and evaluating, upon a user request being received and connected with a search query for the genomic variation, a set of datasets from the memory, the datasets being context-related with the genomic variation and the set including the datasets that the user is authorized to receive, and sending the set of datasets to the user. | 2021-03-18 |
20210082547 | HEAT MAP GENERATING SYSTEM AND METHODS FOR USE THEREWITH - A multi-label heat map generating system is operable to receive a plurality of medical scans and a corresponding plurality of global labels that each correspond to one of a set of abnormality classes. A computer vision model is generated by training on the medical scans and the global labels. Probability matrix data, which includes a set of image patch probability values that each indicate a probability that a corresponding one of the set of abnormality classes is present in each of a set of image patches, is generated by performing an inference function that utilizes the computer vision model on a new medical scan. Heat map visualization data can be generated for transmission to a client device based on the probability matrix data that indicates, for each of the set of abnormality classes, a color value for each pixel of the new medical scan. | 2021-03-18 |
20210082548 | HEALTH PLATFORM - A computer-implemented healthcare management platform includes a device-agnostic data collection engine that collects healthcare data from users and a cryptocurrency engine that allows the users to share their healthcare data with others in exchange for tokens and/or health insights. | 2021-03-18 |
20210082549 | GATHERING INFORMATION FROM A HEALTHCARE CONSUMER USING CONTEXT-BASED QUESTIONS, AND PROGRESSIVELY PRESENTING INFORMATION ASSOCIATED WITH A RANKED LIST OF SUGGESTED HEALTHCARE PROVIDERS - A computer-implemented method includes displaying a number of questions on a stack of overlapping graphical objects that dynamically indicates a status of the number of remaining questions, determining an output based on answers input by a user, and displaying an indication of the output. | 2021-03-18 |
20210082550 | METHODS AND SYSTEMS FOR ANALYZING ACCESSING OF MEDICAL DATA - Various aspects described herein relate to presenting electronic patient data accessing information. Data related to a plurality of access events, by one or more employees, of electronic patient data can be received. A set of access events of the plurality of access events can be determined as constituting, by the one or more employees, possible breach of the electronic patient data. An alert related to the set of access events can be provided based on determining that the set of access events constitute possible breach of the electronic patient data. | 2021-03-18 |
20210082551 | METHOD AND APPARATUS FOR PROVIDING REAL-TIME PERIODIC HEALTH UPDATES - Various embodiments enable generation of a detailed health report for a patient based at least in part on patient data collected and/or generated at a wearable client device. The patient data may be generated by one or more sensors onboard and/or in communication with the wearable client device. The patient data is provided to a centralized monitoring system, which analyzes the patient data in accordance with user input provided by one or more healthcare providers having access to anonymized versions of the patient data. The monitoring system then generates the detailed health report based at least in part on the results of the analysis performed on the patient data. | 2021-03-18 |
20210082552 | SYSTEMS AND METHODS FOR PREDICTING SKIN TREATMENT OUTCOMES USING SKIN PH INFORMATION - An electronic sensor for pH measurement may be used (e.g. an ISFET sensor, a glass electrode sensor, an antimony electrode sensor) to collect skin pH information from a subject. An application is provided on a computing device that detects and analyzes the pH measurements reported by the electronic sensor to determine skin pH values for analysis. Based on the determined skin pH values and questionnaire responses, the application may recommend a skin regimen/treatment to restore skin function. The application may also provide visualizations of predicted effects of the skin regimen on a skin condition of the subject. | 2021-03-18 |
20210082553 | A TOOL AND SYSTEM FOR GENERATION AND USE OF PERSONALIZED, INTERACTIVE LABORATORY REPORTS USING REAL-TIME REPORT - A system and method for generating real-time cumulative personalized health screening report that provides more specific reporting pattern taking into account of interplay at the cellular/tissue and organ level. Further, the system and method for health screening and diagnosis is based on the outcomes in the present report, past diagnostic test readings and overall health condition besides trying to map with similar looking/matched population. | 2021-03-18 |
20210082554 | PROVIDING LIVE FIRST AID RESPONSE GUIDANCE USING A MACHINE LEARNING BASED COGNITIVE AID PLANNER - Techniques are described for providing live first aid response guidance using a machine learning based cognitive aid planner. In one embodiment, a computer-implemented method is provided that comprises classifying, by a system operatively coupled to a processor, a type of an injury endured by a patient. The method further comprises, employing, by the system, one or more machine learning models to estimate a risk level associated with the injury based on the type of the injury and a current context of the patient. | 2021-03-18 |
20210082555 | Programmed Computer with Smart Goal Setting for Depression Management - A depression scoring system obtains data from a large population of individuals including data about each of a plurality of different activities in relevant categories, and information about each of the individuals. Cohorts of individuals are defined as individuals who have similar statistical characteristics such as similar age, socioeconomic status, and sex. For each of the cohorts, a distribution of the data is obtained, and the scores of the top n %, e.g., 25% is set as a goal for the remaining members of the cohort. These goals are incrementally set and personalized for individual users to easily meet. This process is repeated constantly. | 2021-03-18 |
20210082556 | AUTOMATIC PET MEDICINE SYSTEM AND METHOD - A system includes a memory and at least one processor to receive a photograph of a pet and store the photograph of the pet in a database, automatically determine at least one pet medicine subscription that is ready to ship based on an estimated delivery date by iterating over a list of pet medicine subscriptions, begin processing an automatic shipment associated with the at least one pet medicine subscription and retrieve shipment data associated with the at least one pet medicine subscription from the database, transmit the shipment data associated with the at least one pet medicine subscription to a server computing device, receive a shipment label from the server computing device, the shipment label associated with the shipment, and generate a personalized pet label for the at least one pet medicine subscription, the personalized pet label having the photograph of the pet. | 2021-03-18 |
20210082557 | PHARMACY/HEALTHCARE INFORMATION SYSTEM CARE PROVIDER, ORDER AND SERVICE MANAGEMENT SYSTEM - This disclosure relates generally to a system and method for the optimized management of pharmacy workflow, specifically, workflow associated with fulfilment of prescription orders for medications and health-related products in a pharmacy environment. A computer-controlled system coordinates and controls pharmacy workflow to sequence prescriptions for fulfilment in a most efficient path thereby minimizing a cost function associated with fulfilment of the prescription order. The system coordinates and controls prescription order fulfilment from automated and non-automated storage locations and can be easily adapted to the specific layout and level of automation desired by the operator. A smartphone, a laptop computer, a portable communicating device, a cloud computing device, or a data storage device is capable of communicating with the computer. Pharmaceutical care management system-connects care providers (in a hierarchical manner based on care-decision authority level), pharmacy team and delivery teams for quick, clear, and efficient communication and feedback/follow up features. Reduces errors of, unawareness about and time & effort for seeking pharmaceutical care. In order words, it makes a care-need assessment, order placement, fulfilment and status tracking a breeze. | 2021-03-18 |
20210082558 | MEDICATION MANAGEMENT DEVICE, MEDICATION MANAGEMENT METHOD, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM STORING MEDICATION MANAGEMENT PROGRAM - A medication management device includes an acquisition unit configured to acquire biological information, dosing information, and side effect information related to a managed subject in one or more unit diagnosis periods, and a side effect management unit configured to generate, on the basis of the biological information, the dosing information, and the side effect information thus acquired, management screen data configured to display the biological information, the dosing information, and the side effect information thus acquired in a chart in association with each other for each of the one or more unit diagnosis periods. | 2021-03-18 |
20210082559 | METHODS AND SYSTEMS FOR ANALYZING ACCESSING OF DRUG DISPENSING SYSTEMS - Various aspects described herein relate to presenting drug dispensing information. Data related to a plurality of dispensing events initiated by one or more employees, of an electronic drug dispensing system can be received. A set of dispensing events of the plurality of dispensing events can be determined as constituting possible misappropriation of drugs by the one or more employees. An alert related to the set of dispensing events can be provided based on determining that the set of dispensing events constitute possible misappropriation of drugs. | 2021-03-18 |
20210082560 | AUTOMATIC SAFETY ADJUSTMENT SYSTEM - A method may include presenting, on a display of an infusion device, a first patient parameter and a second patient parameter. The infusion device may receive a first entry, which may include a first value of the first patient parameter. The infusion device may determine a default value of the second patient parameter based on the entered first value of the first patient parameter. The infusion device may present the determined default value of the second patient parameter. The infusion device may receive a second entry, which includes a second value of the second patient parameter. The second value may be an adjustment of the default value of the second patient parameter that is an accurate representation of the second patient parameter. Related methods and articles of manufacture, including apparatuses and computer program products, are also disclosed. | 2021-03-18 |
20210082561 | METHOD AND SYSTEM FOR AUTOMATICALLY GENERATING A RADIOLOGY IMPRESSION | 2021-03-18 |
20210082562 | DENTAL LASER INTERFACE SYSTEM AND METHOD - Embodiments of the invention provide a system of controlling a dental laser system. The system can include a dental laser and a control system for controlling certain functions of the dental laser. A graphical user interface can be used to provide input to the control system. The graphical user interface can include a first display and an second display with selectable segments, and a menu navigation portion located adjacent the second display. Treatment categories, procedures or laser control options can be selected using the interface, and the interface can be updated based on data from the station. | 2021-03-18 |
20210082563 | METHODS FOR IMPROVING PSYCHOLOGICAL THERAPY OUTCOME - A method of determining the effectiveness of a therapist, comprising: obtaining data relating to one or more patient variables and/or one or more service variables for one or more patient suffering from a mental health disorder and allocated to the therapist; attributing a score to the data for each of the patient variables and/or the service variables, wherein the scores are based on a correlation between historic cohort treatment outcomes and historic cohort data comprising cohort patient and/or service variables; combining the scores to calculate an aggregate score; comparing the aggregate score with a scale to produce a prediction of psychological therapy outcome for the one or more patient; obtaining an observation of psychological therapy outcome for the one or more patient after treatment by the therapist has been provided; and comparing the observation of psychological therapy outcome and the prediction of psychological therapy outcome for the one or more patient to make a determination of the effectiveness of the therapist. | 2021-03-18 |
20210082564 | ACTIVITY ASSISTANCE SYSTEM - An activity assistance system includes a video camera arranged to acquire video of a person performing an activity, an output device configured to output human-perceptible prompts, and an electronic processor programmed to execute an activity script. The script comprises a sequence of steps choreographing the activity. The execution of each step includes presenting a prompt via the output device and detecting an event or sequence of events subsequent to the presenting of the prompt. Each event is detected by performing object detection on the video to detect one or more objects depicted in the video and applying one or more object-oriented image analysis functions to detect a spatial or temporal arrangement of one or more of the detected objects. Each event detection triggers an action comprising at least one of presenting a prompt via the output device and and/or going to another step of the activity script. | 2021-03-18 |
20210082565 | METHOD AND SYSTEM FOR PREDICTING NEUROLOGICAL TREATMENT - A computer-implemented method for predicting neurological treatment for a patient. The method includes analyzing a pre-stored brain image of the patient by means of a Convolutional Neural Network to determine brain image analysis result including at least one of: a presence of a tumor or lesion, brain age, brain health, gyrification coefficient; receiving additional data, including at least one of: voice recognition index, additional symptom checks, blood work results, genetic sequencing results; and combining the brain image analysis result with the additional data to determine a score related to a probability that the patient may have a particular disease. | 2021-03-18 |