11th week of 2021 patent applcation highlights part 64 |
Patent application number | Title | Published |
20210082866 | DOUBLE ETCH STOP LAYER TO PROTECT SEMICONDUCTOR DEVICE LAYERS FROM WET CHEMICAL ETCH - In some embodiments, the present disclosure relates to a method of forming a package assembly. A wet etch stop layer is formed over a frontside of a semiconductor substrate. A sacrificial semiconductor layer is formed over the wet etch stop layer, and a dry etch stop layer is formed over the sacrificial semiconductor layer. A stack of semiconductor device layers may be formed over the dry etch stop layer. A bonding process is performed to bond the stack of semiconductor device layers to a frontside of an integrated circuit die, wherein the frontside of the semiconductor substrate faces the frontside of the integrated circuit die. A wet etching process is performed to remove the semiconductor substrate, and a dry etching process is performed to remove the wet etch stop layer and the sacrificial semiconductor layer. | 2021-03-18 |
20210082867 | SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, in a semiconductor manufacturing apparatus, a controller relatively moves a bonding tool and a stage close to each other while causing a semiconductor chip to adhere by suction to a surface via a tape using at least a first suction structure in a first period. In a second period, the controller controls the temperature of the bonding tool to a first target temperature while keeping substantially equal to a target pressure a pressure applied to the semiconductor chip by the bonding tool. In a third period, the controller controls a relative distance between the bonding tool and the stage so that the pressure applied to the semiconductor chip by the bonding tool is kept equal to the target pressure and controls the temperature of the bonding tool to a second target temperature. The second target temperature is higher than the first target temperature. | 2021-03-18 |
20210082868 | METHOD OF JOINING A SURFACE-MOUNT COMPONENT TO A SUBSTRATE WITH SOLDER THAT HAS BEEN TEMPORARILY SECURED - A method of joining a surface-mount component to a substrate includes placing a piece of solder on top of the substrate and temporarily bonding the piece of solder to the substrate with at least one temporary bond. The method also includes placing a surface-mount component on top of the substrate with a bottom face of the surface-mount component facing the substrate. The surface-mount component has at least one lateral side. The method further includes positioning the surface-mount component with the at least one lateral side proximate the piece of solder, heating the substrate and the piece of solder to a joining temperature for a time sufficient for the solder to flow into an area between the bottom face of the surface-mount component and the substrate, and cooling the substrate and solder. | 2021-03-18 |
20210082869 | WAFER-LEVEL PACKAGE STRUCTURE - Wafer-level packaging structure is provided. First chips are bonded to the device wafer. A first encapsulation layer is formed on the device wafer, covering the first chips. The first chip includes: a chip front surface with a formed first pad, facing the device wafer; and a chip back surface opposite to the chip front surface. A first opening is formed in the first encapsulation layer to expose at least one first chip having an exposed chip back surface for receiving a loading signal. A metal layer structure is formed covering the at least one first chip, a bottom and sidewalls of the first opening, and the first encapsulation layer, followed by an alloying treatment on the chip back surface and the metal layer structure to form a back metal layer on the chip back surface. | 2021-03-18 |
20210082870 | SHIFT CONTROL METHOD IN MANUFACTURE OF SEMICONDUCTOR DEVICE - A shift control method in manufacture of semiconductor device includes at least the following step. An overlay offset of a first target of a semiconductor die and a second target of the semiconductor die is determined, where the second target is disposed on the first target. The semiconductor die is placed over a carrier, where placing the semiconductor die includes feeding back the overlay offset to result in a positional control of the semiconductor die. The semiconductor die is post processed to form a semiconductor device. Other shift control methods in manufacture of semiconductor device are also provided. | 2021-03-18 |
20210082871 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING - Integrated fan-out devices, wafer level packages, and methods of manufacturing the same are described herein. Die-attach pads and leveling film are used to attach a plurality of heterogeneous semiconductor dies to a substrate to align external contacts of the semiconductor dies at a first level. The leveling film may also be used during deposition of an encapsulant to at least partially fill a gap between the semiconductor dies. Once the leveling film is removed, a protection layer is formed over the semiconductor dies and within a recess of the encapsulant left behind by the leveling film during encapsulation. A redistribution layer and external connectors are formed over the protection layer to form the InFO device and an interposer may be attached to the redistribution layer to form the wafer level package. | 2021-03-18 |
20210082872 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a package substrate, a logic chip on an upper surface of the package substrate and electrically connected to the package substrate, a heat sink contacting an upper surface of the logic chip to dissipate a heat generating from the logic chip, and a memory chip disposed on an upper surface of the heat sink and electrically connected to the package substrate. | 2021-03-18 |
20210082873 | BACKSIDE CONTACT FOR THERMAL DISPLACEMENT IN A MULTI-WAFER STACKED INTEGRATED CIRCUIT - In some embodiments, the present disclosure relates to a three dimensional (3D) integrated circuit (IC) stack, including a first IC die having a first substrate and a first interconnect structure over a frontside of the first substrate; a second IC die having a second substrate and a second interconnect structure over the frontside of the second substrate; and a third IC die vertically between the first and second IC dies and having a third substrate, a third interconnect structure over the frontside of the third substrate, and a third bonding structure over a backside of the third substrate. A heat dissipation path extends from the third substrate to at least the first or second substrate, and includes a backside contact that extends from the third bonding structure to the backside of the third substrate and that is thermally coupled to at least the first or second interconnect structure. | 2021-03-18 |
20210082874 | PACKAGE AND MANUFACTURING METHOD OF RECONSTRUCTED WAFER - A package includes a carrier substrate, a first die, and a second die. The first die includes a first bonding layer, a second bonding layer opposite to the first bonding layer, and an alignment mark embedded in the first bonding layer. The first bonding layer is fusion bonded to the carrier substrate. The second die includes a third bonding layer. The third bonding layer is hybrid bonded to the second bonding layer of the first die. | 2021-03-18 |
20210082875 | DYNAMICALLY CONFIGURABLE MULTI-CHIP PACKAGE - A semiconductor die includes one or more semiconductor devices (e.g., memory array, processors), first and second banks of I/O ports arranged along one or more sides of the die, and a multiplexing circuit. The multiplexing circuit can be changed between a first state and a second state. In the first state the first bank of I/O ports is coupled to the semiconductor device(s) and the second bank of I/O ports is not coupled to the semiconductor device(s), and in the second state the first bank of I/O ports is not coupled to the semiconductor device(s) and the second bank of I/O ports is coupled to the semiconductor device(s). The state of the multiplexing circuit can be set, for example, by an on-die fuse circuit or an externally accessible select line. The semiconductor die can be included in a chip package, which can be included on a printed circuit board. | 2021-03-18 |
20210082876 | ELECTRIC DEVICE WITH TWO OR MORE CHIP COMPONENTS - An electric device comprises a substrate (SU) as a carrier and at least two chip components mounted thereto. In the top surface of the substrate a recess (RC) is formed. One or more chip component (BC) is mounted to the bottom surface of the recess referred to as buried chip component. One or more top chip component (TC) is mounted to the top surface of the substrate to cover at least to some extend the recess and the buried chip component. Device pads (PD) are arranged on the bottom surface of the substrate. Each of them is electrically interconnected with one or both of the chip components. | 2021-03-18 |
20210082877 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a substrate, a logic circuit provided on the substrate, and a memory cell array provided over the logic circuit that includes a plurality of electrode layers stacked on top of one another and a semiconductor layer provided over the plurality of electrode layers. The semiconductor device further includes a first plug and a second plug provided above the logic circuit and electrically connected to the logic circuit, a bonding pad provided on the first plug, and a metallic wiring layer provided on the memory cell array, electrically connected to the semiconductor layer, and electrically connected to the second plug. | 2021-03-18 |
20210082878 | SEMICONDUCTOR DEVICE - A semiconductor device in an embodiment includes a first chip on a substrate and a second chip adhered to a first region of the first chip using a first adhesive layer. The second chip is positioned so a second region of the first semiconductor is not overlapped. The first adhesive layer covers a lower surface of the second chip but not the second region. A third chip is adhered to a third region of the second chip with a second adhesive layer. The third chip is positioned so a fourth region of the second chip is not overlapped. The second adhesive layer covers a lower surface of the third chip but not the fourth region. An end of the second adhesive layer is above the second region, but not contacting. A coating covers the fourth region and the ends of the second adhesive layer and third chip. | 2021-03-18 |
20210082879 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell, a first voltage generator and a second voltage generator. The memory cell is provided above a substrate. The first voltage generator is provided between the substrate and the memory cell. The first voltage generator is configured to generate a first voltage to be supplied to the memory cell. The second voltage generator is provided between the substrate and the memory cell. The second voltage generator is configured to generate the first voltage and have a circuit configuration equivalent to the first voltage generator. | 2021-03-18 |
20210082880 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a substrate, a plurality of transistors provided on the substrate. The device further includes a first interconnect layer provided above the transistors and electrically connected to at least one of the transistors, one or more first plugs provided on the first interconnect layer, and a first pad provided on the first plugs. The device further includes a second pad provided on the first pad, one or more second plugs provided on the second pad, and a second interconnect layer provided on the second plugs. The device further includes a memory cell array provided above the second interconnect layer and electrically connected to the second interconnect layer. A number of the second plugs on the second pad is larger than a number of the first plugs under the first pad. | 2021-03-18 |
20210082881 | SEMICONDUCTOR PACKAGE - A semiconductor package including a substrate; a semiconductor stack on the substrate; an underfill between the substrate and the semiconductor stack; an insulating layer conformally covering surfaces of the semiconductor stack and the underfill; a chimney on the semiconductor stack; and a molding member surrounding side surfaces of the chimney, wherein the semiconductor stack has a first upper surface that is a first distance from the substrate and a second upper surface that is a second distance from the substrate, the first distance being greater than the second distance, wherein the chimney includes a thermally conductive filler on the first and second upper surfaces of the semiconductor stack, the thermally conductive filler having a flat upper surface; a thermally conductive spacer on the thermally conductive filler; and a protective layer on the thermally conductive spacer, and wherein an upper surface of the thermally conductive spacer is exposed. | 2021-03-18 |
20210082882 | SEMICONDUCTOR PACKAGE STRUCTURE - The present disclosure provides a semiconductor package, including a substrate, a semiconductor die, and a conductive bump. The substrate has a first surface and a second surface opposite to the first surface. The substrate further includes a conductive line surrounded by a dielectric, and a conductive via connected to the conductive line and protruding from the dielectric at the second surface. The semiconductor die is connected to the first surface of the substrate. The conductive bump is connected to the conductive via at the second surface. | 2021-03-18 |
20210082883 | BACKLIGHT MODULE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - The present disclosure provides a backlight module, a manufacturing method thereof, and a display device. The backlight module including a substrate, a plurality of LED chips disposed on the substrate, a plurality of encapsulation units encapsulating the LED chips in a one-to-one correspondence; each of the encapsulation units includes at least two encapsulation layers, an innermost one of the encapsulation layers completely covers the LED chip, and a refractive index of an encapsulation layer far from the LED chip is less than a refractive index of an encapsulation layer near the LED chip. | 2021-03-18 |
20210082884 | DISPLAY ELEMENT, DISPLAY DEVICE AND METHOD FOR PRODUCING A CONTACT STRUCTURE IN A PLURALITY OF DISPLAY ELEMENTS - A display element for a video wall having a plurality of light-emitting components on a carrier, which has a front side, a rear side and an edge side running between the front and rear sides. The circuit structures are arranged on the front side and the rear side and are electrically conductively connected to one another via a contact structure arranged on the edge side. The edge side is embodied in a scored, broken, ground, polished, melted, sawn, chamfered, rounded or notched way. | 2021-03-18 |
20210082885 | METHOD OF MANUFACTURING LIGHT-EMITTING MODULE - A method of manufacturing a light-emitting module that includes providing a light-transmissive member joined body that includes a plurality of submounts, a plurality of light-emitting elements each of which is disposed on a respective one of submounts, and a single light-transmissive member disposed on the light-emitting elements. The method further includes disposing the light-transmissive member joined body on a module board such that the submounts face the module board, forming a plurality of element structures by dividing the single light-transmissive member for each light-emitting element into the element structures each of which includes the submount, the light-emitting element, and the light-transmissive member positioned in this order, and forming a first covering member on the module board to cover lateral surfaces of the element structures. | 2021-03-18 |
20210082886 | -LED, -LED DEVICE, DISPLAY AND METHOD FOR THE SAME - The invention relates to various aspects of a μ-LED or a μ-LED array for augmented reality or lighting applications, in particular in the automotive field. The μ-LED is characterized by particularly small dimensions in the range of a few μm. | 2021-03-18 |
20210082887 | LIGHT EMITTING DEVICE FOR DISPLAY AND LIGHT EMITTING PACKAGE HAVING THE SAME - A light emitting device for a display including a first LED sub-unit, a second LED sub-unit disposed on the first LED sub-unit, and a third LED sub-unit disposed on the second LED sub-unit, in which the third LED sub-unit is configured to emit light having a shorter wavelength than that of light emitted from the first LED sub-unit, and to emit light having a longer wavelength than that of light emitted from the second LED sub-unit. | 2021-03-18 |
20210082888 | IPD Modules with Flexible Connection Scheme in Packaging - A package includes a first package and a second package over and bonded to the first package. The first package includes a first device die, and a first encapsulant encapsulating the first device die therein. The second package includes an Independent Passive Device (IPD) die, and a second encapsulant encapsulating the IPD die therein. The package further includes a power module over and bonded to the second package. | 2021-03-18 |
20210082889 | STACKED DIE MULTICHIP MODULE PACKAGE - A multichip module (MCM) power package includes a multilayer routable leadframe substrate (MRLF) substrate including a first and a second RLF layer. A multilayer extending via extends from the first into the second RLF layer. A first vertical FET has a side flipchip attached to a bottom side of the second RLF. A second vertical FET has a side flipchip attached to a bottom side of the second RLF layer, and contacts the multilayer extending via. A controller integrated circuit (IC) is flipchip attached a top side of the MRLF substrate at least partially over the first vertical FET. A top mold compound is on a top side of the MRLF substrate lateral to the controller IC that is lateral to a metal pad on the multilayer extending via. A bottom side of the first and second vertical FET are exposed by a bottom mold compound layer. | 2021-03-18 |
20210082890 | PASSIVE DEVICE MODULE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A semiconductor package including a lower redistribution layer including wiring patterns; a lower substrate on the lower redistribution layer, the lower substrate including a cavity; an application processor on the lower redistribution layer in the cavity; a cache memory chip on the application processor; a passive device module on the application processor; a plurality of first through-silicon vias penetrating the application processor to connect the lower redistribution layer to the passive device module; and lower bumps on a bottom surface of the lower redistribution layer, wherein the passive device module is adjacent to a side of the cache memory chip. | 2021-03-18 |
20210082891 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - An exemplary semiconductor device can comprise (a) a substrate comprising a substrate dielectric structure between the substrate top side and the substrate bottom side, conductive pads at the substrate bottom side, and a substrate cavity through the substrate dielectric structure, (b) a base electronic component comprising inner short bumps; outer short bumps bounding a perimeter around the inner short bumps, and tall bumps between the outer short bumps and an edge of the base component top side, and (c) a mounted electronic component coupled to the inner short bumps of the base electronic component. The tall bumps of the base component can be coupled to the conductive pads of the substrate. The mounted electronic component can be located in the substrate cavity. The substrate bottom side can cover at least a portion of the outer short bumps of the base electronic component. Other examples and related methods are disclosed herein. | 2021-03-18 |
20210082892 | DISPLAY DEVICE - A display device including a substrate, a plurality of pixels, a plurality of inorganic light-emitting elements, a flattening film, and an inorganic film. The pixels are arrayed on the substrate and display different colors. The inorganic light-emitting elements are provided to the respective pixels. The flattening film surrounds at least a side surface of the inorganic light-emitting element. The inorganic film covers the flattening film and the inorganic light-emitting element. The upper surface of the inorganic light-emitting element is exposed from the flattening film and is in contact with the inorganic film. Alternatively, the flattening film is provided covering the upper surface of the inorganic light-emitting element. | 2021-03-18 |
20210082893 | DISPLAY DEVICE AND ARRAY SUBSTRATE - A display device includes a substrate, a plurality of pixels arrayed on the substrate, an inorganic light-emitting element provided to each of the pixels, an anode electrode electrically coupled to the inorganic light-emitting element, a transistor provided on a first surface of the substrate, and coupling wiring that couples the anode electrode and the transistor. The anode electrode protrudes from an inside to an outside of the inorganic light-emitting element in planar view from a normal direction of the substrate. | 2021-03-18 |
20210082894 | PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation. | 2021-03-18 |
20210082895 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a semiconductor device, a substrate has a main surface. A first semiconductor chip has a first front surface and a first back surface, and is mounted on the main surface via a plurality of bump electrodes. A first spacer has a second front surface and a second back surface that is mounted on the main surface. A height of the second front surface from the main surface is within a range between a highest height and a lowest height of the first back surface from the main surface. A second spacer has a third front surface and a third back surface that is mounted on the main surface. A height of the third front surface from the main surface is within the range between the highest height and the lowest height of the first back surface from the main surface. | 2021-03-18 |
20210082896 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes first and second chips. The first chip includes memory cells provided on a first substrate in a memory cell region, a plurality of first pads provided on a first surface of the first substrate and disposed in an edge region of the first chip that surrounds the memory cell region, and a first conductive layer provided on the first substrate and electrically connected to the first pads. The second chip includes a first circuit provided on a second substrate in a circuit region, a plurality of second pads provided on the second substrate and disposed in an edge region of the second chip that surrounds the circuit region, and a second conductive layer provided on the second substrate and electrically connected to the second pads. The first pads of the first chip and the second pads of the second chip are bonded facing each other. | 2021-03-18 |
20210082897 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes first and second chips and first and second power supply electrodes. The first chip includes conductive layers arranged in a first direction, a semiconductor pillar extending in the first direction and facing the conductive layers, first contacts extending in the first direction and connected to the conductive layers, second contacts extending in the first direction and connected to a first power supply electrode, third contacts extending in the first direction, facing the second contacts in a direction crossing the first direction, and connected to the second power supply electrode, and first bonding electrodes connected to the first contacts. The second chip includes a semiconductor substrate, transistors provided on the semiconductor substrate, fourth contacts connected to the transistors, and second bonding electrodes connected to the fourth contacts. The first and second chips are bonded together so that respective first and second bonding electrodes are connected together. | 2021-03-18 |
20210082898 | SEMICONDUCTOR DEVICE - A semiconductor device, having a substrate including an insulating plate and a circuit board provided on a front surface of the insulating plate. The circuit board has a first disposition area and a second disposition area with a gap therebetween, and a groove portion, of which a longitudinal direction is parallel to the gap, formed in the gap. The semiconductor device further includes a first semiconductor chip and a second semiconductor chip located on the circuit board in the first disposition area and the second disposition area, respectively, and a blocking member located in the gap across the groove portion in parallel to the longitudinal direction in a plan view of the semiconductor device. | 2021-03-18 |
20210082899 | Discrete Three-Dimensional Processor - A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). The first die does not comprise the off-die peripheral-circuit component. The first and second dice are communicatively coupled by a plurality of inter-die connections. The preferred discrete 3-D processor can be applied to mathematical computing, computer simulation, configurable gate array, pattern processing and neural network. | 2021-03-18 |
20210082900 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to an embodiment, a method for manufacturing a semiconductor device includes forming a slit in a first wafer in which a first semiconductor layer is formed on a first substrate, sticking together the first wafer in which the slit is formed and a second wafer in which a second semiconductor layer is formed on a second substrate, the sticking being performed between a side of the first semiconductor layer and a side of the second semiconductor layer, thinning the first substrate or the second substrate of a member obtained by the sticking, forming an interconnection on a face of the substrate that is thinned, and dicing a member on which the interconnection is formed in accordance with a position of the slit. | 2021-03-18 |
20210082901 | METHOD FOR FABRICATION OF HIGH DENSITY LOGIC AND MEMORY FOR ADVANCED CIRCUIT ARCHITECTURE - Techniques herein include methods for fabricating high density logic and memory for advanced circuit architecture. The methods can include forming multilayer stacks on separate substrates and forming bonding films over the multilayer stacks, then contacting and bonding the bonding films to form a combined structure including each of the multilayer stacks. The method can be repeated to form additional combinations. In between iterations, transistor devices may be formed from the combined structures. Ionized atom implantation can facilitate cleavage of a substrate destined for growth of additional multilayers, wherein an anneal weakens the substrate at a predetermined penetration depth of the ionized atom implantation. | 2021-03-18 |
20210082902 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A capacitive element using VNW FETs is provided. First and second components each constituting a transistor are arranged in an X direction. From the first component, a first gate interconnect extends away from the second component, and a first top interconnect and a first bottom interconnect extend toward the second component. From the second component, a second gate interconnect extends toward the first component, and a second top interconnect and a second bottom interconnect extend away from the first component. The first top interconnect, the first bottom interconnect, and the second gate interconnect are connected. | 2021-03-18 |
20210082903 | SEMICONDUCTOR DEVICE INCLUDING SOURCE/DRAIN CONTACT HAVING HEIGHT BELOW GATE STACK - A method is disclosed, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, in which the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, in which the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region. | 2021-03-18 |
20210082904 | SEMICONDUCTOR DEVICE AND LAYOUT THEREOF - A semiconductor device includes a first fin, a first continuous fin and continuous gates. The first fin is formed on a substrate, and includes first and second portions that are spaced apart by a first recess. A side of the first portion and a side of the second portion are located at two sides of the first recess, respectively. The first continuous fin is formed on the substrate, and extends along the first portion, the first recess and the second portion. The continuous gates are formed on the substrate, and arranged to intersect the first continuous fin and the first fin in a layout view. A first number of the continuous gates are disposed across the first recess and each of the first number of the continuous gates is disposed between the two sides of the first recess in a layout view. A method is also disclosed herein. | 2021-03-18 |
20210082905 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An ESD protection device may include a substrate, a first conductivity region arranged at least partially within the substrate, a second conductivity region arranged at least partially within the first conductivity region, third and fourth conductivity regions arranged at least partially within the second conductivity region, and first and second terminal portions arranged at least partially within the third and fourth conductivity regions respectively. The third and fourth conductivity regions may be spaced apart from each other. The substrate and the second conductivity region may have a first conductivity type. The first conductivity region, third conductivity region, fourth conductivity region and first and second terminal portions may have a second conductivity type different from the first conductivity type. The first and second terminal portions may have higher doping concentrations than the third and fourth conductivity regions respectively. | 2021-03-18 |
20210082906 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal. | 2021-03-18 |
20210082907 | Electrostatic Discharge Device - An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells. | 2021-03-18 |
20210082908 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a circuit region formed on a semiconductor substrate, and a guard ring region spaced from one side of the circuit region by a predetermined distance. The guard ring region extends in a first direction, the first direction being a direction in which the one side of the circuit region extends, includes a guard ring line, an element isolation region, a first defect trapping layer, a second defect trapping layer. The first defect trapping layer extends from a boundary location between the circuit region and the element isolation region to a location spaced from a boundary location between the element isolation region and the guard ring line by an offset distance toward the element isolation region in the second direction. | 2021-03-18 |
20210082909 | SEMICONDUCTOR APPARATUS AND SYSTEM - A semiconductor system includes a control device, and a semiconductor apparatus coupled with the control device through a first line and a second line. A loading of the second line is greater than a loading of the first line, wherein the semiconductor apparatus includes a first receiving circuit which is electrically coupled with the first line and a second receiving circuit which is electrically coupled with the second line. Further a loading between the first line and the first receiving circuit is greater than a loading between the second line and the second receiving circuit. | 2021-03-18 |
20210082910 | 3D SEMICONDUCTOR DEVICE AND STRUCTURE - A 3D semiconductor device, the device comprising: a first level, wherein said first level comprises a first layer, said first layer comprising first transistors, and wherein said first level comprises a second layer comprising first interconnections; a second level overlaying said first level, wherein said second level comprises a third layer, said third layer comprising second transistors, and wherein said second level comprises a fourth layer comprising second interconnections; and a plurality of connection paths, wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors, wherein said second level is bonded to said first level, wherein said bonded comprises oxide to oxide bond regions and metal to metal bond regions, wherein said second level comprises at least one memory array, wherein said third layer comprises crystalline silicon, and wherein said second level comprises at least one SerDes circuit. | 2021-03-18 |
20210082911 | 3D SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A 3D semiconductor structure includes a buffer layer, a n-type high electron mobility transistor (HEMT) disposed on a first surface of the buffer layer, and a p-type high hole mobility transistor (HHMT) disposed on a second surface of the buffer layer opposite to the first surface. | 2021-03-18 |
20210082912 | SEMICONDUCTOR DEVICE - An active region has first and second cell regions respectively disposed in a main IGBT and a sensing IGBT. The second cell region has a detecting region in which the sensing IGBT is disposed and an extracting region that surrounds a periphery of the detecting region. A resistance region containing polysilicon and connected to the sensing IGBT is provided on the semiconductor substrate, in the extracting region. The resistance region connected to the sensing IGBT has a first portion connected to the gate electrodes of the sensing IGBT and a second portion connecting the first portion to the gate runner, and configures a built-in resistance of the second portion having a resistance value in a range from 10Ω to 5000Ω. As a result, a trade-off relationship between enhancing ESD tolerance of a current sensing region that includes the sensing IGBT and reducing transient sensing voltage may be improved. | 2021-03-18 |
20210082913 | SINGLE DIFFUSION BREAK LOCAL INTERCONNECT - Certain aspects of the present disclosure generally relate to a single diffusion break having a conductive portion. An example semiconductor device generally includes a first semiconductor region, a second semiconductor region, a dielectric region, and a single diffusion break (SDB). The dielectric region is disposed between the first semiconductor region and the second semiconductor region. The SDB intersects at least one of the first semiconductor region or the second semiconductor region, and the SDB comprises an electrically conductive portion. | 2021-03-18 |
20210082914 | INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - An integrated circuit device includes a fin-type active region protruding from a substrate and extending in a first direction, a plurality of semiconductor patterns disposed apart from an upper surface of the fin-type active region, the plurality of semiconductor patterns each including a channel region; a gate electrode surrounding the plurality of semiconductor patterns, extending in a second direction perpendicular to the first direction, and including a main gate electrode, which is disposed on an uppermost semiconductor pattern of the plurality of semiconductor patterns and extends in the second direction, and a sub-gate electrode disposed between the plurality of semiconductor patterns; a spacer structure disposed on both sidewalls of the main gate electrode; and a source/drain region connected to the plurality of semiconductor patterns, disposed at both sides of the gate electrode, and contacting a bottom surface of the spacer structure. | 2021-03-18 |
20210082915 | MULTI-THRESHOLD VOLTAGE NON-PLANAR COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR DEVICES - A device is provided. The device includes an interfacial layer on a semiconductor device channel. The device further includes a dipole layer on the interfacial layer, and a gate dielectric layer on the dipole layer. The device further includes a first work function layer associated with a first field effect transistor device; and a second work function layer associated with a second field effect transistor device, such that the first field effect transistor device and second field effect transistor device each have a different threshold voltage than a first field effect transistor device and second field effect transistor device without a dipole layer. | 2021-03-18 |
20210082916 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor device includes: a first well region of N-type and a second well region of P-type; a PMOS transistor provided in the first well region; and an NMOS transistor provided in the second well region. The PMOS transistor includes a first gate insulating layer and a first gate electrode. The NMOS transistor includes a second gate insulating layer and a second gate electrode. The first gate electrode includes a first semiconductor layer of P-type, a first insulating layer, and a first conductive layer. The second gate electrode includes a second semiconductor layer of N-type, a second insulating layer, and a second conductive layer. A film thickness of the first insulating layer is thicker than a film thickness of the second insulating layer. | 2021-03-18 |
20210082917 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second active patterns on first and second active regions of a substrate, respectively, a pair of first source/drain patterns and a first channel pattern therebetween which are in an upper portion of the first active pattern, a pair of second source/drain patterns and a second channel pattern therebetween which are in an upper portion of the second active pattern, and first and second gate electrodes intersecting the first and second channel patterns, respectively. Each of the first and second gate electrodes includes a first metal pattern adjacent to a corresponding one of the first and second channel patterns. The first and second channel patterns include SiGe. A Ge concentration of the second channel pattern is higher than a Ge concentration of the first channel pattern. A thickness of the first metal pattern of the second gate electrode is greater than a thickness of the first metal pattern of the first gate electrode. | 2021-03-18 |
20210082918 | Integrated Circuit Device With Low Threshold Voltage - A method of manufacturing a semiconductor device is provided. A substrate is provided. The substrate has a first region and a second region. An n-type work function layer is formed over the substrate in the first region but not in the second region. A p-type work function layer is formed over the n-type work function layer in the first region, and over the substrate in the second region. The p-type work function layer directly contacts the substrate in the second region. And the p-type work function layer includes a metal oxide. | 2021-03-18 |
20210082919 | Replacement Gate Process for FinFET - A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an isolation layer; and depositing a dielectric layer over the fin and the isolation layer. The method further includes forming a second trench in the dielectric layer over a channel region of the semiconductor device, the second trench exposing the isolation layer. The method further includes etching the isolation layer through the second trench to expose an upper portion of the fin in the channel region of the semiconductor device, and forming a dummy gate in the second trench over the isolation layer and engaging the upper portion of the fin. | 2021-03-18 |
20210082920 | SEMICONDUCTOR DEVICE - A semiconductor device having high operation frequency is provided. The semiconductor device includes a transistor including a first conductive layer, a first insulating layer, a second insulating layer, a first oxide, a second oxide, a third oxide, a third insulating layer, and a second conductive layer that are stacked in this order, and a fourth insulating layer. The first conductive layer and the second conductive layer include a region overlapping with the second oxide. In a channel width direction of the transistor, a level of the bottom surface of the second oxide is from more than or equal to −5 nm to less than 0 nm when a level of a region of the bottom surface of the second conductive layer which does not overlap with the second oxide is regarded as a reference. | 2021-03-18 |
20210082921 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes a plurality of first wires extending in a first direction, a plurality of second wires extending in a second direction intersecting the first direction, and a plurality of first semiconductor transistors. Each first semiconductor transistor is respectively connected between one of the plurality of first wires and one of the plurality of second wires. Each first semiconductor transistor includes a gate electrode connected to the respective first wire and a channel layer on a first surface of the second wire and also a side surface of the respective second wire. | 2021-03-18 |
20210082922 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a plurality of capacitor contacts positioned over the substrate, at least one of the plurality of capacitor contacts having a neck portion and a head portion over the neck portion, wherein an upper width of the head portion is larger than an upper width of the neck portion; a plurality of bit line contacts positioned over the substrate and a plurality of bit lines positioned over the plurality of bit line contacts, wherein at least one of the plurality of bit line is a wavy line extending between two adjacent capacitor contacts; and a capacitor structure positioned over the head portion. | 2021-03-18 |
20210082923 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING SAME AND MEMORY - A semiconductor device, a method of fabricating the semiconductor device and a memory are disclosed. In the provided semiconductor device, bit line contact plugs partially reside on insulating material layers in gate trenches in active areas and thus can come into sufficient contact with the active areas. This ensures good electrical transmission between the bit line contact plugs and the active areas even when there are internal voids in the bit line contact plugs. Such bit line contact plugs allowed to contain internal voids can be fabricated in an easier and faster manner, thus allowing a significantly enhanced memory fabrication throughput. | 2021-03-18 |
20210082924 | SEMICONDUCTOR MEMORY DEVICES - A semiconductor memory device includes a substrate having a memory cell region, a peripheral region, and a dam region between the memory cell region and the peripheral region, the memory cell region having a rectangular shape according to a top view and having a plurality of active regions defined therein; a plurality of bit line structures extending on the substrate in the memory cell region to be parallel with each other in a first horizontal direction, each including a bit line; a plurality of buried contacts filling lower portions of spaces among the plurality of bit line structures on the substrate; a plurality of landing pads on the plurality of buried contacts; and a dam structure including a first dam structure and a second dam structure in the dam region and being at the same level as the plurality of landing pads. | 2021-03-18 |
20210082925 | FINFET HAVING NON-MERGING EPITAXIALLY GROWN SOURCE/DRAINS - A semiconductor device includes a layer having a semiconductive material. The layer includes an outwardly-protruding fin structure. An isolation structure is disposed over the layer but not over the fin structure. A first spacer and a second spacer are each disposed over the isolation structure and on sidewalls of the fin structure. The first spacer is disposed on a first sidewall of the fin structure. The second spacer is disposed on a second sidewall of the fin structure opposite the first sidewall. The second spacer is substantially taller than the first spacer. An epi-layer is grown on the fin structure. The epi-layer protrudes laterally. A lateral protrusion of the epi-layer is asymmetrical with respect to the first side and the second side. | 2021-03-18 |
20210082926 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device has a first and second region, and a semiconductor channel. The first region includes a peak of a concentration profile of a first impurity of a first conductivity type. The first region extends from a surface of the substrate, through a depth range including the concentration profile of a second impurity of a second conductivity type, to a depth of an intersection of the concentration profile of the first impurity and the concentration profile of the second impurity. The second region includes a concentration profile of a third impurity, and the second region overlaps at least part of the first region. The concentration profile of the third impurity is higher in concentration than the concentration profile of the first impurity throughout a depth direction of the second region. One end of the semiconductor channel reaches the first and second region. | 2021-03-18 |
20210082927 | NAND MEMORY CELL STRING HAVING A STACKED SELECT GATE STRUCTURE AND PROCESS FOR FOR FORMING SAME - A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells. | 2021-03-18 |
20210082928 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a lower intermetal dielectric (IMD) layer, a middle conductive line, and a ferroelectric random access memory (FRAM) structure. The middle conductive line is embedded in the lower IMD layer. The FRAM structure is over the lower IMD layer and the middle conductive line. The FRAM structure includes a bottom electrode, a ferroelectric layer, and a top electrode. The bottom electrode is over the middle conductive line and in contact with the lower IMD layer. The ferroelectric layer is over the bottom electrode. The top electrode is over the ferroelectric layer. | 2021-03-18 |
20210082929 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate; a first transistor provided at an upper surface of the semiconductor substrate; and a first capacitor provided above the first transistor and connected to a gate of the first transistor. A tunnel current is able to flow between the gate and the semiconductor substrate. | 2021-03-18 |
20210082930 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate; a first semiconductor layer; a first conductor; a first power supply line; a second power supply line; and a circuit. The semiconductor substrate has a first surface, a second surface facing the first surface, and a third surface disposed between the first surface and the second surface. The first semiconductor layer is disposed along the first surface from the third surface. The first conductor is disposed on the first semiconductor layer. The first power supply line is electrically connected to the first conductor. The second power supply line is electrically connected to the semiconductor substrate. The circuit is disposed on the semiconductor substrate and connected to the first power supply line and the second power supply line. | 2021-03-18 |
20210082931 | THREE-DIMENSIONAL MEMORY DEVICES HAVING THROUGH ARRAY CONTACTS AND METHODS FOR FORMING THE SAME - Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including interleaved a plurality of dielectric layers and a plurality of sacrificial layers is formed above a substrate. A channel structure extending vertically through the dielectric stack is formed. A first opening extending vertically through the dielectric stack is formed. A spacer is formed in a plurality of shallow recesses and on a sidewall of the first opening. The plurality of shallow recesses abut the sidewall of the first opening. A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening. A slit extending vertically through the dielectric stack is formed. | 2021-03-18 |
20210082932 | EMBEDDED MEMORY WITH IMPROVED FILL-IN WINDOW - Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A memory cell structure is disposed on the memory region. A logic device is disposed on the logic region having a logic gate electrode separated from the substrate by a logic gate dielectric. A sidewall spacer is disposed along a sidewall surface of the logic gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with sidewall surfaces of the pair of select gate electrodes within the memory region, and extending upwardly along the sidewall spacer within the logic region. | 2021-03-18 |
20210082933 | SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, a semiconductor memory device includes a first conductive layer and second conductive layers arranged at intervals in a first direction above the first conductive layer. A semiconductor layer extends in the first direction in the second conductive layers to be in contact with the first conductive layer. A charge storage layer is between the semiconductor layer and the second conductive layers. A metal layer extends in the first direction and a second direction above the first conductive layer, and separates the second conductive layers. The device further includes an insulating layer. The insulating layer includes a portion between the metal layer and the first conductive layer and a portion between the metal layer and the second conductive layers. | 2021-03-18 |
20210082934 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes: a single-crystal semiconductor substrate having a recessed surface; an under layer provided above the semiconductor substrate; a stacked body, provided over the under layer, that includes at least one conductive layer and at least one insulating layer alternately stacked on top of one another; a single-crystal semiconductor layer extending in a first direction perpendicular to the semiconductor substrate, penetrating the stacked body, and including a first end in contact with the recessed surface of the semiconductor substrate; and a memory film provided between the semiconductor layer and the at least one conductive layer. A crystal orientation of the semiconductor layer and a crystal orientation of the semiconductor substrate are the same. | 2021-03-18 |
20210082935 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor storage device includes a substrate, a stacked film including a plurality of first insulating layers and a plurality of electrode layers that are alternately provided on the substrate, and a second insulating layer provided on the stacked film. The device further includes a plurality of pillar portions, each of which including a first insulator, a charge storage layer, a second insulator, a first semiconductor layer and a third insulator that are sequentially provided in the stacked film and the second insulating layer. Furthermore, a width of the second insulating layer sandwiched between the pillar portions is narrower than a width of the stacked film sandwiched between the pillar portions, in at least a portion of the second insulating layer. | 2021-03-18 |
20210082936 | Self-Aligned Select Gate Cut for 3D NAND - Electronic devices and methods of forming the electronic devices are described. The electronic devices comprise a plurality of memory holes extending along a first direction through a plurality of alternating oxide and nitride layers. Each memory hole has a core oxide surrounded by a semiconductor material, the semiconductor material surrounded by a dielectric. The memory holes are staggered to provide a plurality of memory hole lines having spaced memory holes so that adjacent memory hole lines have the memory holes in a staggered configuration. A conductive material is on top of the stack of alternating oxide and nitride layers. A dielectric filled cut line extends through the conductive material in a direction across the plurality of memory hole lines. The dielectric filled cut line separates a first memory hole line from an adjacent second memory hole line without disabling the functionality of the memory holes. | 2021-03-18 |
20210082937 | Integrated Structures Containing Vertically-Stacked Memory Cells - Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium. | 2021-03-18 |
20210082938 | SINGLE POLY NON-VOLATILE MEMORY DEVICE, METHOD OF MANUFACTURING THE SAME AND SINGLE POLY NON-VOLATILE MEMORY DEVICE ARRAY - A single poly non-volatile memory device that includes: a first type lower well; first and second wells separately formed in an upper portion of the first type lower well; a source electrode, a selection transistor, a sensing transistor, and a drain electrode sequentially disposed in an upper portion of the first well. A control gate is formed in an upper portion of the second well with separated on an opposite side of the source electrode from the first well and connected to the gate of the sensing transistor. | 2021-03-18 |
20210082939 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A first region includes a memory cell transistor. A second region is adjacent to the first region in a first direction, and includes first and second subregions aligned in a second direction. First members include a portion extending along the first direction, and are provided in the first subregion. The first members are arranged in such a manner that the first members aligned in the second direction in an n-th row and an (n+1)-th row, counted from a side of the second subregion, are shifted in the first direction. The first members adjacent to each other in the second direction are arranged in such a manner that portions extending in the first direction face each other. | 2021-03-18 |
20210082940 | MEMORY DEVICE - According to one embodiment, a memory device includes a substrate; a structure including a plurality of conductive layers stacked on the substrate; and a pillar arranged inside the structure and including a semiconductor layer that extends in a direction perpendicular to a surface of the substrate. The semiconductor layer includes a first portion on a side of an upper portion of the structure, and a second portion between the first portion and the substrate. The first portion has a thickness larger than a thickness of the second portion. | 2021-03-18 |
20210082941 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is disclosed. The device includes a peripheral circuit structure on a substrate, a semiconductor layer on the peripheral circuit structure, an electrode structure on the semiconductor layer, the electrode structure including electrodes stacked on the semiconductor layer, a vertical channel structure penetrating the electrode structure and being connected to the semiconductor layer, a separation structure penetrating the electrode structure, extending in a first direction, and horizontally dividing the electrode of the electrode structure into a pair of electrodes, an interlayered insulating layer covering the electrode structure, and a through contact penetrating the interlayered insulating layer and being electrically connected to the peripheral circuit structure. | 2021-03-18 |
20210082942 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer. | 2021-03-18 |
20210082943 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to an embodiment, a semiconductor memory device includes a semiconductor substrate, a control circuit arranged on the semiconductor substrate, and a memory cell array arranged above the control circuit. The memory cell array includes a plurality of three-dimensionally-arranged memory cells, and is controlled by the control circuit. A first nitride layer is arranged between the control circuit and the memory cell array, and a second nitride layer is arranged between the control circuit and the first nitride layer. | 2021-03-18 |
20210082944 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate, a logic circuit provided on the substrate, a wiring layer including a plurality of wirings that are provided above the logic circuit, a first insulating film below the wiring layer, a plug, and a second insulating film. Each of the wirings contains copper and extends along a surface plane of the substrate in a first direction. The wirings are arranged along the surface plane of the substrate in a second direction different from the first direction. The plug extends through the first insulating film in a third direction crossing the first and second directions and is electrically connected to one of the wirings. The plug contains tungsten. The second insulating film is provided between the first insulating film and the plug. | 2021-03-18 |
20210082945 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first insulating layer; a first conductive layer provided in the first insulating layer and extending in the first direction; a second conductive layer extending in the first direction and provided adjacent to the first conductive layer in a second direction; and a contact plug coupled to one surface of the first conductive layer in a third direction. Thicknesses in the third direction of portions of the first and second conductive layers that overlap the contact plug in the third direction are smaller than thicknesses in the third direction of portions of the first and second conductive layers that do not overlap the contact plug in the third direction. | 2021-03-18 |
20210082946 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a via provided above a substrate, a conductive layer provided on the via, and a via provided on the conductive layer. The via, the conductive layer, and the via are one continuous structure. | 2021-03-18 |
20210082947 | MEMORY DEVICE - A memory device includes a substrate, first, second, and third conductive layers, a stack of fourth conductive layers, a memory pillar, and an insulator. The first, second, and third conductive layer are provided above the substrate. The stack of fourth conductive layers is provided above the third conductive layer. The memory pillar extends in the thickness direction through the stack and the third conductive layer and into the second conductive layer in a first region of the memory device. The insulator extends in a thickness direction through the stack, the third conductive layer, and the second conductive layer in a second region of the memory device. The insulator also extends in a second surface direction of the substrate. A thickness of the third conductive layer in a region through which the insulator extends is greater than a thickness of the third conductive layer in the first region. | 2021-03-18 |
20210082948 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a substrate having a first region and a second region arranged in a first direction. The first region includes word line layers and interlayer insulating layers laminated in a second direction, a first semiconductor layer opposed to the word line layers, and an electric charge accumulating film disposed between them. The second region includes a part of the word line layers and the interlayer insulating layers, first insulating layers and a part of the interlayer insulating layers that separate from the word line layers, a contact that has an outer peripheral surface connected to the first insulating layers, and a second insulating layer disposed between the word line layers and the first insulating layers. The first insulating layers have side surfaces connected to the word line layers and side surfaces connected to the second insulating layer. | 2021-03-18 |
20210082949 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first stacked body disposed between the belt-like portions and stacked a plurality of first conductive layers via a first insulating layer, a second stacked body disposed in a region in the first stacked body and stacked a plurality of second insulating layers via the first insulating layer, a first pillar extending in the first stacked body in a stacking direction of the first stacked body, and a plurality of second pillars extending in the stacking direction on both sides of the second stacked body facing the belt-like portions and arranged in the first direction, in which the second pillars each include a plate-like portion disposed at a height position of each of the first conductive layers, and the adjacent second pillars are connected to each other by the plate-like portion. | 2021-03-18 |
20210082950 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes: first and second interconnect layers; a plurality of third interconnect layers stacked between the first and second interconnect layers; a first insulating layer passing through the plurality of third interconnect layers, and including one end that is in contact with a first face of the first interconnect layer; a first memory pillar including a first semiconductor layer passing through the plurality of third interconnect layers and a charge storage layer provided between the plurality of third interconnect layers and the first semiconductor layer. A distance between a third face of the first interconnect layer opposite to the first face and the second interconnect layer in the first direction, differs at a position corresponding to the first insulating layer from at positions corresponding to the third interconnect layers. | 2021-03-18 |
20210082951 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment includes: a first transistor, the first transistor including a substrate including a first region of first conductive type and a second region of first conductive type, a first insulating film provided on the first region and the second region, a first wiring of first conductive type provided on the first region, the first wiring being electrically connected to the first region, and the first wiring including a higher impurity concentration of first conductive type than an impurity concentration of the first region, and a second wiring of first conductive type provided on the second region, the second wiring being electrically connected to the second region, and the second wiring including a higher impurity concentration of first conductive type than an impurity concentration of the second region; a conductive layer provided parallel to a substrate plane above the first transistor; a pillar penetrating the conductive layer, the pillar including a semiconductor film; and a charge storage film provided between the semiconductor film and the conductive layer. | 2021-03-18 |
20210082952 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device according to one embodiment is provided with: a substrate; a stacked body provided on the substrate; and a pillar portion penetrating the stacked body. The pillar portion has a first film including a first material and a second material, and a second film provided on an inner side of the first film. The second material is a material that increases an etching rate of the first material as a composition rate relative to the first material is higher, and the composition rate gradually decreases from an upper part to a lower part of the first film. | 2021-03-18 |
20210082953 | THREE-DIMENSIONAL MEMORY DEVICES HAVING THROUGH STAIR CONTACTS AND METHODS FOR FORMING THE SAME - Embodiments of three-dimensional (3D) memory devices having through stair contacts (TSCs) and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack and a TSC. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. Edges of the interleaved conductive layers and dielectric layers define a staircase structure on a side of the memory stack. The TSC extends vertically through the staircase structure of the memory stack. The TSC includes a conductor layer and a spacer circumscribing the conductor layer. | 2021-03-18 |
20210082954 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes first and second wiring layers above a semiconductor substrate, a memory pillar extending through the first and second wiring layers, a first plug contacting the first wiring layer, a second plug contacting the second wiring layer, a first pillar adjacent to the first plug and extending through the first wiring layer, and a second pillar adjacent to the second plug and extending through the first and second wiring layers. The memory pillar includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and a third insulating layer, a charge storage layer, and a fourth insulating layer on a side surface of the second semiconductor layer. The distance between the center of the first plug and the center of the first pillar is greater than the distance between the center of the second plug and the center of the second pillar. | 2021-03-18 |
20210082955 | THREE-DIMENSIONAL MEMORY DEVICE CONTAINING FERROELECTRIC MEMORY ELEMENTS ENCAPSULATED BY TRANSITION METAL-CONTAINING CONDUCTIVE ELEMENTS AND METHOD OF MAKING THEREOF - A three-dimensional ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where each of the electrically conductive layers contains a transition metal element-containing conductive liner and a conductive fill material portion, a vertical semiconductor channel extending vertically through the alternating stack, a vertical stack of tubular transition metal element-containing conductive spacers laterally surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers, and a ferroelectric material layer located between the vertical stack of tubular transition metal element-containing conductive spacers and the transition metal element-containing conductive liner. | 2021-03-18 |
20210082956 | SEMICONDUCTOR MEMORY DEVICE - Provided is a semiconductor memory device according to an embodiment including: a stacked body including gate electrode layers stacked in a first direction; a semiconductor layer provided in the stacked body and extending in the first direction; and a gate insulating layer provided between the semiconductor layer and at least one of the gate electrode layers, and the gate insulating layer including a first region containing a first oxide including at least one of a hafnium oxide and a zirconium oxide, in which a first length of the at least one of the gate electrode layers in the first direction is larger than a second length of the first region in the first direction. | 2021-03-18 |
20210082957 | STORAGE DEVICE - Provided is a storage device according to an embodiment including: a stacked body including gate electrode layers stacked in a first direction; a semiconductor layer provided in the stacked body and extending in the first direction; and a gate insulating film provided between the semiconductor layer and the gate electrode layer, the gate insulating film having a first region disposed between the gate electrode layer and the semiconductor layer and a second region disposed between the two first regions adjacent to each other in the first direction, the gate insulating film containing a hafnium oxide, in which a first thickness of the first region in the second direction from the semiconductor layer toward the gate electrode layer is smaller than a second thickness of the second region in the second direction. | 2021-03-18 |
20210082958 | MEMORY CELL ARRANGEMENT AND METHODS THEREOF - A memory cell arrangement is provided that may include: a plurality of electrode layers, wherein each of the plurality of electrode layers comprises a plurality of through holes, each of the plurality of through holes extending from a first surface to a second surface of the respective electrode layer; a plurality of electrode pillars, wherein each of the plurality of electrode pillars comprises a plurality of electrode portions, wherein each of the plurality of electrode portions is disposed within a corresponding one of the plurality of through holes; wherein at least one remanent-polarizable portion is disposed in each of the plurality of through holes in a gap between the respective electrode layer and the respective electrode portion. | 2021-03-18 |
20210082959 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a stacked body and a columnar body. The stacked body includes a plurality of conductive layers spaced apart from each other in a stacking direction. The columnar body penetrates the stacked body in the stacking direction. The columnar body includes a columnar ferroelectric film, a semiconductor film disposed between the ferroelectric film and the conductive layers, and an insulating film disposed between the semiconductor film and the conductive layers. | 2021-03-18 |
20210082960 | INTEGRATED CIRCUIT DEVICE WITH IMPROVED LAYOUT - An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1. | 2021-03-18 |
20210082961 | DISPLAY DEVICE AND ARRAY SUBSTRATE THEREOF - The present invention teaches a display device and its array substrate. The array substrate includes pixel units arranged in an array, each including pixel electrode, TFT, touch electrode, scan line, and data line. The scan and data lines are configured along first and second directions, respectively. The scan lines and data lines cross each other. The pixel electrodes are connected to the scan and data lines through the TFTs. Each pixel unit also includes first and second metallic lines configured along the first and second directions, respectively. The first and second metallic lines are disposed in a same layer as the scan and data lines, respectively. Two neighboring first metallic lines along the first direction are connected by a second metallic line. The first metallic lines are connected to the second metallic line through first vias. The second metallic line is connected to a touch electrode through a second via. | 2021-03-18 |
20210082962 | TFT ARRAY SUBSTRATE AND DISPLAY DEVICE - The present invention teaches a TFT array substrate and a display device. The TFT array substrate disposes second fanout lines of the fanout area on a first metallic layer, and disposes first fanout lines of the fanout area on a second metallic layer. Data lines and their corresponding second fanout lines, and second fanout lines and their corresponding first fanout lines, are connected together through vias. The first metallic layer has a greater surface resistivity than that of the second metallic layer. The present invention's fanout lines corresponding to a same data line have a significantly increased total impedance, and the impedance variation of the fanout lines has a less impact. As data signals propagate to the data lines through the fanout lines, the data signals' arrival times to the data lines have little difference, thereby enhancing the display quality, more reliable manufacturing process, and lower risk for short circuit. | 2021-03-18 |
20210082963 | ELECTROSTATIC PROTECTION CIRCUIT AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY APPARATUS - An electrostatic protection circuit and a manufacturing method thereof, an array substrate and a display apparatus in the field of display technology are provided. This electrostatic protection circuit includes: a discharge sub-circuit, a buffer sub-circuit and an electrostatic protection line, wherein the electrostatic protection line is a common electrode line; the buffer sub-circuit includes a third transistor and a fourth transistor; a gate and a second electrode of the third transistor are both connected to a first electrode of the fourth transistor, and the first electrode of the third transistor is connected to a signal line; a gate and a second electrode of the fourth transistor are both connected to the signal line. | 2021-03-18 |
20210082964 | DISPLAY PANEL - A display panel includes a plurality of sub-pixel structures and a plurality of transfer elements. The sub-pixel structures include a plurality of first sub-pixel structures. A data line of each of the first sub-pixel structures is disposed adjacent to a corresponding transfer element, and a scan line of each of the first sub-pixel structures is electrically connected to the corresponding transfer element. The first sub-pixel structures include a plurality of first-type sub-pixel structures and a plurality of second-type sub-pixel structures. When the display panel displays a grayscale picture, each of the first-type sub-pixel structures has first brightness, each of the second-type sub-pixel structures has second brightness. The first brightness is less than the second brightness. A total number of the first sub-pixel structures of the display panel is A, a number of the first-type sub-pixel structures in the first sub-pixel structures is a, and 50%<(a/A)<100%. | 2021-03-18 |
20210082965 | Method for Manufacturing Thin Film Transistor, Thin Film Transistor, and Display Apparatus - The present disclosure provides a method for manufacturing a thin film transistor, a thin film transistor, and a display apparatus. The method for manufacturing a thin film transistor includes: forming a gate layer on a substrate; forming a gate insulating layer on the gate layer; forming an active layer on the gate insulating layer; forming a source/drain layer on the active layer; and performing a plasma bombardment treatment on a surface of the active layer on which the source/drain layer is formed, and controlling the plasma bombardment treatment to be performed at a gas flow rate of 4K sccm to 70K sccm, at a pressure of 600 mTorr to 1200 mTorr, at a power of 4 KW to 12 KW for a treatment time of 10 s to 60 s. | 2021-03-18 |