12th week of 2020 patent applcation highlights part 70 |
Patent application number | Title | Published |
20200091867 | ELECTRONIC CIRCUIT, OSCILLATOR, AND CALCULATING DEVICE - According to one embodiment, an electronic circuit includes a first conductive component, a second conductive component, a first current path, and a second current path. The second conductive component is capacitively coupled to the first conductive component. The first current path of a superconductor includes a first portion and a second portion. The first portion is connected to the first conductive component. The second portion is connected to the second conductive component. The first current path includes N first Josephson junctions connected in series and provided between the first and second portions. The second current path of a superconductor includes a third portion and a fourth portion. The third portion is connected to the first conductive component. The fourth portion is connected to the second conductive component. The second current path includes a second Josephson junction connected in series and provided between the third and fourth portions. | 2020-03-19 |
20200091868 | METHOD AND APPARATUS FOR CALIBRATION OF A BAND-PASS FILTER AND SQUELCH DETECTOR IN A FREQUENCY-SHIFT KEYING TRANSCEIVER - Various embodiments relate to a method for calibration of a center frequency of a BPF in an FSK transceiver, the method including the steps of filtering a carrier frequency signal by the BPF to produce a filtered signal, detecting, by a phase-frequency detector (“PFD”), a difference in phase between the carrier frequency signal and the filtered signal from the BPF, sweeping a calibration code of the BPF, detecting a transition in the sign of the phase difference and capturing a calibration code associated with the transition in the sign of the phase difference for calibration of the BPF. | 2020-03-19 |
20200091869 | AMPLIFIER CIRCUIT AND TRANSMITTING DEVICE - According to one embodiment, an amplifier circuit includes N (N>=3) transistors, two first branches and N−2 second branches. The N (N>=3) transistors are connected in parallel. The two first branches each include the transistor and a first transmission line which is connected to an output terminal of the transistor. The N−2 second branches each include the transistor and a second transmission line which is connected to the output terminal of the transistor. For each of the first branches, a sum between an electrical length of a parasitic component of the transistor and the electrical length of the first transmission line are odd multiples of approximately 90 degrees. For each of the second branches, the sum between the electrical length of the parasitic component of the transistor and the electrical length of the second transmission line are multiples of approximately 180 degrees. | 2020-03-19 |
20200091870 | ENHANCED AMPLIFIER EFFICIENCY THROUGH CASCODE CURRENT STEERING - According to some implementations, a power amplifier (PA) includes a common emitter configured to receive a radio-frequency (RF) signal. The PA also includes a carrier amplifier coupled to the common emitter to form a carrier cascode configuration, a collector of the carrier amplifier provided with a first supply voltage. The PA further includes a peaking amplifier coupled to the common emitter to form a peaking cascode configuration, a collector of the peaking amplifier provided with a second supply voltage greater than the first supply voltage. | 2020-03-19 |
20200091871 | DOHERTY AMPLIFIER - A Doherty amplifier includes a carrier amplifier, a peaking amplifier, and a phase compensation circuit. The carrier amplifier | 2020-03-19 |
20200091872 | ACTIVE LIMITING SYSTEM - An active limiting system that is suitable to protect a low noise amplifier against the high power signals received from a signal input includes, at least one first switch, source of which is connected to a gate voltage; at least first resistor which is connected between the gate and source of the first switch; at least one second resistor, which is connected between a drain voltage and drain of the first switch; at least one second switch, source of which is connected to said drain voltage and drain of which is connected to a signal input; at least one third resistor which is connected between the drain of the first switch and gate of the second switch; at least one first filtering element, which blocks DC currents/voltages and which is connected between the source of the second switch and ground. | 2020-03-19 |
20200091873 | METHOD FOR OVERTEMPERATURE PROTECTION AND AUDIO APPARATUS - The invention relates to a method for protecting a component ( | 2020-03-19 |
20200091874 | RADIO FREQUENCY POWER AMPLIFIER AND POWER AMPLIFIER MODULE - In a radio frequency power amplifier, a semiconductor chip includes at least one first transistor amplifying a radio frequency signal, a first external-connection conductive member connected to the first transistor, a bias circuit including a second transistor that applies a bias voltage to the first transistor, and a second external-connection conductive member connected to the second transistor. The second external-connection conductive member at least partially overlaps with the second transistor when viewed in plan. | 2020-03-19 |
20200091875 | LOW SWAP CIRCUIT CARD DESIGN FOR RF POWER AMPLIFIERS - A system and method for using an embedded microprocessor in an RF amplifier. The use of an embedded microprocessor avoids manual calibration. The Microprocessor collects initial amplifier performance data based on a set of parameters and calculates the needed corrections. The microprocessor can change levels within the circuit to achieve those operating points. The embedded microprocessor sets voltage levels with internal circuitry and communicates this information externally through a serial communication port, or the like, to allow a user to communicate with and look at the amplifier data and readjust the internal bias levels, as needed. Thus, the internal microprocessor provides for calibration, self-testing, and monitoring of the RF amplifier and also functions as an in situ bias and temperature compensation controller for use in the presence of temperature variation and provides bias sequencing control to protect against improper applied timing of voltage inputs to the amplifier. | 2020-03-19 |
20200091876 | Compact Architecture for Multipath Low Noise Amplifier - Methods and devices used in mobile receiver front end to support multiple paths and multiple frequency bands are described. The presented devices and methods provide benefits of scalability, frequency band agility, as well as size reduction by using one low noise amplifier per simultaneous outputs. Based on the disclosed teachings, variable gain amplification of multiband signals is also presented. | 2020-03-19 |
20200091877 | AUDIO PROCESSING DEVICE AND METHOD FOR CONTROLLING AUDIO PROCESSING DEVICE - An audio processing device includes: a signal processing circuit configured to select between a first state for outputting a first signal obtained by reducing components that fall below a first frequency in an audio signal and a second state for outputting a second signal obtained by reducing components that fall below a second frequency in the audio signal, and output one of the selected first or second signal as an output signal, where the second frequency is higher than the first frequency; a class-D amplifier that amplifies the output signal; a processor configured to: determine whether or not an intensity of a low-frequency component in the audio signal exceeds a threshold value; and control the signal processing circuit to select: the first state in a case where a determination result is negative, where the intensity of the low-frequency component in the audio signal is determined to not exceed the threshold value; and the second state in a case where the determination result is affirmative, where the intensity of the low-frequency component in the audio signal is determined to exceed the threshold value. | 2020-03-19 |
20200091878 | PA OUTPUT MEMORY NEUTRALIZATION USING BASEBAND I/O CAPACITANCE CURRENT COMPENSATION - Power amplifier (PA) output memory neutralization is disclosed, using baseband input/output (I/O) capacitance current compensation. Radio frequency (RF) PAs experience I/O memory effects when used with envelope tracking supply modulation schemes. Envelope tracking supply modulation results in a nonlinear variation of the I/O capacitance. Traditional approaches compensate for such effects with a current provided by a bias circuit which is band-limited. This results in memory effects which distort the amplified signal, becoming more significant as the modulation bandwidth increases. An RF communications system according to embodiments disclosed herein mitigates such memory effects by compensating for the non-linear effect of the I/O capacitance in an RF PA. | 2020-03-19 |
20200091879 | POWER AMPLIFICATION SYSTEM WITH REACTANCE COMPENSATION - Power amplification system is disclosed. A power amplification system can include a Class-E push-pull amplifier including a transformer balun. The power amplification can further include a reactance compensation circuit coupled to the transformer balun. In some embodiments, the reactance compensation circuit is configured to reduce variation over frequency of a fundamental load impedance of the power amplification system. | 2020-03-19 |
20200091880 | CHOPPER STABILIZED AMPLIFIER WITH PARALLEL NOTCH FILTERS - A chopper stabilized amplifier includes a first transconductance amplifier, first chopping circuitry coupled to an input of the first transconductance amplifier for chopping an input signal and applying the chopped input signal to the input of the first transconductance amplifier, and second chopping circuitry coupled to an output of the first transconductance amplifier for chopping an output signal produced by the first transconductance amplifier. A ping-pong notch filter is connected to an output of the second chopping circuitry and performs an integrate and transfer function on a chopped output signal produced by the second chopping circuitry to filter ripple voltages. The ping-pong notch filter includes parallel connected first and second notch filters, each of which has an input coupled to the output of the second chopping circuitry. | 2020-03-19 |
20200091881 | DIFFERENTIAL TRANS-IMPEDANCE AMPLIFIER - In conventional high data rate receivers, the transmitted optical signal has poor extinction ratio and translates into a small modulated current with a large DC current, which saturates the receiver TIA and amplifiers, and significantly degrades the gain and bandwidth performance. Consequently, cancelling PD DC current in high data rate receivers is desired for proper operation. Differential TIA schemes, i.e. providing separate AC-coupled and DC-coupled paths, in parallel, provide better linearity for large input currents and low gain settings. To AC couple the PD to the TIA using passive AC-coupling circuitry, an AC-coupling capacitor (C | 2020-03-19 |
20200091882 | DIFFERENTIAL AMPLIFIER CIRCUIT AND SERIAL TRANSMISSION CIRCUIT - A differential amplifier circuit has a first current circuit comprising a first transistor and a second transistor, and to flow a current depending on a voltage of a first input signal, a second current circuit comprising a third transistor and a fourth transistor, and to flow a current depending on a voltage of a second input signal, a fifth transistor comprising a gate connected to a gate and the drain of the second transistor, and to flow a current that is M times greater than the current flowing between the drain and the source of the second transistor, and a sixth transistor comprising a gate connected to a gate and the drain of the fourth transistor and cascode-connected to the first transistor, and to flow a current that is N times greater than the current flowing between the drain and the source of the fourth transistor. | 2020-03-19 |
20200091883 | ETHERNET LINE DRIVER - Some aspects of the disclosure provide for a circuit. In an example, the circuit includes an amplifier, a first transistor network, a second transistor network, a first resistor, a second resistor, and a third resistor. The amplifier has first and second inputs and first, second, third, and fourth outputs. The first transistor network is coupled to the first output of the amplifier and the second output of the amplifier. The second transistor network is coupled to the third output of the amplifier and the fourth output of the amplifier. The first resistor is coupled between the first transistor network and the second transistor network. The second resistor is coupled between the first transistor network and the first input of the amplifier. The third resistor is coupled between the second transistor network and the second input of the amplifier. | 2020-03-19 |
20200091884 | AMPLIFIER WITH COMMON MODE DETECTION - An analog discrete current mode negative feedback amplifier circuit for use with a micro-fused strain gauge is disclosed. The amplifier circuit includes a Wheatstone bridge coupled to a first power supply and a second power supply. The first power supply and the second power supply can be configured such that the periodically alternate between two voltage levels. The Wheatstone bridge can be coupled to a negative feedback amplifier circuit with common mode detection. The amplifier circuit can comprise a differential amplifier with a negative feedback configuration coupled to a common mode amplifier. In addition, the output of each of the amplifiers can be coupled to a common-mode amplifier. In a pressure sensing application, the output of the common mode amplifier serves to output the temperature while the differential amplifiers serve to output the pressure. | 2020-03-19 |
20200091885 | VOLTAGE FOLLOWER CIRCUIT - A voltage follower circuit according to an embodiment includes first and second paths, the first path includes a first nMOS transistor and a first pMOS transistor, the second path includes a second nMOS transistor and a second pMOS transistor, an input voltage is supplied to the gate of the first nMOS transistor, an output voltage is supplied to the gate of the second nMOS transistor, a voltage lower than the output voltage is supplied to the gate of the first pMOS transistor, and a voltage lower than the input voltage is supplied to the gate of the second pMOS transistor. | 2020-03-19 |
20200091886 | POSITIONS OF RELEASE PORTS FOR SACRIFICIAL LAYER ETCHING - A film bulk acoustic wave resonator includes a piezoelectric film disposed over a cavity. The cavity is shaped as partial ellipse including first, second, and third vertices. The film bulk acoustic wave resonator further includes three release ports in positions that minimize etch time to remove all sacrificial material from within the cavity. | 2020-03-19 |
20200091887 | BAND PASS FILTER - A band pass filter includes: a first circuit unit including a first series LC resonant circuit disposed between a first terminal and a second terminal; a second circuit unit disposed between the first circuit unit and the second terminal, and including a first parallel LC resonant circuit; and a third circuit unit disposed between the first terminal and a ground, and including a second series LC resonant circuit, wherein a resonant frequency of the first circuit unit is in a pass band. | 2020-03-19 |
20200091888 | BULK-ACOUSTIC WAVE RESONATOR AND METHOD FOR MANUFACTURING THE SAME - A bulk-acoustic wave resonator includes a substrate, a first layer, a second layer, a membrane layer, and a resonance portion. The substrate includes a substrate protection layer. The first layer is disposed on the substrate protection layer. The second layer is disposed outside of the first layer. The membrane layer forms a cavity with the substrate protection layer and the first layer. The resonance portion is disposed on the membrane layer. Either one or both of the substrate protection layer and the membrane layer includes a protrusion disposed in the cavity. | 2020-03-19 |
20200091889 | ELASTIC WAVE DEVICE - A longitudinally coupled resonator elastic wave filter is disposed on a piezoelectric substrate. IDT electrodes include first and second busbars. An inorganic insulating layer is provided on at least one side in a direction perpendicular or substantially perpendicular to an elastic wave propagation direction to cover the first or second busbars, and a first wiring line is disposed on the inorganic insulating layer to extend in the elastic wave propagation direction. A second wiring line three-dimensionally crosses the first wiring line with the inorganic insulating layer interposed therebetween. The first wiring line is connected to busbars, which are connected to the same potential, by extending through the inorganic insulating layer. | 2020-03-19 |
20200091890 | STACKED WAFER-LEVEL PACKAGING DEVICES - Stacked wafer-level packaging devices. In some embodiments, a wireless device includes a transceiver configured to generate a radio-frequency (RF) signal. The wireless device also includes a front-end module (FEM) in communication with the transceiver, the front-end module including a packaging substrate configured to receive a plurality of components, the front-end module further including a stacked assembly implemented on the packaging substrate, the stacked assembly including a first wafer-level packaging (WLP) device having a radio-frequency (RF) shield, the stacked assembly further including a second wafer-level packaging device having an RF shield, the second wafer-level packaging device positioned over the first wafer-level packaging device such that the RF shield of the second wafer-level packaging device is electrically connected to the RF shield of the first wafer-level packaging device. The wireless device further includes an antenna in communication with the front-end module, the antenna configured to transmit the amplified radio-frequency signal. | 2020-03-19 |
20200091891 | LAYERED BODY AND SAW DEVICE - A layered body includes a ceramic substrate formed of a polycrystalline ceramic and having a supporting main surface and a piezoelectric substrate formed of a piezoelectric material and having a bonding main surface that bonds to the supporting main surface through Van der Waals force. The ceramic substrate includes a supporting main surface amorphous layer formed so as to include the supporting main surface. The piezoelectric substrate includes a bonding main surface amorphous layer formed so as to include the bonding main surface. The supporting main surface amorphous layer has a smaller thickness than the bonding main surface amorphous layer. | 2020-03-19 |
20200091892 | ACOUSTIC WAVE DEVICE, FILTER, MULTIPLEXER, RADIO-FREQUENCY FRONT-END CIRCUIT, AND COMMUNICATION DEVICE - In an acoustic wave device, a piezoelectric body is directly or indirectly provided on a high acoustic velocity material layer, an interdigital transducer electrode is directly or indirectly provided on the piezoelectric body, the interdigital transducer electrode includes a first busbar, a second busbar spaced away from the first busbar, a plurality of first electrode fingers, and a plurality of second electrode fingers, and a weighting is applied to the interdigital transducer electrode by providing a floating electrode finger not electrically connected to the first busbar or the second busbar or applied by providing an electrode finger formed by metallizing a gap between the first electrode fingers or a gap between the second electrode fingers to integrate the first electrode fingers or the second electrode fingers. | 2020-03-19 |
20200091893 | BANDPASS FILTER WITH FREQUENCY SEPARATION BETWEEN SHUNT AND SERIES RESONATORS SET BY DIELECTRIC LAYER THICKNESS - Filter devices and methods of fabrication are disclosed. A filter device includes a piezoelectric plate attached to a substrate, portions of the piezoelectric plate forming diaphragms spanning respective cavities in the substrate. A conductor pattern formed on a surface of the piezoelectric plate includes a plurality of interdigital transducers (IDTs) of a respective plurality of acoustic resonators including a shunt resonator and a series resonator, interleaved fingers of each of the plurality of IDTs disposed on one of the diaphragms. Radio frequency signals applied to the IDTs excite respective primary shear acoustic modes in the respective diaphragms. A thickness of a first dielectric layer disposed on the front surface between the fingers of the IDT of the shunt resonator is greater than a thickness of a second dielectric layer disposed on the front surface between the fingers of the IDT of the series resonator. | 2020-03-19 |
20200091894 | EXTRACTOR - An extractor includes a band elimination filter that is connected between a common terminal and a first input-output terminal and that has a stop band equal or substantially equal to a first frequency band, and a band pass filter that is connected between the common terminal and a second input-output terminal and that has a pass band equal or substantially equal to a second frequency band that overlaps the first frequency band. The band pass filter includes, series arm resonators, three or more parallel arm resonators, and three or more inductors that are connected between the ground and the parallel arm resonators. The L value of a first inductor that is connected and nearest to the common terminal is smaller than the L value of a third inductor, and the L value of a second inductor that is connected and second-nearest to the common terminal is smaller than the L value of the third inductor. | 2020-03-19 |
20200091895 | DYNAMIC HIGH VOLTAGE (HV) LEVEL SHIFTER WITH TEMPERATURE COMPENSATION FOR HIGH-SIDE GATE DRIVER - Various embodiments of the present application are directed towards a level shifter with temperature compensation. In some embodiments, the level shifter comprises a transistor, a first resistor, and a second resistor. The first resistor is electrically coupled from a first source/drain of the transistor to a supply node, and the second resistor is electrically coupled from a second source/drain of the transistor to a reference node. Further, the first and second resistors have substantially the same temperature coefficients and comprise group III-V semiconductor material. By having both the first and second resistors, the output voltage of the level shifter is defined by the resistance ratio of the resistors. Further, since the first and second resistors have the same temperature coefficients, temperature induced changes in resistance is largely cancelled out in the ratio and the output voltage is less susceptible to temperature induced change than the first and second resistors individually. | 2020-03-19 |
20200091896 | LEVEL SHIFTING CIRCUIT AND METHOD FOR OPERATING A LEVEL SHIFTER - A level shifting circuit generates a pulse signal, when both of the logic levels of two complementary input signals of a level shifter has changed while both of the logic levels of two output signals of the level shifter present at low logic level, to pull up either one of the output signals of the level shifter to a second high logic level. Once the logic level of both output signals at the first output node and the second output node present complementary, the level shifting circuit stops pulling up the output signal. | 2020-03-19 |
20200091897 | Relaxation oscillator - This invention provides a relaxation oscillator, including a first comparator, a second comparator, an SR latch, and a capacitor control module. Input ends of the two comparators are coupled with the capacitor control module and an external reference threshold voltage, and two output ends are coupled with the input ends of the SR latch; output ends of the SR latch are coupled with input ends of the capacitor control module; According to the external reference threshold voltage, a first comparison signal generated by the first comparator and a second comparison signal generated by the second comparator are inputted into the SR latch to generate a control signal. According to a bias current of the external bias current source and the control signal outputted by the SR latch, periodic charging and discharging of a first capacitor and a second capacitor are controlled to generate oscillating signals. | 2020-03-19 |
20200091898 | SEMICONDUCTOR DEVICE AND CONTROL METHODS THEREOF - A semiconductor device includes a first oscillator circuit, a clock monitoring circuit and a timing signal generation circuit for periodically switching the operating mode of the clock monitoring circuit to one of the first to third modes. The clock monitoring circuit includes: a clock counter configured for counting the number of oscillations of the clock signal in the first mode and configured for shifting the pulses of the input signal to the output signal at normal time in the third mode; a comparison circuit for comparing whether the count value per predetermined period by the clock counter is within an expected value in the second mode; and an edge detection circuit for detecting whether the pulses of the input signal are shifted to the output signal of the clock counter in the third mode. | 2020-03-19 |
20200091899 | EQUALIZING CIRCUIT AND RECEIVER - An equalizing circuit may include a first signal line, a second signal line, a first current source, a first switch, a second switch, a second current source, a third switch, and a fourth switch. The second signal line forms a differential pair with the first signal line. The first switch connects the first signal line and the first current source. The second switch connects the second signal line and the first current source. The third switch connects the first signal line and the second current source. The fourth switch connects the second signal line and the second current source. | 2020-03-19 |
20200091900 | BALANCED FREQUENCY DOUBLER - The invention inter alia relates to a balanced frequency doubler comprising a first frequency doubler unit providing a first input port and a second input port, a second frequency doubler unit providing a third input port and a fourth input port, wherein the first, second, third and fourth input port are configured to receive a first, second, third and fourth input signal, respectively, wherein the first, second, third and fourth input signals all have the same first harmonic frequency, but are phase-shifted relative to one another, wherein a first current, the frequency spectrum of which comprises a second harmonic frequency that is double the first harmonic frequency, is driven through the first frequency doubler unit in response to the first and second input signal, wherein a second current, the frequency spectrum of which also comprises the second harmonic frequency, is driven through the second frequency doubler unit in response to the third and fourth input signals, and wherein a balanced output signal of the frequency doubler is influenced by the first and second current. | 2020-03-19 |
20200091901 | GLITCH-FREE CLOCK GENERATOR AND METHOD FOR GENERATING GLITCH-FREE CLOCK SIGNAL - A clock generator that generates an output clock signal, includes a clock generating circuit that generates an internal clock signal, first and second filter circuits, and an output gate. The first filter circuit receives the internal clock signal and an enable signal, and provides a first filtered enable signal in response to the enable signal having a duration of at least two cycles of the clock signal. The second filter circuit receives the first filtered enable signal, provides a second filtered enable signal in response to the first filtered enable signal, and provides a delayed signal that is a delayed version of the second filtered enable signal. The output gate receives the internal clock signal from the clock generating circuit and the second filtered enable signal from the second filter circuit, and generates the output clock signal. | 2020-03-19 |
20200091902 | DEVICE INCLUDING MULTI-MODE INPUT PAD - A circuit component has an address determined from a voltage level applied to a single electrical contact of the circuit component. The circuit component is configured to be assigned one of at least three unique addresses and to select from among the at least three unique addresses based on the voltage level. | 2020-03-19 |
20200091903 | COMPARATOR CIRCUITRY - A comparator circuitry includes an input pair circuit, a load circuit, and a compensation circuit. The input pair circuit is configured to compare a first input signal with a second input signal, in order to control a first bias current. The load circuit is coupled to the input pair circuit, and is configured to output an output signal having a first level from a first output terminal of the load circuit in response to the first bias current. The compensation circuit is coupled to the input pair circuit and the load circuit, and is configured to drain a compensation current from the first output terminal to a voltage source during the load circuit generates the output signal having a first level, in which the voltage source is configured to provide a voltage having a second level. | 2020-03-19 |
20200091904 | SYSTEM AND METHOD FOR ANTI-AMBIPOLAR HETEROJUNCTIONS FROM SOLUTION-PROCESSED SEMICONDUCTORS - Van der Waals heterojunctions are extended to semiconducting p-type single-walled carbon nanotube (s-SWCNT) and n-type film that can be solution-processed with high spatial uniformity at the wafer scale. The resulting large-area, low-voltage p-n heterojunctions can exhibit anti-ambipolar transfer characteristics with high on/off ratios. The charge transport can be efficiently utilized in analog circuits such as frequency doublers and keying circuits that are widely used, for example, in telecommunication and wireless data transmission technologies. | 2020-03-19 |
20200091905 | GATE DRIVER WITH CONTINUOUSLY-VARIABLE CURRENT - Circuits, methods, and systems are provided for setting a current level to be used by a current-mode gate driver. The current level may be used to source, sink, or both source and sink current to/from the gate terminal of a power device. The current level is based upon a current or voltage level input from an analog current-setting terminal. This input current or voltage level may take a value from a continuous range of current or voltage values. | 2020-03-19 |
20200091906 | ELECTRONIC CIRCUIT - According to one embodiment, an electronic circuit includes: a current supply circuit, a detection circuit, a timing generation circuit, a sample hold circuit and a calculation circuit. The current supply circuit supplies a sine wave current for measurement to a gate terminal of a semiconductor switching device. The detection circuit detects a sine wave voltage generated in response to supply of the sine wave current to generate a detection signal. The timing generation circuit counts cycles of the sine wave voltage. The sample hold circuit samples the detection signal at a timing depending on a count value of the timing generation circuit. The calculation circuit calculates a gate resistance of the semiconductor switching device based on the sampled voltage. | 2020-03-19 |
20200091907 | ELECTRONIC CIRCUIT - According to one embodiment, an electronic circuit includes a plurality of first transistors, a control circuit, a sample hold circuit and a calculation circuit. The control circuit selectively performs a first operation and a second operation, the first operation supplying a driving control signal to a gate terminal of a semiconductor switching element using the plurality of first transistors, and the second operation supplying a pulse current for measurement to the gate terminal using part of the plurality of first transistors. The sample hold circuit samples a voltage of the gate terminal during a period in which the pulse current is supplied to the gate terminal in the second operation. The calculation circuit calculates a gate resistance of the semiconductor switching element based on the sampled voltage. | 2020-03-19 |
20200091908 | PULSE GENERATOR AND CONSUMPTION METER - A pulse generator has a galvanically isolated output, in particular for a consumption meter. A control output of a control unit of the pulse generator is coupled to an input of an opto-isolator of the pulse generator in order to output at the output of the opto-isolator an output current controlled by the control unit. The opto-isolator is connected to a field-effect transistor in such a way that the output current from the opto-isolator charges a capacitor via a rectifying component, which blocks the capacitor from discharging via the opto-isolator. The voltage drop across the capacitor is the gate voltage of the field-effect transistor. The field-effect transistor switches the output of the pulse generator directly or indirectly. | 2020-03-19 |
20200091909 | SEMICONDUCTOR DEVICE FOR RADIO FREQUENCY SWITCH, RADIO FREQUENCY SWITCH, AND RADIO FREQUENCY MODULE - Provided is a semiconductor device for radio frequency switch that includes an SOI substrate and a gate electrode. The SOI substrate includes a buried oxide film and a semiconductor layer on a carrier substrate. The gate electrode is provided on the semiconductor layer. The semiconductor layer includes a first area below the gate electrode and a second area other than the first area. A third area is provided in at least part of the second area. A fourth area is provided in at least part of the first area. The fourth area has a different thickness from a thickness of the third area. | 2020-03-19 |
20200091910 | SEMICONDUCTOR MODULE - A semiconductor module according to embodiments includes a first external terminal, a second external terminal, a first semiconductor switch which is electrically connected between the first external terminal and the second external terminal and includes a first gate electrode, a second semiconductor switch which is electrically connected in parallel with the first semiconductor switch, between the first external terminal and the second external terminal, and includes a second gate electrode, a first fuse electrically connected between the first external terminal and the first semiconductor switch, and a second fuse electrically connected between the second external terminal and the first semiconductor switch. | 2020-03-19 |
20200091911 | SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING SEMICONDUCTOR DEVICE - A semiconductor device includes a main switching circuit implemented by a first semiconductor element and a second semiconductor element having a semiconductor region of a first conductivity type as a common region, including respectively a first well region of a second conductivity type and a second well region of a second conductivity type provided in an upper portion of the common region, the first semiconductor element being provided with a first source region of the first conductivity type in an upper portion of the first well region, the second semiconductor element being provided with a second source region of the first conductivity type in an upper portion of the second well region; and a drive circuit configured to independently apply a first drive signal and a second drive signal respectively to a control electrode of the first semiconductor element and a control electrode of the second semiconductor element. | 2020-03-19 |
20200091912 | LEVEL SHIFTING CIRCUIT AND INTEGRATED CIRCUIT - A level shifting circuit includes a first inverter, a second inverter, and a third inverter which are connected in a cascade. The first inverter operates at a first power supply voltage supplied to a first power supply line, and the third inverter operates at a second power supply supplied to a second power supply line. The second inverter includes a first p-type transistor having a source connected to the first power supply line, a second p-type transistor having a source connected to the second power supply line, and a first n-type transistor having a source connected to a ground line. Each gate of the first and second p-type transistors and the first n-type transistor is connected to an output terminal of the first inverter, and each drain of the first and second p-type transistors and the first n-type transistor is connected to an input terminal of the third inverter. | 2020-03-19 |
20200091913 | SEMICONDUCTOR DEVICE - A semiconductor device includes first, second and third semiconductor regions, each surrounded by an element isolation layer, first and second transistors of the first semiconductor region connected in parallel between first and second nodes, a third transistor of the second semiconductor region between the second node and the first transistor, and a fourth transistor of the third semiconductor region between the second node and the second transistor. Gates of the first and second transistors extend in a first direction and are spaced from each other in a second direction. A first distance which is equal to a longer of two distances between the element isolation layer and the gate electrode of the first transistor in the second direction, is greater than a second distance which is equal to a longer of two distances between the element isolation layer and the gate electrode of the third transistor in the second direction. | 2020-03-19 |
20200091914 | RECONFIGURABLE CIRCUIT USING NONVOLATILE RESISTIVE SWITCHES - A reconfigurable circuit includes: a plurality of first lines; one or more second lines; a non-volatile resistive cell coupling one of the first lines with one of the second lines at each cross-point between the first lines and the second lines; and first switch elements including first terminals respectively coupled to the first lines, wherein each of the first switch elements is separately turned on or off in accordance with a control signal applied thereto. | 2020-03-19 |
20200091915 | SEMICONDUCTOR INTEGRATED CIRCUIT AND RECONFIGURABLE SEMICONDUCTOR SYSTEM - A semiconductor integrated circuit includes a plurality of logic circuits each being configurable to perform a logic function according to configuration data set therein, a memory that stores configuration information for use in setting the configuration data in each of the plurality of logic circuits, a test circuit configured to perform a test for detecting an error in each logic circuit, and an output circuit configured to output information indicating whether the error exists in one or more of the logic circuits based on a result of the test. In response to the output of the information indicating that the error exists, the configuration information stored in the memory is updated with new configuration information for setting the configuration data of each of the logic circuits other than one or more logic circuits having the error. | 2020-03-19 |
20200091916 | HIGHSPEED/LOW POWER SYMBOL COMPARE - An integrated circuit includes a pipeline of compare logic stages. The pipeline, at successive pipeline stages, determines whether each of a set of input symbols meets a corresponding programmable criteria. The compare logic stages each compare the set of input symbols to a respective programmable value. The compare logic stages also each provide, to a respective successive compare logic stage, a corresponding plurality of indicators of whether respective ones of the set of input symbols met the corresponding programmable criteria for that compare logic stage. The corresponding programmable criteria are configurable to be based at least in part on the corresponding plurality of indicators from a respective previous compare logic stage. | 2020-03-19 |
20200091917 | OSCILLATOR CIRCUIT AND ASSOCIATED OSCILLATOR DEVICE - The present invention provides an oscillator circuit and associated oscillator device. The oscillator circuit comprises a negative-temperature-coefficient (NTC) bias current generating circuit and a set of oscillator sub-block circuits. The NTC bias current generating circuit is coupled between a supply voltage and a ground voltage, and is arranged to generate at least one NTC bias current. The set of oscillator sub-block circuits are coupled to each other to form an oscillator. Each oscillator sub-block circuit of the set of oscillator sub-block circuits comprises a plurality of transistors coupled between the supply voltage and a node within the NTC bias current generating circuit, wherein the NTC bias current generating circuit and the aforementioned each oscillator sub-block circuit share at least one transistor in the plurality of transistors. | 2020-03-19 |
20200091918 | Frequency Synthesis with Accelerated Locking - An apparatus is disclosed that implements frequency synthesis with accelerated locking. In an example aspect, the apparatus includes an oscillating signal source, a modulus compensator, and a frequency generator. The oscillating signal source is configured to provide a reference signal having a reference frequency. The modulus compensator is coupled to the oscillating signal source and is configured to receive the reference signal. The modulus compensator is configured to produce a compensated modulus value based on the reference frequency, a fixed oscillator frequency of a fixed-frequency oscillator signal, and a modulus value. The frequency generator is coupled to the oscillating signal source and the modulus compensator and is configured to receive the compensated modulus value. The frequency generator is configured to generate an output signal having an output frequency that is based on the reference frequency and the compensated modulus value. | 2020-03-19 |
20200091919 | HYBRID PHASE LOCK LOOP - Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operational mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operational mode of the hybrid PLL. | 2020-03-19 |
20200091920 | FREQUENCY GENERATOR AND ASSOCIATED METHOD - A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) obtained according to the estimated DCO normalization value. An associated method is also disclosed. | 2020-03-19 |
20200091921 | FREQUENCY SYNTHESIS DEVICE WITH HIGH MULTIPLICATION RANK - A frequency synthesis device with high multiplication rank, including a base frequency generator generating two first base signals of square shape of same frequency and opposite to each other, a first synthesis stage including two first switching power supply oscillators, of which the power supplies are respectively switched by the two first base signals, a second synthesis stage including a second switching power supply oscillator of which the supply is switched by a combination of the output signals of the two first oscillators, the output of the second switching power supply oscillator being filtered by a frequency discriminator circuit realized with an injection locked oscillator. | 2020-03-19 |
20200091922 | DEVICE FOR ADJUSTING THE LOCKING OF AN INJECTION LOCKED FREQUENCY MULTIPLIER - Device for adjusting the locking of an injection locked frequency multiplier, including:
| 2020-03-19 |
20200091923 | Digital-to-Analog Converter Transfer Function Modification - The present disclosure relates to a digital-to-analog converter (DAC) which includes a resistor string and a transfer function modification circuit. The transfer function modification circuit may be a calibration circuit for calibrating the DAC, The calibration circuit may include a plurality of current sources, which may be current DACs. Each of the current DACS inject current into, or drain current from, a respective node of the resistor string, in order to correct for voltage errors. The injected currents may be positive or negative, depending on the voltage error. The current DACs are controlled by trim codes, which are set dependent on the measured or simulated voltage errors for a given resistor string. | 2020-03-19 |
20200091924 | Pipelined analog-to-digital converter - The present invention discloses a pipelined analog-to-digital converter (ADC) including a sub-ADC, a multiplying digital-to-analog converter (MDAC) and a decoder. The decoder provides a ground signal for the MDAC. The sub-ADC is electrically connected to a ground pad via a first metal trace, and the decoder is electrically connected to the ground pad via a second metal trace. | 2020-03-19 |
20200091925 | Control circuit and control method of successive approximation register analog-to-digital converter - This invention discloses a control circuit and a control method of a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC includes a comparator and a switched-capacitor digital-to-analog converter (DAC). The control circuit includes a memory, an inverter and a data path. The memory is configured to store an output value of the comparator. The inverter has an output coupled to a first end of a capacitor of the switched-capacitor DAC. A second end of the capacitor is coupled to an input of the comparator. The data path, coupled between an output of the comparator and an input of the inverter, temporarily causes a voltage at the first end of the capacitor to be controlled by the output value of the comparator. The data path does not contain any memory. | 2020-03-19 |
20200091926 | Successive approximation register analog-to-digital converter and control circuit thereof - This invention discloses a successive approximation register analog-to-digital converter (SAR ADC) and a control circuit thereof. The SAR ADC includes a comparator, a switched-capacitor digital-to-analog converter (DAC), and a control circuit. The switched-capacitor DAC includes a capacitor and a driving circuit that is electrically connected to the capacitor. The driving circuit comprises a P-type MOSFET and an N-type MOSFET, and the gates of the two MOSFETs are not electrically connected. The P-type MOSFET is controlled by a first control signal, and the N-type MOSFET is controlled by a second control signal. The control circuit controls the voltage at one end of the capacitor to switch from a high voltage level to a low voltage level by controlling the rising edge of the first control signal to lead the rising edge of the second control signal. | 2020-03-19 |
20200091927 | DAC AND OSCILLATION CIRCUIT - The present technology relates to a DAC (Digital to Analog Converter) and an oscillation circuit that allow widening of a range of a voltage to be output from the DAC. A plurality of first switches is connected to a voltage-dividing resistor and each configured to output, as a first voltage, a voltage at a corresponding one of connection points between the voltage-dividing resistor and the plurality of first switches. A plurality of second switches is connected to the voltage-dividing resistor and each configured to output, as a second voltage, a voltage at a corresponding one of connection points between the voltage-dividing resistor and the plurality of second switches. The present technology can be applied to, for example, a VCO (Voltage-Controlled Oscillator) and the like that oscillates a signal with a frequency according to a voltage to be output from a DAC. | 2020-03-19 |
20200091928 | DIGITAL TO ANALOG CONVERTER, METHOD FOR DRIVING THE SAME, AND DISPLAY DEVICE - A digital to analog converter, a method for driving the same, and a display device are provided. The digital to analog converter includes: a first resistor string, 2 | 2020-03-19 |
20200091929 | Correction method and correction circuit for sigma-delta modulator - A correction method and a correction circuit for a sigma-delta modulator (SDM) are disclosed. The SDM includes a loop filter, a quantizer, and a digital-to-analog converter (DAC), and the loop filter includes a resonator. The correction circuit includes a memory and a control circuit. The memory stores multiple program instructions. The control circuit executes the program instructions to correct the SDM. The correction procedure of the SDM includes the following steps: inputting a test signal to the SDM; obtaining a signal characteristic value of an output signal of the SDM; and adjusting the resonator according to the signal characteristic value. | 2020-03-19 |
20200091930 | FLOATING POINT DATA SET COMPRESSION - Computer-implemented methods, systems, and devices to perform lossless compression of floating point format time-series data are disclosed. A first data value may be obtained in floating point format representative of an initial time-series parameter. For example, an output checkpoint of a computer simulation of a real-world event such as weather prediction or nuclear reaction simulation. A first predicted value may be determined representing the parameter at a first checkpoint time. A second data value may be obtained from the simulation. A prediction error may be calculated. Another predicted value may be generated for a next point in time and may be adjusted by the previously determined prediction error (e.g., to increase accuracy of the subsequent prediction). When a third data value is obtained, the adjusted prediction value may be used to generate a difference (e.g., XOR) for storing in a compressed data store to represent the third data value. | 2020-03-19 |
20200091931 | EMBEDDED CYCLICAL REDUNDANCY CHECK VALUES - A method and a device for generating a data packet to be transmitted comprising data and at least one value for a cyclic redundancy check (CRC) value, are described, wherein the CRC value is generated using at least one previously determined polynomial on the basis of at least some of the data and the method comprises initializing a counter value, counting units of data, wherein the counter value changes for each unit of data, and adding a CRC value into the data packet, when the counter value reaches a reference value or all units of data in the data packet have already been counted, wherein the CRC value is generated over the units of data which have been counted since the counter value last reached the reference value or since the counter value was initialized. Furthermore, a method and a device for checking a corresponding received data packet are described. | 2020-03-19 |
20200091932 | BIT BLOCK STREAM BIT ERROR DETECTION METHOD AND DEVICE - A method includes: sending a first boundary bit block; sequentially sending an I | 2020-03-19 |
20200091933 | Iterative decoding with early termination criterion that permits errors in redundancy part - An apparatus includes an interface and a decoder. The interface is configured to receive a code word, produced in accordance with an Error Correction Code (ECC) represented by a set of parity check equations. The code word includes a data part and a redundancy part, and contains one or more errors. The decoder is configured to hold a definition of a partial subgroup of the parity check equations that, when satisfied, indicate that the data part is error-free with a likelihood of at least a predefined threshold, to decode the code word by performing an iterative decoding process on the parity check equations, so as to correct the errors, and during the iterative decoding process, to estimate whether the data part is error-free based only on the partial subgroup of the parity check equations, and if the data part is estimated to be error-free, terminate the iterative decoding process. | 2020-03-19 |
20200091934 | INFORMATION PROCESSING METHOD AND COMMUNICATIONS APPARATUS - This application discloses an information processing method and apparatus, a communications device, and a communications system. The method includes: encoding an input sequence by using a low-density parity-check (LDPC) matrix, to obtain a bit sequence D, where a base matrix of the LDPC matrix is represented as a matrix of m rows and n columns, each column corresponds to a group of Z consecutive bits in the bit sequence D, and n and Z are both integers greater than 0; and obtaining an output bit sequence based on a bit sequence V, where the bit sequence V is obtained by permuting two groups of bits corresponding to at least two parity check columns in the bit sequence D. | 2020-03-19 |
20200091935 | CODING METHOD, WIRELESS DEVICE, AND CHIP - A coding method, a wireless device, and a chip are described. A coding method may include obtaining, based on a sequence whose length is 2 | 2020-03-19 |
20200091936 | Polar Code Encoding Method and Apparatus - A polar code encoding method and apparatus are provided, to improve accuracy of reliability sorting of polar channels. The method is: determining a sorted sequence used to encode to-be-encoded bits, where the sorted sequence is used to represent reliability sorting of N polar channels, N is a mother code length of a polar code, and N is a positive integer power of 2; and performing polar code encoding on the to-be-encoded bits by using the sorted sequence, to obtain encoded bits. | 2020-03-19 |
20200091937 | GENERATING HAMMING WEIGHTS FOR DATA - Embodiments herein provide for a controller that is operable to soft read a data bit a plurality of times, to generate a bit set for the data bit from the soft reads, to logically operate on the bit set, and to generate a Hamming weight for the data bit based on the logical operation. The Hamming weight has fewer bits than the bit set and is operable to correct the data bit. | 2020-03-19 |
20200091938 | METHODS AND SYSTEMS FOR TRANSCODER, FEC AND INTERLEAVER OPTIMIZATION - An interleaved encoder includes a number of encoders consisting of L parallel encoders, and a first switch circuit to sequentially couple an input node to an input port of one of the encoders. The input node receives a group of K*L symbols. Each symbol of the group of K*L symbols is received in synch with a respective clock pulse of a group of K*L clock pulses. The first switch circuit is synched with clock pulses of the group of K*L clock pulses, and sequentially couples the input node to an input port of a subsequent one of the encoders in response to each clock pulse of the group of K*L clock pulses. | 2020-03-19 |
20200091939 | ENCODER, ASSOCIATED ENCODING METHOD AND FLASH MEMORY CONTROLLER - An encoding method includes: processing a plurality of data blocks to generate a plurality of partial parity blocks, wherein the partial parity blocks includes a first portion and a second portion; using a first computing circuit to generate a first calculating result according to the second portion of the partial parity blocks; using the first calculating result to adjust the first portion of the partial parity blocks; performing circulant convolution operations upon the adjusted first portion to generate a first portion of parity blocks; and using a second computing circuit to generate a second portion of the parity blocks according to at least the first portion of parity blocks; wherein the first portion of the parity blocks and the second portion of the parity blocks serve as a plurality of parity blocks generated in response to encoding the data blocks. | 2020-03-19 |
20200091940 | CLOUD-BASED SOLID STATE DEVICE (SSD) WITH DYNAMICALLY VARIABLE ERROR CORRECTING CODE (ECC) SYSTEM - Example apparatus and methods control an error correcting code (ECC) approach for data stored on a solid state device (SSD). The control may be based on a property (e.g., reliability, error state, speed) of an SSD, or on an attribute of the data to be stored. Approaches including a hybrid rateless Reed-Solomon ECC approach or a fountain code ECC approach may be selected. Example apparatus and methods may store padded portions of an ECC at different locations in an SSD. Example apparatus and methods may dynamically generate performance test data about the SSD, and dynamically control the ECC approach based on the performance test data. Different types or numbers of ECC may be produced, stored, and provided for different data sets stored at different SSDs or at different physical locations within an SSD. The SSD may be local, or may be part of a cloud-based storage system. | 2020-03-19 |
20200091941 | MEMORY SYSTEM AND DECODING METHOD - According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller calculates a reliability metric on the basis of at least a soft-decision input value calculated on the basis of read information that is read from the nonvolatile memory, and a decoded word, stores reference information that is a history of a plurality of reliability metrics or statistical information obtained from the history, calculates reliability from the reliability metric by using correspondence information, calculates decoding information on the basis of the decoded word and the reliability, and updates the correspondence information on the basis of the reference information. | 2020-03-19 |
20200091942 | MEMORY SYSTEM - A memory system includes a nonvolatile memory and a memory controller, which determines a read voltage for first data encoded by a first encoding scheme from the nonvolatile memory, by generating a first histogram indicating the number of memory cells for each threshold voltage, and estimating the read voltage using: (a) the first histogram that is corrected based on a first parameter, which is a parameter of the first encoding scheme and a second parameter, which is a parameter of a second encoding scheme, and an estimation function for estimating a read voltage for second data encoded by the second encoding scheme, (b) the uncorrected first histogram, and the estimation function that is corrected based on the first and second parameters, or (c) the first histogram after partial correction based on the first and second parameters, and the estimation function after partial correction based on the first and second parameters. | 2020-03-19 |
20200091943 | BUTTERFLY NETWORK ON LOAD DATA RETURN - A method is shown that is operable to transform and align a plurality of fields from an input to an output data stream using a multilayer butterfly or inverse butterfly network. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits. | 2020-03-19 |
20200091944 | Technique For Generating a Protocol Data Unit Signal - A technique for generating a radio signal ( | 2020-03-19 |
20200091945 | WIRELESS SENSOR NODE WITH HIERARCHICAL PROTECTION STRUCTURE - The present invention discloses a wireless sensor node with a hierarchical protection structure, including a node hardware circuit and a node hierarchical protection structure. The node hardware circuit includes a sensor module, a data processor module and a wireless communication module, and the node hierarchical protection structure includes a primary sealed protection structure and a secondary strengthened protection structure; the primary sealed protection structure includes an ABS spherical inner shell; the data processor module and the wireless communication module are disposed in the ABS spherical inner shell; gaps in the ABS spherical inner shell are filled with EPE cushioning foam; a flame-retardant and thermal-insulating layer made of a nanometer aerogel insulation blanket is covered on the outside of the ABS spherical inner shell; the secondary strengthened protection structure includes a spherical nylon outer shell with vent holes; the spherical nylon outer shell and the ABS spherical inner shell are connected with each other through support of rubber dampers; and the sensor module is disposed in the spherical nylon outer shell. The node according to the present invention can be deployed by ejection, is highly adaptive to catastrophes, can acquire environmental information effectively, and has relatively low costs. | 2020-03-19 |
20200091946 | Radio Frequency Transmitter - A radio frequency transmitter includes a digital-to-analog converter, a passive network, two buffers, a frequency mixer, and a power amplifier. Two output ends of the digital-to-analog converter are respectively coupled to two input nodes of the passive network, and the two output ends of the digital-to-analog converter are respectively coupled to input ends of the two buffers. Output ends of the two buffers are respectively coupled to two input ends of the frequency mixer. An output end of the frequency mixer is coupled to an input end of the power amplifier. An output end of the power amplifier is coupled to an antenna. The passive network is configured to perform filtering processing on an input current signal, and convert the current signal into a voltage signal. | 2020-03-19 |
20200091947 | DIGITAL SIGNAL CONDITIONER SYSTEM - One example includes a digital signal conditioner (DSC) system. A sample selector bank receives a digital sample block of an input signal that is provided at a supported input oversampling factor and selects a subset of samples from the digital sample block based on a selection signal. A tap weights selector bank generates a set of tap weights based on the selection signal. A filter bank receives the subset of the samples from each of the sample selectors and a respective set of tap weights. Each filter provides a weighted sample associated with the respective subset of samples and the respective set of tap weights. A reformattor receives the weighted sample from each of the filters and provides a filtered sample block including the weighted sample from a subset of the filters at an output oversampling factor for each supported input oversampling factor based on a selected supported resampling ratio. | 2020-03-19 |
20200091948 | REDUCING INTERFERENCE IN RADIO BROADCAST BANDS - In one example, the present disclosure describes a device, computer-readable medium, and method for reducing interference on the frequency modulation (FM) radio broadcast band from the G.fast protocol standard spectrum. For instance, in one example, a method includes delivering broadband service to a customer over a spectrum that overlaps with a frequency modulation radio broadcast band, and applying a notch filter to a target frequency of the frequency modulation radio broadcast band based on a profile that is customized for the customer, wherein the notch filter prevents the broadband service from using the target frequency during the delivering. | 2020-03-19 |
20200091949 | SLIDING INTERMEDIATE-FREQUENCY RECEIVER - This disclosure provides an apparatus for receiving and demodulating a radio frequency signal with a sliding intermediate frequency (IF) receiver. The sliding IF receiver may include a local oscillator (LO) and a clock divider, and a logic block. The clock divider may be configured to generate a first divided LO signal and a second divided LO signal based on an LO signal. The logic block may be configured to generate a first composite LO signal and a second composite LO signal. The first composite LO signal may be based on the first divided LO signal and the LO signal. The second composite LO signal may be based on the second divided LO signal and the LO signal. The first and the second composite LO signals may be used to demodulate a received RF signal and generate baseband signals. | 2020-03-19 |
20200091950 | TELEPHONE HANDSET CONTAINING A REMEDIAL DEVICE - A remedial signal for potentially harmful radiation that is emitted by a portable electronic battery powered communication device is implemented directly within the handset of the portable communication device the portable communication device is operated by a microprocessor ( | 2020-03-19 |
20200091951 | INCONSPICUOUS SUPPORT SYSTEM FOR PROPPING AND SUSPENDING MOBILE COMPUTING DEVICES TO MULTIPLE ANGLES AND ORIENTATIONS WITH RESPECT TO A RESTING SURFACE OR BASE - An inconspicuous support system of angled and straight cavities for latching support elements, such as a stylus, an independent arm, or plate; or support structures, such as a desktop stand, a floor stand, a hook, or a plurality of hooks, to mobile computing devices and its use to prop and to suspend these devices to multiple angles and orientations with respect to a resting surface or base. | 2020-03-19 |
20200091952 | SPRING-LOADED FALL PROTECTOR FOR PREVENTING A MOBILE TERMINAL DEVICE FROM FALLING - A housing for an electronic device includes at least one damping unit which is movable between a retracted position and an extended position, the damping unit including a spring and a damper, at least one sensor which is configured to detect a fall of the electronic device, a release unit which is configured to cause the at least one damping unit to move from the retracted position to the extended position when the fall is detected, the spring and the damper being configured to change their shape when moving from the retracted position to the extended position. | 2020-03-19 |
20200091953 | BASE STATION ANTENNAS HAVING TRANSMITTERS AND RECEIVERS THEREIN THAT SUPPORT TIME DIVISION DUPLEXING (TDD) WITH ENHANCED BIAS CONTROL FOR HIGH SPEED SWITCHING - Base station antennas utilize RF transmitters and receivers, which operate with enhanced bias control to achieve very high speed switching during TDD operation. A radio frequency communication circuit for TDD includes a transmit/receive amplifier (e.g., MMIC) having first and second input terminals, which are responsive to a bias control voltage and radio frequency input signal. A bias control circuit is provided, which is electrically coupled to the first input terminal and a current receiving terminal of the transmit/receive amplifier. The bias control circuit includes a closed-loop feedback path between the current receiving terminal and the first input terminal, which is configured to regulate a magnitude of the bias control voltage with high precision to thereby achieve a substantially constant quiescent bias current at the current receiving terminal when the transmit/receive amplifier is enabled. | 2020-03-19 |
20200091954 | DISCRETE SPECTRUM TRANSCEIVER - A discrete spectrum (DS) signal transmitter includes a first circuit element comprising a DS signal generator that generates a plurality of DS signals, each DS signal having a different DS frequency, each DS frequency being (a) a harmonic of a fundamental frequency or (b) the fundamental frequency. A second circuit element receives as an input the DS signals and that generates as an output (a) a finite summation of the DS signals or (b) pulses that represent a mathematical equivalent of a summation of an infinite number of the DS signals. An antenna is electrically coupled to an output of the second circuit element. The analog DS signals transmitted by the DS signal transmitter are received by a DS signal receiver that converts the analog DS signals to DS discrete signals and performs a fast Fourier transform of the DS discrete signals. | 2020-03-19 |
20200091955 | SECOND-ORDER HARMONIC REDUCTION FOR RADIO FREQUENCY TRANSMITTER - Certain aspects of the present disclosure provide methods and apparatus for simultaneous multi-band transmission, including techniques and circuitry for reducing the coupling of a second-order harmonic signal into a victim circuit. One example radio frequency front-end circuit generally includes a first transmit output stage circuit configured to output signals in a first frequency band and a second transmit output stage circuit configured to output signals in a second frequency band. The first transmit output stage circuit generally includes a first adjustable transconductance stage comprising an input stage and a cascode stage coupled to the input stage; and a first adjustable impedance stage coupled to the first adjustable transconductance stage. For certain aspects, the second transmit output stage circuit generally includes a second adjustable transconductance stage and a second adjustable impedance stage coupled to the second adjustable transconductance stage. | 2020-03-19 |
20200091956 | METHOD AND DEVICE FOR THE DETECTION OF A PULSE OF A SIGNAL - A method for the detection of a pulse of a signal received by a receiver device, the received signal corresponding to data emitted with a predetermined period T | 2020-03-19 |
20200091957 | Identifying Audio Characteristics of a Room Using a Spread Code - Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments, and/or combinations and sub-combinations thereof, for identifying audio characteristics of a room using a spread code. In some embodiments, an audio responsive receives a spread spectrum signal from a smart speaker over an audio data channel. The audio responsive remote control determines a time of receipt of the spread spectrum signal based on despreading. The audio responsive remote control calculates an airtime delay associated with the smart speaker based on the time of receipt and a time of transmission. The audio responsive remote control then adjusts playback of audiovisual content at the smart speaker and a second smart speaker for a location based on the airtime delay. The audio responsive remote control can also determine whether the smart speaker is present in the room with it based on the airtime delay. | 2020-03-19 |
20200091958 | Audio Synchronization of a Dumb Speaker and a Smart Speaker Using a Spread Code - Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments, and/or combinations and sub-combinations thereof, for synchronizing playback of audiovisual content with a dumb speaker. In some embodiments, a display device transmits a spread spectrum signal to a dumb speaker over a data channel using a spread spectrum code. The display device then receives the spread spectrum signal from the dumb speaker over an audio data channel. The display device despreads the spread spectrum signal based on the spreading code. The display device determines a time of receipt of the spread spectrum signal. The display device calculates an audiovisual output path delay for the dumb speaker based on the time of receipt and a time of transmission. The display device then synchronizes the playback of the audiovisual content at the dumb speaker and a smart speaker based on the audiovisual output path delay. | 2020-03-19 |
20200091959 | Wireless Audio Synchronization Using a Spread Code - Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments, and/or combinations and sub-combinations thereof, for synchronizing playback of audiovisual content among multiple speakers. In some embodiments, a first smart speaker receives a spread spectrum signal from a second smart speaker over an audio data channel. The first smart speaker despreads the spread spectrum signal based on a spreading code. The first smart speaker determines a time of receipt of the spread spectrum signal based on the despreading. The first smart speaker receives a time of transmission of the spread spectrum signal. The first smart speaker then calculates a playback delay based on the time of receipt and the time of transmission. Then the first smart speaker controls the playback of the audiovisual content based on the playback delay. | 2020-03-19 |
20200091960 | COMMUNICATION DEVICE, SPREAD-SPECTRUM RECEIVER, AND RELATED METHOD USING NORMALIZED MATCHED FILTER FOR IMPROVING SIGNAL-TO-NOISE RATIO IN HARSH ENVIRONMENTS - A communication device, a method of operating a communication device, and a spread-spectrum receiver are disclosed. The method includes receiving an incoming RF signal, demodulating the incoming RF signal to generate a baseband signal, filtering the baseband signal with a normalized matched filter having filter characteristics matched to a pulse-shaping filter of the transmitter that generated the incoming RF signal, and extracting a received signal from a normalized output generated by the normalized matched filter. As a result, interferences and noise from harsh environments may be suppressed. | 2020-03-19 |
20200091961 | METHOD AND APPARATUS FOR TRANSMITTING SIGNAL IN A WIRELESS COMMUNICATION SYSTEM - A method for transmitting a signal by a Device-to-Device (D2D) User Equipment (UE) in a wireless communication system includes mapping block of complex-valued symbols to Physical Resource Blocks (PRBs) based on a subband based-frequency hopping related to an uplink frequency hopping; generating a Single Carrier Frequency Division Multiple Access (SC-FDMA) signal; and transmitting the SC-FDMA signal. Further, a slot index for the subband based-frequency hopping is re-indexed based on subframe indexes re-indexed within a D2D resource pool based on the block of complex valued symbols for a D2D communication signal. | 2020-03-19 |
20200091962 | Methods and Apparatus for Signal Spreading and Multiplexing - Binary forward error correcting (FEC) encoding is applied to a stream of input bits, to generate a stream of coded bits. The coded bits are mapped to multiple binary streams. In some embodiments, at least one coded bit is mapped to more than one of the binary streams and none of the binary streams are identical to each other. Stream-specific modulations are applied to the binary streams. Non-binary FEC encoding could be applied after the stream-specific modulations. | 2020-03-19 |
20200091963 | ACOUSTIC ECHO CANCELLATION WITH ROOM CHANGE DETECTION - Acoustic echo cancelling includes receiving a source signal and a sink signal; providing a first error signal representative of an echo-free residual signal based on a first set of coefficients based on the source signal and the sink signal, the first error signal forming an output signal of the controller; providing a second error signal based on a second set of coefficients based on the source signal and the sink signal; detecting a room change if the evaluated first second error signal is greater than a sum or product of the evaluated second first error signal and a first threshold; copying one of sets of reference coefficients stored in a memory to the second acoustic echo canceller; and copying the first set of coefficients from the first acoustic echo canceller as a set of reference coefficients into at least one of the second acoustic echo canceller and the memory. | 2020-03-19 |
20200091964 | COMMUNICATIONS NETWORK FOR COMMUNICATION BETWEEN A POWER ELECTRONICS ELEMENT AND A CONTROL UNIT - A communications network for communication between at least one power electronics element and at least one control unit is disclosed. According to one or more embodiments, the communications network can be described as a communications network having parts or portions thereof employing multi-hop and/or hybrid communication. | 2020-03-19 |
20200091965 | ACTIVE NEAR-FIELD COMMUNICATION DEVICE FACILITATION OF LOW POWER CARD DETECTION - A device implementing a system for NFC communication includes a processor configured to receive, from an other device, pulse signals for detecting proximity of the device with the other device. The processor is further configured to determine an interval at which the pulse signals are received from the other device. The processor is further configured to determine a time when the other device is expected to transmit a subsequent pulse signal based at least in part on the determined interval. The processor is further configured to transmit a signal to the other device based on the determined time when the other device is expected to transmit the subsequent pulse signal. | 2020-03-19 |
20200091966 | POWER TRANSMISSION DEVICE, POWER TRANSMISSION METHOD, AND POWER TRANSMISSION SYSTEM - A power transmission device includes a communication unit that transmits a power capability information transmission request via a communication channel and receives power capability information in response to the power capability information transmission request. The power transmission device also includes a processing unit that sets a parameter based on the power capability information. Further, the power transmission device includes a power transmission unit that wirelessly transmits power using the parameter. The communication unit transmits the power capability information transmission request before the power transmission unit wirelessly transmits the power. | 2020-03-19 |