12th week of 2014 patent applcation highlights part 47 |
Patent application number | Title | Published |
20140080244 | METHOD FOR MANUFACTURING OPTICAL IMAGE STABILIZER EMPLOYING SCRATCH DRIVE ACTUATOR - A method for an optical image stabilizer including: providing an SOI wafer substrate which has a plurality of cells, the SOI wafer substrate including an insulating layer, and first and second silicon layers disposed on both sides of the insulating layer; forming scratch drive arrays and supporting members on each of the cells by etching the first silicon layer; forming the table through cells' separation by etching the second silicon layer and the insulating layer; removing the insulating layer interposed between the scratch drive arrays and the table; mounting the image sensor on the table; forming the substrate which has an electrode layer corresponding to the scratch drive arrays; and assembling the table with the image sensor and the scratch drive arrays on the substrate having the electrode layer in such a manner that the scratch drive arrays face the electrode layer each other. | 2014-03-20 |
20140080245 | METHOD FOR FABRICATING OPTICAL MICRO STRUCTURE AND APPLICATIONS THEREOF - A method for fabricating an image sensor, wherein the method comprises steps as follows: Firstly, a transparent substrate is formed on a working substrate. Pluralities of micro lens are formed in the transparent substrate, wherein the lenses have a refraction ratio differing from that of the transparent substrate. Subsequently, a color filter is formed on the lenses. Afterward, the color filter is engaged with an image sensing device by flipping around the working substrate. | 2014-03-20 |
20140080246 | MANUFACTURING METHOD FOR SOLAR CELL - The present invention reduces the time required to manufacture a solar cell. After etching main surfaces ( | 2014-03-20 |
20140080247 | METHOD OF PRODUCING SEMICONDUCTOR EPITAXIAL WAFER, SEMICONDUCTOR EPITAXIAL WAFER, AND METHOD OF PRODUCING SOLID-STATE IMAGE SENSING DEVICE - The present invention provides a method of more efficiently producing a semiconductor epitaxial wafer, which can suppress metal contamination by achieving higher gettering capability. | 2014-03-20 |
20140080248 | Optoelectronic Devices And Applications Thereof - In one aspect, optoelectronic devices are described herein. In some embodiments, an optoelectronic device comprises a fiber core, a radiation transmissive first electrode surrounding the fiber core, at least one photosensitive inorganic layer surrounding the first electrode and electrically connected to the first electrode, and a second electrode surrounding the inorganic layer and electrically connected to the inorganic layer. In some embodiments, the device comprises a photovoltaic cell. | 2014-03-20 |
20140080249 | HEAT TREATMENT BY INJECTION OF A HEAT-TRANSFER GAS - A heat treatment of a precursor that reacts with temperature, and that comprises in particular the steps of: preheating or cooling a heat-transfer gas to a controlled temperature, and injecting the preheated or cooled gas over the precursor. Advantageously, besides the temperature of the heat-transfer gas, the following are also controlled: the flow rate of the gas at the injection over the precursor, and also a distance between the precursor and an outlet for injection of the gas over the precursor, in order to finely control the temperature of the precursor receiving the injected gas. | 2014-03-20 |
20140080250 | Method of Fabricating High Efficiency CIGS Solar Cells - A method is disclosed for fabricating high efficiency CIGS solar cells including the deposition of a multi-component metal precursor film on a substrate. The substrate is then inserted into a system suitable for exposing the precursor to a chalcogen to form a chalcogenide TFPV absorber. One or more Na precursors are used to deposit a Na-containing layer on the precursor film in the system. This method eliminates the use of dedicated equipment and processes for introducing Na to the TFPV absorber. | 2014-03-20 |
20140080251 | HYBRID POLYSILICON HETEROJUNCTION BACK CONTACT CELL - A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells. | 2014-03-20 |
20140080252 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - A solid-state imaging device including a substrate, a through-hole, a vertical gate electrode, and a charge fixing film. A photoelectric conversion unit generating signal charges in accordance with the amount of received light is formed in the substrate. The through-hole is formed from a front surface side through a rear surface side of the substrate. The vertical gate electrode is formed through a gate insulating film in the through-hole and reads out the signal charges generated by the photoelectric conversion unit to a reading-out portion. The charge fixing film has negative fixed charges formed to cover a portion of the inner circumferential surface of the through-hole at the rear surface side of the substrate while covering the rear surface side of the substrate. | 2014-03-20 |
20140080253 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes the steps of: forming a gate electrode over a substrate; forming a gate insulating film over the gate electrode; forming an oxide semiconductor film; performing heat treatment to form a second oxide semiconductor film after the step of forming the first oxide semiconductor film; forming a first conductive film; forming a first resist mask including regions whose thicknesses are different; etching the second oxide semiconductor film and the first conductive film using the first resist mask to form a third oxide semiconductor film and a second conductive film; reducing the size of the first resist mask to form a second resist mask; selectively etching the second conductive film using the second resist mask to remove a part of the second conductive film so that a source electrode and a drain electrode are formed. | 2014-03-20 |
20140080254 | Fabricating Method Of Thin Film Transistor, Fabricating Method Of Array Substrate And Display Device - An embodiment of the present invention provides a fabricating method of a thin film transistor, a fabricating method of an array substrate, and a display device. The fabricating method of a thin film transistor comprises: forming a gate electrode on a substrate; and forming a gate insulating layer, a semiconductor layer, source and drain electrodes and a channel region on the substrate, wherein, the semiconductor layer is formed of a metal oxide, and two etching steps are used to form the channel region, and in a first etching step, a part of a source-drain metal layer above the semiconductor layer corresponding to the channel region is removed by using a dry etching, and in a second etching step, a remaining part of the source-drain metal layer above the semiconductor layer corresponding to the channel region is removed by using a wet etching, thereby forming the channel region. | 2014-03-20 |
20140080255 | ULTRA-LOW POWER SWNT INTERCONNECTS FOR SUB-THRESHOLD CIRCUITS - Ultra-low power single metallic single-wall-nano-tube (SWNT) interconnects for sub-threshold circuits are provided. According to some embodiments, an interconnect structure for use in electronic circuits can generally comprise a first substrate, a second substrate, and an interconnect. The first substrate can be spaced apart from the second substrate. The interconnect is preferably a single wall carbon nanotube (SWNT) interconnect. The SWNT interconnect can be disposed between the first and second substrates to electrically connect the substrates. The substrates can form parts of electrical components (e.g., a transistor, processor, memory, filters, etc.) operating in a subthreshold operational state. Other aspects, features, and embodiments are claimed and described. | 2014-03-20 |
20140080256 | METHOD FOR MANUFACTURING PACKAGE STRUCTURE WITH ELECTRONIC COMPONENT - A fabrication method of manufacturing a package a plurality of electronic components in an encapsulation body, firstly, mounting the plurality of electronic components and one ends of a plurality of metal resilient units on a substrate. After that, the plurality of electronic components and the plurality of metal resilient units are encapsulated on the substrate to form an encapsulation body with another ends of the plurality of metal resilient units exposed on an exterior surface of the encapsulation body. Then etching remaining epoxy resin on the other ends of the plurality of metal resilient units. | 2014-03-20 |
20140080257 | METHOD FOR NON-PLANAR CHIP ASSEMBLY - Methods and apparatuses for assembly of a non-planar device based on curved chips are described. Slots may be created as longitudinal openings in the chips to reduce bending stresses to increase allowable degrees of deformation of the chips. The chips may be deformed to a desired deformation within the allowable degrees of deformation via the slots. Holding constraints may be provided on at least a portion of the chips to allow the chips to remain curved according the desired deformation. | 2014-03-20 |
20140080258 | COMPLIANT PRINTED CIRCUIT SEMICONDUCTOR PACKAGE - A method of making a package for a semiconductor device having electrical terminals. At least one semiconductor device is located on a substrate. A first dielectric layer is printed on at least a portion of the semiconductor device to include first recesses aligned with a plurality of the electrical terminals. A conductive material is deposited in the first recesses forming contact members. A second dielectric layer is printed on at least a portion of the first dielectric layer to include second recesses aligned with a plurality of the first recesses. A conductive material is deposited in at least a portion of the second recesses to include a circuit geometry and a plurality of exposed terminals. A compliant material is deposited in recesses in one or more of the first and second dielectric layers adjacent to a plurality of the exposed terminals. | 2014-03-20 |
20140080259 | MANUFACTURING METHOD FOR LAYERED CHIP PACKAGES - In a manufacturing method for layered chip packages, a layered substructure with at least one additional package joined thereto is used to produce a plurality of layered chip packages. The layered substructure includes a plurality of main bodies to be separated from each other later. Each main body includes: a main part having top and bottom surfaces and including a plurality of layer portions stacked on each other; and a plurality of main terminals disposed on at least one of the top and bottom surfaces of the main part. The additional package includes an additional semiconductor chip and at least one additional terminal that is electrically connected to the additional semiconductor chip and in contact with at least one of the plurality of main terminals. | 2014-03-20 |
20140080260 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To provide a semiconductor device having an improved quality. The semiconductor device of the invention has a tape substrate having a semiconductor chip thereon, a plurality of land pads placed around the semiconductor chip, a plurality of wires for electrically coupling the electrode pad of the semiconductor chip to the land pad, and a plurality of terminal portions provided on the lower surface of the tape substrate. An average distance between local peaks of the surface roughness of a first region between the land pad of the tape substrate and the semiconductor chip is smaller than an average distance of local peaks of the surface roughness of a second region between the land pad of the tape substrate and the first region. | 2014-03-20 |
20140080261 | METHOD FOR FABRICATING A CHIP HAVING A WATER-REPELLENT OBVERSE SURFACE AND A HYDROPHILIC REVERSE SURFACE - In order to provide a novel method for producing a chip having a water-repellent obverse surface and a hydrophilic reverse surface, the characteristic of the present disclosure lies in that the obverse surface of the chip having a hydroxyl group is brought into contact with an organic solvent in which R | 2014-03-20 |
20140080262 | METHOD FOR PRODUCING THE SAME - A method for producing a semiconductor device includes solder-connecting a semiconductor chip, onto an insulating substrate including a ceramic board and having conductor layers on two surfaces thereof, with a lead-free solder; warping a radiating base such that a surface of the radiating base on a side opposite to the insulating substrate is convex; and solder-connecting the insulating substrate onto the warped radiating base with the lead-free solder so as to provide a substantially flat solder-connected radiating base. | 2014-03-20 |
20140080263 | Semiconductor Packaging Method Using Connecting Plate for Internal Connection - A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding. | 2014-03-20 |
20140080264 | METHOD FOR FABRICATING LEADFRAME-BASED SEMICONDUCTOR PACKAGE - A semiconductor package and a method for fabricating the same are provided. A leadframe including a die pad and a plurality of peripheral leads is provided. A carrier, having a plurality of connecting pads formed thereon, is attached to the die pad, wherein a planar size of the carrier s greater than that of the die pad, allowing the connecting pads on the carrier to be exposed from the die pad. At least a semiconductor chip is attached to a side of an assembly including the die pad and the carrier, and is electrically connected to the connecting pads of the carrier and the leads via bonding wires. A package encapsulant encapsulates the semiconductor chip, the bonding wires, a part of the carrier and a part of the leadframe, allowing a bottom surface of the carrier and a part of the leads to be exposed from the package encapsulant. | 2014-03-20 |
20140080265 | FABRICATION METHOD OF CARRIER-FREE SEMICONDUCTOR PACKAGE - A carrier-free semiconductor package includes a circuit structure having an insulating layer and a circuit layer embedded in the insulating layer and having a plurality of conductive traces and RF (radio frequency) traces, a chip disposed on a first surface of the insulating layer and electrically connected to the conductive traces, an encapsulant covering the chip and the circuit layer, a ground layer formed on a second surface of the insulating layer opposite to the first surface, and a plurality of solder balls disposed on the conductive traces or terminals on the conductive traces, wherein portions of the solder balls electrically connect the ground layer so as to allow the RF traces and the ground layer to form a microstrip line having an RF function, thus obtaining a single-layer carrier-free semiconductor package having low cost and simplified RF design. | 2014-03-20 |
20140080266 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are a semiconductor package and a method of manufacturing the same, the semiconductor package including: a molding member having a cavity formed therein; a device mounted in the cavity; an insulating member formed inside the cavity and on and/or beneath the molding member and the device; a circuit layer formed on the insulating member, and including vias and connection pads electrically connected with the device; a solder resist layer formed on the circuit layer, and having openings exposing upper portions of the connection pads; and solder balls formed in the openings. | 2014-03-20 |
20140080267 | METHOD OF MAKING A THIN FILM TRANSISTOR DEVICE - A method of making a thin film transistor device includes: forming a semiconductor layer, a dielectric layer, and a gate-forming layer on the dielectric layer to define a layered structure, forming a gray scale photoresist pattern on the gate-forming layer, stripping the gray scale photoresist pattern isotropically to cause removal of source and drain defining regions, etching the gate-forming layer anisotropically so as to remove source and drain covering region, doping a first type dopant into source and drain regions, and removing a gate defining region from the gate-forming layer. | 2014-03-20 |
20140080268 | FABRICATING PHOTONICS DEVICES FULLY INTEGRATED INTO A CMOS MANUFACTURING PROCESS - Disclosed are process enhancements to fully integrate the processing of a photonics device into a CMOS manufacturing process flow. A CMOS wafer may be divided into different portions. One of the portions is for the CMOS devices and one or more other portions are for the photonics devices. The photonics devices include a ridged waveguide. One or more process steps may be performed simultaneously on the CMOS devices and the photonics devices. | 2014-03-20 |
20140080269 | FABRICATING PHOTONICS DEVICES FULLY INTEGRATED INTO A CMOS MANUFACTURING PROCESS - Disclosed are process enhancements to fully integrate the processing of a photonics device into a CMOS manufacturing process flow. A CMOS wafer may be divided into different portions. One of the portions is for the CMOS devices and one or more other portions are for the photonics devices. The photonics devices include a ridged waveguide and a germanium photodetector. The germanium photodetector may utilize a seeded crystallization from melt process so there is more flexibility in the processing of the germanium photodetector. | 2014-03-20 |
20140080270 | BACKPLANE FOR FLAT PANEL DISPLAY APPARATUS, FLAT PANEL DISPLAY APPARATUS, AND METHOD OF MANUFACTURING THE BACKPLANE - A backplane includes: a substrate, a pixel electrode, which includes a transparent conductive material, on the substrate, a capacitor first electrode formed on the same layer as the pixel electrode, a first protection layer covering the capacitor first electrode and an upper edge of the pixel electrode, a gate electrode of a thin film transistor (TFT) formed on the first protection layer, a capacitor second electrode formed on the same layer as the gate electrode, a first insulating layer that covers the gate electrode and the capacitor second electrode, a semiconductor layer that is formed on the first insulating layer and includes a transparent conductive material, a second insulating layer covering the semiconductor layer, source and drain electrodes of the TFT that are formed on the second insulating layer, and a third insulating layer that covers the source and drain electrodes and exposes the pixel electrode. | 2014-03-20 |
20140080271 | METHOD OF FORMING THIN FILM TRANSISTOR - A method of forming TFT is provided. The TFT includes a gate electrode, a gate insulating layer, a first protective pattern, a second protective pattern, a source electrode, a drain electrode, a semiconductor channel layer, and a passivation layer. The first protective pattern and the second protective pattern are disposed on the gate insulating layer above the gate electrode. The source electrode is disposed on the gate insulating layer and the first protective pattern. The drain electrode is disposed on the gate insulating layer and the second protective pattern. The semiconductor channel layer is disposed on the gate insulating layer, the source electrode, and the drain electrode. In an extending direction from the source electrode to the drain electrode, a length of the first protective pattern is shorter than that of the source electrode, and a length of the second protective pattern is shorter than that of the drain electrode. | 2014-03-20 |
20140080272 | CONTINUOUS MESH THREE DIMENSIONAL NON-VOLATILE STORAGE WITH VERTICAL SELECT DEVICES - A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. | 2014-03-20 |
20140080273 | VERTICAL-TYPE SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated. | 2014-03-20 |
20140080274 | METHOD OF FORMING CHANNEL LAYER OF ELECTRIC DEVICE AND METHOD OF MANUFACTURING ELECTRIC DEVICE USING THE SAME - A method of forming a channel layer of an electric device according to an embodiment is provided. First, a conductive substrate including an insulating layer on the substrate is provided. The conductive substrate and a metal to be plated are used as respective electrodes to carry out electroplating within an electrolyte solution. In this case, electrons provided by a tunneling current passing through the insulating layer from the conductive substrate are bonded with ions of the metal within the electrolyte solution to form a metal channel layer on the insulating layer. | 2014-03-20 |
20140080275 | Multigate FinFETs with Epitaxially-Grown Merged Source/Drains - Method of forming multi-gate finFETs with epitaxially-grown merged source/drains. Embodiments of the invention may include forming a plurality of semiconductor fins joined by a plurality of inter-fin semiconductor regions, depositing a sacrificial gate over a center portion of each of the plurality of fins, forming a first merge layer over a first end of each of the plurality of fins to form a first merged fin region, forming a second merge layer over the second end of each of the plurality of fins to form a second merged fin region, etching a portion of the first merged fin region to form a first source/drain base region, etching a portion of the second merged fin region to form a second source/drain base region, forming a first source/drain region on the first source/drain base region, and forming a second source/drain region on the second source/drain base region. | 2014-03-20 |
20140080276 | Technique For Forming A FinFET Device - A three-dimensional structure disposed on a substrate is processed so as to alter the etch rate of material disposed on at least one surface of the structure. In some embodiments, a conformal deposition of material is performed on the three-dimensional structure. Subsequently, an ion implant is performed on at least one surface of the three-dimensional structure. This ion implant serves to alter the etch rate of the material deposited on that structure. In some embodiments, the ion implant increases the etch rate of the material. In other embodiments, the ion implant decreases the etch rate. In some embodiments, ion implants are performed on more than one surface, such that the material on at least one surface is etched more quickly and material on at least one other surface is etched more slowly. | 2014-03-20 |
20140080277 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A compound semiconductor device including an electron transport layer that is formed on a substrate and includes a III-V nitride compound semiconductor, a gate insulating film that is positioned above the compound semiconductor layer, and a gate electrode that is positioned on the gate insulating film. The gate insulating film includes a first insulating film that includes oxygen, at least a single metal element selected from a metal bonding with the oxygen and forming a metal oxide having a dielectric constant no less than 10, and at least a single metal element selected from Si and Al. | 2014-03-20 |
20140080278 | SEMICONDUCTOR DEVICE HAVING A RESISTOR AND METHODS OF FORMING THE SAME - In a semiconductor device and a method of making the same, the semiconductor device comprises a substrate including a first region and a second region. At least one first gate structure is on the substrate in the first region, the at least one first gate structure including a first gate insulating layer and a first gate electrode layer on the first gate insulating layer. At least one isolating structure is in the substrate in the second region, a top surface of the isolating structure being lower in height than a top surface of the substrate. At least one resistor pattern is on the at least one isolating structure. | 2014-03-20 |
20140080279 | MULTILEVEL MIXED VALENCE OXIDE (MVO) MEMORY - Various embodiments include a memory device and methods of forming the same. The memory device can include an electrode coupled to one or more memory elements, to store information. The electrode may comprise a number of metals, where a first one of the metals has a Gibbs free energy for oxide formation lower than the Gibbs free energy of oxidation of a second one of the metals. | 2014-03-20 |
20140080280 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME - An embodiment relates to a method of forming a semiconductor structure, comprising: forming a first semiconductor layer; forming a second semiconductor layer over the first semiconductor layer; forming a third semiconductor layer over the second semiconductor layer; forming an opening in the first, second and third semiconductor layers; forming a conductive region within the first, the and third semiconductor layer, the conductive region surrounding the opening, the conductive region being electrically coupled to the first semiconductor layer; forming a dielectric layer in the opening and over the conductive region; and forming a conductive layer over the dielectric layer in the opening. | 2014-03-20 |
20140080281 | Method of Fabricating Isolated Capacitors and Structure Thereof - A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors. | 2014-03-20 |
20140080282 | Leakage reduction in DRAM MIM capacitors - A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high-k phase of a subsequently deposited dielectric layer. The high-k dielectric layer includes a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer. | 2014-03-20 |
20140080283 | INTERFACIAL MATERIALS FOR USE IN SEMICONDUCTOR STRUCTURES AND RELATED METHODS - A method of forming a semiconductor structure. The method comprises forming a high-k dielectric material, forming a continuous interfacial material over the high-k dielectric material, and forming a conductive material over the continuous interfacial material. Additional methods and semiconductor structures are also disclosed. | 2014-03-20 |
20140080284 | High Temperature ALD Process of Metal Oxide for DRAM Applications - A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive metal oxide formed using a high temperature, low pressure ALD process. The high temperature ALD process results in a layer with enhanced crystallinity, higher density, reduced shrinkage, and lower carbon contamination. The high temperature ALD process can be used for either or both the bottom electrode and the top electrode layers. | 2014-03-20 |
20140080285 | METHOD AND APPARATUS FOR FORMING SHALLOW TRENCH ISOLATION STRUCTURES HAVING ROUNDED CORNERS - Methods for rounding the bottom corners of a shallow trench isolation structure are described herein. Embodiments of the present invention provide a method comprising forming a first masking layer on a sidewall of an opening in a substrate, removing, to a first depth, a first portion of the substrate at a bottom surface of the opening having the first masking layer therein, forming a second masking layer on the first masking layer in the opening, and removing, to a second depth, a second portion of the substrate at the bottom surface of the opening having the first and second masking layers therein. Other embodiments also are described. | 2014-03-20 |
20140080286 | METHOD FOR PRODUCING A SEMICONDUCTOR BODY - A method of producing a semiconductor body includes providing a semiconductor wafer having at least two chip regions and at least one separating region arranged between the chip regions, wherein the semiconductor wafer includes a layer sequence, an outermost layer of which has, at least within the separating region a transmissive layer transmissive to electromagnetic radiation, carrying out at least one of: removing the transmissive layer within the separating region, applying an absorbent layer within the separating region, increasing the absorption coefficient of the transmissive layer within the separating region, and separating the chip regions along the separating regions by a laser. | 2014-03-20 |
20140080287 | METHOD FOR SINGULATING A COMPONENT COMPOSITE ASSEMBLY - A method relates to separating a component composite into a plurality of component regions, wherein the component composite is provided having a semiconductor layer sequence comprising a region for generating or for receiving electromagnetic radiation. The component composite is mounted on a rigid subcarrier. The component composite is separated into the plurality of component regions, wherein one semiconductor body is produced from the semiconductor layer sequence for each component region. The component regions are removed from the subcarrier. | 2014-03-20 |
20140080288 | LASER PROCESSING METHOD - A laser processing method which can highly accurately cut objects to be processed having various laminate structures is provided. An object to be processed comprising a substrate and a laminate part disposed on the front face of the substrate is irradiated with laser light L while a light-converging point P is positioned at least within the substrate, so as to form a modified region due to multiphoton absorption at least within the substrate, and cause the modified region to form a starting point region for cutting. When the object is cut along the starting point region for cutting, the object | 2014-03-20 |
20140080289 | METHOD OF FORMING GETTERING LAYER - Disclosed herein is a method of forming a gettering layer for capturing metallic ions on the back side of a semiconductor wafer formed with devices on the face side thereof. The method includes irradiating the back-side surface of the semiconductor wafer with a pulsed laser beam having a pulse width corresponding to a thermal diffusion length of 10 to 230 nm, to thereby form the gettering layer. | 2014-03-20 |
20140080290 | METHOD OF SELECTIVE GROWTH WITHOUT CATALYST ON A SEMICONDUCTING STRUCTURE - A method of selective growth without catalyst on a semi-conducting structure. According to the method, which is applicable in electronics in particular: a semi-conducting structure is formed from first gaseous or molecular flows; at a same time or subsequently, at least one second gaseous or molecular flow is added thereto, to selectively in situ grow a dielectric layer on the structure; and then another semi-conducting structure is grown thereon from third gaseous or molecular flows. | 2014-03-20 |
20140080291 | METHOD FOR PRODUCING A GRAPHENE NANO-RIBBON - A method for producing a graphene nanoribbon is disclosed. This production method includes the steps of: forming a crystalline catalytic metal layer composed of copper or nickel on a (110) plane or a (112) plane of a MgAl | 2014-03-20 |
20140080292 | METHOD OF PRODUCING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer ( | 2014-03-20 |
20140080293 | SOLAR CELLS HAVING NANOWIRES AND METHODS OF FABRICATING NANOWIRES - A solar cell includes a plurality of nanowires arranged such that diameters of the nanowires sequentially increase in a first direction along a path of incident light. In a method of forming nanowires, a catalyst layer is formed on a substrate, a plurality of nanoparticles are formed by thermally processing the catalyst layer, and nanowires are grown from the plurality of nanoparticles. The catalyst layer has a thickness that increases in a first direction, and the plurality of nanoparticles have diameters that increase in the first direction. | 2014-03-20 |
20140080294 | Method for Manufacturing a Semiconductor Structure - According to an embodiment, a method for manufacturing a semiconductor structure includes providing a first monocrystalline semiconductor portion having a first lattice constant in a reference direction and forming a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion. | 2014-03-20 |
20140080295 | Surface Doping and Bandgap Tunability in Hydrogenated Graphene - A method of introducing a bandgap in single layer graphite on a SiO | 2014-03-20 |
20140080296 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a gate pattern on a substrate, and etching sides of the gate pattern using a first wet-etching process to form a first recess. The first wet-etching process includes using an etchant containing a first chemical substance including a hydroxyl functional group (—OH) and a second chemical substance capable of oxidizing the substrate. The concentration of the second chemical substance is 1.5 times or less the concentration of the first chemical substance. | 2014-03-20 |
20140080297 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - According to one embodiment, a semiconductor device, including a substrate, a stacked layer body provided above the substrate, the stacked layer body alternately stacking an insulator and an electrode film one on another, silicon pillars contained with fluorine, the silicon pillar penetrating through and provided in the stacked layer body, a tunnel insulator provided on a surface of the silicon pillar facing to the stacked layer body, a charge storage layer provided on a surface of the tunnel insulator facing to the stacked layer body, a block insulator provided on a surface of the charge storage layer facing to the stacked layer body, the block insulator being in contact with the electrode film, and an embedded portion provided in the silicon pillars. | 2014-03-20 |
20140080298 | NON-VOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A non-volatile memory device includes a field region that defines an active region in a semiconductor substrate, a floating gate pattern on the active region, a dielectric layer on the floating gate pattern and a control gate on the dielectric layer. The control gate includes a first conductive pattern that has a first composition that crystallizes in a first temperature range, and a second conductive pattern that has a second composition that is different from the first composition and that crystallizes in a second temperature range that is lower than the first temperature range, the first conductive pattern being between the dielectric layer and the second conductive pattern. | 2014-03-20 |
20140080299 | Processes for NAND Flash Memory Fabrication - Narrow word lines are formed in a NAND flash memory array using a double patterning process in which sidewall spacers define word lines. Sidewall spacers also define edges of select gates so that spacing between a select gate and the closest word line is equal to spacing between adjacent word lines. | 2014-03-20 |
20140080300 | MULTI-LAYER CIRCUIT SUBSTRATE FABRICATION METHOD PROVIDING IMPROVED TRANSMISSION LINE INTEGRITY AND INCREASED ROUTING DENSITY - An integrated circuit substrate is designed and fabricated with a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs. | 2014-03-20 |
20140080301 | FABRICATING A SEMICONDUCTOR DIE HAVING COEFFICIENT OF THERMAL EXPANSION GRADED LAYER - A method of fabricating a semiconductor die includes circuit elements configured to provide a circuit function. A substrate including a bottomside and a topside is provided. At least one multi-layer structure is formed. The forming is done by depositing a coefficient of thermal expansion (CTE) graded layer comprising at least a dielectric portion on a first material having a first CTE to provide a first side facing said first material and a second side opposite the first side. The depositing includes flowing a first reactive component and at least a second reactive component. A gas flow ratio of the first reactive component relative to the second reactive component is automatically changed during a deposition time to provide a non-constant composition profile which has a graded CTE that increases from the first side to the second side. A metal layer comprising a second material having a second CTE is formed on the second side. The second CTE is higher than the first CTE. | 2014-03-20 |
20140080302 | METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including forming a first sacrificial layer on a substrate, the first sacrificial layer including a conductive material, forming a second sacrificial layer on the first sacrificial layer, the second sacrificial layer including an insulating material, patterning the second sacrificial layer and the first sacrificial layer to form an opening successively penetrating the second and first sacrificial layers, conformally forming a seed layer on the second and first sacrificial layers including the opening, and forming a conductive pattern filling the opening having the seed layer by a plating process. | 2014-03-20 |
20140080303 | METHODS OF MANUFACTURING SEMICONDUCTOR STRUCTURES AND DEVICES INCLUDING NANOTUBES, AND SEMICONDUCTOR STRUCTURES, DEVICES, AND SYSTEMS FABRICATED USING SUCH METHODS - A method of forming a plurality of nanotubes is disclosed. Particularly, a substrate may be provided and a plurality of recesses may be formed therein. Further, a plurality of nanotubes may be formed generally within each of the plurality of recesses and the plurality of nanotubes may be substantially surrounded with a supporting material. Additionally, at least some of the plurality of nanotubes may be selectively shortened and at least a portion of the at least some of the plurality of nanotubes may be functionalized. Methods for forming semiconductor structures intermediate structures, and semiconductor devices are disclosed. An intermediate structure, intermediate semiconductor structure, and a system including nanotube structures are also disclosed. | 2014-03-20 |
20140080304 | INTEGRATED TOOL FOR SEMICONDUCTOR MANUFACTURING - An integrated tool to reduce defects in manufacturing a semiconductor device by reducing queue times during a manufacturing process. The integrated tool may include at least one a polishing tool comprising at least one polishing module and at least one deposition tool comprising at least one deposition chamber. At least one pump-down chamber may connect the polishing tool to the deposition tool. The at least one pump-down chamber includes a passage through which the semiconductor device is passed. Defects in the semiconductor device are reduced by reducing the queue time at various stages of the fabrication process. | 2014-03-20 |
20140080305 | DOUBLE PATTERNING PROCESS - A double patterning process is described. A substrate having a first area and a second area is provided. A target layer is formed over the substrate. A patterned first photoresist layer is formed over the target layer, wherein the patterned first photoresist layer has openings and has a first thickness in the first area, and at least a portion of the patterned first photoresist layer in the second area has a second thickness less than the first thickness. A second photoresist layer is then formed covering the patterned first photoresist layer and filling in the openings. | 2014-03-20 |
20140080306 | METHOD OF FORMING FINE PATTERNS - A method of forming a fine pattern comprises depositing a modifying layer on a substrate. A photoresist layer is deposited on the modifying layer, the photoresist layer having a first pattern. The modifying layer is etched according to the first pattern of the photoresist layer. A treatment is performed to the etched modifying layer to form a second pattern, the second pattern having a smaller line width roughness (LWR) and/or line edge roughness (LER) than the first pattern. The second pattern is then etched into the substrate. | 2014-03-20 |
20140080307 | PATTERN-FORMING METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A pattern-forming method for forming a predetermined pattern serving as a mask when etching film on a substrate includes the steps of: an organic film pattern-forming step for forming an organic film pattern on a film to be processed; forming a silicon nitride film on the organic film pattern; etching the silicon nitride film so that the silicon nitride film remains only on the lateral wall sections of the organic film pattern; and removing the organic film, thereby forming the predetermined silicon nitride film pattern on the film to be processed on a substrate. With the temperature of the substrate maintained at no more than 100° C., the film-forming step excites a processings gas and generates a plasma, performs plasma processing with the plasma, and forms a silicon nitride film having stress of no more than 100 MPa. | 2014-03-20 |
20140080308 | RADICAL-COMPONENT OXIDE ETCH - A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents combine with a nitrogen-and-hydrogen-containing precursor. Reactants thereby produced etch the patterned heterogeneous structures with high silicon oxide selectivity while the substrate is at high temperature compared to typical Siconi™ processes. The etch proceeds without producing residue on the substrate surface. The methods may be used to remove silicon oxide while removing little or no silicon, polysilicon, silicon nitride or titanium nitride. | 2014-03-20 |
20140080309 | DIFFERENTIAL SILICON OXIDE ETCH - A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch created from a remote plasma etch. The remote plasma excites a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor. Reactants thereby produced etch the patterned heterogeneous structures to remove two separate regions of differing silicon oxide at different etch rates. The methods may be used to remove low density silicon oxide while removing less high density silicon oxide. | 2014-03-20 |
20140080310 | SILICON-CARBON-NITRIDE SELECTIVE ETCH - A method of etching exposed silicon-nitrogen-and-carbon-containing material on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and an oxygen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the exposed regions of silicon-nitrogen-and-carbon-containing material. The plasma effluents react with the patterned heterogeneous structures to selectively remove silicon-nitrogen-and-carbon-containing material from the exposed silicon-nitrogen-and-carbon-containing material regions while very slowly removing selected other exposed materials. The silicon-nitrogen-and-carbon-containing material selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region. The ion suppression element controls the number of ionically-charged species that reach the substrate. The methods may be used to selectively remove silicon-nitrogen-and-carbon-containing material at a faster rate than exposed silicon oxide or exposed silicon nitride. | 2014-03-20 |
20140080311 | PLASMA PROCESSING METHOD - A plasma processing method includes holding a target substrate on a holding table installed in a processing chamber; generating a microwave for plasma excitation; supplying a reactant gas having dissociation property; generating an electric field by introducing the microwave via a dielectric plate disposed to face the holding table; setting a distance between the holding table and the dielectric plate is set to a first distance based on periodicity of a standing wave formed in the dielectric plate by the introduction of the microwave, and generating plasma in the processing chamber in a state where the electric field is generated in the processing chamber; and after the generating of the plasma, setting the distance to a second distance shorter than the first distance by moving the holding table up and down, and performing the plasma process on the target substrate. | 2014-03-20 |
20140080312 | SUBSTRATE PROCESSING METHOD, SUBSTRATE PROCESSING APPARATUS, AND STORAGE MEDIUM - A wafer is held horizontally and rotated by a substrate holding mechanism. An aqueous alkaline solution is supplied to a wafer by a nozzle and caused to flow from a central portion to a peripheral edge portion of the wafer, thereby etching the wafer. An amount of oxygen, which is equal to or more than the amount of oxygen in atmospheric air involved in the aqueous alkaline solution flowing on the wafer, is previously dissolved in the aqueous alkaline solution. | 2014-03-20 |
20140080313 | ETCHING COMPOSITION AND METHOD FOR ETCHING A SEMICONDUCTOR WAFER - An etching composition for a semiconductor wafer is provided, including 0.5-50 wt % base, 10-80 wt % alcohol, 0.01-15 wt % additive and water. A method for etching a semiconductor wafer is also provided. When the etching composition is applied to the entire surface or a partial surface of the semiconductor wafer at 60-200° C., the etching composition reacts on the semiconductor wafer to form a foam that etches the semiconductor wafer and includes a solid, a liquid and a gas. At the same time, the additive forms an oxide mask on the surface of the semiconductor wafer. Therefore, an excellent texture structure is formed on the surface of the semiconductor wafer, and a single surface of the semiconductor wafer is etched. | 2014-03-20 |
20140080314 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - A method of manufacturing a semiconductor device includes forming a thin film containing a predetermined element, oxygen, carbon, and nitrogen on a substrate by performing a cycle a predetermined number of times after supplying a nitriding gas to the substrate. The cycle includes performing the following steps in the following order: supplying a carbon-containing gas to the substrate; supplying a predetermined element-containing gas to the substrate; supplying the carbon-containing gas to the substrate; supplying an oxidizing gas to the substrate; and supplying the nitriding gas to the substrate. | 2014-03-20 |
20140080315 | METHOD OF FORMING LAMINATED FILM AND FORMING APPARATUS THEREOF - A method of forming a laminated film includes forming a silicon oxide film on a plurality of target objects loaded in a reaction chamber, and forming a silicon oxynitride film on the plurality of target objects by supplying a silicon source, an oxidizing agent and a nitride agent to the reaction chamber, wherein forming the silicon oxide film and forming the silicon oxynitride film are repeatedly performed for a predetermined number of times on the plurality of target objects to form a laminated film including the silicon oxynitride film and the silicon oxide film. | 2014-03-20 |
20140080316 | METHODS OF FORMING GATE DIELECTRIC MATERIAL - A method of fabricating a semiconductor device includes contacting water with a silicon oxide layer. The method further includes diffusing an ozone-containing gas through water to treat the silicon oxide layer. The method further includes forming a dielectric layer over the treated silicon oxide layer. | 2014-03-20 |
20140080317 | MEHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - A stress of a film formed on a substrate can be reduced. A method of manufacturing a semiconductor device includes: forming a film on the substrate by supplying a process gas to the substrate while heating the substrate to a first temperature; controlling a stress to the film by changing a stress value of the film formed on the substrate, by supplying a plasma-excited process gas to the substrate while changing a temperature of the substrate to a second temperature different from the first temperature; and unloading the substrate from the processor chamber. | 2014-03-20 |
20140080318 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS AND RECORDING MEDIUM - Provided are: forming a thin film made of a specific element alone on a substrate by performing a specific number of times a cycle of: supplying a first source to the substrate, the first source containing the specific element and a halogen-group; and supplying a second source to the substrate, the second source containing the specific element and an amino-group, and having amino-group-containing ligands whose number is two or less in its composition formula and not more than the number of halogen-group-containing ligands in the composition formula of the first source. | 2014-03-20 |
20140080319 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - A method of manufacturing a semiconductor device includes forming a thin film containing a predetermined element, oxygen, carbon, and nitrogen on a substrate by performing a cycle a predetermined number of times. The cycle includes supplying a predetermined element-containing gas to the substrate; supplying a carbon-containing gas and a plasma-excited inert gas to the substrate; supplying an oxidizing gas to the substrate; and supplying a nitriding gas to the substrate. | 2014-03-20 |
20140080320 | SEMICONDUCTOR PROCESSING SYSTEM INCLUDING VAPORIZER AND METHOD FOR USING SAME - A method for using a system, which includes a film formation apparatus for forming a high-dielectric constant thin film on target substrates together and a gas supply apparatus for supplying a process gas. The method includes a preparatory stage of determining a set pressure range of pressure inside a vaporizing chamber for a liquid material cooled at a set temperature. The preparatory stage includes obtaining a first limit value of pressure at which vaporization of the liquid material starts being inhibited due to an increase in the pressure, obtaining a second limit value of pressure at which vaporization of the liquid material starts being unstable and the pressure starts pulsating movement due to a decrease in the pressure, and determining the set pressure range to be defined by an upper limit lower than the first limit value and a lower limit higher than the second limit value. | 2014-03-20 |
20140080321 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - A method of manufacturing a semiconductor device includes performing a cycle a predetermined number of times, the cycle including supplying a first precursor containing a specific element and a halogen group to form a first layer and supplying a second precursor containing the specific element and an amino group to modify the first layer into a second layer. A temperature of the substrate is set such that a ligand containing the amino group is separated from the specific element in the second precursor, the separated ligand reacts with the halogen group in the first layer to remove the halogen group from the first layer, the separated ligand is prevented from being bonded to the specific element in the first layer, and the specific element from which the ligand is separated in the second precursor is bonded to the specific element in the first layer. | 2014-03-20 |
20140080322 | Emissivity Profile Control for Thermal Uniformity - A substrate for processing in a heating system is disclosed. The substrate includes a bottom portion for absorbing heat from a radiating heat source, the bottom portion having a first region having a first emissivity and a second region having a second emissivity less than the first emissivity. The first region and the second region promote thermal uniformity of the substrate by compensating for thermal non-uniformity of the radiating heat source. | 2014-03-20 |
20140080323 | METHOD AND APPARATUS FOR FORMING A STRAIGHT LINE PROJECTION ON A SEMICONDUCTOR SUBSTRATE - An apparatus for irradiating a semiconductor is disclosed. The apparatus has a curved mirror with a reflective surface of revolution, and a point source generating an irradiation beam being incident on the curved mirror along an incident direction. The curved mirror and the point source form a system having an axis of revolution wherein the point source is provided on or near said axis of revolution. The axis of revolution substantially coincides with a straight line projection to be generated on a semiconductor substrate. Additionally, the use of such an apparatus for manufacturing a selective emitter grid, or for irradiating a large area semiconductor surface in a scanning movement, is disclosed. | 2014-03-20 |
20140080324 | MULTI-STATION SEQUENTIAL CURING OF DIELECTRIC FILMS - The present invention addresses provides improved methods of preparing a low-k dielectric material on a substrate. The methods involve multiple operation ultraviolet curing processes in which UV intensity, wafer substrate temperature and other conditions may be independently modulated in each operation. In certain embodiments, a film containing a structure former and a porogen is exposed to UV radiation in a first operation to facilitate removal of the porogen and create a porous dielectric film. In a second operation, the film is exposed to UV radiation to increase cross-linking within the porous film. In certain embodiments, the curing takes place in a multi-station UV chamber wherein UV intensity and substrate temperature may be independently controlled at each station. | 2014-03-20 |
20140080325 | SWIVEL CABLE CONNECTOR MOUNTING STRUCTURE - A swivel cable connector mounting structure includes a device housing having a through hole at a peripheral wall thereof, a rotary connector including a cylindrical base rotatably inserted through the through hole, two metal pivot rods affixed to an outer coupling end of the cylindrical base outside the device housing and two metal conducting terminals embedded in an inner end of the cylindrical base and respectively connected to the two metal pivot rods, a spring member mounted around the rotary connector and stopped between the peripheral wall of the device housing and a part of the cylindrical base of the rotary connector, a swivel connector including a U-shaped base pivotally coupled to the two metal pivot rods and two metal conductors embedded in the U-shaped base and kept in positive contact with the two metal pivot rods, and an electrical cable electrically connected to the two metal conductors. | 2014-03-20 |
20140080326 | CONNECTOR - A connector for receiving an expansion card includes a base and a number of metal pins. A top of the base defines a slot. The slot extends through an end of the base. The metal pins are mounted inside the slot. Each metal pin extends through a bottom of the base to be electronically connected to corresponding traces on a motherboard. | 2014-03-20 |
20140080327 | SHIELDING SOCKET WITH A SHIELDING PLATE EXTENDING OUTSIDE FROM AN INSULATIVE HOUSING - An electrical connector electrically connecting a chip module to a printed circuit board includes an insulative housing having a matching surface, a mounting surface and a receiving slot penetrated from the matching surface to the mounting surface, a number of terminals received in the receiving slot and a number of shielding plates received in the receiving slot; the shielding plate includes a body portion, a supporting portion bending outwardly from one side of the body portion and a contact portion extending outwardly from another side of the body portion, the contact portion includes a main body, a spring beam extending upwardly from the main body and a clip extending downwardly from the main body, the spring beam extending upwardly beyond the matching surface and the clip extending downwardly beyond the mounting surface. | 2014-03-20 |
20140080328 | ELECTRICAL CONNECTOR WITH A SLEEVE ASSEMBLED THEREON - An electrical connector for electrically connecting an IC package to a printed circuit board includes an insulating housing, a number of contacts received in the insulating housing and at least one sleeve assembled on the insulating housing. The insulating housing includes a bottom wall and a number of side walls extending upwardly from the bottom wall. The bottom wall and the side walls define a cavity for accommodating the IC package. The sleeve is assembled on the side wall and defines a supporting portion towards the cavity. The supporting portion includes a pair of abutting walls perpendicular to each other. | 2014-03-20 |
20140080329 | ELECTRONIC CONTROL DEVICE - An electronic control device including a circuit board, a connector with connector pins having a board connecting portion at which the connector pins are electrically connected with the circuit board, a pair of housing members accommodating the circuit board and the connector therebetween, a waterproof seal portion through which connection between the connector and the pair of housing members and connection between the pair of housing members are provided in a fluid-tight manner, the waterproof seal portion including a connector-side waterproof seal portion disposed between the connector and one of the pair of housing members which is opposed to the board connecting portion of the connector pins, and a barrier portion disposed between the board connecting portion of the connector pins and the connector-side waterproof seal portion. | 2014-03-20 |
20140080330 | ELECTRICAL CONTACT AND ELECTRICAL CONNECTOR USED THEREOF - An electrical contact ( | 2014-03-20 |
20140080331 | ELECTRICAL CONNECTOR AND CIRCUIT BOARD ASSEMBLY INCLUDING THE SAME - Circuit board assembly including an electrical connector having a connector body having a mounting side and an array of signal contacts disposed along the mounting side. The array of signal contacts has gaps formed between adjacent signal contacts of the array. The circuit board assembly also includes a circuit board having an engagement side. The circuit board includes signal vias and ground vias that are exposed along the engagement side. The circuit board assembly also includes a grounding matrix that is positioned between the engagement side and the mounting side. The grounding matrix includes a plurality of ground contacts that are interconnected in a web-like manner to define a plurality of openings, wherein the signal contacts of the electrical connector extend through the openings to engage the signal vias. The ground contacts electrically couple the ground vias of the circuit board to a ground pathway through the electrical connector. | 2014-03-20 |
20140080332 | USB PLUG CONNECTOR STRUCTURE - A USB plug connector structure can use the same set of terminals to apply on different USB connector patterns, such as plate edge connector or wire edge connector, through the design of various soldering portions and base portions being positioned on the same plane. Furthermore, the common mode signals generated from first and second differential signal transmission conductor sets can be restrained by means of first and second grounding base portions of a grounding transmission conductor surrounding first and second differential signal transmission conduct sets. In addition, crosstalk interference generated from the first and second differential signal transmission conductor sets to a signal transmission conductor set can be similarly isolated through the first and second grounding base portions. Furthermore, a bended angle of each bended portion ranges from 120 to 150 degrees, thereby guide scattered radio frequency interference. | 2014-03-20 |
20140080333 | MODULAR JACK - A modular jack is composed of: a base connector installed on a printed circuit board, and a socket connector with a parallel crank mechanism at an extremity thereof, the parallel crank mechanism being slidably connected to the base connector and switching an upper housing between a raised state and a lowered state. When the upper housing is laid toward the front side of the socket connector, the socket connector can be housed inside the casing and both faces of the upper housing, the socket housing, and the base housing are made in a flat plate-like shape. This contributes to height reduction in the modular jack. The socket connector is configured such that, when the upper housing is pulled out from a side face of the casing and raised outside the casing, a plug can be electrically connected to the socket connector. | 2014-03-20 |
20140080334 | CONNECTOR CAP WATERPROOF STRUCTURE - A connector cap for use in a portable electronic device including a base; a connector-facing portion formed integrally with the base; and a sealing member formed of an elastic material in a ring-like shape and joined to the base, wherein the connector-facing portion includes a flexible member that has an elongated shape and is configured to extend away from the base and toward an inside of a casing of the portable device, wherein the flexible member is disposed from a position on the connector-facing portion that is within an inner area enclosed by the ring-like shape of the sealing member. | 2014-03-20 |
20140080335 | CARD READER AND ELECTRONIC DEVICE HAVING MOVABLE CARD INSERTION MECHANISM - A card reader is disposed in a case body of an electronic device for connecting an electronic card. The card reader includes an electrical connection socket, at least one guiding member, at least one guiding rail and a cover. The electrical connection socket is disposed in the case body for inserting an electrical connector of the electronic card thereinto. The guiding member is disposed in the case body and provides a guiding slot extending along a guiding direction. The guiding direction is parallel to a direction in which the electrical connector is inserted into the electrical connection socket. The guiding rail includes a sliding portion sliding in the guiding slot and a lower support portion extending from the sliding portion for guiding the electronic card to pass through the insertion hole of the case body. The cover is pivoted to the guiding rail and for closing the insertion hole. | 2014-03-20 |
20140080336 | CARD ACCOMMODATING DEVICE - An accommodating device for holding a card having an engaging portion in place is illustrated. The accommodating device includes a tray, a spring member, a covering member mounted on the tray, a latching mechanism, and a depressible button. The tray includes a bottom plate and two first sidewalls protruding from opposite edges of the bottom plate, which cooperatively defines a receiving channel for insertion of the card. The spring member is positioned on the bottom plate and compressed by the card when the card is received in the receiving channel. The latching mechanism includes a first resilient strip having a first hunched portion, a second resilient strip fixed to the cover, and a latching block fixed to the first and second resilient strips. The latching block is configured for lockingly engage with the engaging portion. The depressible button is arranged above the first hunched portion of the first resilient strip. | 2014-03-20 |
20140080337 | PLUG AND SOCKET CONVERTIBLE ELECTRICAL CONNECTOR ASSEMBLY - A plug and socket convertible electrical connector assembly including a connector body and a slide cover is disclosed. The connector body includes a housing defining an oblong insertion opening and multiple insertion slots at two adjacent walls thereof, a rack mounted in the housing, an electrical socket mounted in the rack and aimed at the insertion opening. The slide cover carrying multiple metal conducting blades is mounted in the housing and movable between a received position where the insertion opening is opened for allowing insertion of an external power adapter cable into the electrical socket, and an extended position where the slide cover blocks the insertion opening and the metal conducting blades are extended out of the insertion slots for connection to a city power supply outlet. | 2014-03-20 |
20140080338 | ANNULAR COUPLER FOR DRILL STEM COMPONENT - A pair of contact or capacitive HF couplers for drill stem components. Each of the first and second couplers includes a central conductor, a supplemental conductor, and an annular dielectric mechanism. The dielectric mechanism is disposed between the conductors. The conductors are isolated from each other. The supplemental conductor includes two electrical contact surfaces. The central conductor includes an electrical contact surface or electrode. The central conductors of the first and second couplers interact electrically in the coupled state. The supplemental conductors of the first and second couplers are in electrical contact in the coupled state. The supplemental conductors surround the central conductors. In the mounted state, the supplemental conductors form a shielding for the central conductors. | 2014-03-20 |
20140080339 | CONNECTOR, CONNECTOR DEVICE, AND BATTERY UNIT - A connector is provided with a first housing, a second housing attached to the first housing and forming a contact receiving portion jointly with the first housing, and a contact at least partially received in the contact receiving portion. The second housing is attached to the first housing so as to be movable in a predetermined direction relative to the first housing. The contact is received in the contact receiving portion in a state where the contact is not fixed to the first housing or the second housing so as to be movable relative to the first housing and the second housing. | 2014-03-20 |
20140080340 | CONNECTOR - A connector includes a housing ( | 2014-03-20 |
20140080341 | ELECTRICAL CABLE ASSEMBLY - A cable assembly structure, the structure including a connector having a connector body having a back end and a front end, a cam extending from and coupled to the back end of the connector body, a wire bundle extending from and coupled to the back end of the connector body; and a pair of guidance features extending from the front end of the connector body; and a receptacle having a receptacle body having a fixed end and an open end, and a pair of cam guides positioned on a top and a bottom surface of the receptacle. The cam is operable to couple the connector with the receptacle based on the guidance features aligning the connector with the receptacle, the cam guides being operable to receive the cam associated with the connector. | 2014-03-20 |
20140080342 | HALF FITTING PREVENTION CONNECTOR - A half fitting prevention connector includes a cylindrical case, a connector body for supplying electric power that is slidably accommodated in a front half part of the cylindrical case, a lever rotatably attached to the cylindrical case, and a holder that has a lever receiving portion for receiving an end portion of the lever. The connector body is moved in the cylindrical case in accordance with a rotational operation of the lever. The holder is provided on a rotation locus of the lever. The end portion of the lever is received in the lever receiving portion of the holder in a state that the connector body is completely fitted with a mating connector by the rotational operation of the lever. | 2014-03-20 |
20140080343 | LOWER PROFILE CARD EDGE CONNECTOR FOR SINGLE SIDED SO-DIMM MODULE AND ASSEMBLY OF THE SAME - A card edge connector assembly includes a card edge connector and an electronic card defining a first surface and a second surface opposite to each other and a mating end having a plurality of conductive pads thereof. The card edge connector includes a longitudinal base and a plurality of conductive terminals retained in the longitudinal base. The longitudinal base defines a longitudinal slot for receiving the mating end, the conductive terminals define elastic contacting portions exposed to the longitudinal slot and connecting portions along a mounting surface of the base. The longitudinal slot is defined with an upper inner surface and a lower inner surface inside therein. The first surface of the electronic card is flush with the upper inner surface of the slot and the second surface projects from lower inner surface to the mounting surface when the electronic card is inserted into the longitudinal slot. | 2014-03-20 |