12th week of 2013 patent applcation highlights part 44 |
Patent application number | Title | Published |
20130071931 | PROCESS FOR HEPATIC DIFFERENTIATION FROM INDUCED HEPATIC STEM CELLS, AND INDUCED HEPATIC PROGENITOR CELLS DIFFERENTIATED THEREBY - A method for hepatic differentiation of a stem cell selected from among embryonic stem cells, induced pluripotent stem cells or induced hepatic stem cells is presented. More specifically, a stem cell selected from among embryonic stem cells, induced pluripotent stem cells or induced hepatic stem cells is cultured for 1 to 4 weeks in the presence of a TGF-β inhibitor, whereby the hepatic differentiation of the stem cell is realized. | 2013-03-21 |
20130071932 | CULTURE METHOD FOR CAUSING DIFFERENTIATION OF PLURIPOTENT MAMMALIAN CELLS - Provided is a method that achieves control of embryoid body size and can induce differentiation in a state where the embryoid body size is controlled, by using a cell culture chamber having a plurality of microchambers formed therein. A culture method for causing differentiation of pluripotent mammalian cells uses a cell culture chamber ( | 2013-03-21 |
20130071933 | CITRUS SHOOT REGENERATION COMPOSITIONS, METHODS, AND SYSTEMS - The present disclosure relates, according to some embodiments, to citrus shoot regeneration compositions, methods, and systems. For example, citrus shoot regeneration compositions (e.g., culture media) may comprise one or more non-ionic surfactants. Methods may comprise preparing and using these compositions in some embodiments. Regeneration systems may comprise, in some embodiments, one or more of these compositions and/or one or more citrus explants. | 2013-03-21 |
20130071934 | METHOD AND SYSTEM FOR MEASUREMENT OF RESERVOIR FLUID PROPERTIES - A method and system that characterizes hydrogen sulfide in petroleum fluid employs a tool that includes a fluid analyzer for performing fluid analysis (including optical density (OD) for measuring carbon dioxide concentration) of a live oil sample, and a storage chamber for an analytical reagent fluidly coupled to a measurement chamber. An emulsion from fluid of the sample and the reagent is produced into the measurement chamber. The reagent changes color due to pH changes arising from chemical reactions between components of the sample and the reagent in the measurement chamber. The tool includes an optical sensor system that measures OD of a water phase of the emulsion at one or more determined wavelengths. The pH of the water phase is derived from such OD measurements. The pH of the water phase and the carbon dioxide concentration in the sample is used to calculate hydrogen sulfide concentration in the sample. | 2013-03-21 |
20130071935 | Dual Inlet Microchannel Device And Method For Using Same - A dual inlet microchannel device and a method for using the device to perform a flow-through kinetic assay are described. A microplate having an array of the dual inlet microchannel devices and in particular their specially configured flow chambers is also described. Several embodiments of the dual inlet microchannel devices and specially configured flow chambers are also described. | 2013-03-21 |
20130071936 | FRET-BASED ZINC(II) ION INDICATOR - The present invention is directed to an indicator for targeting zinc(II) ions in a composition, e.g., a biological sample such as for targeting mitochondrial zinc (II) ions. The present invention is directed to a method for preparing an indicator that targets mitochondrial zinc(II), and a method of measuring the concentration of mitochondrial zinc(II) ions. | 2013-03-21 |
20130071937 | TEST STRIP FOR THE DETECTION OF EQUOL - Subject of the invention is a test strip for the detection of equol by a color change. Subject of the invention are also methods for producing the test strip, methods for using the test strip, and uses of the test strip. | 2013-03-21 |
20130071938 | METHOD FOR ANALYZING SUGAR CHAIN BY MASS SPECTROMETRY - It has been found out that it is possible to increase the ionization efficiency of a sample sugar chain by methylating hydroxyl groups of the sugar chain before MALDI-TOF MS measurement. This enables quantitative and structural analyses on the sample sugar chain with high accuracy. | 2013-03-21 |
20130071939 | URINE ANALYSIS METHOD, DEVICE THEREOF, PROGRAM USED IN URINE ANALYSIS METHOD, AND STORAGE MEDIUM THEREOF - An analysis device includes determination means, capable of performing a first determination on whether a specific component in urine is positive or negative, on the basis of a color reaction between a reagent and the specific component in urine; and optical measurement means capable of working out data on light absorption characteristics of the urine itself with respect to light of a predefined wavelength region. When the data on the light absorption characteristics lies within a predefined range, and a result of the first determination is either positive or negative as established beforehand, the determination means changes the result of the first determination to a false positive or a false negative, or performs second determination to the effect that there is a likelihood of a false positive or a false negative. | 2013-03-21 |
20130071940 | METHODS OF CHEMOSELECTIVE DERIVATION OF MULTIPLE CLASSES OF METABOLITES - Chemoselective derivatization of biological amines, carboxylic acids, aldehydes or ketones are employed in methods to detect a plurality of components, or members of a component, such as metabolites, that vary in molecular structure. The methods of the invention can be employed in aqueous and nonaqueous conditions. | 2013-03-21 |
20130071941 | GRAPHENE DEFECT DETECTION - Technologies are generally described for a method and system configured effective to detect a defect in a sample including graphene. An example method may include receiving a sample, where the sample may include at least some graphene and at least some defects in the graphene. The method may further include exposing the sample to a gas under sufficient reaction conditions to produce a marked sample, where the marked sample may include marks bonded to at least some of the defects. The method may further include placing the marked sample in a detector system. The method may also include detecting at least some of the marks with the detector system. | 2013-03-21 |
20130071942 | System and Method for Small Molecule Detection - A system for analyzing a content of a sample material is presented. The system includes a fiber sensitized to a first substance, and at least one electrode configured to expose the fiber to an electric field. The system includes an optical sensor configured to detect a displacement of the fiber when the fiber is exposed to the electric field, and a processor configured to use the displacement of the fiber to characterize a content of the sample material. | 2013-03-21 |
20130071943 | SURFACE WITH TWO PAINT STRIPS FOR DETECTION AND WARNING OF CHEMICAL WARFARE AND RADIOLOGICAL AGENTS - A system for warning of corrosion, chemical, or radiological substances. The system comprises painting a surface with a paint or coating that includes an indicator material and monitoring the surface for indications of the corrosion, chemical, or radiological substances. | 2013-03-21 |
20130071944 | SAMPLE PREPARATION DISPOSABLE DEVICES AND SAMPLE COLLECTION AND PREPARATION METHODS USING SAME - An article of manufacture embodiment comprises a sample cartridge including a sample substrate, and an enclosure including a sample ingress port. The enclosure mates with the sample cartridge to define a sample container containing the sample substrate which is accessible in the sample container via the sample ingress port. The sample cartridge including the sample substrate is removable from the sample container. A sampling method embodiment comprises disposing a sample on a sample substrate in a sample container and removing a sample cartridge including the sample substrate from the sample container. An article of manufacture embodiment comprises a sample substrate, a sample container containing the sample substrate and including a sample ingress port providing access to the sample substrate in the sample container, and a sample cartridge including the sample substrate. The sample cartridge including the sample substrate is removable as a unit from the sample container. | 2013-03-21 |
20130071945 | MATERIALS AND METHODS FOR CAPILLARY MICROEXTRACTION IN COMBINATION WITH HIGH-PERFORMANCE LIQUID CHROMATOGRAPHY - Germania-based sol-gel organic-inorganic hybrid coatings were prepared for on-line coupling of capillary microextraction with high-performance liquid chromatography. A germania-based sol-gel precursor, tetra-n-butoxygermane and a hydroxy-terminated triblock copolymer, poly(ethylene oxide)-block-poly(propylene oxide)-block-poly(ethylene oxide), were chemically anchored to the inner walls of a fused silica capillary (0.25 mm I.D.). Scanning electron microscopy images of the sol-gel germania triblock polymer coating were obtained to estimate the coating thickness. The analyte distribution constants between a sol-gel germania organic-inorganic hybrid coating and the samples (K | 2013-03-21 |
20130071946 | Suspension Container For Binding Particles For The Isolation Of Biological Material - A device, method and system is provided for binding particles for the separation and/or isolation of biological materials. In particular, a container is provided including a suspension of binding particles for the isolation of biological material, inner walls forming an elongate groove at the bottom of said container, and a cover having openings and/or being penetrable for a linear arrangement of multiple pipets or pipet tips, said openings being located above and parallel to said elongate groove. | 2013-03-21 |
20130071947 | CHIRALITY SENSOR AND METHOD FOR DETECTION OF AFLATOXIN BY USING THE SENSOR - A universal chirality sensor based on immuno-recognition-driven nanoparticle assembly has been fabricated. The design of smart 10 nm AuNP-antigen and 20 nmAuNP-antibody described for the detection of aflatoxin B1. 10 nm AuNP-antigen and 20 nmAuNP-antibody assemble to symmetric plasmonic nanoparticle dimers, which induced CD signal. The addition of aflatoxin B1 to the chirality sensor resulted in transverse CD signal compared to a blank control as shown by CD measurements. This process also allowed the rapid and facile determination of concentrations of aflatoxin B1 in drinking water (tap water). Good linearity for all calibration curves was obtained, and the limit of detection (LOD) for aflatoxin B1 was 0.02 ng/mL in tap water. | 2013-03-21 |
20130071948 | PROCESS FOR PRODUCING SUPRAMOLECULAR FIBER - A method for preparing a linearly extended supramolecular fiber or a plurality of linearly aligned supramolecular fibers, which comprises the step of allowing supramolecular monomers to be self-assembled in a microfluidic channel. | 2013-03-21 |
20130071949 | IMMUNOASSAY FOR QUANTIFICATION OF AN UNSTABLE ANTIGEN SELECTED FROM BNP AND proBNP - The present invention relates to an immunoassay for detection of BNP, proBNP and fragments thereof. Essentially the assay comprises: a) contacting the antigen with a first antibody specific to a fragment corresponding to amino acids 11-22 of BNP, or to a part of this peptide comprising at least three amino acids of said sequence, to obtain a first order immune complex. b) contacting the first order immune complex obtained at step (a) with a second antibody recognizing said first order immune complex, to obtain a second order immune complex, wherein said antibody is unable to recognize free BNP, proBNP or free first antibody; c) Detecting the second order immune complex. | 2013-03-21 |
20130071950 | Agglutination Based Sample Testing Device - A sample testing device for testing for the presence of a component of interest in a liquid sample includes: (a) a capillary pathway having an upstream end and a downstream end and incorporating a reagent system capable of causing agglutination with the component; (b) optionally, a control capillary pathway; (c) a sampling region to which the liquid sample is applied and from which the sample is able to enter the upstream ends of the test and control capillaries; (d) a power source; (e) detection arrangements electrically associated with the power source for detecting the presence of liquid at a downstream region of the capillaries; (f) a display operated by the power source for indicating the result of the test; and (g) a signal processor associated with the power source, detection arrangement and display for evaluating the result of the test and providing the result on the display. | 2013-03-21 |
20130071951 | METHODS AND COMPOSITIONS FOR DETERMINING THE PURITY OF CHEMICALLY SYNTHESIZED NUCLEIC ACIDS - This application describes an antibody that specifically binds to a synthetic oligomer (e.g., an oligonucleotide or oligopeptide) having a organic protecting group covalently bound thereto, which antibody does not bind to that synthetic oligomer when the organic protecting group is not covalently bound thereto. Methods of making and using such antibodies are also disclosed, along with cells for making such antibodies and articles carrying immobilized oligomers that can be used in assay procedures with such antibodies. | 2013-03-21 |
20130071952 | LUMINESCENT POLYMER CYCLIC AMPLIFICATION - The present invention is directed to a luminescent immunoassay method for detecting an analyte in a liquid sample with high sensitivity. The invention provides a unique combination of (i) using a probe having a small sensing surface area for binding analyte molecules, (ii) using a high molecular weight branched polymer conjugated with multiple binding molecules and multiple luminescent labels, and (iii) cycling the probe having immunocomplex formed back to the reagent vessel and amplification vessel 1-10 times and repeating the reaction with the reagent and the amplification polymer, to improve the sensitivity of detection level. For each cycling, the luminescent signal is increased significantly over the noise. | 2013-03-21 |
20130071953 | GDF-15 BASED MEANS AND METHODS FOR SURVIVAL AND RECOVERY PREDICTION IN ACUTE INFLAMMATION - A method for diagnosing whether a subject suffering from an acute inflammation and in some cases systemic inflammatory response syndrome (SIRS) is at increased risk for mortality. The method comprises determining the amount of the biomarker GDF-15 in a sample of said subject and comparing said amount to a reference. The method also relates to monitoring the development of acute inflammation in a subject by determining the amount of the biomarker GDF-15 in a first and a second sample of said subject wherein said first sample has been obtained prior to said second sample and comparing the amount of GDF-15 in said first and said second sample. Further encompassed are diagnostic devices and kits for carrying out the aforementioned methods. | 2013-03-21 |
20130071954 | MAGNETIC RANDOM ACCESS MEMORY (MRAM) WITH ENHANCED MAGNETIC STIFFNESS AND METHOD OF MAKING SAME - A spin toque transfer magnetic random access memory (STTMRAM) element and a method of manufacturing the same is disclosed having a free sub-layer structure with enhanced internal stiffness. A first free sub-layer is deposited, the first free sub-layer being made partially of boron (B). Annealing is performed of the STTMRAM element at a first temperature after depositing the first free sub-layer to reduce the B content at an interface between the first free sub-layer and the barrier layer. Cooling down of the STTMRAM element to a second temperature that is lower than the first temperature is performed and a third free sub-layer is directly deposited on top of the second free layer, with the third free sub-layer being made partially of boron (B), wherein the amount of B in the third sub-free layer is less than the amount of B in the second free sub-layer. | 2013-03-21 |
20130071955 | PLASMA ETCHING METHOD - A method for processing a substrate to form a desired pattern by an etching process after forming a mask pattern over the substrate includes the steps of: forming two layers over the substrate; measuring a width of the mask pattern or an etched pattern of one of the two layers; and adjusting a flow rate of any one of HBr and other gases, used in the etching process, based on the measured width. The two layers may include a silicon nitride layer and an organic dielectric layer. | 2013-03-21 |
20130071956 | Die Bonder and Bonding Method - With a die bonder or a bonding method, the die is adsorbed by the collet, the dicing tape to which the die is adsorbed is thrust up, the die adsorbed by the collet, and thrust up is peeled from the dicing tape, and the peeled die is bonded to the substrate. When the decrease in the air leak flow rate through the gap between the collet and the die upon the thrust up is smaller than the decrease in the normal peel by a predetermined amount, it is judged that a deflection occurs in the die. | 2013-03-21 |
20130071957 | System and Methods for Semiconductor Device Performance Prediction During Processing - Methods and systems for predicting semiconductor device performance criteria during processing. A method is described that includes receiving a semiconductor wafer; performing semiconductor processing on the semiconductor wafer forming active devices that, when completed, will exhibit a device performance criteria; during the semiconductor processing, measuring in line at least one device performance criteria related physical parameter; projecting an estimated value for the device performance criteria of the active devices using the at least one in line measurement and using estimated measurements for device performance criteria related physical parameters corresponding to later semiconductor processing steps; comparing the estimated value for the device performance criteria to an acceptable range; and determining, based on the comparing, whether the active devices on the semiconductor wafer will have a device performance criteria within the acceptable range. A system for processing semiconductor wafers that includes a programmable processor for performing the methods is described. | 2013-03-21 |
20130071958 | MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In wafer probe inspection for a flip-chip semiconductor device having a solder bump, electric test may be performed at a high temperature by causing a probe needle to directly contact a solder bump over a wafer. The inventors have examined such high temperature probe tests in various ways and revealed the following problems. When a high temperature probe test is performed at 90° C. or higher using a palladium alloy probe needle, tin diffusion due to a solder bump occurs at the needle point to raise resistance, resulting in causing open failure. According to the invention of the present application, at least the tip of a palladium-based probe needle has mainly a granular grain structure in a high temperature probe test performed with the palladium-based probe needle contacting a solder bump electrode over a semiconductor wafer. | 2013-03-21 |
20130071959 | OVJP PATTERNING OF ELECTRONIC DEVICES - A method for forming an electronic device such as a passive color OLED display. Bottom electrodes are patterned onto a substrate in rows. Raised posts formed by photoresist are patterned into columns oriented orthogonally to the bottom row electrodes. One or more organic layers, such as R, G, B organic emissive layers are patterned over the raised posts and bottom electrodes using organic vapor jet printing (OVJP). An upper electrode layer is applied over the entire device and forms electrically isolated columnar electrodes due to discontinuities in the upper electrode layer created by the raised columnar posts. This permits patterning of the upper electrodes over the organic layers without using photolithography. A device formed by this method is also described. | 2013-03-21 |
20130071960 | INTEGRATED RARE EARTH DEVICES - The invention includes a single chip having multiple different devices integrated thereon for a common purpose. The chip includes a substrate having a peripheral area, a mid-chip area, and a central area. A plurality of FETs are formed in the peripheral area with each FET having a layer of single crystal rare earth material in at least one of a conductive channel, a gate insulator, or a gate stack. A plurality of photonic devices including light emitting diodes or vertical cavity surface emitting lasers are formed in the mid-chip area with each photonic device having an active layer of single crystal rare earth material. A plurality of photo detectors are formed in the central area. | 2013-03-21 |
20130071961 | LARGE AREA HERMETIC ENCAPSULATION OF AN OPTOELECTRONIC DEVICE USING VACUUM LAMINATION - Apparatus for accurately picking and placing one or more optoelectronic devices for vacuum lamination of materials in a way that minimizes stress to the materials. | 2013-03-21 |
20130071962 | Method of Manufacturing TFT Array Substrate and TFT Array Substrate - The invention discloses a method of manufacturing TFT array substrate and a TFT array substrate, wherein the manufacturing method comprises the following steps: sequentially depositing a metal film, a insulating layer, and a semiconductor layer, and manufacturing a gate line and a gate electrode using a composition method; depositing a insulating layer, and manufacturing a channel region protecting layer using the composition method; sequentially depositing a doped semiconductor layer and a metal layer; forming a source electrode, a drain electrode and a data line using the composition method; and cutting the doped semiconductor layer and the metal layer to form an energizing channel; and depositing an ITO layer, and forming a pixel electrode by the ITO layer using the composition method. Because four-composition technologies are used by the invention, the gate electrode, the gate line, and the active layer are manufactured by the single-composition technology, and the pixel electrode, the data line, the source electrode, the drain electrode, the channel and the like are directly formed by the completely developed photoetching or dry etching method; the manufacturing difficulty of the array substrate is greatly reduced; the production cost of the array substrate is reduced; and the production efficiency is increased. The TFT component formed by the array substrate is of back-channel protection type structure in favour of reduction of the off-state current of the component. | 2013-03-21 |
20130071963 | METHOD OF FABRICATING A THIN FILM TRANSISTOR AND METHOD OF FABRICATING AN ORGANIC LIGHT-EMITTING DISPLAY DEVICE - A thin film transistor fabrication method allows forming a first photoresist pattern on a triple layer of insulation, conductive and metal films opposite to a semiconductor pattern. A first metal pattern and a conductive pattern are formed through an etch process before forming source and drain regions through a first ion injection process. A second photoresist pattern with a narrower width than that of the first photoresist pattern is derived from the first photoresist pattern. The first metal pattern is reformed into a second metal pattern with a narrower width than that of the second photoresist pattern. A process is performed that includes removing the second photoresist pattern, forming LDD (Lightly Doped Drain) regions in the semiconductor pattern, and forming GOLDD (Gate Overlap LDD) regions in the semiconductor pattern. A second insulation film is formed before forming source and drain electrodes on the second insulation film. | 2013-03-21 |
20130071964 | METHOD OF MANUFACTURING AN ELECTROMECHANICAL TRANSDUCER - Provided is a method of manufacturing an electromechanical transducer having a reduced variation in a breakdown strength caused by a variation in flatness of an insulating layer. In the method of manufacturing the electromechanical transducer, a first insulating layer is formed on a first substrate, a barrier wall is formed by removing a part of the first insulating layer, and a second insulating layer is formed on a region of the first substrate after the part of the first insulating layer has been removed. Next, a gap is formed by bonding a second substrate on the barrier wall, and a vibration film that is opposed to the second insulating layer via the gap is formed from the second substrate. In the forming of the barrier wall, a height on a gap side in a direction vertical to the first substrate becomes lower than a height of a center portion. | 2013-03-21 |
20130071965 | In-Situ Fabrication Method for Silicon Solar Cell - An in-situ fabrication method for a silicon solar cell includes the following steps: pretreating a silicon chip; placing the pretreated silicon chip in an implantation chamber of a plasma immersion ion implantation machine; completing the preparation of black silicon via a plasma immersion ion implantation process; making a PN junction and forming a passivation layer on the black silicon; after making the PN junction and forming the passivation layer, removing the black silicon from the plasma immersion ion implantation machine; preparing a metal back electrode on the back of the black silicon; preparing a metal grid on the passivation layer; obtaining a solar cell after encapsulation. Said method enables black silicon preparation, PN junction preparation, and passivation layer formation in-situ, greatly reducing the amount of equipment needed for the preparation of solar cells and the preparation cost. In addition, the method is simple and easy to control. | 2013-03-21 |
20130071966 | COMBINATORIAL METHODS FOR DEVELOPING SUPERSTRATE THIN FILM SOLAR CELLS - Methods for developing and investigating materials and processes for various layers used in manufacturing CdTe, CIGS, and CZTS TFPV superstrate devices using high productivity combinatorial techniques is described. Typical layers subjected to the HPC techniques include the buffer layers, absorber layers, and the contact interface layers. | 2013-03-21 |
20130071967 | Method for Making a Nickel Film for Use as an Electrode of an N-P Diode or Solar Cell - Disclosed is a method for making a nickel film for use as an electrode of an n-p diode or solar cell. A light source is used to irradiate an n-type surface of the n-p diode or solar cell, thus producing electron-hole pairs in the n-p diode or solar cell. For the electric field effect at an n-p interface, electrons drift to and therefore accumulate on the n-type surface. With a plating agent, the diode voltage is added to the chemical potential for electroless plating of nickel on the n-type surface. The nickel film can be used as a buffer layer between a contact electrode and the diode or solar cell. The nickel film reduces the contact resistance to prevent a reduced efficiency of the diode or solar cell that would otherwise be caused by diffusion of the atoms of the electrode in following electroplating. | 2013-03-21 |
20130071968 | COMPOSITION FOR FORMING P-TYPE DIFFUSION LAYER, METHOD OF FORMING P-TYPE DIFFUSION LAYER, AND METHOD OF PRODUCING PHOTOVOLTAIC CELL - The composition for forming a composition for forming a p-type diffusion layer, the composition containing a glass powder and a dispersion medium, in which the glass powder includes an acceptor element and a total amount of a life time killer element in the glass powder is 1000 ppm or less. A p-type diffusion layer and a photovoltaic cell having a p-type diffusion layer are prepared by applying the composition for forming a p-type diffusion layer, followed by a thermal diffusion treatment. | 2013-03-21 |
20130071969 | ELECTRONIC ASSEMBLY APPARATUS AND ASSOCIATED METHODS - A method of fabricating an electronic assembly includes fabricating first and second interconnects. The first interconnect is adapted to interconnect a first die to a substrate. The second interconnect is adapted to interconnect the first die to a second die. The method further includes assembling the first die, the second die, and the substrate together such that the first die is disposed above the substrate, and the second die is disposed below the first die. | 2013-03-21 |
20130071970 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The present invention makes it possible to inhibit cutting burrs from forming in package dicing. | 2013-03-21 |
20130071971 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided. | 2013-03-21 |
20130071972 | METHOD FOR FABRICATING THIN-FILM SEMICONDUCTOR DEVICE FOR DISPLAY - A method for fabricating a thin-film semiconductor device for display according to the present disclosure includes: preparing a glass substrate; forming, above the glass substrate, an undercoat layer including a nitride film; forming a molybdenum metal layer above the undercoat layer; forming a gate electrode from the metal layer by an etching process; forming a gate insulating film above the gate electrode; forming a non-crystalline silicon layer as a non-crystalline semiconductor layer above the gate insulating film; forming a polycrystalline semiconductor layer which is a polysilicon layer by annealing the non-crystalline silicon layer at a temperature in a range from 700° C. to 1400° C.; forming a source electrode and a drain electrode above the polysilicon layer; and performing hydrogen plasma treatment at a stage after the metal layer is formed and before the polysilicon layer is formed, using a radio frequency power in a range from 0.098 W/cm | 2013-03-21 |
20130071973 | METHOD FOR FABRICATING THIN FILM TRANSISTOR ARRAY SUBSTRATE - A method of fabricating a thin film transistor array substrate is disclosed. The method includes: sequentially forming a first passivation layer, a photo acryl layer and a first transparent metal layer on the substrate provided with the source/drain electrodes and so on; forming a common electrode, which is disposed in the pixel region, and first through third contact holes, which are positioned in regions of the drain electrode, the gate pad and the data pad, respectively, using one of a half-tone mask and a diffractive mask; forming a second passivation layer on the substrate provided with the first through third contact holes; exposing the drain electrode, the gate pad and the data pad by removing the first and second passivation layers from the drain electrode region, the gate pad region and data pad region; and forming a pixel electrode on the second passivation layer opposite to the common electrode by forming a second transparent metal layer on the substrate and performing a third mask procedure for the second transparent metal layer. | 2013-03-21 |
20130071974 | Single-Shot Semiconductor Processing System and Method Having Various Irradiation Patterns - High throughput systems and processes for recrystallizing thin film semiconductors that have been deposited at low temperatures on a substrate are provided. A thin film semiconductor workpiece is irradiated with a laser beam to melt and recrystallize target areas of the surface exposed to the laser beam. The laser beam is shaped into one or more pulses. The beam pulses have suitable dimensions and orientations to pattern the laser beam radiation so that the areas targeted by the beam have dimensions and orientations that are conductive to semiconductor recrystallization. The workpiece is mechanically translated along linear paths relative to the laser beam to process the entire surface of the workpiece at high speeds. Position sensitive triggering of a laser can be used to generate laser beam pulses to melt and recrystallize semiconductor material at precise locations on the surface of the workpiece while it is translated on a motorized stage. | 2013-03-21 |
20130071975 | METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present invention provides a method and apparatus for manufacturing a semiconductor device using a PVD method and enabling achievement of a desired effective work function and reduction in leak current without increasing an equivalent oxide thickness. A method for manufacturing a semiconductor device in an embodiment of the present invention includes the steps of: preparing a substrate on which an insulating film having a relative permittivity higher than that of a silicon oxide film is formed; and depositing a metal nitride film on the insulating film. The metal nitride depositing step is a step of sputtering deposition in an evacuatable chamber using a metal target and a cusp magnetic field formed over a surface of the metal target by a magnet mechanism in which magnet pieces are arranged as grid points in such a grid form that the adjacent magnet pieces have their polarities reversed from each other. | 2013-03-21 |
20130071976 | NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME - Nonvolatile memory devices and methods of forming the same are provided, the nonvolatile memory devices may include first regions and second regions which extend in a first direction and are alternately disposed in a semiconductor substrate along a second direction crossing the first direction. Buried doped lines are formed at the first regions respectively and extend in the first direction. The buried doped lines may be doped with a dopant of a first conductivity type. Bulk regions doped with a dopant of a second conductivity type and device isolation patterns are disposed along the second direction. The bulk regions and the device isolation patterns may be formed in the second regions. Word lines crossing the buried doped lines and the bulk regions are formed parallel to one another. Contact structures are connected to the buried doped lines and disposed between the device isolation patterns. | 2013-03-21 |
20130071977 | METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING GATE TO ACTIVE AND GATE TO GATE INTERCONNECTS - Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes processing the IC in a replacement gate technology including forming dummy gates, sidewall spacers on the dummy gates, and metal silicide contacts to active areas. A fill layer is deposited and planarized to expose the dummy gates and the dummy gates are removed. A mask is formed having an opening overlying a portion of the channel region from which the dummy gate was removed and a portion of an adjacent metal silicide contact. The fill layer and a portion of the sidewall spacers exposed through the mask opening are etched to expose a portion of the adjacent metal silicide contact. A gate electrode material is deposited overlying the channel region and exposed metal silicide contact and is planarized to form a gate electrode and a gate-to-metal silicide contact interconnect. | 2013-03-21 |
20130071978 | FABRICATING METHOD OF TRANSISTOR - A fabricating method of a transistor is provided. A patterned sacrificed layer is formed on a substrate, wherein the patterned sacrificed layer includes a plurality of openings exposing the substrate. By using the patterned sacrificed layer as a mask, a doping process is performed on the substrate, thereby forming a doped source region and a doped drain region in the substrate exposed by the openings. A selective growth process is performed to form a source and a drain on the doped source region and the doped drain region, respectively. The patterned sacrificed layer is removed to expose the substrate between the source and the drain. A gate is formed on the substrate between the source and the drain. | 2013-03-21 |
20130071979 | Field Effect Transistor Device with Raised Active Regions - A method for fabricating a field effect transistor device includes forming a gate stack on a substrate, forming a spacer on the substrate, adjacent to the gate stack, forming a first portion of an active region on the substrate, the first portion of the active region having a first facet surface adjacent to the gate stack, forming a second portion of the active region on a portion of the first portion of the active region, the second portion of the active region having a second facet surface adjacent to the gate stack, the first facet surface and the second facet surface partially defining a cavity adjacent to the gate stack. | 2013-03-21 |
20130071980 | METHOD FOR FABRICATING A FINFET DEVICE - A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes forming a fin structure on a semiconductor substrate and forming a gate structure on the fin structure. A capping layer is then formed over the semiconductor substrate, fin structure, and gate structure. The capping layer is patterned to form an opening exposing a second portion of the fin structure. An epitaxial layer is grown in the opening and on the second portion of the fin structure. At least one of a source region and a drain region is provided in the epitaxial layer. The method may continue to remove the capping layer. | 2013-03-21 |
20130071981 | FABRICATING METHOD OF SEMICONDUCTOR ELEMENTS - A fabricating method of a semiconductor element includes the following steps. First, a substrate is provided. A metal gate structure and source/drain electrodes are already formed on the substrate. An amorphization process is performed in the source/drain electrodes to form an amorphous portion. An interlayer dielectric layer is formed on surfaces of the source/drain electrodes and a through hole contact is formed within the interlayer dielectric layer. A silicidation process is performed with the through hole contact and the amorphous portion of the source/drain electrodes to form a metal silicide layer. The fabricating method is capable of finishing the formation of the metal silicide layer in the condition that diameters of the through hole contact is becoming smaller and smaller. | 2013-03-21 |
20130071982 | Nonvolatile Memory Elements with Metal-Deficient Resistive-Switching Metal Oxides - Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal. | 2013-03-21 |
20130071983 | Inductors and Methods for Integrated Circuits - Inductors and methods for integrated circuits that result in inductors of a size compatible with integrated circuits, allowing the fabrication of inductors, with or without additional circuitry on a first wafer and the bonding of that wafer to a second wafer without wasting of wafer area. The inductors in the first wafer are comprised of coils formed by conductors at each surface of the first wafer coupled to conductors in holes passing through the first wafer. Various embodiments are disclosed. | 2013-03-21 |
20130071984 | ATOMIC LAYER DEPOSITION OF HAFNIUM AND ZIRCONIUM OXIDES FOR MEMORY APPLICATIONS - Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack having a metal oxide buffer layer disposed on or over a metal oxide bulk layer. The metal oxide bulk layer contains a metal-rich oxide material and the metal oxide buffer layer contains a metal-poor oxide material. The metal oxide bulk layer is less electrically resistive than the metal oxide buffer layer since the metal oxide bulk layer is less oxidized or more metallic than the metal oxide buffer layer. In one example, the metal oxide bulk layer contains a metal-rich hafnium oxide material and the metal oxide buffer layer contains a metal-poor zirconium oxide material. | 2013-03-21 |
20130071985 | PHASE CHANGE MEMORY DEVICE CAPABLE OF REDUCING DISTURBANCE AND FABRICATION METHOD THEREOF - A phase change memory device capable of reducing disturbances between adjacent PRAM memory cells and a fabrication method are presented. The phase change memory device includes word lines, heating electrodes, an interlayer insulating layer, and a phase change lines. The word lines are formed on a semiconductor substrate and extend in parallel with a constant space. The heating electrodes are electrically connected to the plurality of word lines. The interlayer insulating layer insulates the heating electrodes. The phase change lines extend in a direction orthogonal to the word line and are electrically connected to the heating electrodes. Curves are formed on a surface of the interlayer insulating layer between the word lines such that the effective length of the phase change layer between adjacent heating electrodes is larger than the physical distance between the adjacent heating electrodes. | 2013-03-21 |
20130071986 | PARTIAL ETCH OF DRAM ELECTRODE - A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is first etched and then annealed in a reducing atmosphere or an inert atmosphere to promote the formation of a desired crystal structure and to remove oxygen rich compounds. The binary metal compound may be a metal oxide. Etching the metal oxide (i.e. molybdenum oxide) may result in the removal of oxygen rich phases and the formation of a first electrode material (i.e. MoO | 2013-03-21 |
20130071987 | Band Gap Improvement In DRAM Capacitors - A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic % and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO | 2013-03-21 |
20130071988 | INTERFACIAL LAYER FOR DRAM CAPACITOR - A method for reducing leakage current in DRAM capacitor stacks by introducing dielectric interface layers between the electrodes and the bulk dielectric material. The dielectric interface layers are typically amorphous dielectric materials with a k value between about 10 and about 30 and are less than about 1.5 nm in thickness. Advantageously, the thickness of each of the dielectric interface layers is less than 1.0 nm. In some cases, only a single dielectric interface layer is used between the bulk dielectric material and the second electrode. | 2013-03-21 |
20130071989 | SINGLE-SIDED NON-NOBLE METAL ELECTRODE HYBRID MIM STACK FOR DRAM DEVICES - A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited first dielectric layer. The first high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous, doped high k second dielectric material is form on the first dielectric layer. The dopant concentration and the thickness of the second dielectric layer are chosen such that the second dielectric layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the second dielectric layer is formed on the second dielectric layer. | 2013-03-21 |
20130071990 | Yttrium and Titanium High-K Dielectric Films - This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions. | 2013-03-21 |
20130071991 | Electrode Treatments for Enhanced DRAM Performance - A method for fabricating a dynamic random access memory capacitor is disclosed. The method may comprise depositing a first titanium nitride (TiN) electrode; creating a first layer of titanium dioxide (TiO | 2013-03-21 |
20130071992 | SEMICONDUCTOR PROCESS - A semiconductor process is provided. An insulating layer is formed on a semiconductor substrate. A portion of the insulating layer is removed, so as to form a plurality of isolation structures and a mesh opening disposed between the isolation structures and exposing the semiconductor substrate. By performing a selective growth process, a semiconductor layer is formed from a surface of the semiconductor substrate exposed by the mesh opening, so that the isolation structures are disposed in the semiconductor layer. | 2013-03-21 |
20130071993 | Preparation Method for Full-Isolated SOI with Hybrid Crystal Orientations - A preparation method for a full-isolated silicon on insulator (SOI) substrate with hybrid crystal orientations and a preparation method of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) based on the method are disclosed. In the preparation method for the full-isolated SOI substrate with hybrid crystal orientations provided in the present invention, a SiGe layer is adopted to serve as an epitaxial virtual substrate layer with a first crystal orientation, so as to form a strained top silicon with the first crystal orientation; a polysilicon supporting material is adopted to serve as a support for connecting the top silicon with the first crystal orientation and a top silicon with a second crystal orientation, so that the SiGe layer below the strained top silicon with the first crystal orientation may be removed, and an insulating material is filled to form an insulating buried layer. The top silicon and the insulating buried layer formed in the method have uniform and controllable thickness, the strained silicon formed in the window and the top silicon outside the window have different crystal orientations, so as to provide higher mobility for the NMOS and the PMOS respectively, thereby improving the performance of the CMOS IC. | 2013-03-21 |
20130071994 | METHOD OF INTEGRATING HIGH VOLTAGE DEVICES - The present invention is directed to a method for forming multiple active components, such as bipolar transistors, MOSFETs, diodes, etc., on a semiconductor substrate so that active components with higher operation voltage may be formed on a common substrate with a lower operation voltage device and incorporating the existing proven process flow of making the lower operation voltage active components. The present invention is further directed to a method for forming a device of increasing operation voltage over an existing device of same functionality by adding a few steps in the early manufacturing process of the existing device therefore without drastically affecting the device performance. | 2013-03-21 |
20130071995 | Method of Manufacturing a Semiconductor Device - A method of manufacturing a semiconductor device is disclosed. The exemplary method includes providing a substrate having a source region and a drain region. The method further includes forming a first recess in the substrate within the source region and a second recess in the substrate within the drain region. The first recess has a first plurality of surfaces and the second recess has a second plurality of surfaces. The method also includes epi-growing a semiconductor material in the first and second recesses and, thereafter, forming shallow isolation (STI) features in the substrate. | 2013-03-21 |
20130071996 | JOINT METHOD, JOINT APPARATUS AND JOINT SYSTEM - When joining a processing target substrate and a supporting substrate together by suction-holding the processing substrate and the supporting substrate respectively on a first holding unit and a second holding unit arranged to face each other and pressing the second holding unit toward the first holding unit while heating the substrates by heating mechanisms of the holding units, the present invention preheats at least the processing target substrate before suction-holding the processing target substrate on the first holding unit to suppress generation of particles when joining the processing target substrate and the supporting substrate together so as to properly perform the joining of the processing target substrate and the supporting substrate. | 2013-03-21 |
20130071997 | METHOD FOR REDUCING IRREGULARITIES AT THE SURFACE OF A LAYER TRANSFERRED FROM A SOURCE SUBSTRATE TO A GLASS-BASED SUPPORT SUBSTRATE - A method for reducing irregularities at the surface of a layer transferred from a source substrate to a glass-based support substrate, by generating a weakening zone in the source substrate; contacting the source substrate and the glass-based support substrate; and splitting the source substrate at the weakening zone; wherein the glass-based substrate has a thickness of between 300 μm and 600 μm. | 2013-03-21 |
20130071998 | Electrical Fuse With Metal Line Migration - An electrical fuse device is disclosed. A circuit apparatus can include the fuse device, a first circuit element and a second circuit element. The fuse includes a first contact that has a first electromigration resistance, a second contact that has a second electromigration resistance and a metal line, which is coupled to the first contact and to the second contact, that has a third electromigration resistance that is lower than the second electromigration resistance. The first circuit element is coupled to the first contact and the second circuit element coupled to the second contact. The fuse is configured to conduct a programming current from the first contact to the second contact through the metal line. Further, the programming current causes the metal line to electromigrate away from the second contact to electrically isolate the second circuit element from the first circuit element. | 2013-03-21 |
20130071999 | HIGH THROUGHPUT EPITAXIAL LIFT OFF FOR FLEXIBLE ELECTRONICS - A method of removing a semiconductor device layer from an underlying base substrate is provided in which a sacrificial phosphide-containing layer is formed between a semiconductor device layer and a base substrate. In some embodiments, a semiconductor buffer layer can be formed on an upper surface of the base substrate prior to forming the sacrificial phosphide-buffer layer. The resultant structure is then etched utilizing a non-HF etchant to release the semiconductor device layer from the base semiconductor substrate. After releasing the semiconductor device layer from the base substrate, the base substrate can be re-used. | 2013-03-21 |
20130072000 | Thin film processing equipment and the processing method thereof - This invention discloses a thin film processing equipment for depositing a film on a substrate and a process for depositing a film on a substrate using the same. The thin film processing equipment comprises a reaction chamber, a gas supplying mechanism, and a transferring mechanism. The thin film processing equipment is characterized in that a gas supplying mechanism is capable of moving up-and-down or left-and-right, and a tray is capable of moving up-and-down, thereby the distance between the gas supplying mechanism and the substrate can be adjusted. The film processing equipment is also provided with a heating mechanism with a pumped circulating heat source to improve the formation of thin films | 2013-03-21 |
20130072001 | Nitride Nanowires and Method of Producing Such - The present invention relates to the growing of nitride semiconductors, applicable for a multitude of semiconductor devices such as diodes, LEDs and transistors. According to the method of the invention nitride semiconductor nanowires are grown utilizing a CVD based selective area growth technique. A nitrogen source and a metal-organic source are present during the nanowire growth step and at least the nitrogen source flow rate is continuous during the nanowire growth step. The V/III-ratio utilized in the inventive method is significantly lower than the V/III-ratios commonly associated with the growth of nitride based semiconductor. | 2013-03-21 |
20130072002 | Batch-Type Remote Plasma Processing Apparatus - A plasma processing apparatus comprises a processing chamber in which a plurality of substrates are stacked and accommodated; a pair of electrodes extending in the stacking direction of the plurality of substrates, which are disposed at one side of the plurality of substrates in said processing chamber, and to which high frequency electricity is applied; and a gas supply member which supplies processing gas into a space between the pair of electrodes. | 2013-03-21 |
20130072003 | SCHOTTKY BARRIER DIODE AND METHOD OF FORMING A SCHOTTKY BARRIER DIODE - Disclosed is a silicon-on-insulator-based Schottky barrier diode with a low forward voltage that can be manufactured according to standard SOI process flow. An active silicon island is formed using an SOI wafer. One area of the island is heavily-doped with an n-type or p-type dopant, one area is lightly-doped with the same dopant, and an isolation structure is formed on the top surface above a junction between the two areas. A metal silicide region contacts the lightly-doped side of the island forming a Schottky barrier. Another discrete metal silicide region contacts the heavily-doped area of the island forming an electrode to the Schottky barrier (i.e., a Schottky barrier contact). The two metal silicide regions are isolated from each other by the isolation structure. Contacts to each of the discrete metal silicide regions allow a forward and/or a reverse bias to be applied to the Schottky barrier. | 2013-03-21 |
20130072004 | METHOD OF INTEGRATING HIGH VOLTAGE DEVICES - The present invention is directed to a method for forming multiple active components, such as bipolar transistors, MOSFETs, diodes, etc., on a semiconductor substrate so that active components with higher operation voltage may be formed on a common substrate with a lower operation voltage device and incorporating the existing proven process flow of making the lower operation voltage active components. The present invention is further directed to a method for forming a device of increasing operation voltage over an existing device of same functionality by adding a few steps in the early manufacturing process of the existing device therefore without drastically affecting the device performance. | 2013-03-21 |
20130072005 | METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR SUBSTRATE - To provide a method for manufacturing a nitride semiconductor substrate capable of reducing a cleavage during slicing of a nitride semiconductor single crystal, and capable of improving a yield rate of the nitride semiconductor substrate, comprising: growing a nitride semiconductor single crystal on a seed crystal substrate by vapor phase epitaxy; grinding an outer peripheral surface of the grown nitride semiconductor single crystal; and slicing the nitride semiconductor single crystal with its outer peripheral surface ground, wherein a grinding amount of the outer peripheral surface of the nitride semiconductor single crystal in the step of grinding is 1.5 mm or more. | 2013-03-21 |
20130072006 | Methods of Forming Doped Regions in Semiconductor Substrates - Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant. | 2013-03-21 |
20130072007 | Method for Fabricating Black Silicon by Using Plasma Immersion Ion Implantation - A method for fabricating black silicon by using plasma immersion ion implantation is provided, which includes: putting a silicon wafer into a chamber of a black silicon fabrication apparatus; adjusting processing parameters of the black silicon fabrication apparatus to preset scales; generating plasmas in the chamber of the black silicon fabrication apparatus; implanting reactive ions among the plasmas into the silicon wafer, and forming the black silicon by means of the reaction of the reactive ions and the silicon wafer. The method can form the black silicon which has a strong light absorption property and is sensitive to light, and has advantages of high productivity, low cost and simple production process. | 2013-03-21 |
20130072008 | TECHNIQUE FOR ION IMPLANTING A TARGET - A technique for ion implanting a target is disclosed. In accordance with one exemplary embodiment, the technique may be realized as a method for ion implanting a target, the method comprising: providing a predetermined amount of processing gas in an arc chamber of an ion source, the processing gas containing implant species and implant species carrier, where the implant species carrier may be one of O and H; providing a predetermined amount of dilutant into the arc chamber, wherein the dilutant may comprise a noble species containing material; and ionizing the processing gas and the dilutant. | 2013-03-21 |
20130072009 | METHOD FOR PREPARING A SUBSTRATE BY IMPLANTATION AND IRRADIATION - A method for preparing a substrate for detaching a layer by irradiation of the substrate with a light flux for heating a buried region of the substrate and bringing about decomposition of the material of that region to detach said detachment layer. The method includes fabricating an intermediate substrate including a first buried layer, and a second covering layer that covers all or part of the first layer, with the covering layer being substantially transparent to the light flux and with the buried layer formed by implantation of particles into the substrate, followed by absorbing the flux, and selectively and adiabatically irradiating a treated region of the buried layer until at least partial decomposition of the material constituting it ensues. | 2013-03-21 |
20130072010 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a silicon substrate, a nitride semiconductor layer formed on the silicon substrate, and metal electrodes formed in contact with the silicon substrate. The metal electrodes has first metal layers which are formed in a shape of discrete islands and in contact with the silicon substrate, and second metal layers which are in contact with the silicon substrate exposed among the islands of the first metal layers and are formed to cover the first metal layers. Further, the second metal layers are made of a metal capable of forming ohmic contact with silicon, and the first metal layers are made of an alloy containing a metal and silicon, in which the metal is different than that in the second metal layer. | 2013-03-21 |
20130072011 | METHOD OF REPAIRING PROBE PADS - A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced. | 2013-03-21 |
20130072012 | Method For Forming Package Substrate With Ultra-Thin Seed Layer - A method for forming a package substrate with a seed layer is provided, which includes a step of etching away the metal foil laminated on the substrate, so that the substrate has a rough surface, and a step of forming an ultra-thin seed layer on the rough surface of the substrate, wherein the ultra-thin seed layer is formed along the rough surface of the substrate, and thereby the ultra-thin seed layer has a rough surface. Consequently, the adhesion between the metal bumps or circuits formed on the ultra-thin rough seed layer and the substrate can be increased. Furthermore, because the seed layer is ultra thin, the metal bumps or the circuit lines formed on the package substrate can be made finer in line widths and line pitches, and the good yield of the package substrate with fine circuit lines can be increased. | 2013-03-21 |
20130072013 | Etching Method and Apparatus - An etching method comprises etching an oxide layer with a first dc bias of a plasma chamber, removing a photoresist layer with a second dc bias of the plasma chamber and etching through a liner film with a third dc bias of the plasma chamber. In order to reduce the copper deposition on the wall of the plasma chamber, the third dc bias is set to be less than the first and second dc bias. | 2013-03-21 |
20130072014 | Method for Forming Contact in an Integrated Circuit - A method for forming an integrated circuit system includes providing an integrated circuit device; and forming an integrated contact over the integrated circuit device including: providing a via over the integrated circuit device; forming a selective metal in the via; forming at least one nanotube over the selective metal; and forming a cap over the nanotubes. | 2013-03-21 |
20130072015 | Inexpensive Electrode Materials to Facilitate Rutile Phase Titanium Oxide - This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO | 2013-03-21 |
20130072016 | METHODS OF FORMING CONDUCTIVE CONTACTS WITH REDUCED DIMENSIONS - Disclosed herein are various methods of forming conductive contacts with reduced dimensions and various semiconductor devices incorporating such conductive contacts. In one example, one method disclosed herein includes forming a layer of insulating material above a semiconducting substrate, wherein the layer of material has a first thickness, forming a plurality of contact openings in the layer of material having the first thickness and forming an organic material in at least a portion of each of the contact openings. This illustrative method further includes the steps of, after forming the organic material, performing an etching process to reduce the first thickness of the layer of insulating material to a second thickness that is less than the first thickness, after performing the etching process, removing the organic material from the contact openings and forming a conductive contact in each of the contact openings. | 2013-03-21 |
20130072017 | Lithographic Method for Making Networks of Conductors Connected by Vias - A method of lithography for formation of two networks of conductors connected by vias in microelectronic integrated circuits comprises, after formation of a first network of buried conductors under an insulating layer: deposition and etching of a sacrificial layer on a substrate, formation of spacers along all edges of elements of the sacrificial layer; removal of this layer; etching of a masking layer. Then, two successive etchings of the insulating layer are carried out, over two successive depths, one defining the depth of the conductors of the second network, the other defining a complement of depth needed at the desired locations for the vias. One of the etchings is defined by the masking layer and corresponds to the locations of the conductors of the second network; the other is defined both by the spacers and by openings in a layer etched by lithography and corresponds to the locations of the vias. Lastly, following the two etchings, the regions etched into the insulating material of the substrate are filled with a conductive material which forms the conductors and the vias at the same time. | 2013-03-21 |
20130072018 | Repair of Damaged Surface Areas of Sensitive Low-K Dielectrics of Microstructure Devices After Plasma Processing by In Situ Treatment - Damaged surface areas of low-k dielectric materials may be efficiently repaired by avoiding the saturation of dangling silicon bonds after a reactive plasma treatment on the basis of OH groups, as is typically applied in conventional process strategies. The saturation of the dangling bond may be accomplished by directly initiating a chemical reaction with appropriate organic species, thereby providing superior reaction conditions, which in turn results in a more efficient restoration of the dielectric characteristics. | 2013-03-21 |
20130072019 | METHODS FOR FORMING SEMICONDUCTOR DEVICES - Embodiments of methods for forming a semiconductor device are provided. The method includes forming a metal layer overlying a dielectric material. A thickness of the metal layer is reduced including oxidizing an exposed outer portion of the metal layer to form a metal oxide portion overlying a remaining portion of the metal layer and removing the metal oxide portion. | 2013-03-21 |
20130072020 | Method For Ensuring DPT Compliance for Auto-Routed Via Layers - A method of generating an integrated circuit with a DPT compatible via pattern using a reduced DPT compatible via design rule set. A reduced DPT compatible via design rule set. A method of forming an integrated circuit using a via pattern generated from a reduced DPT compatible design rule set. | 2013-03-21 |
20130072021 | COMPOSITION AND METHOD FOR POLISHING ALUMINUM SEMICONDUCTOR SUBSTRATES - The invention provides a chemical-mechanical polishing composition comprising coated α-alumina particles, an organic carboxylic acid, and water. The invention also provides a chemical-mechanical polishing composition comprising an abrasive having a negative zeta potential in the polishing composition, an organic carboxylic acid, at least one alkyldiphenyloxide disulfonate surfactant, and water, wherein the polishing composition does not further comprise a heterocyclic compound. The abrasive is colloidally stable in the polishing composition. The invention further provides methods of polishing a substrate with the aforesaid polishing compositions. | 2013-03-21 |
20130072022 | METHOD OF FORMING PATTERNS FOR SEMICONDUCTOR DEVICE - Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region. | 2013-03-21 |
20130072023 | METHOD OF CONTROLLED LATERAL ETCHING - A method of controlled lateral etching is disclosed. In one embodiment, the method may comprise: forming on a first material layer, which comprises a protruding structure, a second material layer; forming spacers on outer surfaces of the second material layer opposite to vertical surfaces of the protruding structure; forming a third material layer on surfaces of the second material layer and the spacers; forming on the third material layer a mask layer which extends in a direction lateral to a surface of the first material layer; and laterally etching portions of the respective layers arranged on the vertical surfaces of the protruding structure. | 2013-03-21 |
20130072024 | APPARATUS FOR SPATIAL AND TEMPORAL CONTROL OF TEMPERATURE ON A SUBSTRATE - An apparatus for control of a temperature of a substrate has a temperature-controlled base, a heater, a metal plate, a layer of dielectric material. The heater is thermally coupled to an underside of the metal plate while being electrically insulated from the metal plate. A first layer of adhesive material bonds the metal plate and the heater to the top surface of the temperature controlled base. This adhesive layer is mechanically flexible, and possesses physical properties designed to balance the thermal energy of the heaters and an external process to provide a desired temperature pattern on the surface of the apparatus. A second layer of adhesive material bonds the layer of dielectric material to a top surface of the metal plate. This second adhesive layer possesses physical properties designed to transfer the desired temperature pattern to the surface of the apparatus. The layer of dielectric material forms an electrostatic clamping mechanism and supports the substrate. | 2013-03-21 |
20130072025 | COMPONENT OF A SUBSTRATE SUPPORT ASSEMBLY PRODUCING LOCALIZED MAGNETIC FIELDS - A component of a substrate support assembly such as a substrate support or edge ring includes a plurality of current loops incorporated in the substrate support and/or the edge ring. The current loops are laterally spaced apart and extend less than halfway around the substrate support or edge ring with each of the current loops being operable to induce a localized DC magnetic field of field strength less than 20 Gauss above a substrate supported on the substrate support during plasma processing of the substrate. When supplied with DC power, the current loops generate localized DC magnetic fields over the semiconductor substrate so as to locally affect the plasma and compensate for non-uniformity in plasma processing across the substrate. | 2013-03-21 |
20130072026 | Formation of a Masking Layer on a Dielectric Region to Facilitate Formation of a Capping Layer on Electrically Conductive Regions Separated by the Dielectric Region - A masking layer is formed on a dielectric region of an electronic device so that, during formation of a capping layer on electrically conductive regions that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; capping layer material formed over the dielectric region can be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material a semiconductor material, or an electrically insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition. | 2013-03-21 |
20130072027 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING METHOD, SUBSTRATE PROCESSING APPARATUS AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM - Provided is a method of manufacturing a semiconductor device having a structure in which an oxide film and a nitride film are stacked. The method includes forming a stacked film having an oxide film and a nitride film stacked therein on a substrate in a processing container by alternately performing a first cycle and a second cycle a predetermined number of times, the first cycle comprising forming the oxide film by supplying a source gas, a nitriding gas and an oxidizing gas to the substrate in the processing container a predetermined number of times, and the second cycle comprising forming the nitride film by supplying the source gas and the nitriding gas to the substrate in the processing container a predetermined number of times, wherein the forming of the oxide film and the forming of the nitride film are consecutively performed while retaining a temperature of the substrate constant. | 2013-03-21 |
20130072028 | PROCESS FOR FABRICATING SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING METAL OXIDE SEMICONDUCTOR DEVICE - A process for fabricating a semiconductor device is described. A silicon oxide layer is formed. A nitridation process including at least two steps is performed to nitridate the silicon oxide layer into a silicon oxynitride (SiON) layer. The nitridation process comprises a first nitridation step and a second nitridation step in sequence, wherein the first nitridation step and the second nitridation step are different in the setting of at least one parameter. | 2013-03-21 |
20130072029 | SURFACE TREATING METHOD AND FILM DEPOSITING METHOD - A surface treating method for treating a surface of a substrate inside a process chamber includes the steps of generating an atmosphere containing no moisture in the process chamber, heating the substrate inside the atmosphere containing no moisture in the process chamber; and causing a reaction between the substrate and an adhesion accelerating agent by feeding the adhesion accelerating agent gas into the process chamber. | 2013-03-21 |
20130072030 | METHOD FOR PROCESSING HIGH-K DIELECTRIC LAYER - A method for processing a high-k dielectric layer includes the following steps. A semiconductor substrate is provided, and a high-k dielectric layer is formed thereon. The high-k dielectric layer has a crystalline temperature. Subsequently, a first annealing process is performed, and a process temperature of the first annealing process is substantially smaller than the crystalline temperature. A second annealing process is performed, and a process temperature of the second annealing process is substantially larger than the crystalline temperature. | 2013-03-21 |