12th week of 2012 patent applcation highlights part 29 |
Patent application number | Title | Published |
20120069612 | ARRANGEMENT FOR EXCHANGING POWER - An arrangement for exchanging power with a three-phase electric power network includes a Voltage Source Converter having three phase legs with each a series connection of switching cells. The three phase legs are interconnected in a neutral point by forming a wye-connection. The arrangement also includes a device connected to the neutral point of the converter and configured to provide a current path for a zero-sequence current. A control unit is configured to calculate a value for amplitude and phase position for a zero-sequence current for which, when added to said three phase legs upon generation of a negative-sequence current, the resulting energy stored in energy storing capacitors in each phase leg will be constant and to control semiconductor devices of said switching cells to add such a zero-sequence current to the currents of each phase leg of the converter. | 2012-03-22 |
20120069613 | TRANSFER CONTROL DEVICE - There is provided a control device which controls a transformer in accordance with a total loss imposed on a load driving system including the transformer and a load. In a control device of a transformer that boosts or drops an output voltage of a DC power supply and provides the output voltage to a load, the control device includes: a switching controller which performs switching control of the transformer; a load power deriving unit which derives load power; a transformer loss decrease amount deriving unit which derives a decrease amount of loss generated in the transformer, based on the load power derived by the load power deriving unit and a transformer ratio of the transformer, when the switching controller performs intermittent control of the transformer; a load loss increase amount deriving unit which derives an increase amount of loss generated in the load when the switching controller performs the intermittent control of the transformer; and a control command unit which instructs the switching controller to perform the intermittent control of the transformer when the decrease amount of transformer loss derived by the transformer loss decrease amount deriving unit is larger than the increase amount of load loss derived by the load loss increase amount deriving unit. | 2012-03-22 |
20120069614 | POWER SUPPLY SYSTEM AND METHOD INCLUDING POWER GENERATOR AND STORAGE DEVICE - The present invention relates to a power supply system and method including a power generator and a storage device. Specifically, the power supply method using a power supply system which includes a power generator, a storage device, a unidirectional converter, and a bidirectional interleaved converter, and in which the other side of the unidirectional converter is connected to the other side of the bidirectional interleaved converter and power is output from the other side of the unidirectional converter, the power supply method comprises measuring one or more of an amount of power generation of the power generator and an amount of power storage of the storage device; forming a power transfer path by analyzing one or more of the amount of power generation and the amount of power storage; and controlling activation of devices on the formed power transfer path. | 2012-03-22 |
20120069615 | BRIDGELESS POWER FACTOR CORRECTION CONVERTER - A bridgeless power factor correction converter is configured such that a gate driver controls the ON ratio of a booster converter switch so that the ON ratio is gradually increased from 0, i.e., performs soft start control, every time the voltage polarity of an AC input in a totem-pole bridgeless power factor converter (TPBL converter is inverted) is inverted. | 2012-03-22 |
20120069616 | SWITCHING POWER SUPPLY DEVICE, AND ADJUSTABLE POWER SUPPLY SYSTEM INCLUDING THE SAME - According to one embodiment of the invention, there is provided a switching power supply device including a rectifying circuit and a switching operation conversion circuit. The rectifying circuit receives a phase-controlled alternating voltage to rectify to a direct voltage. The switching operation conversion circuit starts up by being applied with the direct voltage, and includes a normally on type switching element and an off driving circuit. The normally on type switching element passes an input current, and the off driving circuit turns off the switching element when the input current reaches a prescribed value. The switching operation conversion circuit converts the direct voltage to an output voltage different from the direct voltage by repeating a switching operation of turning on and off the switching element. | 2012-03-22 |
20120069617 | Switching Power Converters and Controllers Having Auxiliary Power Circuits - Switching device controllers, drive circuits, power converters and related methods are disclosed. One example controller for a switching device includes a drive circuit for controlling the switching device and an auxiliary circuit coupled to the drive circuit. The auxiliary circuit includes an input for receiving a waveform having alternating first and second intervals. The auxiliary circuit is configured to energize the drive circuit during the first intervals and de-energize the drive circuit during the second intervals. One example method of energizing and de-energizing a drive circuit for a switching device includes receiving a waveform having alternating first and second intervals, energizing the drive circuit during the first intervals, and de-energizing the drive circuit during the second intervals. | 2012-03-22 |
20120069618 | INVERTER CONTROL SYSTEM - An inverter control apparatus is provided that offers a ‘soft turn off’ to a gate operation of the inverter so as to securely protect the IGBT. In particular, an inverter control system according to the present invention may include a gate operating portion that controls turn on/off of an IGBT and forcibly turns off the IGBT if a short circuit or an over current is detected from the IGBT, a current buffer that amplifies a control current for the turn on/off of the IGBT that is outputted from the gate operating portion, and a filter that delays the forcible turn off control current that is outputted from the gate operating portion. | 2012-03-22 |
20120069619 | Modular Power Converters Usable Alone or In A Multiphase Power Converter - A power converter module for use alone or with other modules in a multiphase power converter. The power converter module has an enclosure that surrounds internal components to prevent radiation of electromagnetic energy, which internal components also limit conduction of electromagnetic energy. The internal components include an EMI filter, a ripple filter, a power converter, and a control interface that communicates with a control system of a power conversion system. The control interface includes a memory that stores information related to the power converter modules so as to improve interchangeability of similar power modules with the multiphase power converter. | 2012-03-22 |
20120069620 | System Including Vertically Stacked Embedded Non Flash Re Writable Non Volatile Memory - A multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of memory planes that are vertically stacked upon one another. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power. | 2012-03-22 |
20120069621 | Integrated Circuits Using Non Volatile Resistivity Sensitive Memory For Emulation Of Embedded Flash Memory - Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element, and retain stored data in the absence of power. A plurality of the memory elements can be arranged in a cross-point array configuration. The interface circuitry electrically communicates with a system configured for memory types, such as DRAM, SRAM, and FLASH, for example, and is operative to communicate with the non-volatile resistivity-sensitive memory to emulate one or more of those memory types. The interface circuitry can be fabricated in a logic plane on a substrate with at least one non-volatile resistivity-sensitive memory vertically positioned over the logic plane. The non-volatile resistivity-sensitive memories may be vertically stacked upon one another. | 2012-03-22 |
20120069622 | Sector Array Addressing for ECC Management - An addressing scheme for non-volatile memory arrays having short circuit defects that manages the demand for error correction. The scheme generally avoids simultaneous active driving of the row line and column line of the selected cell during write. Instead, only a single row or column line is actively driven at any one time and all other array lines are left floating. In addition, the number of memory cells accessed from a given row or column during a fetch may be limited. The benefits of the scheme include preventing short circuits from drawing excess currents through the array and limiting the frequency of read or write failures caused by short circuits to a manageable number. In one embodiment, the scheme maintains the demand for error correction to within the error correction capability of a flash controller. Exemplary embodiments include phase-change memory arrays. | 2012-03-22 |
20120069623 | FERROELECTRIC MEMORY - One embodiment provides a ferroelectric memory including: memory cells each including a ferroelectric memory; first and second bitlines configured to read out cell signals from the memory cells; a first circuit configured to fix, when the cell signal is read from the memory cell to the first bitline, a voltage of the second bitline to a first power-supply voltage, and then set the second bitline to a second power-supply voltage different from the first power-supply voltage; a second circuit configured to set, after the first circuit sets the second bitline to the second power-supply voltage, the second bitline to a reference voltage; and a third circuit configured to amplify a voltage difference between the first bitline to which the cell signal is read and the second bitline to which the reference voltage is set. | 2012-03-22 |
20120069624 | REACTIVE METAL IMPLATED OXIDE BASED MEMORY - Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming an oxide over the first conductive element, implanting a reactive metal into the oxide, and forming a second conductive element over the oxide. | 2012-03-22 |
20120069625 | RESISTANCE CHANGE ELEMENT AND RESISTANCE CHANGE MEMORY - According to one embodiment, a resistance change element includes a first film provided on a first electrode side, a second film provided on a second electrode side, a barrier film sandwiched between the first film and the second film, and metal impurities added in the first or second film, the metal impurities migrating between the first and second films bi-directionally according to a direction of a first electric field generated between the first and second electrodes. The resistance change element has a first resistance state when the metal impurities are present in the first film, and the resistance change element has a second resistance state different from the first resistance state when the metal impurities are present in the second film. | 2012-03-22 |
20120069626 | SEMICONDUCTOR MEMORY DEVICE - The invention provides a semiconductor memory device including a variable resistance element capable of decreasing a variation of a resistance value of stored data due to a large number of times of switching operations and capable of performing a stable writing operation. The device has a circuit that applies a reforming voltage pulse to a memory cell including a variable resistance element of a degraded switching characteristic and a small read margin due to a large number of times of application of a write voltage pulse, to return each resistance state of the variable resistance element to an initial resistance state. By applying the reforming voltage pulse, the variable resistance element can recover at least one resistance state from a variation from the initial resistance state, and can recover the switching characteristic. Accordingly, there is obtained a semiconductor memory device in which a reduction of a read margin is suppressed. | 2012-03-22 |
20120069627 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes: a memory cell array including plural first lines, plural second lines, and plural memory cells each including a variable resistance element; a first decoder connected to at least one ends of the plurality of first lines and configured to select at least one of the first lines; at least one pair of second decoders connected to both ends of the plurality of second lines and configured such that one of the pair of second decoders is selected for selecting the second lines according to a distance between the one of the first lines selected by the first decoder and the both ends of the second lines; and a voltage application circuit configured to apply a certain voltage between the first line and the second line selected by the first decoder and the second decoder. | 2012-03-22 |
20120069628 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device comprises a memory cell which includes a variable resistance element and a current-limiting element that has a nonlinear current-voltage characteristic and a driver which changes the resistance of the variable resistance element by causing a first current to flow in the memory cell. In addition, the nonvolatile semiconductor memory device further comprises a detection module which detects a change in the resistance of the memory cell based on the magnitude of the first current and a current supplying module which causes a second current to flow in the detection module in place of the first current. | 2012-03-22 |
20120069629 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first reference cell being arranged in a first cell array, and a plurality of first fuse cells being arranged in the first cell array. The first reference cell and the plurality of first fuse cells are arranged on the same row or column. | 2012-03-22 |
20120069630 | WRITE VERIFY METHOD FOR RESISTIVE RANDOM ACCESS MEMORY - Write verify methods for resistance random access memory (RRAM) are provided. The methods include applying a reset operation voltage pulse across a RRAM cell to change a resistance of the RRAM cell from a low resistance state to a high resistance state and applying a forward resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance value less than a selected lower resistance limit value. The method also includes applying a reverse resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance values is greater than a selected upper resistance limit value. The reverse resetting voltage pulse has a second polarity being opposite the first polarity. | 2012-03-22 |
20120069631 | MEMORY ELEMENT AND MEMORY DEVICE - A memory device of a resistance variation type, in which data retaining characteristic at the time of writing is improved, is provided. The memory device includes: a plurality of memory elements in which a memory layer is provided between a first electrode and a second electrode so that data is written or erased in accordance with a variation in electrical characteristics of the memory layer; and pulse applying means applying a voltage pulse or a current pulse selectively to the plurality of memory elements. The memory layer includes an ion source layer including an ionic-conduction material and at least one kind of metallic element, and the ion source layer further contains oxygen. | 2012-03-22 |
20120069632 | CURRENT CONTROL, MEMORY ELEMENT, MEMORY DEVICE, AND PRODUCTION METHOD FOR CURRENT CONTROL ELEMENT - Provided is a current steering element that can prevent write didturb even when an electrical pulse with different polarities is applied and that can cause a large current to flow through a variable resistance element. The current steering element includes a first electrode ( | 2012-03-22 |
20120069633 | NONVOLATILE STORAGE DEVICE AND METHOD FOR WRITING INTO THE SAME - The nonvolatile storage device includes a variable resistance element ( | 2012-03-22 |
20120069634 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR INSPECTING THE SAME - When the threshold voltage V | 2012-03-22 |
20120069635 | CAPACITY AND DENSITY ENHANCEMENT CIRCUIT FOR SUB-THRESHOLD MEMORY UNIT ARRAY - A capacity and density enhancement circuit for a sub-threshold memory unit array which can decrease the drain current in the bit lines and enhance the pull-up capability of memory cells. The capacity and density enhancement circuit is composed of a first enhancement transistor, a second enhancement transistor, a first mask transmission gate, a second mask transmission gate, a first logic memory capacitor and a second logic memory capacitor. | 2012-03-22 |
20120069636 | STATIC RANDOM ACCESS MEMORY (SRAM) HAVING BIT CELLS ACCESSIBLE BY SEPARATE READ AND WRITE PATHS - A method is for reading a first bit cell of a static random access memory in which the static random access memory has a first plurality of bit cells including the first bit cell. Each bit cell of the first plurality of bit cells includes a cross coupled pair of inverters for storing a logic state, optimized for being written, and powered by a read voltage during a read of the first plurality of bit cells. Each bit cell of the first plurality of bit cells is coupled to a true read bit line and a true write bit line, and a second plurality of bit cells is coupled to a complementary read bit line and a complementary write bit line. The true and complementary read bit lines are precharged to a precharge voltage of about half the read voltage. The true read bit line is predisposed to a logic low condition. One of a group consisting of a high impedance from the first bit cell to indicate that the logic state is a logic low and a signal voltage greater than the intermediate voltage to indicate that the logic state is a logic high is output from the first bit cell to the true read bit line. | 2012-03-22 |
20120069637 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE - An object is to provide a semiconductor memory device which holds data of an SRAM or a flip-flop circuit and holds data in the SRAM while electric power is not supplied from a reader or electric power is not enough, without changing a battery for driving a power supply corresponding to deterioration of the battery with time, and a semiconductor device provided with the semiconductor memory device. An SRAM cell, a decoder connected to the SRAM cell through a word line, a read/write circuit connected to the SRAM cell through the data line, and a power storage unit connected to the SRAM cell are provided. The power storage unit is charged when data is written to or read from the SRAM cell through the data line. | 2012-03-22 |
20120069638 | SEMICONDUCTOR DEVICE - A semiconductor device which it can accommodate variations in a write current threshold in each memory cell and can secure a write margin is provided. An MRAM device includes an MTJ memory cell arranged in a matrix, plural bit lines each arranged corresponding to a memory cell column, plural digit lines each arranged corresponding to a memory cell row, and a write current adjusting unit which adjusts a current amount of a write current to be flowed through a bit line and/or a digit line, in order to perform a data write to each MTJ memory cell normally. The write current adjusting unit divides the plural bit lines and/or the plural digit lines into units of at least one write current line as division units, and includes plural write current adjusting circuits which adjust the current amount of write current in each of the division units. | 2012-03-22 |
20120069639 | SEMICONDUCTOR STORAGE DEVICE - A memory according to an embodiment includes bit lines, word lines, source lines, magnetic tunnel junction elements and transistors that are serially connected between the bit lines and the source lines, respectively, and a sense amplifier that detects data stored in the magnetic tunnel junction elements. The semiconductor storage device includes multiplexers between the bit lines and the sense amplifier in order to select one of the bit lines to be connected to the sense amplifier, and write amplifiers that are located corresponding to memory cell blocks each of which includes memory cells each including the magnetic tunnel junction element and the transistor and are connected to the bit lines or connected via the multiplexers to the bit lines. To write data, the sense amplifier applies a write voltage to the bit lines and then the write amplifiers hold the write voltage. | 2012-03-22 |
20120069640 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - A magnetoresistive element according to an embodiment includes: a first and second magnetic layers having an easy axis of magnetization in a direction perpendicular to a film plane; and a first nonmagnetic layer interposed between the first and second magnetic layers, at least one of the first and second magnetic layers including a structure formed by stacking a first and second magnetic films, the second magnetic film being located closer to the first nonmagnetic layer, the second magnetic film including a structure formed by repeating stacking of a magnetic material layer and a nonmagnetic material layer at least twice, the nonmagnetic material layers of the second magnetic film containing at least one element selected from the group consisting of Ta, W, Hf, Zr, Nb, Mo, Ti, V, and Cr, one of the first and second magnetic layers having a magnetization direction that is changed by applying a current. | 2012-03-22 |
20120069641 | MAGNETIC MEMORY - According to one embodiment, a magnetic memory includes a magnetoresistive element includes a first reference layer, a first nonmagnetic layer, a recording layer, a second nonmagnetic layer, and a second reference layer which are sequentially stacked, the recording layer being connected to a terminal to which a high-level voltage is applied, a magnetization direction of the recording layer being variable, magnetization directions of the first and second reference layers being invariable and antiparallel, a first selection transistor connected between a first bit line and the first reference layer, and constituted of an N-channel MOSFET, a second selection transistor connected between a second bit line and the second reference layer, and constituted of an N-channel MOSFET, and a word line connected to gates of the first and second selection transistors. | 2012-03-22 |
20120069642 | MAGNETORESISTIVE ELEMENT AND MAGNETIC RANDOM ACCESS MEMORY - According to one embodiment, a magnetoresistive element includes an electrode layer, a first magnetic layer, a second magnetic layer and a nonmagnetic layer. The electrode layer includes a metal layer including at least one of Mo, Nb, and W. The first magnetic layer is disposed on the metal layer to be in contact with the metal layer and has a magnetization easy axis in a direction perpendicular to a film plane and is variable in magnetization direction. The second magnetic layer is disposed on the first magnetic layer and has a magnetization easy axis in the direction perpendicular to the film plane and is invariable in magnetization direction. The nonmagnetic layer is provided between the first and second magnetic layers. The magnetization direction of the first magnetic layer is varied by a current that runs through the first magnetic layer, the nonmagnetic layer, and the second magnetic layer. | 2012-03-22 |
20120069643 | NON-UNIFORM SWITCHING BASED NON-VOLATILE MAGNETIC BASED MEMORY - A non-uniform switching based non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer. Switching current is applied, in a direction that is substantially perpendicular to the fixed layer, barrier layer, first free layer, non-uniform switching layer and the second free layer causing switching between states of the first free layer, second free layer and non-uniform switching layer with substantially reduced switching current. | 2012-03-22 |
20120069644 | Replaceable, precise-tracking reference lines for memory products - Systems and methods to improve reliability of sensing operations of semiconductor memory arrays requiring reading references such as MRAM or any type of phase change memory (PCM), and to improve yield of the memory arrays have been achieved. The memory array is divided into multiple parts, such as sections or segments. Reference word lines or reference bit lines or both are deployed in each of the multiple parts. Thus, the distance between an accessed line and the correspondent reference line is reduced, and hence the parasitic parameter tracking capability is enhanced significantly. Additionally spare reference word lines or spare reference bit lines can be deployed in each of the multiple parts. | 2012-03-22 |
20120069645 | MULTIPLE BIT PHASE CHANGE MEMORY CELL - A phase change memory cell has more than one memory region ( | 2012-03-22 |
20120069646 | SPIN TORQUE TRANSFER MEMORY CELL STRUCTURES AND METHODS - Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an antiferromagnetic material and a multiferroic material in contact with the ferromagnetic storage material, wherein the antiferromagnetic material, the ferromagnetic storage material, and the pinned ferromagnetic material are located between a first electrode and a second electrode. | 2012-03-22 |
20120069647 | SPIN TORQUE TRANSFER MEMORY CELL STRUCTURES AND METHODS - Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more SIT memory cell structures comprise a STT stack including; a pinned ferromagnetic material in contact with an antiferromagnetic material; a tunneling barrier material positioned between a ferromagnetic storage material and the pinned ferromagnetic material; a multiferroic material in contact with the ferromagnetic storage material; and a first electrode and a second electrode, wherein the antiferromagnetic material, the pinned ferromagnetic material, and the ferromagnetic storage material are located between the first electrode and the second electrode. The STT memory cell structure can include a third electrode and a fourth electrode, wherein at least a first portion of the multiferroic material is located between the third and the fourth electrode. | 2012-03-22 |
20120069648 | SPIN TORQUE TRANSFER MEMORY CELL STRUCTURES AND METHODS - Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an antiferromagnetic material. The tunneling barrier material is a multiferroic material and the antiferromagnetic material, the ferromagnetic storage material, and the pinned ferromagnetic material are positioned between a first electrode and a second electrode. | 2012-03-22 |
20120069649 | NON-UNIFORM SWITCHING BASED NON-VOLATILE MAGNETIC BASED MEMORY - A non-uniform switching based non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer. Switching current is applied, in a direction that is substantially perpendicular to the fixed layer, barrier layer, first free layer, non-uniform switching layer and the second free layer causing switching between states of the first free layer, second free layer and non-uniform switching layer with substantially reduced switching current. | 2012-03-22 |
20120069650 | SUB-THRESHOLD MEMORY CELL CIRCUIT WITH HIGH DENSITY AND HIGH ROBUSTNESS - A high-density and high-robustness sub-threshold memory cell circuit, having two PMOS transistors P | 2012-03-22 |
20120069651 | EEPROM-based, data-oriented combo NVM design - A nonvolatile memory device has a combination of FLOTOX EEPROM nonvolatile memory arrays. Each FLOTOX-based nonvolatile memory array is formed of FLOTOX-based nonvolatile memory cells that include at least one floating gate tunneling oxide transistor such that a coupling ratio of the control gate to the floating gate of the floating gate tunneling oxide transistor is from approximately 60% to approximately 70% and a coupling ratio of the floating gate to the drain region of the floating gate tunneling oxide transistor is maintained as a constant of is from approximately 10% to approximately 20% and such that a channel length of the channel region is decreased such that during the programming procedure a negative programming voltage level is applied to the control gate and a moderate positive programming voltage level is applied to the drain region to prevent the moderate positive programming voltage level from exceeding a drain-to-source breakdown voltage. | 2012-03-22 |
20120069652 | Semiconductor Memory Having Both Volatile and Non-Volatile Functionality and Method of Operating - Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a substrate, a floating body to store data in volatile memory and a floating gate or trapping layer configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell. | 2012-03-22 |
20120069653 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to one embodiment includes: a memory cell array; word lines each connected to nonvolatile memory cells; and a control circuit. When executing the data reading operation, the control circuit applies to a selected word line connected to a selected memory cell a first voltage obtained by adding a first adjusting voltage to an intermediate voltage between adjoining two of the threshold voltage distributions; applies to first non-selected word lines adjoining the selected word line a second voltage obtained by subtracting a second adjusting voltage from a reading pass voltage; applies to second non-selected word lines adjoining the first non-selected word lines a third voltage obtained by adding the second adjusting voltage to the reading pass voltage; and applies to third non-selected word lines, the third non-selected word lines being non-selected word lines except the first and second non-selected word lines, the reading pass voltage. | 2012-03-22 |
20120069654 | MEMORY DEVICE AND METHOD FOR ESTIMATING CHARACTERISTICS OF MULTI-BIT PROGRAMMING - Memory devices and/or methods that may estimate characteristics of multi-bit cell are provided. A memory device may include: a multi-bit cell array; a monitoring unit to extract a threshold voltage change over time value for reference threshold voltage states selected from a plurality of threshold voltage states corresponding to data stored in the multi-bit cell array; and an estimation unit to estimate a threshold voltage change over time values for the plurality of threshold voltage states based on the extracted threshold voltage change. Through this, it is possible to monitor a change over time of threshold voltages of a memory cell. | 2012-03-22 |
20120069655 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory string is configured by a plurality of memory transistors and a spare memory transistor connected in series. Word lines are connected to gates of the memory transistors. A spare word line is connected to a gate of the spare memory transistor. The memory string comprises a first semiconductor layer, a charge storage layer, a plurality of first conductive layers, and a second conductive layer. The first semiconductor layer extends in a perpendicular direction with respect to a substrate. The charge storage layer surrounds a side surface of the first semiconductor layer. The plurality of first conductive layers surround a side surface of the first semiconductor layer with the charge storage layer interposed therebetween, and function as the word lines. The second conductive layer surrounds a side surface of the first semiconductor layer with the charge storage layer interposed therebetween, and functions as the spare word line. | 2012-03-22 |
20120069656 | SEMICONDUCTOR STORAGE DEVICE - A memory includes plurality of word lines extending in a first direction, plurality of bit lines extending in a second direction to intersect with the word lines, and a memory cell array including plurality of memory cells connected to the word lines and the bit lines. Plurality of sense amplifiers include detectors configured to detect data transmitted from the memory cells to sense nodes via the corresponding bit lines, and capacitors connected between the sense nodes and a reference potential, respectively, and are provided to be arranged in the second direction from at least a side of one ends of the bit lines. Each of k capacitors corresponding to k detectors, where k is equal to or greater than 2, has a width corresponding to widths of the k detectors, the k capacitors are arranged in the second direction, and the k detectors are arranged in the first direction. | 2012-03-22 |
20120069657 | MEMORY DEVICE AND SELF INTERLEAVING METHOD THEREOF - A memory device includes a memory cell array, a self interleaver configured to interleave and load data on the fly into a buffer circuit using an interleaving scheme, and a control logic configured to control programming of the interleaved data in the memory cell array. | 2012-03-22 |
20120069658 | METHODS, DEVICES, AND SYSTEMS FOR DEALING WITH THRESHOLD VOLTAGE CHANGE IN MEMORY DEVICES - The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having sense circuitry coupled to the array. The control circuitry is configured to determine changes in threshold voltages (Vts) associated with the memory cells without using a reference cell, and adjust the sense circuitry based on the determined changes and without using a reference cell. | 2012-03-22 |
20120069659 | MEMORY WITH INTERLEAVED READ AND REDUNDANT COLUMNS - Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality of groups of regular columns and a plurality of groups of redundant columns. The apparatus also includes a plurality of data latches. Each of the data latches is configured to store data read from a respective one group of regular columns. The apparatus further includes a plurality of redundant data latches. Each of the redundant data latches is configured to store data read from a respective one group of redundant columns. The apparatus also includes a multiplexer configured to selectively output data from the plurality of data latches and the plurality of redundant data latches. | 2012-03-22 |
20120069660 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first transistor has one end connected to one end of the memory string. The second transistor is provided between the other end of the memory string and a second line. The diode is provided between the other end of the first transistor and a first line. The diode comprises a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type. | 2012-03-22 |
20120069661 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit during an erase operation sets a voltage of a first line connected to a selected cell unit to a voltage larger than a voltage of a gate of a first transistor included in the selected cell unit by an amount of a first voltage, sets a voltage difference between a voltage of a first line connected to an unselected cell unit and a voltage of a gate of a first transistor included in the unselected cell unit to a second voltage which differs from the first voltage, applies in the selected cell unit and the unselected cell unit a third voltage to a gate of at least one of dummy memory transistors in a dummy memory string, and applies a fourth voltage to a gate of another one of the dummy memory transistors in the dummy memory string, the fourth voltage being lower than the third voltage. | 2012-03-22 |
20120069662 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes memory cell units including serially-connected memory cells, which includes a semiconductor pillar and conductive and insulation films surrounding the semiconductor pillar. The memory cell units constitute blocks each of which is the minimum unit of data erasure. A pipe layer in at least one pair of adjacent first and second memory cell units of the memory cell units includes a semiconductor layer connected to the semiconductor pillars in the first and second memory cell units, and are connected to first ends of the first and second memory cell units. A conductive plate between the first ends of the first and second memory cell units and the semiconductor substrate contain the pipe layers of at least two blocks and controls conduction of the pipe layers. A supply path structure is connected to the plate and transmitting a potential the plate. | 2012-03-22 |
20120069663 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit. | 2012-03-22 |
20120069664 | FLASH MEMORY SYSTEM AND WORD LINE INTERLEAVING METHOD THEREOF - Provided are a flash memory system and a word line interleaving method thereof. The flash memory system includes a memory cell array, and a word line interleaving logic. The memory cell array is connected to a plurality of word lines. The word line (WL) interleaving logic performs an interleaving operation on WL data corresponding to at least two different wordlines and programming data, including the interleaved data, to the memory cell array. | 2012-03-22 |
20120069665 | Memory Device With Vertically Embedded Non Flash Non Volatile Memory For Emulation Of Nand Flash Memory - A system and a method for emulating a NAND memory system are disclosed. In the method, a command associated with a NAND memory is received. After receipt of the command, a vertically configured non-volatile memory array is accessed based on the command. In the system, a vertically configured non-volatile memory array is connected with an input/output controller and a memory controller. The memory controller is also connected with the input/output controller. The memory controller is operative to interface with a command associated with a NAND memory and based on the command, to access the vertically configured non-volatile memory array for a data operation, such as a read operation or write operation. An erase operation on the vertically configured non-volatile memory array is not required prior to the write operation. The vertically configured non-volatile memory array can be partitioned into planes, blocks, and sub-planes, for example. | 2012-03-22 |
20120069666 | MEMORY SYSTEM - A memory system includes a controller and a memory part including a memory cell array including memory cells, word lines, bit lines including bit line pairs each composed of an even bit line and an odd bit line adjacent to each other, and sense amplifiers provided to the bit line pairs and configured to detect data in selected memory cells connected to a selected word line. When reading data is performed from first memory cells to which writing data is performed first in memory cell pairs each including two adjacent memory cells respectively connected to one of the even bit lines and one of the odd bit lines, the controller controls the memory part so as to change a read level voltage applied to the selected word line depending on a data write state of second memory cells in the memory cell pairs to which writing data is performed later. | 2012-03-22 |
20120069667 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SPEEDING UP DATA WRITE - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array having a plurality of memory cells is connected to a plurality of word lines stacked on a semiconductor substrate, and the memory cells having a charge accumulation layer, and the charge accumulation layers are united between adjacent memory cells. When writing data to a memory cell group connected to the nth (n is a natural number) word line of the memory cell array, the control circuit controls to simultaneously apply the same program voltage to memory cell groups connected to the (n−1)th and (n+1)th word lines. | 2012-03-22 |
20120069668 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor storage device includes a transistor, a first node, a first capacitor, a first switch, and a second switch. One end of the transistor is connected to a first voltage source supplying a first voltage. The first node is charged to the first voltage by the transistor. One of electrodes of the first capacitor is connected to the first node, and the other of the electrodes of the first capacitor is supplied with a first clock signal having a second voltage. One end of the first switch is connected to the first node. The first switch outputs a potential of the first node at a first time at which the first switch is turned on. One end of the second switch is connected to the first node. The second switch outputs the potential of the first node at a second time. | 2012-03-22 |
20120069669 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING AND MANUFACTURING THE SAME - A nonvolatile semiconductor storage device is disclosed. The device includes a cell group having a first memory cell and a second memory cell located first directionally adjacent to the first memory cell, and a programming circuit. The first memory cell is used for data retention and the second memory cell is used for adjustment of a threshold voltage of the first memory cell. The programming circuit is configured to program the first memory cell by applying voltage to the second memory cell to control the threshold voltage of the first memory cell to be higher than a first threshold voltage. | 2012-03-22 |
20120069670 | Semiconductor Integrated Circuit Device for Driving Liquid Crystal Display - The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits. | 2012-03-22 |
20120069671 | MEMORY AND OPERATION METHOD THEREFOR - An operation method for a memory device having a plurality of memory cells includes: reading the plurality of memory cells by a first word line voltage to get a first number of a first logic state; reading the plurality of memory cells by a second word line voltage to get a second number of the first logic state, the second word line voltage different from the first word line voltage; and using the second word line voltage as a target word line voltage if the first number of the first logic state is equal to the second number of the first logic state. | 2012-03-22 |
20120069672 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A nonvolatile semiconductor memory device in accordance with an embodiment includes a memory cell array. A control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write operation being an operation to apply a write pulse voltage to a selected memory cell and an intermediate voltage to an unselected memory cell. The control unit controls the step-up operation such that, in a first period, the intermediate voltage is maintained at a constant value, and, in a second period, the intermediate voltage is raised by a certain value. The control unit controls the step-up operation such that the first period includes an operation to raise the write pulse voltage by a first step-up value, and the second period includes an operation to raise the write pulse voltage by a second step-up value smaller than the first step-up value. | 2012-03-22 |
20120069673 | METHOD AND DEVICE FOR PROGRAMMING DATA INTO NON-VOLATILE MEMORIES - A device includes a non-volatile memory and a control unit, wherein the control unit is configured to change over programming of data of the non-volatile memory from a first programming mode to a second, different programming mode based on the occurrence of a control signal. | 2012-03-22 |
20120069674 | FLASH MEMORY DEVICE AND RELATED PROGRAM VERIFICATION METHOD - A nonvolatile memory device performs a program operation using an incremental pulse programming (ISPP) scheme in which a plurality of program loops alternate between a coarse-fine verify operation, and a fine verify operation according to a value of a program loop counter. | 2012-03-22 |
20120069675 | REDUCING NOISE IN SEMICONDUCTOR DEVICES - The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes sensing the state of the semiconductor device after applying the reset voltage. | 2012-03-22 |
20120069676 | SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME - The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened. | 2012-03-22 |
20120069677 | NONVOLATILE MEMORY DEVICE AND ERASURE METHOD THEREOF - A method in performing an erasure operation of a nonvolatile memory device includes a step of performing a block erasure operation wherein a plurality of memory cells in a selected block are erased at once, a step of selecting an over-programmed memory cell having a threshold voltage higher than an upper bound verification voltage, and a step of erasing selectively the over-programmed memory cell. | 2012-03-22 |
20120069678 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR DRIVING THE SAME - A storage device according to one embodiment includes memory cells which are connected in series in a first direction and are arranged in a matrix by the arranged series connections, and word lines which connect control gates of the memory cells in a second direction perpendicular to the first direction, in which a first interval and a second interval wider than that are alternately repeated for intervals in the second direction between the memory cells. The storage device according to the embodiment comprises a drive unit for writing data in a first cell, then writing data in a second cell which is connected to the same word line as the first cell and is spaced at the first interval in the second direction, then reading the data in the second cell, and reading the data in the first cell with correction based on the read value of the second cell. | 2012-03-22 |
20120069679 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a memory string including a plurality of memory cells and, a driving unit. In sequentially reading data stored in the memory cells by applying a first signal to the memory cells, a second signal is applied to a second cell. The driving unit applies a third signal to the gate electrodes of all the memory cells prior to the sequential reading. The third signal has a voltage smaller than the second signal and time duration equal to or more than that of a sum of time duration during which the first signal is applied to all the memory cells. In a period prior to the third signal application, the driving unit performs at least one of applying a fourth signal to the gate electrodes and matching a potential of the gate electrodes with that of the semiconductor layer. | 2012-03-22 |
20120069680 | NAND WITH BACK BIASED OPERATION - Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are performed with back biased operation, such as to improve high voltage device isolation and cutoff in string drivers and bit line drivers, and no nodes of the circuitry are biased at zero volts | 2012-03-22 |
20120069681 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes a cell array, a controller, and a voltage generator. The cell array includes cells. Each of the cells holds data “0” or “1”. The controller counts the number of times N of sequentially writing the data into the cells. The controller transfers a write voltage and a read voltage. The write voltage and the read voltage are variable according to the number of times N. The voltage generator generates the write voltage and the read voltage. When the N-th (≧2) write request is issued to the cell, the controller causes the voltage generator to generate the read voltage corresponding to an (N−1)th time. The controller causes the voltage generator to generate the write voltage which changes a threshold voltage of the cell. When the cell has reached a prescribed value, the controller erases the data held in the cell. | 2012-03-22 |
20120069682 | WORD LINE BOOSTER FOR FLASH MEMORY DEVICE - A nonvolatile memory device includes an array of rows and columns of memory cells and a plurality of word lines and bit lines associated with the memory cells. The memory device further includes a word line booster circuit coupled with the word lines for supplying a selected word line with the specific voltage as a drive voltage during an operation of the memory device, wherein the word line booster circuit includes a first boosting capacitor and a second boosting capacitor connected in parallel each other adapted to generate a boosting voltage and a first precharge circuit for precharging the first boosting capacitor and the second boosting capacitor. the word line booster circuit further includes a third boosting capacitor operatively connected to the first boosting capacitor and the second boosting capacitor via a charge-sharing transistor, the third boosting capacitor being connected to one end of a load resistor to generate an output signal at the other end of the load resistor when the charge sharing transistor is enabled. In addition, the word line booster circuit includes a high voltage detector to generate a detecting signal in response to a control signal from an address transition detector and the output signal generated by the third boosting capacitor and load resistor and a clock control circuit adapted to enable the charge sharing transistor and to disable one of the first boosting capacitor and the second boosting capacitor upon receiving the control signal from the address transition detector and the detecting signal from the voltage detector. The word line booster circuit further includes a discharge circuit to discharge the boosting voltage at a node connected to the third boosting capacitor. | 2012-03-22 |
20120069683 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes a cell array, an even line, an odd line, and sense amplifiers. The cell array includes memory cells holding data. The even line connects to the memory cells. The odd line connects to the memory cells. The memory cells connect to an odd column or the even column. Each the sense amplifiers selectively connect to the odd line or the even line. Each the sense amplifiers includes a latch circuit, a first transistor, a second transistor, and a third transistor. The latch circuit includes a first node and a second node, and holds the data supplied to the first node. The first transistor supplies read data to the latch circuit. The second transistor transfers the data held by the latch circuit to the wiring. The third transistor transfers the data held by the latch circuit to the wiring. | 2012-03-22 |
20120069684 | SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a semiconductor integrated circuit includes a memory cell array includes data storage units which are arranged at intersections of word lines and bit lines and hold data, a reversing circuit which logically reverses held data stored in the data storage units, and a flag bit column which stores, for each row, a flag for identifying presence/absence of logic reversal of data stored in the data storage units. | 2012-03-22 |
20120069685 | Semiconductor device having optical fuse and electrical fuse - A semiconductor device includes a plurality of first chips, a second chip that controls the first chips, and internal wiring that connects the first chips and the second chip. The first chips each include: an optical fuse; a first latch circuit that retains information on the optical fuse; a second latch circuit that retains information on an electrical fuse, the information being supplied from the second chip through the internal wiring; and a select circuit that selects the information retained in either one of the first and second latch circuits. A redundancy determination signal is generated from the information selected. The information on the electrical fuse is transferred from the second chip to the first chips through the internal wiring. | 2012-03-22 |
20120069686 | LATCH TIMING ADJUSTMENT DEVICE AND MEMORY ACCESS SYSTEM USING THE SAME - A latch timing adjustment device includes: first to third variable delay sections configured to delay a strobe signal by first to third variable delay amounts, respectively; first to third data latch sections configured to latch a data signal in response to the outputs of the first to third variable delay sections, respectively; a comparison section configured to perform comparison between the outputs of the first and second data latch sections and comparison between the outputs of the second and third data latch sections; and a delay adjustment section configured to adjust the first and third variable delay amounts based on the comparison results from the comparison section, and adjust the second variable delay amount based on the first and third variable delay amounts adjusted. | 2012-03-22 |
20120069687 | Semiconductor memory device and read wait time adjustment method thereof, memory system, and semiconductor device - A controller includes a set of first terminals to be coupled to a device that is under control of the controller, and a control circuit configured to generate and output onto the set of first terminals synchronous mode information including a selected one of selection and non-selection modes, the selection mode causing the device to return to the controller a first data signal while activating a first data strobe signal that is synchronous in phase with a system clock, the non-selection mode causing the device to return to the controller a second data signal while activating a second data strobe signal that is asynchronous in phase with the system clock signal, and edge specifying information including a selected one of first and second states, the first state causing the device to activate the first data strobe signal at a first timing. | 2012-03-22 |
20120069688 | IMPLEMENTING SINGLE BIT REDUNDANCY FOR DYNAMIC SRAM CIRCUIT WITH ANY BIT DECODE - A method and a dynamic Static Random Access Memory (SRAM) circuit for implementing single bit redundancy with any bit decode, and a design structure on which the subject circuit resides are provided. The SRAM circuit includes a plurality of bitline columns and a pair of redundancy columns respectively coupled to a respective merged bit column select and redundancy steering multiplexer. Each merged bit column select and redundancy steering multiplexer receives a respective select signal input. A select signal generation circuit receives a redundancy steering signal and a respective one-hot bit select signal, generating the respective select signal input. | 2012-03-22 |
20120069689 | BUILT-IN SELF REPAIR FOR MEMORY - A method for repairing a memory includes running a built-in self-test of the memory to find faulty bits. A first repair result using a redundant row block is calculated. A second repair result using a redundant column block is calculated. The first repair result and the second repair result are compared. A repair method using either the redundant row block or the redundant column block is selected. The memory is repaired by replacing a row block having at least one faulty bit with the redundant row block or replacing a column block having at least one faulty bit with the redundant column block. | 2012-03-22 |
20120069690 | SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD - A semiconductor integrated circuit for selecting one from a plurality of external storage devices and loading an execution program that includes a fuse part having a plurality of internal fuse circuits, and a processing unit that loads the execution program from the external storage device selected according to a value indicated by the internal fuse circuit. | 2012-03-22 |
20120069691 | BLOCK REPAIR SCHEME - Systems, memory arrays and methods (e.g., methods of block repair) are provided. One such system includes a memory array including a memory bank including a plurality of sections, wherein each of the plurality of sections includes at least one redundant row. Further embodiments provide for mapping non-redundant rows associated with a section associated with a block failure to distributed redundant rows. | 2012-03-22 |
20120069692 | SEMICONDUCTOR DEVICE - A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing. | 2012-03-22 |
20120069693 | DYNAMIC RANDOM ACCESS MEMORY AND BOOSTED VOLTAGE PRODUCER THEREFOR - A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump circuits that are selectively activated by a pump control circuit based on a refresh time for refreshing data in the DRAM cells in the sleep mode. | 2012-03-22 |
20120069694 | STIRRING ARRANGEMENT - The invention relates to a stirring arrangement having a rotating stirring body ( | 2012-03-22 |
20120069695 | Capstir - A Capstir is any handheld device or instrument that is manufactured, sold, promoted, distributed, or used for the primary purpose of mixing, or stirring, laundry detergent/softener, with the water in the washing machine. The primary goal of a Capstir is to better dissolve and distribute the laundry detergent/softener in the water in the washing machine. It is believed that a Capstir is the first, and only, handheld device that claims the preceding to be its primary purpose and primary goal. Additionally, the surface area of a Capstir may also serve as a place for companies to advertise/promote other products and services they offer. | 2012-03-22 |
20120069696 | PAINT STIRRER WITH PAINT BRUSH HOLDER - Paint stirrer with an elongate narrow main shape, which under the action of gravity can stably stand in a diagonal position in a paint can without the need to Mount it to the edge of the can, characterised in that the brush can be stably supported relative to the paint stirrer in such a manner that the brush hairs extend substantially parallel to the paint stirrer and downward above or in the opening of the can. This offers the advantage that paint rests flowing out the brush, stay inside the can. | 2012-03-22 |
20120069697 | DYNAMIC MIXER - A dynamic mixer comprising a rotor, which is coupled to a drive shaft and which is rotationally mounted in a mixing chamber provided inside a rotor housing; at least one first and one second constituent can be fed to said mixing chamber; the drive shaft comprises at least one wavy channel via which the second constituent can be introduced into the mixing chamber; the mixing device is simplified since the second constituent is fed through the channel provided in the drive shaft; no separate connection for supplying the second constituent is provided on the rotor housing whereby enabling the rotor housing to have a simple design and be economically produced; the assembly and disassembly of parts are also simplified, particularly of the rotor and rotor housing, which can be disposed of or cleaned after the mixer has been used, allowing the dynamic mixer to be repeatedly reused. | 2012-03-22 |
20120069698 | MIXERS FOR IMMISCIBLE FLUIDS - A mixer for mixing immiscible fluids includes a mixer housing defining a flow passage therethrough from a first fluid inlet to an outlet thereof. An upstream portion of the flow passage defines a main longitudinal axis. A second fluid inlet is provided downstream of the first fluid inlet in fluid communication with the upstream portion of the flow passage. The second fluid inlet is offset with respect to the main longitudinal axis of the flow passage to introduce fluid along a path that is offset with respect to the main longitudinal axis for inducing swirl on fluids introduced at the first and second fluid inlets. In certain embodiments, a mixer section is included having a flow constriction defined in a downstream portion of the flow passage with a flow area smaller than that of the upstream portion of the flow passage for enhancing turbulent mixing of fluids therein. | 2012-03-22 |
20120069699 | HORIZONTAL DOUGH MIXER ASSEMBLY WITH MULTI-REDUCTION GEAR ARRANGEMENT FOR BOWL TILT - A mixing bowl-tilt system for a horizontal mixer includes a multi-stage gear reduction unit having an input and an output, wherein the input is connected to be rotated by a motor and the output is operatively connected to rotate a mixing bowl. Rotation of the input results in rotation of the mixing bowl. The multi-stage gear reduction unit is non-back driving and self locking and includes a first stage reduction and a second stage reduction. | 2012-03-22 |
20120069700 | Gearbox with Breather System - A gearbox is provided having an integrated breather system. The output shaft of the gearbox has integrated therein a breather bore with a top port in the top end of the output shaft and a bottom end in the side of the output shaft. The top end is in communication with the atmosphere while the bottom end is in communication with the inner oil reservoir of the gearbox. By incorporating the breather directly into the output shaft, air locking is reduced or even prevented. Further, the distance between the maximum and minimum oil fill levels is increased thereby allowing for a reduction in accidental over or under filling of the gearbox. In addition, accidental spillage of oil into the environment is reduced as the top breather port exists on top of the gearbox and may optionally include a breather line extending further upward. The reduction in air locking allows for increased accuracy in oil filling as well as reduced maintenance on the gearbox. | 2012-03-22 |
20120069701 | ULTRASONIC TRANSDUCER AND ULTRASONIC DIAGNOSTIC APPARATUS PROVIDED WITH SAME - For disposing projections of insulating film protruding into a hollow part in CMUT in order to suppress injection of electrical charge into the insulating film due to contact of a lower surface of a membrane with a lower surface of the hollow part, there are provided a structure of disposed projections preferred for suppressing increase in driving voltage for CMUT and decrease in receiving sensitivity, and an ultrasonic diagnostic apparatus using the same. The ultrasonic transducer of the present invention comprises a first electrode, a lower insulating film formed on the first electrode, an upper insulating film provided so as to form a hollow part above the lower insulating film, and a second electrode formed on the upper insulating film, and is characterized in that the lower insulating film or the upper insulating film has projections on the side of the hollow part, and the first electrode or the second electrode has openings formed at positions corresponding to the positions at which the projections are formed. | 2012-03-22 |
20120069702 | MARINE SEISMIC SURVEY SYSTEMS AND METHODS USING AUTONOMOUSLY OR REMOTELY OPERATED VEHICLES - Systems and methods for carrying out seismic surveys and/or conducting permanent reservoir monitoring with autonomous or remote-controlled water vehicles, including surface and submersible vehicles, are described. Additional methods carried out by autonomous or remote-controlled water vehicles and associated with seismic surveys further described. | 2012-03-22 |
20120069703 | SEISMIC STREAMER - There is provided a solid seismic streamer cable for use in seismic surveying in marine environments. The streamer is characterised by a buffer layer | 2012-03-22 |
20120069704 | METHODS AND APPARATUS FOR DETERMINING SEISMIC STREAMER ARRAY GEOMETRY AND SEISMIC SENSOR RESPONSE - A method for marine seismic surveying includes determining at least an initial depth of a plurality of spaced apart seismic sensors in a body of water. The sensors each include a substantially collocated pressure responsive sensor and motion responsive sensor. A ghost time delay is determined for each sensor based on the at least an initial depth. Seismic signals detected by each motion responsive sensor and each pressure responsive sensor are cross ghosted. The at least initial depth is adjusted, and the determining ghost time delay and cross ghosted seismic signals are repeated until a difference between the cross ghosted motion responsive signal and the cross ghosted pressure responsive signal falls below a selected threshold. Other embodiments, aspects and features are also disclosed. | 2012-03-22 |
20120069705 | EMAT Acoustic Signal Measurement Using Modulated Gaussian Wavelet and Hilbert Demodulation - Casing signals generated by an EMAT in a borehole are processed using at least two orthogonal band-limited filters. The band-limited filters may include Gaussian or Cauchy Wavelet filters. By using the Hilbert transform, an envelope of the filtered signals is determined and amplitudes and arrival times of individual arrivals are estimated. These can be used to estimate casing and cement properties. | 2012-03-22 |
20120069706 | Land Seismic Cable and Method - A seismic cable for use in land applications is described. The cable includes seismic sensors for measuring seismic signals reflected from subterranean or subsea formations. The cable may be deployed in trenches dug in the survey region to provide adequate sensor coupling to ground. Sensor units may be inline with the cable and may further be disposed in slim casings, thus facilitating handling and deployment. | 2012-03-22 |
20120069707 | METHOD FOR MONITORING A SUBSOIL ZONE, PARTICULARLY DURING STIMULATED FRACTURING OPERATIONS - The invention relates to a method for monitoring a subsoil zone, wherein a plurality of receivers are arranged on a surface of the soil or near said surface, straight above a geological zone to be monitored, comprising the following steps: generating a set of reference seismic data recording seismic data by means of said receivers; correlating the seismic data recorded ( | 2012-03-22 |
20120069708 | APPARATUS AND METHOD FOR GENERATING BROAD BANDWIDTH ACOUSTIC ENERGY - An acoustic transmitter includes: an acoustic diaphragm configured to transmit acoustic waves into a medium; a piezoelectric actuator assembly configured to deform in an axial direction in response to an applied electrical signal; and a highly incompressible elastic material disposed between the piezoelectric actuator and the acoustic diaphragm and configured to transmit pressure waves to the acoustic diaphragm in response to motion of the piezoelectric actuator. | 2012-03-22 |
20120069709 | METHOD AND SYSTEM FOR REAL-TIME AUTOMATED CHANGE DETECTION AND CLASSIFICATION FOR IMAGES - A computer based system and method for real-time display of co-registered historical and current side scan sonar imagery during a side scan sonar survey. Embodiments also include modules for detection of clutter in the current imagery, identification of features, extraction of snippets, filtering based on predetermined size and shape parameters, and determination if a current feature is the same as a previously identified contact from historical imagery. | 2012-03-22 |
20120069710 | Method and System for Real-time Automated Change Detection and Classification for Images - A computer based system and method for real-time display of co-registered historical and current side scan sonar imagery during a side scan sonar survey. Embodiments also include modules for detection of clutter in the current imagery, identification of features, extraction of snippets, filtering based on predetermined size and shape parameters, and determination if a current feature is the same as a previously identified contact from historical imagery. | 2012-03-22 |
20120069711 | TERMINAL DEVICE, MOBILE TERMINAL, AND NAVIGATION PROGRAM - A terminal device includes an orientation calculating unit that calculates the orientation of a device with respect to the target. Furthermore, the terminal device also includes a degree-of-processing determining unit that determines the degree of processing related to an attribute of a sound that indicates the target in accordance with the orientation calculated by the orientation calculating unit. Furthermore, the terminal device also includes an output control unit that controls an output of a sound in accordance with the degree of processing determined by the degree-of-processing determining unit. | 2012-03-22 |