12th week of 2012 patent applcation highlights part 42 |
Patent application number | Title | Published |
20120070913 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - A method of manufacturing a semiconductor device includes: carrying a substrate having an oxide film and a nitride film stacked thereon into a processing chamber; supporting and heating the substrate using a substrate support member provided in the processing chamber; adjusting flow rates of hydrogen-containing gas and nitrogen-containing gas in process gas using a gas flow rate controller to set a percentage R of the number of hydrogen atoms with respect to the total number of hydrogen atoms and nitrogen atoms contained in the process gas to be 0%2012-03-22 | |
20120070914 | TEMPERATURE CONTROL MODULE USING GAS PRESSURE TO CONTROL THERMAL CONDUCTANCE BETWEEN LIQUID COOLANT AND COMPONENT BODY - A temperature control module for a semiconductor processing chamber comprises a thermally conductive component body, one or more channels in the component body and one or more tubes concentric therewith, such that gas filled spaces surround the tubes. By flowing a heat transfer liquid in the tubes and adjusting the gas pressure in the spaces, localized temperature of the component body can be precisely controlled. One or more heating elements can be arranged in each zone and a heat transfer liquid can be passed through the tubes to effect heating or cooling of each zone by activating the heating elements and/or varying pressure of the gas in the spaces. | 2012-03-22 |
20120070915 | METHOD FOR COPPER HILLOCK REDUCTION - A method of forming interconnects in integrated circuits includes providing a semiconductor substrate and forming a copper interconnect structure that is formed overlying a barrier layer within a thickness of an interlayer dielectric layer. The copper interconnect structure has a first stress characteristic. The method further loads the semiconductor substrate including the copper interconnect structure into a deposition chamber that contains an inert environment. The semiconductor substrate including the copper interconnect structure is annealed in the inert environment for a period of time to cause the copper interconnect structure to have a second stress characteristic. The semiconductor substrate is maintained in the deposition chamber while an etch stop layer is deposited thereon. The method further deposits an inner-metal dielectric layer overlying the etch stop layer, wherein the annealing reduces copper hillock defects resulting from at least the first stress characteristic. | 2012-03-22 |
20120070916 | MOVABLE INJECTORS IN ROTATING DISC GAS REACTORS - A system and method for uniform deposition of material layers on wafers in a rotating disk chemical vapor deposition reaction system is provided, wherein one or more substrates are rotated on a carrier about an axis while maintaining surfaces of the one or more substrates substantially perpendicular to the axis of rotation and facing in an upstream direction along the axis of rotation. During rotating a first gas is discharged in the downstream direction towards the one or more substrates from a first set of gas inlets. A second gas is discharged in the downstream direction towards the one or more substrates from at least one movable gas injector, and the at least one movable gas inlet is moved with a component of motion in a radial direction towards or away from the axis of rotation. | 2012-03-22 |
20120070917 | APPARATUS AND METHOD FOR MOUNTING SEMICONDUCTOR LIGHT EMITTING ELEMENT - When bump electrodes | 2012-03-22 |
20120070918 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device may include, but is not limited to the following processes. First and second grooves are formed in a semiconductor substrate having a first surface. The first and second grooves have substantially the same vertical dimension. The first surface has first and second regions surrounded by the first and second grooves, respectively. An actual resistance value of the semiconductor substrate between a first point on the first region and a second point on the second region is measured. The vertical dimension of the first and second grooves is calculated with reference to the actual resistance value. | 2012-03-22 |
20120070919 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THEREOF, AND METHOD OF MANUFACTURING BASE MATERIAL - It is an object of the invention to provide a lightweight semiconductor device having a highly reliable sealing structure which can prevent ingress of impurities such as moisture that deteriorate element characteristics, and a method of manufacturing thereof. A protective film having superior gas barrier properties (which is a protective film that is likely to damage an element if the protective film is formed on the element directly) is previously formed on a heat-resistant substrate other than a substrate with the element formed thereon. The protective film is peeled off from the heat-resistant substrate, and transferred over the substrate with the element formed thereon so as to seal the element. | 2012-03-22 |
20120070920 | Method for mounting luminescent device - A method for mounting a luminescent device having a mount layer on a substrate, comprising the steps of coating a metallic nano-particle paste on the substrate, disposing the mount layer of the luminescent device on the metallic nano-particle paste, and heating the mount layer and the metallic nano-particle paste to form an alloy, thereby bonding the luminescent device and the substrate. | 2012-03-22 |
20120070921 | METHOD OF MAKING A LIGHT EMITTING DEVICE HAVING A MOLDED ENCAPSULANT - Disclosed herein is a method of making a light emitting device having an LED die and a molded encapsulant made by polymerizing at least two polymerizable compositions. The method includes: (a) providing an LED package having an LED die disposed in a reflecting cup, the reflecting cup filled with a first polymerizable composition such that the LED die is encapsulated; (b) providing a mold having a cavity filled with a second polymerizable composition; (c) contacting the first and second polymerizable compositions; (d) polymerizing the first and second polymerizable compositions to form first and second polymerized compositions, respectively, wherein the first and second polymerized compositions are bonded together; and (e) optionally separating the mold from the second polymerized composition. Light emitting devices prepared according to the method are also described. | 2012-03-22 |
20120070922 | METHOD FOR FORMING LIGHT EMITTING DEVICE - The invention provides a method for forming a light emitting device. A first substrate is provided. A plurality of patterned masks is formed on the first substrate, or on a semiconductor epitaxial layer grown on the first substrate, or the first substrate is etched to form a plurality of trenches, followed by performing an epitaxial lateral overgrowth process to grow an epitaxy layer over the first substrate. A light emitting structure is formed on the epitaxy layer. A first electrode layer is formed on the light emitting structure. The light emitting structure is wafer bonded to a second substrate. A photoelectrochemical etching process is performed to lift off the first substrate from the epitaxy layer. | 2012-03-22 |
20120070923 | FABRICATION METHOD OF ORGANIC ELECTROLUMINESCENCE DISPLAY HAVING A GETTER LAYER - Provided herein is a method of manufacturing an organic electroluminescence display device, including the steps of: forming a getter layer on a unit sealing substrate using a dry method; providing a device substrate including a device array formed thereon, the device array including a plurality of unit organic electroluminescence devices; attaching the device substrate to the unit sealing substrate such that the getter layer faces the device array, thus forming a module; and imparting fluidity to the getter layer such that the getter layer covers upper and lateral sides of the device array. The method is advantageous in that fluidity is imparted to the getter layer, so that the upper and lateral sides of the device array is covered by the getter layer, thereby greatly improving the moisture resistance of the organic electroluminescence device. | 2012-03-22 |
20120070924 | METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT-EMITTING DEVICE - Disclosed is a method for manufacturing a semiconductor light-emitting device, which carries out a wet-etching process after a dry-etching process so as to form protrusions in a surface of a substrate for growing a nitride semiconductor material thereon. The method comprises coating a substrate with photoresist; forming a mask pattern on the substrate by selectively removing the photoresist; forming protrusions on the substrate by dry-etching the substrate with the mask pattern through the use of etching gas; wet-etching the dry-etched substrate through the use of etching solution; forming a first semiconductor layer on the substrate including the protrusions; forming an active layer on the first semiconductor layer; forming a second semiconductor layer on the active layer; etching predetermined portions of the active layer and second semiconductor layer until the first semiconductor layer is exposed; and forming a first electrode on a predetermined portion of the first semiconductor layer, wherein the active layer and second semiconductor layer are not formed on the predetermined portion of the first semiconductor layer, and forming a second electrode on the second semiconductor layer. | 2012-03-22 |
20120070925 | Method for Producing a Thin-Film Semiconductor Chip - Manufacturing methods for a thin-film semiconductor chip based on a III/V-III/V semiconductor compound material and capable of generating electromagnetic radiation. In one method, a succession of active layers is applied to a growth substrate. Applied to the reverse side of the active layers is a dielectric layer. Laser energy is introduced into a defined volumetric section of the dielectric layer to form an opening. Subsequently, a metallic layer is applied to form a succession of reflective layers, to fill the opening with metallic material and to create a reverse-side electrically conductive contact point to the reverse side of the succession of active layers. Pursuant to another method, a succession of reflective layers is applied to the active layers and laser energy is applied to a volumetric section of the reflective layers, to create a reverse-side electrically conductive contact point. | 2012-03-22 |
20120070926 | METHOD FOR PRODUCING A LIGHT-EMITTING DIODE - A method for producing a light-emitting diode includes providing a light-emitting diode chip including a semiconductor body, and applying a luminescence conversion material to an outer area of the semiconductor body by thermal spraying such that at least part of electromagnetic radiation generated during operation of the light-emitting diode impinges on the luminescence conversion material, or providing a radiation-transmissive carrier, applying a luminescence conversion material to an outer area of the carrier by thermal spraying, and arranging the carrier at a radiation exit area of the light-emitting diode chip such that at least part of electromagnetic radiation generated during operation of the light-emitting diode impinges on the luminescence conversion material. | 2012-03-22 |
20120070927 | METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR COMPONENT - A method for producing an optoelectronic semiconductor component includes providing a first wafer having a patterned surface, wherein the patterned surface is formed at least in places by elevations having first and second heights, wherein the first height is greater than the second height; providing a second wafer; applying a photoresist to outer areas of the second wafer; patterning a surface of the photoresist facing away from the second wafer by impressing the patterned surface of the first wafer into the photoresist, wherein the elevations are impressed as trenches having a first and second depth into the photoresist; applying a patterning method to the patterned surface of the photoresist, wherein the structure applied on the photoresist is transferred at least in places to the outer area of the second wafer. | 2012-03-22 |
20120070928 | THIN FILM DEPOSITION APPARATUS AND METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY DEVICE BY USING THE SAME - A thin film deposition apparatus for forming a thin film on a substrate includes: a deposition source for discharging a deposition material; a deposition source nozzle unit having a plurality of nozzles arranged in a first direction; a patterning slit sheet located opposite to the deposition source and having a plurality of patterning slits arranged in the first direction; and a barrier plate assembly including a plurality of barrier plates that are arranged between the deposition source nozzle unit and the patterning slit sheet in the first direction to partition a space between the deposition source nozzle unit and the patterning slit sheet into a plurality of sub-deposition spaces. The thin film deposition apparatus and the substrate are movable relative to each other in a movement direction that has an angle greater than about 90° and less than about 180° with respect to the first direction. | 2012-03-22 |
20120070929 | METHOD FOR FABRICATING WAFER PRODUCT AND METHOD FOR FABRICATING GALLIUM NITRIDE BASED SEMICONDUCTOR OPTICAL DEVICE - Provided is a method for fabricating a wafer product including an active layer grown on a gallium oxide substrate and allowing an improvement in emission intensity. In step S | 2012-03-22 |
20120070930 | METHOD AND APPARATUS TO FABRICATE POLYMER ARRAYS ON PATTERNED WAFERS USING ELECTROCHEMICAL SYNTHESIS - A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed. | 2012-03-22 |
20120070931 | METHODS FOR REDUCED STRESS ANCHORS - Methods of anchoring components of a Micro-Electro-Mechanical Systems (MEMS) device to a substrate. An exemplary embodiment has a trace anchor bonded to a substrate, a device anchor bonded to the substrate, and an anchor flexure configured to flexibly couple the trace anchor and the device anchor to substantially prevent transmission of a stress induced in the trace anchor from being transmitted to the device anchor. | 2012-03-22 |
20120070932 | LASER PATTERNING APPARATUS AND LASER PATTERNING METHOD - Aspects of the invention are directed to laser patterning apparatus capable of performing laser patterning on a thin film formed on a flexible substrate with a good yield and a laser patterning method thereof. The thin film formed on the flexible substrate can be patterned by laser using a laser patterning apparatus that can include a processing stage that has a reference processing surface on which the flexible substrate having the thin film formed thereon is disposed, a wrinkle removing device that is configured as a mechanism for stretching an outer periphery of a processing region of the flexible substrate so that tension is applied outward in the width direction and forward and backward in the transporting direction, and a laser scanner that scans a predetermined line of the thin film formed on the flexible substrate while emitting a laser beam thereto. | 2012-03-22 |
20120070933 | METHOD FOR MANUFACTURING DYE-SENSITIZED SOLAR CELL - The present invention provides an intermediate structure for use in manufacturing a dye-sensitized solar cell (DSSC) and a method for manufacturing a DSSC with the intermediate structure. The intermediate structure comprises a first electrode coated with a nano-particle oxide and a second electrode laminated with the first electrode by a layer formed of a sealant. The sealant layer has openings in predetermined positions such that at least a portion of the internal space formed by the first electrode, the second electrode, and the sealant layer can communicate with the outside. With the intermediate structure, a superior quality of a DSSC can be manufactured in a simpler and more cost-effective way. | 2012-03-22 |
20120070934 | Method to build transparent polarizing solar cell - The present disclosure provides a means to build a solar cell that is transparent to and polarizes visible light, and to transfer the energy thus generated to electrical power wires. | 2012-03-22 |
20120070935 | TANDEM THIN-FILM SILICON SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME - A tandem thin-film silicon solar cell comprises a transparent substrate, a first unit cell positioned on the transparent substrate, the first unit cell comprising a p-type window layer, an i-type absorber layer and an n-type layer, an intermediate reflection layer positioned on the first unit cell, the intermediate reflection layer including a hydrogenated n-type microcrystalline silicon oxide of which the oxygen concentration is profiled to be gradually increased and a second unit cell positioned on the intermediate reflection layer, the second unit cell comprising a p-type window layer, an i-type absorber layer and an n-type layer. | 2012-03-22 |
20120070936 | ANNEALING THIN FILMS - In an annealing process, a Kesterite film is provided on a substrate. The Kesterite film and the substrate are generally planar, have an interface, and have a substrate exterior side and a Kesterite exterior side. An additional step includes locating the cap adjacent the Kesterite exterior side. A further step includes applying sufficient heat to the Kesterite film and the substrate for a sufficient time to anneal the Kesterite film. The annealing is carried out with the cap adjacent the Kesterite exterior side. In another aspect, the film is not limited to Kesterite, and the cap is employed without any precursor layer thereon. Solar cell manufacturing techniques employing the annealing techniques are also disclosed. | 2012-03-22 |
20120070937 | Method for Producing Compound Semiconductor, Method for Manufacturing Photoelectric Conversion Device, and Solution for Forming Semiconductor - A method for producing a compound semiconductor layer comprises dissolving a metal feedstock comprising at least one of a group I-B element and a group III-B element, in a metal state, in a mixed solvent comprising an organic compound containing a chalcogen element and a Lewis base organic compound to produce a solution for forming a semiconductor; forming a coat using the solution for forming a semiconductor; and heat-treating the coat. | 2012-03-22 |
20120070938 | Method of Fabricating Silicon Nanowire Solar Cell Device Having Upgraded Metallurgical Grade Silicon Substrate - A simplified method for fabricating a solar cell device is provided. The solar cell device has silicon nanowires (SiNW) grown on an upgraded metallurgical grade (UMG) silicon (Si) substrate. Processes of textured surface process and anti-reflection thin film process can be left out for further saving costs on equipment and manufacture investment. Thus, a low-cost Si-based solar cell device can be easily fabricated for wide application. | 2012-03-22 |
20120070939 | STACKED DIE ASSEMBLIES INCLUDING TSV DIE - A method of through substrate via (TSV) die assembly includes positioning a plurality of TSV die with their topside facing down onto a curable bonding adhesive layer on a carrier. The plurality of TSV die include contactable TSVs that include or are coupled to bondable bottomside features protruding from its bottomside. The curable bonding adhesive layer is cured after the positioning. A plurality of second IC die each having a plurality of second bonding features are bonded onto the plurality of TSV die to form a plurality of stacked die assemblies on the carrier. Debonding after the bonding separates the carrier from the plurality of stacked die assemblies. The plurality of stacked die assemblies are then singulated to form a plurality of singulated stacked die assemblies. | 2012-03-22 |
20120070940 | FIXTURE TO CONSTRAIN LAMINATE AND METHOD OF ASSEMBLY - A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions. | 2012-03-22 |
20120070941 | MODULE WITH SILICON-BASED LAYER - The invention concerns a module comprising a carrier element, a semiconductor device mounted on said carrier element and a silicon-based insulating layer. The silicon-based insulating layer is arranged on the side of the carrier element opposite to the semiconductor device. The invention further concerns a module comprising a semiconductor device, a mold compound at least partly covering the semiconductor device and a silicon-based passivation layer. The silicon-based passivation layer covers at least partly the periphery of the mold compound. | 2012-03-22 |
20120070942 | PROCESS FOR FORMING THIN FILM ENCAPSULATION LAYERS - A thin film environmental barrier encapsulation process includes providing an electronic device on a substrate, a first reactant gaseous material, a second reactant gaseous material, an inert gaseous material; and a delivery head through which the reactant gaseous materials and the inert gaseous material are simultaneously directed toward the electronic device and the substrate. One or more of the reactant gaseous materials and the inert gaseous material flows through the delivery head. The flow of the one or more of the reactant gaseous materials and the inert gaseous material generates a pressure to create a gas fluid bearing that maintains a substantially uniform distance between the delivery head and the substrate. Relative motion between the delivery head and the substrate causes the second reactant gaseous material to react with at least a portion of the electronic device and the substrate that has been treated with the first reactant gaseous material. | 2012-03-22 |
20120070943 | CHIP PACKAGING METHOD AND STRUCTURE THEREOF - The present invention relates to a chip packaging method and structure, in which bonding pads provided on the chip are connected by a plurality of metal wires via bonding, each of the metal wires is bending in the middle part to be higher than a predetermined height, and its ends are respectively electrically connected with two of the bonding pads. A molding layer is packaged on the chip and the molding layer is higher than the predetermined height. The molding layer is sliced at the predetermined height. Two upper breakpoints of each metal wire are exposed and a substrate is attached onto the molding layer. A plurality of circuit contacts of the substrate are respectively electrically coupled with the upper breakpoints. Whereby, the invention is capable of reducing the length of the metal wires in order to improve transmission speed, but also to reduce the volume of the packaging structure. | 2012-03-22 |
20120070944 | Methods of Manufacturing Three Dimensional Semiconductor Devices - Provided are methods of manufacturing a three dimensional semiconductor device. The method includes providing a substrate including a cell array region and a peripheral circuit region, forming a peripheral structure on the peripheral circuit region, forming a cell structure being thicker than the peripheral structure in the cell array region, forming an interlayer dielectric to cover the peripheral structure and the cell structure, forming a polishing stop layer on the interlayer dielectric, and planarizing the interlayer dielectric using the polishing stop layer as a planarization stop. | 2012-03-22 |
20120070945 | ORGANIC SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF SAME, ORGANIC TRANSISTOR ARRAY, AND DISPLAY - This disclosure provides an organic semiconductor device including: a substrate; a source electrode and a drain electrode which are formed on the substrate; an insulation partitioned part which is formed on the source electrode and the drain electrode, formed such that an opening part of the insulation partitioned part is disposed above a channel region formed by the source electrode and the drain electrode; an organic semiconductor layer which is formed in the opening part of the insulation partitioned part and on the source electrode and the drain electrode; a gate insulation layer which is formed on the organic semiconductor layer and made of an insulation resin material; and a gate electrode formed on the gate insulation layer, and the insulation partitioned part has a height ranging from 0.1 μm to 1.5 μm. | 2012-03-22 |
20120070946 | METHOD FOR FABRICATING A THIN FILM TRANSISTOR SUBSTRATE - A method for fabricating a thin film transistor substrate includes: (a) forming a gate electrode on a substrate using a first photoresist layer; (b) forming an insulating film, an active semiconductor layer, a doped semiconductor layer, an ohmic contact metal film, a passivation film, and a second photoresist layer on the substrate to cover the gate electrode; (c) disposing a multi-tone mask over the second photoresist layer, followed by performing a lithography process to form the second photoresist layer into a patterned photoresist, which has different thicknesses at a location corresponding in position to the gate electrode and on two opposite sides of the location; and (d) performing etching using the patterned photoresist. | 2012-03-22 |
20120070947 | INDUCING STRESS IN FIN-FET DEVICE - A method of forming a fin-shaped field effect transistor (fin-FET) is disclosed. In one embodiment, the method comprises: partially amorphizing a fin overlying a substrate; forming a stress layer over a portion of the partially amorphized fin; annealing to impart stress in the partially amorphized fin to form a stressed fin; removing the stress layer from over the portion of stressed fin; and forming a gate over the stressed fin after the removing of the stress layer. | 2012-03-22 |
20120070948 | ADJUSTING METHOD OF CHANNEL STRESS - An adjusting method of channel stress includes the following steps. A substrate is provided. A metal-oxide-semiconductor field-effect transistor is formed on the substrate. The MOSFET includes a source/drain region, a channel, a gate, a gate dielectric layer and a spacer. A dielectric layer is formed on the substrate and covers the metal-oxide-semiconductor field-effect transistor. A flattening process is applied onto the dielectric layer. The remaining dielectric layer is removed to expose the source/drain region. A non-conformal high stress dielectric layer is formed on the substrate having the exposed source/drain region. | 2012-03-22 |
20120070949 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes providing a substrate having a memory block and a logic block defined therein, forming a dummy gate pattern on the memory block; forming a first region of a first conductivity type at one side of the dummy gate pattern and a second region of a second conductivity type at the other side of the dummy gate pattern, and forming a nonvolatile memory device electrically connected to the first region. | 2012-03-22 |
20120070950 | Method of Manufacturing a Semiconductor Device - A semiconductor device includes a substrate having a first area and a second area, a first active structure disposed in the first area, a second active structure disposed in the second area, a first transistor disposed in the first area and a second transistor disposed in the second area. The second active structure may have a height substantially the same as a height of the first active structure. The first transistor includes a first gate structure enclosing an upper portion of the first active structure, a first impurity region formed at a lower portion of the first active structure, and a second impurity region formed at the upper portion of the first active structure. The second transistor includes a second gate structure formed on the second active structure and third impurity regions formed at an upper portion of the second active structure. | 2012-03-22 |
20120070951 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR - There is provided a semiconductor device including bit lines ( | 2012-03-22 |
20120070952 | REMOVING METHOD OF A HARD MASK - A removing method of a hard mask includes the following steps. A substrate is provided. At least two MOSFETs are formed on the substrate. An isolating structure is formed in the substrate and located between the at least two MOSFETs. Each of the MOSEFTs includes a gate insulating layer, a gate, a spacer and a hard mask on the gate. A protecting structure is formed on the isolating structure and the hard mask is exposed from the protecting structure. The exposed hard mask is removed to expose the gate. | 2012-03-22 |
20120070953 | METHOD OF FORMING INTEGRATED CIRCUITS - A method of forming an integrated circuit includes forming a gate structure over a substrate. A plasma doping (PLAD) process is performed to at least a portion of the substrate that is adjacent to the gate structure. The doped portion of the substrate is annealed in an ambient with an oxygen-containing chemical. | 2012-03-22 |
20120070954 | METHODS OF FORMING INTEGRATED CIRCUITS - A method of forming an integrated circuit includes forming a gate structure over a substrate. At least one silicon-containing layer is formed in source/drain (S/D) regions adjacent to sidewalls of the gate structure. An N-type doped silicon-containing layer is formed over the at least one silicon-containing layer. The N-type doped silicon-containing layer has an N-type dopant concentration higher than that of the at least one silicon-containing layer. The N-type doped silicon-containing layer is annealed so as to drive N-type dopants of the N-type doped silicon-containing layer to the S/D regions. | 2012-03-22 |
20120070955 | Methods of Forming Conductive Contacts to Source/Drain Regions and Methods of Forming Local Interconnects - The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated. | 2012-03-22 |
20120070956 | Method for Manufacturing Memory Element - A conductive paste including conductive particles each of which has a size of greater than or equal to 0.1 μm and less than or equal to 10 μm, a resin, and a solvent is placed over a first conductor and the solvent is vaporized. In this manner, a second conductor having the conductive particles and a memory layer including the resin between the first conductor and the conductive particles is formed. | 2012-03-22 |
20120070957 | AIR GAP FORMATION - A method of forming air gaps between adjacent raised features on a substrate includes forming a carbon-containing material in a bottom region between the adjacent raised features using a flowable deposition process. The method also includes forming a silicon-containing film over the carbon-containing material using a flowable deposition process, where the silicon-containing film fills an upper region between the adjacent raised features and extends over the adjacent raised features. The method also includes curing the carbon-containing material and the silicon-containing material at an elevated temperature for a period of time to form the air gaps between the adjacent raised features. | 2012-03-22 |
20120070958 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device of an embodiment, at room temperature, a first substrate including a semiconductor laminate body is adhered to a second substrate with a smaller thermal expansion coefficient than that of the first substrate. Then, the first substrate and the second substrate are heated with the first substrate heated at a temperature higher than that of the second substrate. Thus the first substrate and the second substrate are bonded together. The first substrate is either a sapphire substrate including a nitride-based semiconductor layer, or a GaAs substrate including a phosphorus-based semiconductor layer. The second substrate is a silicon substrate, a GaAs substrate, a Ge substrate, or a metal substrate. | 2012-03-22 |
20120070959 | MICROELECTRONIC DEVICE WAFERS AND METHODS OF MANUFACTURING - Methods of forming microelectronic device wafers include fabricating a plurality of semiconductor dies at an active side of a semiconductor wafer, depositing a mask on the semiconductor wafer, removing a central portion of the mask and the semiconductor wafer, and etching. The semiconductor wafer has an outer perimeter edge and a backside that is spaced from the active side by a first thickness. The mask is deposited on the backside of the semiconductor wafer and has a face that is spaced from the backside by a mask thickness. The thinned portion has a thinned surface that is spaced from the active side by a second thickness that is less than the first thickness, and the thinned surface is etched. | 2012-03-22 |
20120070960 | DICING DIE BOND FILM, METHOD OF MANUFACTURING DICING DIE BOND FILM, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The present invention aims to provide a dicing die bond film that is capable of suppressing peeling of the dicing die bond film from a dicing ring. The present invention provides a dicing die bond film in which the pressure-sensitive adhesive layer contains a polymer formed by performing an addition reaction on a specific acrylic polymer with a specific isocyanate compound, and a specific crosslinking agent, and the specific peeling adhesive power of a portion of the pressure-sensitive adhesive layer where the dicing ring is pasted is 1.0 N/20 mm tape width or more and 10.0 N/20 mm tape width or less, the tensile storage modulus at 23° C. of the portion where the dicing ring is pasted is 0.05 MPa or more and less than 0.4 MPa, and the die bond film is pasted to the pressure-sensitive adhesive layer after irradiation with an ultraviolet ray. | 2012-03-22 |
20120070961 | LOW TEMPERATURE ETCHANT FOR TREATMENT OF SILICON-CONTAINING SURFACES - Embodiments provide methods for etching and depositing silicon materials on a substrate. In one example, the method includes heating a substrate containing a silicon-containing material to a temperature of about 800° C. or less and removing a portion of the silicon-containing material and a contaminant to reveal an exposed surface of the silicon-containing material during an etching process and depositing a silicon-containing layer on the exposed surface of the silicon-containing material during a deposition process. The method further provides conducting the etching and deposition processes in the same chamber and utilizing chlorine gas and a silicon source gas during the etching and deposition processes. In some examples, the silicon-containing material is removed at a rate within a range from about 2 Å per minute to about 20 Å per minute during the etching process. | 2012-03-22 |
20120070962 | Freestanding III-Nitride Single-Crystal Substrate and Method of Manufacturing Semiconductor Device Utilizing the Substrate - Freestanding III-nitride single-crystal substrates whose average dislocation density is not greater than 5×10 | 2012-03-22 |
20120070963 | PLASMA DEPOSITION - An apparatus for depositing a group III metal nitride film on a substrate, the apparatus comprising a plasma generator to generate a nitrogen plasma from a nitrogen source, a reaction chamber in which to react a reagent comprising a group III metal with a reactive nitrogen species derived from the nitrogen plasma so as to deposit a group III metal nitride on the substrate, a plasma inlet to facilitate the passage of nitrogen plasma from the plasma generator into the reaction chamber and a baffle having one or more flow channels for passage of the nitrogen plasma. The baffle is located between the plasma inlet and the substrate and prevents a direct line of passage for nitrogen plasma between the plasma inlet and the substrate. | 2012-03-22 |
20120070964 | METHOD FOR ELIMINATING THE METAL CATALYST RESIDUES ON THE SURFACE OF WIRES PRODUCED BY CATALYTIC GROWTH - This method for eliminating the catalyst residues present on the surface of solid structures made from a first material and obtained by catalytic growth, includes the following steps:
| 2012-03-22 |
20120070965 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device includes a first conductive type first semiconductor region, a second semiconductor region, and a second conductive type lateral RESURF region. The first semiconductor region is arranged on a first electrode side. The second semiconductor region includes first conductive type first pillar regions and a terminal part. The second pillar regions are alternately arranged on an element part. The terminal part is formed around the element part along a surface of the first semiconductor region on a second electrode side opposite to the first electrode side of the first semiconductor region. Furthermore, the second conductive type lateral RESURF region is formed in the second semiconductor region on the terminal part. | 2012-03-22 |
20120070966 | METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT - A method for manufacturing a semiconductor element includes etching a surface of a substrate by a dry etching processing, performing a first heat treatment for the surface of the substrate in an atmosphere including halogen, and forming a nitride semiconductor on the surface of the substrate. | 2012-03-22 |
20120070967 | Method for Forming Gallium Nitride Devices with Conductive Regions - Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others. | 2012-03-22 |
20120070968 | SUBSTRATE PROCESSING METHOD AND METHOD OF MANUFACTURING CRYSTALLINE SILICON CARBIDE (SIC) SUBSTRATE - The present invention provides a method of processing a substrate and a method of manufacturing a silicon carbide (SiC) substrate in which, when annealing processing is performed on a crystalline silicon carbide (SiC) substrate, the occurrence of surface roughness is suppressed. A substrate processing method according to an embodiment of the present invention includes a step of performing plasma irradiation on a single crystal silicon carbide (SiC) substrate ( | 2012-03-22 |
20120070969 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes steps of preparing a semiconductor substrate having a first conductive type; implanting a first impurity having the first conductive type in the semiconductor substrate to form a well region having a bottom portion; and implanting a second impurity having a second conductive type in the semiconductor substrate to form an impurity region having a top portion, the top of the impurity region being in contact with the bottom portion of the well region. Implantation of the second impurity includes a first step of implanting the second impurity and a second step of implanting the second impurity, wherein a first implantation area of the first step of implanting the second impurity being broader or narrower than a second implantation area of the second step of implanting the second impurity. | 2012-03-22 |
20120070970 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes; exposing a resist layer | 2012-03-22 |
20120070971 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICES USING STRESS ENGINEERING - There is provided a method for fabricating a semiconductor device comprising the formation of a first device in the first device region, the first device comprising first diffusion regions. A stressor layer covering the substrate in the first device region and the first device is subsequently formed, the stressor layer having a first stress value. A laser anneal to memorize at least a portion of the first stress value in the first device is carried out followed by an activation anneal after the laser anneal to activate dopants in the first diffusion regions. | 2012-03-22 |
20120070972 | NON-UNIFORMITY REDUCTION IN SEMICONDUCTOR PLANARIZATION - Provided is a method of planarizing a semiconductor device. The method includes providing a substrate. The method includes forming a first layer over the substrate. The method includes forming a second layer over the first layer. The first and second layers have different material compositions. The method includes forming a third layer over the second layer. The method includes performing a polishing process on the third layer until the third layer is substantially removed. The method includes performing an etch back process to remove the second layer and a portion of the first layer. Wherein an etching selectivity of the etch back process with respect to the first and second layers is approximately 1:1. | 2012-03-22 |
20120070973 | Methods of Forming Diodes - Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a sacrificial material, at least one dielectric material, and a second conductive material. Spacers may be formed along opposing sidewalls of the stack, and then an entirety of the sacrificial material may be removed to leave a gap between the first conductive material and the at least one dielectric material. In some embodiments of forming diodes, a layer may be formed over a first conductive material, with the layer containing supports interspersed in sacrificial material. At least one dielectric material may be formed over the layer, and a second conductive material may be formed over the at least one dielectric material. An entirety of the sacrificial material may then be removed. | 2012-03-22 |
20120070974 | MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device manufacture method includes: forming a first film above a semiconductor substrate; forming a first mask film above the first film; patterning the first mask film; executing a plasma process for a side wall of the patterned first mask film to transform the side wall into a transformed layer; after the plasma process, forming a second mask film covering the first mask film; etching the second mask film to remove the second mask film above the first mask film and leave the second mask film formed on the side wall; after the etching the second mask film, removing the transformed layer; and after the removing the transformed layer, etching the first film by using the first mask film and the second mask film as mask. | 2012-03-22 |
20120070975 | Methods of Forming Gate Structure and Methods of Manufacturing Semiconductor Device Including the Same - A method of forming agate structure having an improved electric characteristic is disclosed. A gate insulating layer is formed on a substrate and a metal layer is formed on the gate insulating layer. Then, an amorphous silicon layer is formed on the metal layer by a physical vapor deposition (PVD) process. An impurity doped polysilicon layer is formed on the amorphous silicon layer. Formation of an oxide layer at an interface between the amorphous silicon layer and the metal layer may be prevented. | 2012-03-22 |
20120070976 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device includes forming a plurality of preliminary gate structures, forming a capping layer pattern on sidewalls of the plurality of preliminary gate structures, and forming a blocking layer on top surfaces of the plurality of preliminary gate structures and the capping layer pattern such that a void is formed therebetween. The method also includes removing the blocking layer and an upper portion of the capping layer pattern such that at least the upper sidewalls of the plurality of preliminary gate structures are exposed, and a lower portion of the capping layer pattern remains on lower sidewalls of the preliminary gate structures. The method further includes forming a conductive layer on at least the upper sidewalls of the plurality of preliminary gate structures, reacting the conductive layer with the preliminary gate structures, and forming an insulation layer having an air gap therein. | 2012-03-22 |
20120070977 | Methods For Forming Contacts in Semiconductor Devices - Mask sets, layout design, and methods for forming contacts in devices are described. In one embodiment, a semiconductor device includes a plurality of contacts disposed over a substrate, the plurality of contacts being disposed as rows and columns on an orthogonal grid, each row of the plurality of contacts is spaced from an neighboring row of the plurality of contacts by a first distance, and each column of the plurality of contacts is spaced from an neighboring column of the plurality of contacts by a second distance. | 2012-03-22 |
20120070978 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A miniaturized semiconductor device is provided by reducing the design thickness of a wiring line protecting film covering the surface of a wiring layer, and reducing the distance between the wiring layer and via plugs formed by a self-aligning process. Dummy mask layers extending in the same layout pattern as the wiring layer is formed above the wiring layer covered with a protecting film composed of a cap layer and side wall layers. In the self-aligning process for forming via plugs in a self-aligned manner with the wiring layer and its protecting film, the thickness of the cap layer is reduced and the design interval between the via plugs is reduced, whereby the miniaturization of the semiconductor device is achieved. | 2012-03-22 |
20120070979 | METHOD OF ELECTROLYTIC PLATING AND SEMICONDUCTOR DEVICE FABRICATION - The disclosure relates generally to semiconductor device fabrication, and more particularly to methods of electroplating used in semiconductor device fabrication. A method of electroplating includes: immersing an in-process substrate into an electrolytic plating solution to form a first metal layer on the in-process substrate; then performing a first chemical-mechanical polish to a liner on the in-process substrate followed by immersing the in-process substrate into the electrolytic plating solution to form a second metal layer on the first metal layer and the liner; and performing a second chemical-mechanical polish to the liner. | 2012-03-22 |
20120070980 | MULTI MATERIAL SECONDARY METALLIZATION SCHEME IN MEMS FABRICATION - Processes are provided herein for the fabrication of MEMS utilizing both a primary metal that is integrated into the final MEMS structure and two or more sacrificial secondary metals that provide structural support for the primary metal component during machining. A first secondary metal is thinly plated around the primary metal and over the entire surface of the substrate without using photolithography. A second secondary metal, is then thickly plated over the deposited first secondary metal without using photolithography. Additionally, techniques are disclosed to increase the deposition rate of the first secondary metal between primary metal features in order to prevent voiding and thus enhance structural support of the primary metal during machining. | 2012-03-22 |
20120070981 | ATOMIC LAYER DEPOSITION OF A COPPER-CONTAINING SEED LAYER - The present disclosure relates to the field of microelectronic device fabrication and, more particularly, to the formation of copper-containing seed layers for the fabrication of interconnects in integrated circuits. The copper-containing seed layers may be formed in an atomic layer deposition process with a copper pre-cursor and organometallic co-reagent. | 2012-03-22 |
20120070982 | METHODS FOR FORMING LAYERS ON A SUBSTRATE - Methods for forming layers on a substrate having one or more features formed therein are provided herein. In some embodiments, a method for forming layers on a substrate having one or more features formed therein may include depositing a seed layer within the one or more features; and etching the seed layer to remove at least a portion of the seed layer proximate an opening of the feature such that the seed layer comprises a first thickness disposed on a lower portion of a sidewall of the feature proximate a bottom of the feature and a second thickness disposed on an upper portion of the sidewall proximate the opening of the feature and wherein the first thickness is greater than the second thickness. | 2012-03-22 |
20120070983 | SEMICONDUCTOR DEVICE WITH GATE TRENCH - A method of manufacturing a semiconductor device is presented. The device has: a gate terminal formed from polysilicon and covered by an insulation layer; and a plug extending through an insulation layer to provide an electrical connection to the gate trench. A metal layer is deposited to cover at least a portion of the insulation layer. The metal layer is then etched to remove the metal layer from above the plug. | 2012-03-22 |
20120070984 | METHOD FOR FORMING ELECTRODE STRUCTURE - In a method for forming an electrode structure in a display device, e.g. a source, drain or gate electrode or a pixel electrode, a photoactive conductive layer, which includes conductive material containing photoactive material, is formed above a substrate of the display device. The photoactive conductive layer is then patterned with a photo-mask and partially removed without the presence of a photo-resist to form the electrode structure. | 2012-03-22 |
20120070985 | EXPOSURE METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, an exposure method is disclosed. The method can include applying light to a photomask by an illumination. The method can include converging diffracted beams emitted from the photomask by a lens. In addition, the method can include imaging a plurality of point images on an exposure surface. On the photomask, a light transmitting region is formed at a lattice point represented by nonorthogonal unit cell vectors, and in the illumination, a light emitting region is set so that three or more of the diffracted beams pass through positions equidistant from center of a pupil of the lens. | 2012-03-22 |
20120070986 | SEMICONDUCTOR DEVICE HAVING INSULATING FILM WITH SURFACE MODIFICATION LAYER AND METHOD FOR MANUFACTURING THE SAME - Provided is a semiconductor device, which includes an interlayer insulating film formed on a semiconductor substrate, a wiring layer filled in a recess formed in the interlayer insulating film, and a cap insulating film. The interlayer insulating film includes a first SiOCH film and a surface modification layer including an SiOCH film formed by modifying a surface layer of the first SiOCH film, the SiOCH film having a lower carbon concentration and a higher oxygen concentration than the first SiOCH film has. The cap insulating film contacts with surfaces of the metal wiring and the surface modification layer. | 2012-03-22 |
20120070987 | SEMICONDUCTOR DEVICE HAVING DECREASED CONTACT RESISTANCE - Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure. | 2012-03-22 |
20120070988 | METHODS AND APPARATUSES FACILITATING FLUID FLOW INTO VIA HOLES, VENTS, AND OTHER OPENINGS COMMUNICATING WITH SURFACES OF SUBSTRATES OF SEMICONDUCTOR DEVICE COMPONENTS - A method for removing material from surfaces of at least a portion of at least one recess or at least one aperture extending into a surface of a substrate includes pressurizing fluid so as to cause the fluid to flow into the at least one recess or at least one aperture. The fluid may be pressurized by generating a pressure differential across the substrate, which causes the fluid to flow into or through the at least one aperture or recess. Apparatus for pressurizing fluid so as to cause it to flow into or through recesses or apertures in a substrate are also disclosed. | 2012-03-22 |
20120070989 | Stabilized, Concentratable Chemical Mechanical Polishing Composition And Method Of Polishing A Substrate - A chemical mechanical polishing composition, comprising, as initial components: water; an abrasive; a diquaternary substance according to formula (I), wherein each X is independently selected from N and P; wherein R | 2012-03-22 |
20120070990 | Slurry Composition Having Tunable Dielectric Polishing Selectivity And Method Of Polishing A Substrate - A chemical mechanical polishing slurry composition, comprising, as initial components: water; an abrasive; a halogenated quaternary ammonium compound according to formula (I), wherein R | 2012-03-22 |
20120070991 | CHEMICAL MECHANICAL POLISHING OF SILICON CARBIDE COMPRISING SURFACES - Slurry compositions and chemically activated CMP methods for polishing a substrate having a silicon carbide surface using such slurries. In such methods, the silicon carbide surface is contacted with a CMP slurry composition that comprises i) a liquid carrier and ii) a plurality of particles having at least a soft surface portion, wherein the soft surface portion includes a transition metal compound that provides a Mohs hardness ≦6, and optionally iii) an oxidizing agent. The oxidizing agent can include a transition metal. The slurry is moved relative to the silicon carbide comprising surface, wherein at least a portion of the silicon carbide surface is removed. | 2012-03-22 |
20120070992 | METHOD OF STRIPPING HOT MELT ETCH RESISTS FROM SEMICONDUCTORS - Hot melt etch resist is selectively applied to an anti-reflective coating or a selective emitter on a semiconductor wafer. The exposed portions of the anti-reflective coating or selective emitter are etched away using an inorganic acid containing etch to expose the semiconductor surface. The hot melt etch resist is then stripped from the semiconductor with an alkaline stripper which does not compromise the electrical integrity of the semiconductor. The exposed semiconductor is then metalized to form current tracks. | 2012-03-22 |
20120070993 | PASSIVATION OF INTEGRATED CIRCUITS CONTAINING FERROELECTRIC CAPACITORS AND HYDROGEN BARRIERS - A method for forming a hydrogen barrier layer that overlies ferroelectric capacitors and a buffer region but is removed from a portion of the logic region. | 2012-03-22 |
20120070994 | RESIST UNDERLAYER FILM FORMING COMPOSITION CONTAINING SILICON HAVING SULFIDE BOND - There is provided a resist underlayer film forming composition for lithography for forming a resist underlayer film capable of being used as a hard mask; and a forming method of a resist pattern using the underlayer film forming composition for lithography. A resist underlayer film forming composition for lithography comprising: as a silicon atom-containing compound, a hydrolyzable organosilane containing a sulfur atom-containing group, a hydrolysis product thereof, or a hydrolysis-condensation product thereof, wherein in the whole silicon atom-containing compound, the ratio of a sulfur atom to a silicon atom is less than 5% by mole. The hydrolyzable organosilane is preferably a compound of Formula (1): [R | 2012-03-22 |
20120070995 | METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating a metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a first transistor region and a second transistor region; forming a first metal-oxide semiconductor (MOS) transistor on the first transistor region and a second MOS transistor on the second transistor region, in which the first MOS transistor includes a first dummy gate and the second MOS transistor comprises a second dummy gate; forming a patterned hard mask on the second MOS transistor, in which the hard mask includes at least one metal atom; and using the patterned hard mask to remove the first dummy gate of the first MOS transistor. | 2012-03-22 |
20120070996 | POLAR REGIONS FOR ELECTROSTATIC DE-CHUCKING WITH LIFT PINS - An apparatus for electrostatic chucking and dechucking of a semiconductor wafer includes an electrostatic chuck with a number of zones. Each zone includes one or more polar regions around a lift pin that contacts a bottom surface of the semiconductor wafer. The apparatus also includes one or more controllers that control the lift pins and one or more controllers that control the polar regions. The controller for the lift pins receives data from one or more sensors and uses the data to adjust the upward force of the lift pins. Likewise, the controller for the polar regions receives data from the sensors and uses the data to adjust the voltage in the polar regions. | 2012-03-22 |
20120070997 | GAS SWITCHING SECTION INCLUDING VALVES HAVING DIFFERENT FLOW COEFFICIENT'S FOR GAS DISTRIBUTION SYSTEM - A gas switching system for a gas distribution system for supplying different gas compositions to a chamber, such as a plasma processing chamber of a plasma processing apparatus, is provided. The chamber can include multiple zones, and the gas switching section can supply different gases to the multiple zones. The switching section can switch the flows of one or more gases, such that one gas can be supplied to the chamber while another gas can be supplied to a by-pass line, and then switch the gas flows. | 2012-03-22 |
20120070998 | Composition for Wet Etching of Silicon Dioxide - Provided is an etching composition for electively removing silicon dioxide at a high etch rate, more particularly, a composition for wet etching of silicon dioxide, including 1 to 40 wt % of hydrogen fluoride (HF); 5 to 40 wt % of ammonium hydrogen fluoride (NH | 2012-03-22 |
20120070999 | REPLACEABLE SUBSTRATE MASKING ON CARRIER AND METHOD FOR PROCESSING A SUBSTRATE - A holding device adapted for holding a mask and a substrate during processing is described. The holding device includes a substrate carrier adapted for carrying the substrate; and a mask for masking the substrate, wherein the mask is releasably connected to the substrate carrier; wherein the substrate carrier or the mask has at least one recess adapted for receiving a cover for covering the substrate carrier during deposition. | 2012-03-22 |
20120071000 | MANUFACTURING APPARATUS AND METHOD FOR SEMICONDUCTOR DEVICE - A manufacturing apparatus for a semiconductor device, comprising: a reactor chamber configured to load a wafer therein; a gas supplying mechanism configured to supply a process gas into the reactor chamber; a gas discharging mechanism configured to discharge a gas from the reactor chamber; a wafer supporting member configured to mount the wafer thereon; a ring configured to mount the wafer supporting member thereon; a rotary drive controlling mechanism configured to connect to the ring for rotating the wafer; a heater arranged in the ring for heating the wafer to a predetermined temperature; an electrode part configured to connect to the heater and including a screw concave portion; and an electrode including a screw portion which is connected to the electrode part via the screw concave portion. | 2012-03-22 |
20120071001 | VAPORIZING AND FEED APPARATUS AND VAPORIZING AND FEED METHOD - A vaporizing and feed apparatus for vaporizing and feeding a solid film-forming raw material comprises a supercritical fluid feeding part for producing and feeding a supercritical fluid, a supercritical fluid adjusting part for dissolving the solid film-forming raw material in the supercritical fluid by bringing the supercritical fluid fed from the supercritical fluid feeding part into contact with the solid film-forming raw material, and a vaporizing part for phase-transitioning the supercritical fluid having the dissolved solid film-forming raw material to a gas, the solid film-forming raw material thereby being deposited in the gas, and for vaporizing the deposited solid film-forming raw material. | 2012-03-22 |
20120071002 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - A process of manufacturing a semiconductor device may be simplified, and oxidation of a metal element-containing film may be suppressed. The method of manufacturing a semiconductor device includes loading a substrate including a metal element-containing film and an insulating film formed on the metal element-containing film into a process chamber and supporting the substrate using a substrate support installed in the process chamber; supplying a reactive gas including at least one of hydrogen in excited state and nitrogen in excited state, and oxygen in excited state onto the substrate in the process chamber and processing the substrate; and unloading the substrate from an inside of the process chamber. | 2012-03-22 |
20120071003 | Vacuum Processing Apparatus, Vacuum Processing Method, and Micro-Machining Apparatus - Disclosed is a technology in which a nozzle part is mounted in a vacuum chamber and a silicon substrate is held to face a discharge hole of the nozzle part. For example, ClF | 2012-03-22 |
20120071004 | STRESS-ADJUSTING METHOD OF MOS DEVICE - A stress-adjusting method for use in a manufacturing system of a MOS device is provided. At first, a first stress layer is formed onto a substrate wherein at least two MOSFETs are previously formed on the substrate. The first stress layer overlies an inter-gate region between two adjacent gate regions of the MOSFETs and overlies the two adjacent gate regions. Then, the first stress layer in the inter-gate region is thinned. A second stress layer is further formed onto the substrate to overlie the thinned first stress layer in the inter-gate region to provide the resulting MOS device with satisfactory stress. | 2012-03-22 |
20120071005 | HEAT TREATING APPARATUS, HEAT TREATING METHOD AND STORAGE MEDIUM - A heat treating apparatus, which performs a specified heat treatment on a target object, includes a processing chamber accommodating therein the target object; a mounting table for mounting thereon the target object; a vacuum exhaust system for vacuum evacuating the processing chamber; an electromagnetic wave supply unit for irradiating an electromagnetic wave onto the target object to heat the target object; and a controller for controlling the heat treating apparatus such that the electromagnetic wave is irradiated onto the target object at a high vacuum level at which plasma is not generated. Further, a heat treating method performs a specified heat treatment on a target object, wherein the target object is accommodated in a processing chamber capable of being vacuum evacuated, and the target object is heated by irradiating an electromagnetic wave thereon at a high vacuum level at which plasma is not generated in the processing chamber. | 2012-03-22 |
20120071006 | STARTING MATERIAL FOR USE IN FORMING SILICON OXIDE FILM AND METHOD FOR FORMING SILICON OXIDE FILM USING SAME - Disclosed is a starting material for use in forming a silicon oxide film on a substrate by the CVD method, comprising a siloxane compound having a carbonyl group, wherein the starting material is decomposed by applying energy, thereby releasing CO and producing a product having no dangling bond in the chemical structure, and the product contributes to the formation of the film. As a result, a silicon oxide film having a favorable step coverage is formed. | 2012-03-22 |
20120071007 | SUBSTRATE PROCESSING WITH REDUCED WARPAGE AND/OR CONTROLLED STRAIN - Provided are systems and methods for processing the surface of substrates that scan a laser beam at one or more selected orientation angles. The orientation angle or angles may be selected to reduce substrate warpage. When the substrates are semiconductor wafers having microelectronic devices, the orientation angles may be selected to produce controlled strain and to improve electronic performance of the devices. | 2012-03-22 |
20120071008 | MAGNETIC ELECTRICAL COUPLING ADAPTOR - A magnetic electrical coupling adapter to identify the positive coupling prior to activating an electrical circuit is disclosed. The adapter comprises at least one controlling connector, at least one receiving connector and a plurality of magnets. The magnets provide strong attractive force between the connectors for maintaining positive coupling between the connectors. The controlling connector includes a plurality of male prongs, at least one mating face having a plurality of contact points and at least one regulating circuitry. The regulating circuitry controls the electricity between the male prongs. The receiving connector comprises a plurality of female prongs, at least one mating face having a plurality of contact points and at least one identification circuitry. The identification circuitry provides digital signature to the regulating circuitry when the connectors are positively coupled. Thus the regulating circuitry and the identification circuitry negate the possibility of electrical shock to a user. | 2012-03-22 |
20120071009 | ELECTRICAL SOCKET ASSEMBLY FOR ELECTRICALLY CONNECTING ADJACENT CIRCUIT BOARDS - An electrical socket assembly including a socket housing having coupling and flange portions and a contact cavity that extends through the coupling and flange portions along a central axis. The coupling and flange portions have different peripheral contours that extend about the central axis. The peripheral contour of the flange portion being sized and shaped to prevent the flange portion from advancing through a thru-hole of a circuit board. The socket assembly also includes a fastener that is configured to be secured to the coupling portion. The fastener and the flange portion have respective mating surfaces that face each other in opposite directions along the central axis. The respective mating surfaces are configured to grip the circuit board therebetween such that the socket housing has a fixed position relative to the circuit board. A conductive path exists between the power contact and the circuit board. | 2012-03-22 |
20120071010 | Electronic Control Device - An electronic control device including a plurality of terminal pins each including a first circuit board side connecting portion connected to a first circuit board, a second circuit board side connecting portion connected to a second circuit board, and an intermediate connecting portion disposed between the first and second circuit board side connecting portions and extending in an overlapping direction in which the first and second circuit boards overlap with each other, the intermediate connecting portions being aligned in a row along a predetermined alignment direction, and the terminal pins at least partially including adjacent two terminal pins formed into a bent shape such that the first circuit board side connecting portion of one of the adjacent two terminal pins is offset relative to the first circuit board side connecting portion of the other adjacent two terminal pins in a direction perpendicular to the predetermined alignment direction. | 2012-03-22 |
20120071011 | ADAPTER FOR HIGH-SPEED ETHERNET - An adapter includes a mechanical frame, which is configured to be inserted into a SFP-type receptacle and contains a socket for receiving a plug of a twisted-pair-type cable. First electrical terminals, held by the mechanical frame, are configured to mate with a connector in the receptacle. Second electrical terminals, held within the socket, are configured to mate with electrical connections of the plug. Circuitry connects the first and second electrical terminals so as to enable interoperation of the plug with the receptacle. | 2012-03-22 |
20120071012 | Mini Display Port Structure - A mini display port structure is provided for receiving a connector insert. The mini display port structure includes a circuit board unit and a receptacle unit. The circuit board unit has a base board, wherein an opening is formed on one side of the base board. A portion of the receptacle unit is accommodated in the opening of the circuit board unit and is connected to the base board. Accordingly, the circuit board unit is elevated at a certain position within the height of receptacle unit, and thus the height of the receptacle unit can include the height of the circuit board unit at the same time, thereby shrinking the height of the mini display port structure after the circuit board unit is assembled for making a compact mini display port. | 2012-03-22 |