12th week of 2016 patent applcation highlights part 59 |
Patent application number | Title | Published |
20160087065 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A gate insulating film is provided on a trench. The gate insulating film has a trench insulating film and a bottom insulating film. The trench insulating film covers each of a side wall and a bottom portion. The bottom insulating film is provided on the bottom portion with a trench insulating film being interposed therebetween. The bottom insulating film has a carbon atom concentration lower than that of the trench insulating film. The gate electrode is in contact with a portion of the trench insulating film on the side wall. Accordingly, a low threshold voltage and a large breakdown voltage can be attained. | 2016-03-24 |
20160087066 | VAPOR DEPOSITION OF METAL OXIDES, SILICATES AND PHOSPHATES, AND SILICON DIOXIDE - Metal silicates or phosphates are deposited on a heated substrate by the reaction of vapors of alkoxysilanols or alkylphosphates along with reactive metal amides, alkyls or alkoxides. For example, vapors of tris(tert-butoxy)silanol react with vapors of tetrakis(ethylmethylamido)hafnium to deposit hafnium silicate on surfaces heated to 300° C. The product film has a very uniform stoichiometry throughout the reactor. Similarly, vapors of diisopropylphosphate react with vapors of lithium bis(ethyldimethylsilyl)amide to deposit lithium phosphate films on substrates heated to 250° C. Supplying the vapors in alternating pulses produces these same compositions with a very uniform distribution of thickness and excellent step coverage. | 2016-03-24 |
20160087067 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment includes: a semiconductor layer; a control gate electrode; and an organic molecular layer, which is provided between the semiconductor layer and the control gate electrode, and has organic molecules including a molecular structure described by a molecular formula (1). | 2016-03-24 |
20160087068 | LATERAL BIPOLAR TRANSISTOR WITH BASE EXTENSION REGION - A method of forming a base extension region for a lateral bipolar transistor. The base extension region may include forming an extrinsic base on an intrinsic base layer, the intrinsic base layer is on an insulator layer, a top portion of the intrinsic base layer is exposed on opposite sides of the extrinsic base; forming a base extension region by recessing the exposed top portion of the intrinsic base layer to a recessed surface, the recessed surface is above a top surface of the insulator layer, the base extension region is a region of the intrinsic base layer remaining above the recessed surface; and forming an emitter/collector in the intrinsic base layer, an intrinsic base is a portion of the intrinsic base layer between the emitter/collector, the emitter/collector is a distance from the extrinsic base of no less than a thickness of the base extension region. | 2016-03-24 |
20160087069 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an SOI substrate and a MISFET formed on the SOI substrate. The SOI substrate has a base substrate, a ground plane region formed on the base substrate, a BOX layer formed on the ground plane region and an SOI layer formed on the BOX layer. The base substrate is made of silicon and the ground plane region includes a semiconductor region made of silicon carbide. | 2016-03-24 |
20160087070 | METHOD AND APPARATIS FOR SOURCE-DRAIN JUNCTION FORMATION FINFET WITH QUANTUM BARRIER AND GROUND PLANE DOPING - A portion of a bulk silicon (Si) is formed into a fin, having a fin base and, on the fin base, an in-process fin. The fin base is doped Si and the in-process fin is silicon germanium (SiGe). The in-process SiGe fin has a source region and a drain region. Boron is in-situ doped into the drain region and into the source region. Optionally, boron is in-situ doped by forming an epi-layer, having boron, on the drain region and on the source region, and drive-in annealing to diffuse boron in the source region and the drain region. | 2016-03-24 |
20160087071 | Methods of Forming Diodes - Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer. | 2016-03-24 |
20160087072 | DUMMY BIT LINE MOS CAPACITOR AND DEVICE USING THE SAME - A MOS capacitor, a method of fabricating the same, and a semiconductor device using the same are provided. The MOS capacitor is arranged in an outermost cell block of the semiconductor device employing an open bit line structure. The MOS capacitor includes a first electrode arranged in a semiconductor substrate, a dielectric layer arranged on a semiconductor substrate, and a second electrode arranged on the dielectric layer and including a dummy bit line. | 2016-03-24 |
20160087073 | BIPOLAR JUNCTION TRANSISTORS WITH AN AIR GAP IN THE SHALLOW TRENCH ISOLATION - Device structures, fabrication methods, and design structures for a bipolar junction transistor. A trench isolation region is formed in a substrate. The trench isolation region is coextensive with a collector in the substrate. A base layer is formed on the collector and on a first portion of the trench isolation region. A dielectric layer is formed on the base layer and on a second portion of the trench isolation region peripheral to the base layer. After the dielectric layer is formed, the trench isolation region is at least partially removed to define an air gap beneath the dielectric layer and the base layer. | 2016-03-24 |
20160087074 | Metalization of a Field Effect Power Transistor - A metalization of a field effect power transistor having lateral semiconductor layers on an insulator substrate or an intrinsically conducting semiconductor substrate is described. The lateral semiconductor layers have different band gaps such that a two-dimensional electron gas can form in their semiconductor depletion layer. Upon application of a voltage between source electrode contact areas and drain electrode contact areas or source and drain, an electric current can flow through the lateral semiconductor depletion layer. Current intensity in a channel region between the source electrode contact areas and the drain electrode contact areas is controllable via gate electrode contact areas by means of a gate voltage. | 2016-03-24 |
20160087075 | TRANSISTOR DEVICE AND FABRICATION METHOD - The present disclosure provides a transistor device and fabrication method thereof. A dummy gate is formed on a substrate. An interlayer dielectric layer is formed on the substrate and sidewall surfaces of the dummy gate. The interlayer dielectric layer has a top surface coplanar with a top surface of the dummy gate. A mask layer is formed on the top surface of the interlayer dielectric layer. The mask layer is used as an etch mask to remove the dummy gate to form a trench in the interlayer dielectric layer to provide a trench footing on sidewall surfaces of the trench and near a trench bottom. The trench footing is then removed by applying a dry etching process. A gate electrode is then formed in the trench to form a transistor with improved electrical performance. | 2016-03-24 |
20160087076 | FABRICATING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, a source/drain regions adjacent to the pair of spacers in the substrate, an etch stop layer next to the gate structure and overlying the substrate, a contact plug extending into the source/drain region and partially overlapping the gate structure, a protective layer over the etch stop layer overlying the substrate and covering the etch stop layer next to the gate structure without the contact plug, and an interlayer dielectric layer over the protective layer. The contact plug has no contact-to-gate short issue to the gate structure. | 2016-03-24 |
20160087077 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes preparing a semiconductor substrate, forming a gate electrode on the semiconductor substrate via a gate insulating film, forming a laminated film on the semiconductor substrate so as to cover the gate electrode, the laminated film including a first insulating film and a second insulating film on the first insulating film, forming a first side wall insulating film, formed of the laminated film, on a side wall of the gate electrode by etching back the laminated film, epitaxially growing an epitaxial semiconductor layer on a portion of the semiconductor substrate which is not covered with the gate electrode and the first side wall insulating film but is exposed, forming an oxide film on a surface of the epitaxial semiconductor layer by oxidizing the surface of the epitaxial semiconductor layer, and removing the second insulating film forming the first side wall insulating film. | 2016-03-24 |
20160087078 | MOS Devices Having Epitaxy Regions with Reduced Facets - An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region. | 2016-03-24 |
20160087079 | FIN FIELD EFFECT TRANSISTOR - A method of fabricating a fin field effect transistor (FinFET) including forming a first insulation region and a second insulation region and fin there between. The method further includes forming a gate stack over a portion of the fin and over a portion of the first and second insulation regions. The method further includes tapering the top surfaces of the first and second insulation regions not covered by the gate stack. | 2016-03-24 |
20160087080 | INTEGRATED VERTICAL TRENCH MOS TRANSISTOR - A VTMOS transistor in semiconductor material of a first type of conductivity includes a body region of a second type of conductivity and a source region of the first type of conductivity. A gate region extends into the main surface through the body region and is insulated from the semiconductor material. A region of the gate region extends onto the main surface is insulated from the rest of the gate region. An anode region of the first type of conductivity is formed into said insulated region, and a cathode region of the second type of conductivity is formed into said insulated region in contact with the anode region; the anode region and the cathode region define a thermal diode electrically insulated from the chip. | 2016-03-24 |
20160087081 | LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - The present disclosure relates to a lateral double-diffused metal oxide semiconductor transistor and a method for manufacturing the same. In the method, a high-voltage gate dielectric is formed at a surface of a semiconductor layer. A thin gate dielectric is formed above the substrate and has at least a portion adjacent to the high-voltage gate dielectric. A gate conductor is formed above the thin gate dielectric and the high-voltage gate dielectric. A first mask is used for patterning the gate conductor to define a first sidewall of the gate conductor above the thin gate dielectric. A second mask is used for patterning the gate conductor to define a second sidewall of the gate conductor at least partially above the high-voltage gate dielectric. Source and drain regions are formed to have a first doping type. The method further comprises doping through the first mask to form a body region of a second doping type. The second doping type is opposite to the first doping type. The method simplifies a manufacturer process and improves reliability of the resultant devices. | 2016-03-24 |
20160087082 | POWER LDMOS SEMICONDUCTOR DEVICE WITH REDUCED ON-RESISTANCE AND MANUFACTURING METHOD THEREOF - An electronic semiconductor device including a semiconductor body having a first structural region and a second structural region, which extends on the first structural region and houses a drain region; a body region, which extends into the second structural region; a source region, which extends into the body region; and a gate electrode, which extends over the semiconductor body for generating a conductive channel between the source region and the drain region. The device includes a first conductive trench extending through, and electrically insulated from, the second structural region on one side of the gate electrode; and a second conductive trench extending through the source region, the body region, and right through the second structural region on an opposite side of the gate electrode, electrically insulated from the second structural region and electrically coupled to the body region and to the source region. | 2016-03-24 |
20160087083 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME - A lateral drain metal oxide semiconductor (LDMOS) device includes a well region having a second conductive type in a substrate, a body region having a first conductive type in the well region, a drift region having the second conductive type in the well region and spaced apart from the body region, a source region having the second conductive type in the body region, a drain region having the second conductive type in the drift region, a gate structure on the well region between the source region and the drain region, a shallow trench isolation (STI) structure in the drift region between the drain region and the source region, and a buried layer having the first conductive type in the well region under the drift region, a center of the buried layer being aligned with a center of the STI structure | 2016-03-24 |
20160087084 | LDMOS POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Methods form an electronic semiconductor device that includes a body having a first side and a second side opposite to one another and including a first structural region facing the second side, and a second structural region extending over the first structural region and facing the first side. A body region extends in the second structural region at the first side. A source region extends inside the body region and a lightly-doped drain region faces the first side of the body. A gate electrode is formed over the body region. A trench dielectric region extends through the second structural region in a first trench conductive region immediately adjacent to the trench dielectric region. A second trench conductive region is in electrical contact with the body region and source region. An electrical contact on the body is in electrical contact with the drain region through the first structural region. | 2016-03-24 |
20160087085 | Method for Manufacturing Semiconductor Device - To provide a semiconductor device with improved reliability. To provide a semiconductor device with stable characteristics. To provide a transistor having a low off-state current. To provide a transistor having a high on-state current. To provide a novel semiconductor device, a novel electronic device, or the like. A method for manufacturing the semiconductor device includes the steps of forming a first semiconductor over a substrate; forming a second semiconductor over and in contact with the first semiconductor; forming a first layer over the second semiconductor; performing oxygen plasma treatment and then removing the first layer to expose at least part of a surface of the second semiconductor; forming a third semiconductor over and in contact with the second semiconductor; forming a first insulator over and in contact with the third semiconductor; and forming a first conductor over the first insulator. | 2016-03-24 |
20160087086 | SEMICONDUCTOR DEVICES - Semiconductor devices include an intrinsic semiconductor region on a substrate, a source region adjacent to a first side surface of the semiconductor region and doped with a p-type dopant, a drain region adjacent to a second side surface of the semiconductor region, a gate electrode on the semiconductor region, a source gate electrode on the source region, and a drain gate electrode on the drain region. The second side surface is a reverse side of the first side surface. The drain region is doped with a p-type dopant. | 2016-03-24 |
20160087087 | METHOD OF MAKING A GRAPHENE BASE TRANSISTOR WITH REDUCED COLLECTOR AREA - A method of making a graphene base transistor with reduced collector area comprising forming a graphene material layer, forming a collector material, depositing a dielectric, planarizing the dielectric, cleaning and removing the native oxide, transferring a base graphene material layer to the top surface of the graphene material layer, bonding the base graphene material layer, and photostepping and defining a second graphene material layer. A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region. A graphene base transistor with reduced collector area comprising an electron emitter region, an electron collection region, and a base region. | 2016-03-24 |
20160087088 | Tunnel Junction Field Effect Transistors Having Self-Aligned Source and Gate Electrodes and Methods of Forming the Same - Methods of forming a transistor include providing a semiconductor epitaxial structure including a channel layer and barrier layer on the channel layer, forming a gate electrode on the barrier layer, etching the semiconductor epitaxial structure using the gate electrode as an etch mask to form a trench in the semiconductor epitaxial structure, and depositing a source metal in the trench. The trench extends at least to the channel layer, and the source metal forms a Schottky junction with the channel layer. Related semiconductor device structures are also disclosed. | 2016-03-24 |
20160087089 | Non-Planar Normally Off Compound Semiconductor Device - A normally-off compound semiconductor device includes a first III-nitride semiconductor having a first sloped transition region in which the first III-nitride semiconductor transitions at an angle from a first level to a second level different than the first level, and a second III-nitride semiconductor on the first III-nitride semiconductor and having a different band gap than the first III-nitride semiconductor so that a two-dimensional charge carrier gas arises along an interface between the first and second III-nitride semiconductors. The normally-off compound semiconductor device further includes a gate on the second III-nitride semiconductor and a doped semiconductor over the first sloped transition region and interposed between the gate and the second III-nitride semiconductor. The two-dimensional charge carrier gas is disrupted along the first sloped transition region due solely to the slope of the first sloped transition region if steep enough, or also due to the presence of the doped semiconductor. | 2016-03-24 |
20160087090 | RF POWER TRANSISTOR - A radio frequency (RF) power transistor includes: a semiconductor heterostructure that includes an undoped barrier layer and an active layer and that is formed with a continuous two dimensional electron gas (2DEG) channel having an ohmic source-aligned region, an ohmic drain-aligned region and a Schottky-aligned region; agate electrode; and source and drain electrodes. One of the source and drain electrodes includes an ohmic contact and a Schottky contact that extends from the ohmic contact toward the gate electrode. The 2DEG channel is normally on and extends continuously from the ohmic source-aligned region to the ohmic drain-aligned region. The Schottky contact overlaps and is capacitively coupled to the Schottky-aligned region of the 2DEG channel. | 2016-03-24 |
20160087091 | INSULATING GATE FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF MAKING THE SAME - An insulated gate field-effect transistor (IGFET) device includes a semiconductor body ( | 2016-03-24 |
20160087092 | METHOD FOR MANUFACTURING A FIN MOS TRANSISTOR - A fin MOS transistor is made from an SOI-type structure that includes a semiconductor layer on a silicon oxide layer coating a semiconductor support. A trench formed from the surface of the semiconductor layer delimits at least one fin in the semiconductor layer, that trench extending at least to an upper surface of the semiconductor support. Etched recesses in sides of a portion of the silicon oxide layer located under the fin are filled with a material selectively etchable over silicon oxide. | 2016-03-24 |
20160087093 | MOS DEVICE WITH ISLAND REGION - A semiconductor device formed on a semiconductor substrate, comprising: an epitaxial layer overlaying the semiconductor substrate; a drain formed on back of the semiconductor substrate; a drain region that extends into the epitaxial layer; an active region; and an island region under the contact trench and disconnected from the body, the island region having an opposite polarity as the epitaxial layer. The active region comprises: a body disposed in the epitaxial layer; a source embedded in the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and the body; and an active region contact electrode disposed within the active region contact trench. | 2016-03-24 |
20160087094 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having a main cell region and a sense cell region. A separation trench separating a main second semiconductor region from a sense second semiconductor region is provided in an upper surface of the semiconductor substrate. The semiconductor substrate includes a separation fourth semiconductor region being of a second conductivity type and separated from the main second semiconductor region and the sense second semiconductor substrate by a third semiconductor region. | 2016-03-24 |
20160087095 | SEMICONDUCTOR DEVICE INCLUDING SUPERJUNCTION STRUCTURE FORMED USING ANGLED IMPLANT PROCESS - A semiconductor device includes a superjunction structure formed using simultaneous N and P angled implants into the sidewall of a trench. The simultaneous N and P angled implants use different implant energies and dopants of different diffusion rate so that after annealing, alternating N and P thin semiconductor regions are formed. The alternating N and P thin semiconductor regions form a superjunction structure where a balanced space charge region is formed to enhance the breakdown voltage characteristic of the semiconductor device. | 2016-03-24 |
20160087096 | SEMICONDUCTOR DEVICE AND RELATED FABRICATION METHODS - Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first region of semiconductor material having a first conductivity type and a first dopant concentration, a second region of semiconductor material having a second conductivity type overlying the first region, a drift region of semiconductor material having the first conductivity type overlying the second region, and a drain region of semiconductor material having the first conductivity type. The drift region and the drain region are electrically connected, with at least a portion of the drift region residing between the drain region and the second region, and at least a portion of the second region residing between that drift region and the first region. In one or more exemplary embodiments, the first region abuts an underlying insulating layer of dielectric material. | 2016-03-24 |
20160087097 | QUASI-VERTICAL STRUCTURE HAVING A SIDEWALL IMPLANTATION FOR HIGH VOLTAGE MOS DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a buried layer in a substrate, the buried layer having a first dopant type. The semiconductor device further includes a first layer over the buried layer, the first layer having the first dopant type. The semiconductor device further includes at least one first well in the first layer, the at least one first well having a second dopant type. The semiconductor device further includes an implantation region in a sidewall of the first layer, the implantation region having the second dopant type, wherein the implantation region is below the at least one first well. | 2016-03-24 |
20160087098 | Semiconductor Devices Having Gate Structures and Methods of Manufacturing the Same - Semiconductor devices are provided including an active layer, a gate structure, a spacer, and a source/drain layer. The active layer is on the substrate and includes germanium. The active layer includes a first region having a first germanium concentration, and a second region on both sides of the first region. The second region has a top surface getting higher from a first portion of the second region adjacent to the first region toward a second portion of the second region far from the first region, and has a second germanium concentration less than the first germanium concentration. The gate structure is formed on the first region of the active layer. The spacer is formed on the second region of the active layer, and contacts a sidewall of the gate structure. The source/drain layer is adjacent to the second region of the active layer. | 2016-03-24 |
20160087099 | FINFET WITH HETEROJUNCTION AND IMPROVED CHANNEL CONTROL - Roughly described, a computer program product describes a transistor with a fin, a fin support, a gate, and a gate dielectric. The fin includes a first crystalline semiconductor material which includes a channel region of the transistor between a source region of the first transistor and a drain region of the transistor. The fin is on a fin support. The fin support includes a second crystalline semiconductor material different from the first crystalline semiconductor material. The first crystalline semiconductor material of the fin and the second crystalline semiconductor material of the fin support form a first heterojunction in between. A gate, gate dielectric, and/or isolation dielectric can be positioned to improve control within the channel. | 2016-03-24 |
20160087100 | METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURES INCLUDING FIN STRUCTURES WITH DIFFERENT STRAIN STATES, AND RELATED SEMICONDUCTOR STRUCTURES - Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states. | 2016-03-24 |
20160087101 | SEMICONDUCTOR DEVICES INCLUDING A STRESSOR IN A RECESS AND METHODS OF FORMING THE SAME - Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region. | 2016-03-24 |
20160087102 | SEMICONDUCTOR DEVICE HAVING A STRAIN FEATURE IN A GATE SPACER AND METHODS OF MANUFACTURE THEREOF - A device may include a substrate having a channel region therein, the channel region having a first lattice constant; a gate stack formed over the channel region; a spacer lining a sidewall of the gate stack, the spacer having a recess therein, the recess extending over a lateral portion of the channel region; and a source region having a second lattice constant different from the first lattice constant, the source region extending continuously from a first portion laterally adjacent to the channel region to a second portion extending into the recess and over the channel region. | 2016-03-24 |
20160087103 | FinFET with Buried Insulator Layer and Method for Forming - A fin structure suitable for a FinFET and having a buried insulator layer is disclosed. In an exemplary embodiment, a semiconductor device comprises a substrate with a first semiconductor material and having a fin structure formed thereupon. The fin structure includes a lower region proximate to the substrate, a second semiconductor material disposed on the lower region, a third semiconductor material disposed on the second semiconductor material, and an insulating material selectively disposed on the second semiconductor material such that the insulating material electrically isolates a channel region of the fin structure and further such that the insulating material exerts a strain on the channel region. The semiconductor device further comprises an isolation feature disposed adjacent to the fin structure. | 2016-03-24 |
20160087104 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The device may include an active pattern protruding from a substrate, gate structures crossing the active pattern, and a source/drain region provided between adjacent ones of the gate structures. The source/drain region may include a source/drain epitaxial layer in a recessed region, which is formed in the active pattern between the adjacent ones of the gate structures. Further, an impurity diffusion region may be provided in the active pattern to enclose the source/drain epitaxial layer along inner surfaces of the recessed region. | 2016-03-24 |
20160087105 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, including the steps of forming a semiconductor over a substrate; forming a first conductor over the semiconductor; forming a first insulator over the first conductor; forming a resist over the first insulator; performing light exposure and development on the resist to make a second region and a third region remain and expose part of the first insulator; applying a bias in a direction perpendicular to a top surface of the substrate and generating plasma using a gas containing carbon and halogen; and depositing and etching an organic substance with the plasma. The etching rate of the organic substance is higher than the deposition rate of the organic substance in an exposed part of the first insulator, and the deposition rate of the organic substance is higher than the etching rate of the organic substance in a side surface of the second region. | 2016-03-24 |
20160087106 | E-FLASH CELL BAND ENGINEERING FOR ERASING SPEED ENHANCEMENT - The present disclosure relates to a structure and method for forming a flash memory cell with an improved erase speed and erase current. Si dots are used for charge trapping and an ONO sandwich structure is formed over the Si dots. Erase operation includes direct tunneling as well as FN tunneling which helps increase erase speed without compensating data retention. | 2016-03-24 |
20160087107 | SEMICONDUCTOR DEVICE - A structure is employed in which a first protective insulating layer; an oxide semiconductor layer over the first protective insulating layer; a source electrode and a drain electrode that are electrically connected to the oxide semiconductor layer; a gate insulating layer that is over the source electrode and the drain electrode and overlaps with the oxide semiconductor layer; a gate electrode that overlaps with the oxide semiconductor layer with the gate insulating layer provided therebetween; and a second protective insulating layer that covers the source electrode, the drain electrode, and the gate electrode are included. Furthermore, the first protective insulating layer and the second protective insulating layer each include an aluminum oxide film that includes an oxygen-excess region, and are in contact with each other in a region where the source electrode, the drain electrode, and the gate electrode are not provided. | 2016-03-24 |
20160087108 | Thin Film Transistor, Method for Manufacturing the Same, and Display Device Comprising the Same - A thin film transistor, a method of manufacturing the thin film transistor, and a display device including the thin film transistor are provided. The thin film transistor comprises an oxide semiconductor layer, a gate electrode, a source electrode and a drain electrode formed on a substrate in a coplanar configuration. A first conductive member is in direct contact with the oxide semiconductor layer and in direct contact with the source electrode. A second conductive member is in direct contact with the oxide semiconductor layer and in direct contact with the drain electrode. The first conductive member and the second conductive member are arranged to decrease resistance between a channel region of the oxide semiconductor layer and the source and drain electrodes. | 2016-03-24 |
20160087109 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided just above the charge storage layer, a top layer (C) provided just below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C). The middle layer (B) has higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C). The average coordination number of the middle layer (B) is smaller than both the average coordination number of the top layer (C) and the average coordination number of the bottom layer (A). | 2016-03-24 |
20160087110 | SEMICONDUCTOR DEVICE | 2016-03-24 |
20160087111 | NANO STRUCTURED PARAELECTRIC OR SUPERPARAELECTRIC VARACTORS FOR AGILE ELECTRONIC SYSTEMS - An electronic device in the form a two-dimensional array of nanopillars extending generally normal to a substrate is provided. The nanopillars are made from a paraelectric or superparaelectric material. In addition, a linear dielectric medium is located between individual nanopillars. A two-dimensional array of paraelectric or superparaelectric nanopillars and a linear dielectric medium form the effective dielectric medium of a paraelectric or superparaelectric varactor. In some instances, the nanopillars are cylindrical nanopillars that have an average diameter and/or average height/length between 1-300 nanometers. In other instances, the nanopillars are quasi-nanoparticles that form self-aligned nano-junctions. In addition, each of the nanopillars has a single paraelectric or superparaelectric dipole domain therewithin. As such, each of the nanopillars can be void of crystallographic defects, polycrystallinity, interactions between ferroic domains, and defects due to ferroic domain walls. | 2016-03-24 |
20160087112 | HIGH TEMERATURE, HERMETICALLY SEALED, TRIAXIAL MOUNT FOR A LIGHT SENSITIVE ELEMENT - A sensor assembly for a flame sensor apparatus includes a photodiode that generates a current. The sensor assembly includes a seal assembly supporting the photodiode. The seal assembly includes an inner conductor defining an inner conductor end. The inner conductor includes an inner conductor surface disposed at the inner conductor end. The photodiode is attached to the inner conductor end of the inner conductor and to a middle conductor end of a middle conductor. The photodiode is electrically connected to the inner conductor surface. The seal assembly is triaxial so as to protect the current generated by the photodiode. The seal assembly withstands temperatures up to or greater than about 325° C. The seal assembly forms a hermetic barrier that, with the photodiode supported within a sealed volume, limits the passage of materials/gases through the seal assembly. | 2016-03-24 |
20160087113 | NANO-ELECTRODE MULTI-WELL HIGH-GAIN AVALANCHE RUSHING PHOTOCONDUCTOR - Provided is a detector that includes a scintillator, a common electrode, a pixel electrode, and a plurality of insulating layers, with a plurality of nano-pillars formed in the plurality of insulating layers, a nano-scale well structure between adjacent nano-pillars, with a-Se separating the adjacent nano-pillars, and a method for operation thereof. | 2016-03-24 |
20160087114 | BROADBAND ANTIREFLECTION COATINGS UNDER COVERGLASS USING ION GUN ASSISTED EVAPORATION - The present disclosure generally relates to broadband antireflective coatings for reducing reflection of light in the infrared without compromising visible light reflectance in multijunction solar cells bonded to coverglass, and methods of forming the same. The antireflective coatings include a high index, one or more intermediate index, and low index of refraction dielectric layers. The high index dielectric layer utilizes an ion beam assisted deposition to maximize the density and index of refraction. The intermediate index layer(s) increase the bandwidth of the antireflection coating, thereby improving the performance of the antireflective coating in the infrared spectrum. | 2016-03-24 |
20160087115 | SOLAR CELL STRUCTURE AND METHOD FOR FABRICATING THE SAME - A solar cell structure with a microsphere-roughened antireflection structure comprises a P-type metal contact electrode, a P-type semiconductor layer, a P-type monocrystalline substrate, an N-type semiconductor layer, an N-type metal contact electrode, and a microsphere-roughened antireflection layer. The N-type semiconductor layer and the P-type semiconductor layer are respectively arranged on an upper surface and a lower surface of the P-type monocrystalline substrate. The P-type metal contact electrode is arranged below the P-type semiconductor layer. The N-type metal contact electrode has a specified pattern and is connected with the N-type semiconductor layer. The microsphere-roughened antireflection layer is arranged on an upper surface of the N-type semiconductor layer without covering the N-type metal contact electrode. The microsphere-roughened antireflection layer reduces the reflection of sunlight and increases the transmittance of sunlight to enhance the efficiency of solar cells. | 2016-03-24 |
20160087116 | DISPLAY DEVICE INTEGRATED WITH SOLAR CELL PANEL AND METHODS FOR PRODUCING THE SAME - The present invention discloses a solar cell panel integrated on a display unit, a display device integrated with the solar cell panel and methods for producing the same. The solar cell panel integrated on a display unit according to the present invention comprises a photoelectric material layer with RGB colors comprising red units, green units and blue units, wherein the red units, green units and blue units are arranged corresponding to pixel arrays in the display unit, and one or two of the red units, green units and blue units are made of the photoelectric active material. The photoelectric active material layer with RGB colors according to the present invention can replace a common color filter. | 2016-03-24 |
20160087117 | Cone Shaped Focusing Lens - An optical assembly can be used in various optical devices such as optical proximity sensors, gesture sensors, or imaging sensors. The optical assembly may include a lens assembly and a light detector. The lens assembly may be configured to limit off axis rays at a central area of the light detector. The lens assembly can be a high aspect ratio lens assembly. | 2016-03-24 |
20160087118 | PHOTOELECTRIC CONVERSION DEVICE, AND SOLAR CELL - A photoelectric conversion device of an embodiment has a bottom electrode, an intermediate layer on the bottom electrode, a p-type light absorbing layer on the intermediate layer, and an n-type layer on the p-type light absorbing layer. The bottom electrode is a first metal film or a semiconductor film. When the bottom electrode is a metal film, the intermediate layer comprises an oxide film or a sulfide film. When the bottom electrode is a semiconductor film, the intermediate layer comprises a second metal film and an oxide film or a sulfide film on the second metal film. | 2016-03-24 |
20160087119 | PROTECTION LAYER FOR FOIL-BASED METALLIZATION OF SOLAR CELLS - Approaches for foil-based metallization of solar cells are described. For example, a method of fabricating a solar cell involves placing a metal foil over a metalized surface of a wafer of the solar cell. The method further involves placing a protection layer over the metal foil. The method further involves locating the metal foil with the metalized surface of the wafer. The protection layer preserves an optically consistent surface of the metal foil during the locating. The method also involves, subsequent to the locating, electrically contacting the metal foil to the metalized surface of the wafer. | 2016-03-24 |
20160087120 | MODULE FABRICATION OF SOLAR CELLS WITH LOW RESISTIVITY ELECTRODES - One embodiment of the present invention provides a solar module. The solar module includes a front-side cover, a back-side cover, and a plurality of solar cells situated between the front- and back-side covers. A respective solar cell includes a multi-layer semiconductor structure, a front-side electrode situated above the multi-layer semiconductor structure, and a back-side electrode situated below the multi-layer semiconductor structure. Each of the front-side and the back-side electrodes comprises a metal grid. A respective metal grid comprises a plurality of finger lines and a single busbar coupled to the finger lines. The single busbar is configured to collect current from the finger lines. | 2016-03-24 |
20160087121 | SOLAR CELL HAVING A REAR SIDE METALLIZATION - Various embodiments provide a solar cell. The solar cell includes a substrate having a front side and a rear side. At least the front side receives light. The solar cell further includes a multiplicity of rear side solder pad regions at least partially arranged over the rear side, and a plurality of partial solder pads formed in each rear side solder pad region of the multiplicity of rear side solder pad regions. Each partial solder pad includes a first metal. The partial solder pads in a respective rear side solder pad region are separated from each other. The solar cell further includes a rear side metallization formed at the rear side of the substrate partly overlapping the partial solder pads, the rear side metallization including a second metal different from the first metal. | 2016-03-24 |
20160087122 | SOLAR CELL EMITTER REGION FABRICATION WITH DIFFERENTIATED P-TYPE AND N-TYPE ARCHITECTURES AND INCORPORATING DOTTED DIFFUSION - Methods of fabricating solar cell emitter regions with differentiated P-type and N-type architectures and incorporating dotted diffusion, and resulting solar cells, are described. In an example, a solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed in a plurality of non-continuous trenches in the back surface of the substrate. | 2016-03-24 |
20160087123 | SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME - A solar cell and a method for manufacturing the same are discussed. The solar cell includes a semiconductor substrate, a first doped region of a first conductive type, a second doped region of a second conductive type opposite the first conductive type, a back passivation layer having contact holes exposing a portion of each of the first and second doped regions, a first electrode formed on the first doped region exposed through the contact holes, a second electrode formed on the second doped region exposed through the contact holes, an alignment mark formed at one surface of the semiconductor substrate, and a textured surface that is formed at a light receiving surface of the semiconductor substrate opposite the one surface of the semiconductor substrate in which the first and second doped regions are formed. | 2016-03-24 |
20160087124 | SOLAR CELL INCLUDING ELECTRODE FORMED ON HIGH SHEET RESISTANCE WAFER - A solar cell, including a p-n junction substrate; and an electrode on one surface of the p-n junction substrate. The p-n junction substrate may have a sheet resistance of about 85 Ω/sq to about 150 Ω/sq, and a silver (Ag) crystal having a particle diameter of about 10 nm to about 1,000 nm may be present within the electrode adjacent to an interface between the p-n junction substrate and the electrode. | 2016-03-24 |
20160087125 | PHOTOELECTRIC CONVERSION DEVICE, AND SOLAR CELL - A photoelectric conversion device of an embodiment has a substrate, a bottom electrode on the substrate, a light absorbing layer on the bottom electrode, an n-type layer on the light absorbing layer, a transparent electrode on the n-type layer, and an oxide layer on the transparent electrode. n | 2016-03-24 |
20160087126 | PHOTOELECTRIC CONVERSION DEVICE, SOLAR CELL AND METHOD FOR MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE - A photoelectric conversion device of an embodiment has a bottom electrode, a light absorbing layer on the bottom electrode. The light absorbing layer comprises a thin film of a semiconductor comprising a group Ib element or elements, a group IIIb element or elements, and a group VIb element or elements and having a chalcopyrite structure. The light absorbing layer has an average crystal grain size of 1.5 μm or more. The group IIIb element or elements include Ga, Al, or both of Ga and Al. | 2016-03-24 |
20160087127 | PHOTOELECTRIC CONVERSION DEVICE, SOLAR CELL AND METHOD FOR MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE - A photoelectric conversion device of an embodiment has a substrate, a bottom electrode comprising an electrode layer on the substrate and an intermediate interface layer, a light absorbing layer on the intermediate interface layer. The electrode layer comprises Mo or W. The intermediate interface layer is a compound thin film of a compound comprising Mo or W and at least one element X selected from the group consisting of S, Se, and Te. The intermediate interface layer has a crystal phase and an amorphous phase with which the crystal phase is covered. | 2016-03-24 |
20160087128 | LIGHT HARVESTING ANTENNA COMPLEXES - The invention disclosed concerns a simple ring-hub arrangement of interacting two-level systems using a theoretical quantum jump approach which mimics a biological light-harvesting antenna connected to a reaction center. | 2016-03-24 |
20160087129 | METHODS FOR ENGINEERING POLAR DISCONTINUITIES IN NON-CENTROSYMMETRIC HONEYCOMB LATTICES AND DEVICES INCLUDING A TWO-DIMENSIONAL INSULATING MATERIAL AND A POLAR DISCONTINUITY OF ELECTRIC POLARIZATION - The present invention relates to a device comprising a two-dimensional component, the two-dimensional component including at least one two-dimensional insulating material and including a polar discontinuity of the electric polarization. The present invention also relates to methods for producing such a device. | 2016-03-24 |
20160087130 | COMPOSITION FOR SOLAR CELL SEALING FILM, METHOD FOR PRODUCING SAME AND SOLAR CELL SEALING FILM - The present invention provides a composition for a solar cell sealing film prepared by mixing an ethylene-α-olefin copolymer (m-LLDPE) polymerized using a metallocene catalyst and other polymers as resin components, wherein the composition has the same processability as a composition containing m-LLDPE alone and provides a solar cell sealing film having the same transparency as the case where m-LLDPE is used alone. A composition for a solar cell sealing film comprising m-LLDPE and low-density polyethylene (LDPE), wherein the weight average molecular weight of m-LLDPE (M | 2016-03-24 |
20160087131 | FACADE ELEMENT OR ROOF ELEMENT - A façade element or roof element ( | 2016-03-24 |
20160087132 | Dynamic PV Module And Method Of Manufacturing - There is provided a dynamic photovoltaic module omprising the photovoltaic module comprising a number of cell stacks connected in serial therebetween, each cell stack among said cell stacks comprising a number of photovoltaic cells connected in parallel therebetween. In a preferred embodiment, each cell stack comprises a same number of photovoltaic cells having a same cell voltage and cell current equal to the quotient of the module current and the cell current and the number of cell stacks in the module being equal to the quotient of the module voltage and the cell voltage. The proposed dynamic PV module is adapted to mitigate the problem of mismatch effects hence improving the performance of PV modules caused by conditions such as partial and full shading, soiling, non-uniform illuminations, solar concentration and clouds, inside-module defects like broken cells or connectors. There is also provided a method of manufacturing a dynamic PV module. | 2016-03-24 |
20160087133 | LIGHT CONCENTRATION DEVICE - Light concentration device comprising: —a primary luminescent solar concentrator (LSC) having a polygonal, circular or elliptic form, comprising at least one photoluminescent compound having a first absorption range and a first emission range; —at least a secondary luminescent solar concentrator (LSC) positioned outside said primary luminescent solar concentrator (LSC), said secondary luminescent solar concentrator (LSC) comprising at least one photoluminescent compound having a second absorption range superimposable to said first emission range and a second emission range. Said light concentration device can be advantageously used in photovoltaic devices (or solar devices) such as, for example, photovoltaic cells (or solar cells), photoelectrolytic cells. Said light concentration device can also be advantageously used in photovoltaic windows. | 2016-03-24 |
20160087134 | SOLAR CELL APPARATUS AND METHOD OF FABRICATING THE SAME - Disclosed are a solar cell apparatus and a method of fabricating the same. The solar cell apparatus includes a substrate, a back electrode layer on the substrate, a light absorbing layer on the back electrode layer, a front electrode layer on the light absorbing layer, a bus bar provided beside the light absorbing layer while being connected to the back electrode layer, and a conductive part surrounding the bus bar. The method includes forming a back electrode layer on a substrate, forming a bus bar on the back electrode layer, forming a light absorbing layer beside the bus bar on the back electrode layer, and forming a front electrode layer on the light absorbing layer. A conductive part surrounds the bus bar in the step of forming the bus bar. | 2016-03-24 |
20160087135 | Light-Concentrating Mechanism, Photovoltaic Power Generation Device, Window Structure, and Window Glass - [Problem] To provide a light-concentrating mechanism that is suitable for photovoltaic power generation. [Solution] This light-concentrating mechanism comprises an angle selective reflection means that reflects light having an incident angle of at least a first threshold angle and transmits at least some of the light having an incident angle smaller than the first threshold angle, and an angle-increase reflection means that reflects incident light at an angle greater than the incident angle of said light, the two means being arranged so as to have a gap therebetween. The angle-increase reflection means reflects, at an angle that is equal to or greater than the first threshold angle, at least some of the light that has been transmitted by the angle-selective reflection means, and the angle-selective reflection means reflects the light that has been reflected by the angle-increase reflection means and has an angle that is equal to or greater than the first threshold angle, and light is propagated and concentrated by the gap between the angle-selective reflection means and the angle-increase reflection means. | 2016-03-24 |
20160087136 | SOLAR CELL MODULE - According to one embodiment, a solar cell module includes a solar cell panel and a concentrator. The solar cell panel includes a solar cell. The concentrator reflects light incident from the outside and irradiates the light onto the solar cell. The concentrator has a first surface and a second surface. The first surface reflects light incident at a first incident angle and irradiates the light incident at the first incident angle onto a first portion within the area of the solar cell. The second surface reflects light incident at a second incident angle and irradiates the light incident at the second incident angle onto a second portion within the area of the solar cell. The second incident angle is different from the first incident angle. The second portion is different from the first portion. The first surface and the second surface are asymmetric as viewed from the solar cell. | 2016-03-24 |
20160087137 | MULTI-JUNCTION SOLAR CELL - According to one embodiment, a multi-junction solar cell includes a first solar cell, a second solar cell, and an insulating layer. The first solar cell includes a first photoelectric conversion element. The second solar cell is connected in parallel with the first solar cell. The second solar cell includes multiple second photoelectric conversion elements connected in series. The insulating layer is provided between the first solar cell and the second solar cell. The second photoelectric conversion element includes a p-electrode and an n-electrode. The p-electrode is connected to a p | 2016-03-24 |
20160087138 | TRANSPARENT CONDUCTING OXIDE FOR PHOTOVOLTAIC DEVICES - One embodiment of the present invention provides a solar cell. The solar cell includes a Si base layer, a passivation layer situated above the Si base layer, a layer of heavily doped amorphous Si (a-Si) situated above the passivation layer, a first transparent-conducting-oxide (TCO) layer situated above the heavily doped a-Si layer, a back-side electrode situated below the Si base layer, and a front-side electrode situated above the first TCO layer. The first TCO layer comprises at least one of: GaInO, GaInSnO, ZnInO, and ZnInSnO. | 2016-03-24 |
20160087139 | MATERIALS, FABRICATION EQUIPMENT, AND METHODS FOR STABLE, SENSITIVE PHOTODETECTORS AND IMAGE SENSORS MADE THEREFROM - Optically sensitive devices include a device comprising a first contact and a second contact, each having a work function, and an optically sensitive material between the first contact and the second contact. The optically sensitive material comprises a p-type semiconductor, and the optically sensitive material has a work function. Circuitry applies a bias voltage between the first contact and the second contact. The optically sensitive material has an electron lifetime that is greater than the electron transit time from the first contact to the second contact when the bias is applied between the first contact and the second contact. The first contact provides injection of electrons and blocking the extraction of holes. The interface between the first contact and the optically sensitive material provides a surface recombination velocity less than 1 cm/s. | 2016-03-24 |
20160087140 | SOLAR CELL FABRICATED BY SIMPLIFIED DEPOSITION PROCESS - Methods of fabricating solar cells using simplified deposition processes, and the resulting solar cells, are described. In an example, a method of fabricating a solar cell involves loading a template substrate into a deposition chamber and, without removing the template substrate from the deposition chamber, performing a deposition method. The deposition method involves forming a first silicon layer on the template substrate, the first silicon layer of a first conductivity type. The deposition method also involves forming a second silicon layer on the first silicon layer, the second silicon layer of the first conductivity type. The deposition method also involves forming a third silicon layer above the second silicon layer, the third silicon layer of a second conductivity type. The deposition method also involves forming a solid state doping layer on the third silicon layer, the solid state doping layer of the first conductivity type. | 2016-03-24 |
20160087141 | Composite substrates of silicon and ceramic - Composite substrates include a single crystal silicon layer disposed on a ceramic layer, including a transparent glass layer. Combination of single crystal devices and non-single crystal devices can be fabricated on a ceramic substrate. | 2016-03-24 |
20160087142 | SEMICONDUCTOR LAYER SEQUENCE AND METHOD FOR OPERATING AN OPTOELECTRONIC COMPONENT - The semiconductor layer sequence includes an n-conductive layer, a p-conductive layer and an active zone located therebetween. The active zone comprises N quantum wells with N≧2. At a first working point (W | 2016-03-24 |
20160087143 | HIGH SPEED SURFACE PLASMON COUPLED LIGHT EMITTING DIODES - A light emitting diode device (LED) is provided. The LED comprises a first-doped layer on a substrate, an active layer on the first-doped layer, a second-doped layer on the active layer, and a metal layer on the second-doped layer. The second-doped layer is patterned on a surface opposite to the active layer to define a first portion and a second portion. The first portion of the second-doped layer has a first portion thickness constrained for electron-hole pairs in the active layer to couple efficiently to a surface plasmon mode at an interface of the metal layer and the second-doped layer thereby increasing the spontaneous emission rate of the LED. The second portion of the second-doped layer has a second portion thickness sufficient to ensure formation of a p-n junction in the LED. | 2016-03-24 |
20160087144 | SOLID STATE LIGHTING DEVICES WITHOUT CONVERTER MATERIALS AND ASSOCIATED METHODS OF MANUFACTURING - Solid state lighting devices that can produce white light without a phosphor are disclosed herein. In one embodiment, a solid state lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The active region includes a first sub-region having a first center wavelength and a second sub-region having a second center wavelength different from the first center wavelength. | 2016-03-24 |
20160087145 | SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light emitting element includes: a pit formation layer formed on the first semiconductor layer and having a pyramidal pit; and an active layer formed on the pit formation layer and having a flat portion and an embedded portion which is formed so as to embed the pit. The active layer has a multi-quantum well structure having a well layer and a barrier layer laminated alternately in which each well layer and each barrier layer lie one upon another. The flat portion has a flat well portion corresponding to the well layer. The embedded portion has an embedded well portion corresponding to the well layer. The embedded well portion has a ring portion which is formed in an interface with the flat well portion so as to surround the threading dislocation. The ring portion has a band gap smaller than that of the flat well portion. | 2016-03-24 |
20160087146 | SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light emitting element includes: a pit formation layer formed on a first semiconductor layer and having a pyramidal pit; an active layer formed on the pit formation layer and having an embedded portion formed so as to embed the pit. The active layer has a multi-quantum well structure having at least one pair of well layer and barrier layer laminated alternately. The embedded portion has at least one embedded well portion corresponding to the well layer respectively and at least one embedded barrier portion corresponding to the barrier layer respectively. Each of the embedded well portion and the embedded barrier portion is configured such that a second apex angle of the embedded well portion is smaller than a first apex angle of the embedded barrier portion wherein the embedded well portion is subsequently formed on the embedded barrier portion. | 2016-03-24 |
20160087147 | SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light emitting element includes: a pit formation layer having a pyramidal pit caused by a threading dislocation generated in the first semiconductor layer; an active layer; and an electron blocking layer formed on the active layer to cover the recess portion. The active layer is formed on the pit formation layer and having an embedded portion formed so as to embed the pit and a recess portion formed on a surface of the embedded portion to correspond to the pit. The recess portion of the active layer has an apex formed at a position existing in a layered direction of the active layer within the active layer. | 2016-03-24 |
20160087148 | NON-METALLIC SEMICONDUCTOR QUANTUM DOT AND METHOD OF CARRYING OUT CHEMICAL REACTION OR PHOTOLUMINESCENCE REACTION BY USING THE SAME - A non-metallic semiconductor quantum dot is provided with a non-metallic substrate, and has a particle size ranged from 0.3 to 100 nm. A method of carrying out a chemical reaction or a photoluminescence reaction by using the non-metallic semiconductor quantum dot is also provided. A redox reaction of a target sample is carried out, an active substance is generated, or an electron-hole pair is produced from the non-metallic semiconductor quantum dot by providing the non-metallic semiconductor quantum dot with a predetermined energy. Photons are released by the combination of the electron-hole pair so as to perform the photoluminescence reaction. | 2016-03-24 |
20160087149 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes a semiconductor laminate containing an n-type layer, a light-emitting layer, and a p-type layer, via holes penetrating the p-type and the light-emitting layers exposing the n-type layer, a p-side electrode extending on the p-type layer and having light reflectivity, which is separated from each of the boundary edges of the p-type layer and the plurality of via holes, an insulating layer which covers via hole side surfaces and extends on the p-type layer, and which extends on the boundary edge portion of the p-side electrode, and n-side electrodes which are electrically connected to the n-type layer at the bottoms of the via holes, which are led above the p-type layer and the p-side electrode with the insulating layer intervening therebetween, which overlap the p-side electrode without gaps, in a plan view, and which have light reflectivity. | 2016-03-24 |
20160087150 | LIGHT-EMITTING ASSEMBLY HAVING A SEMICONDUCTOR LAYER SEQUENCE HAVING AN ACTIVE ZONE ON A COLUMNAR STRUCTURE - An assembly has a columnar structure arranged with one end on a substrate, wherein the structure is at least partly covered with a semiconductor layer structure having an active zone that generates electromagnetic radiation, the active zone has a band gap for a radiative recombination, and the band gap decreases along a longitudinal axis of the structure in a direction of a free end of the structure such that a diffusion of charge carriers in the direction of the free end of the structure and a radiative recombination of charge carrier pairs in the region of the free end of the structure are supported. | 2016-03-24 |
20160087151 | LIGHT EMITTING DIODE DIE AND MANUFACTURING METHOD THEREOF - An LED die includes a substrate, a pre-growth layer, a first insulating layer and a light emitting structure. The pre-growth layer, the first insulating layer and the light emitting structure are formed on the structure that order. The substrate includes a first electrode, a second electrode and an insulating part. The insulating part is formed between the first electrode and the second electrode. The LED die further includes a second insulating layer and a metal layer which are formed around the pre-growth layer. The present disclosure includes a method for manufacturing the LED die. | 2016-03-24 |
20160087152 | EPITAXIAL FORMATION SUPPORT STRUCTURES AND ASSOCIATED METHODS - Epitaxial formation support structures and associated methods of manufacturing epitaxial formation support structures and solid state lighting devices are disclosed herein. In several embodiments, a method of manufacturing an epitaxial formation support substrate can include forming an uncured support substrate that has a first side, a second side opposite the first side, and coefficient of thermal expansion substantially similar to N-type gallium nitride. The method can further include positioning the first side of the uncured support substrate on a first surface of a first reference plate and positioning a second surface of a second reference plate on the second side to form a stack. The first and second surfaces can include uniformly flat portions. The method can also include firing the stack to sinter the uncured support substrate. At least side of the support substrate can form a planar surface that is substantially uniformly flat. | 2016-03-24 |
20160087153 | ACTIVE REGION CONTAINING NANODOTS (ALSO REFERRED TO AS "QUANTUM DOTS") INMOTHER CRYSTAL FORMED OF ZINC BLENDE-TYPE (ALSO REFERRED TO AS "CUBICCRYSTAL-TYPE") AlyInxGal-y-xN CRYSTAL(Y . 0, X>0) GROWN ON Si SUBSTRATE, AND LIGHTEMITTING DEVICE USING THE SAME (LED AND LD) - A structure of a high luminance LED and a high luminance LD is provided. The present invention provides a light emitting device containing, on a zinc blende-type BP layer formed on an Si substrate, an Al | 2016-03-24 |
20160087154 | NITRIDE SEMICONDUCTOR STRUCTURE - A nitride semiconductor structure including a substrate, a first type nitride semiconductor layer disposed on the substrate, an active layer disposed between the substrate and the first type nitride semiconductor layer and a second type nitride semiconductor layer disposed between the substrate and the active layer is provided. The active layer includes a first multiple quantum well structure including a plurality of first quantum well layers and a plurality of first barrier layers staggered with each other, and a second multiple quantum well structure including a plurality of second quantum well layers and a plurality of second barrier layers staggered with each other. A second type dopant is doped into at least one of the second barrier layers, and a concentration of the second dopant in the second barrier layer is higher than that of the second dopant in the second type nitride semiconductor layer. | 2016-03-24 |
20160087155 | LIGHT-EMITTING DIODE - The present invention relates to a light-emitting diode (LED), which comprises electrodes having a single metal reflective layer. The single metal reflective layer is thicker than the active layer of the LED. Thereby, at least a portion of light emitted from the active layer is reflected by the single metal reflective layer, and thus enhancing the light-emitting efficiency of the LED. | 2016-03-24 |
20160087156 | LIGHT EMITTING DEVICE - A light emitting device includes at least one layer below or above a reflective layer to prevent delamination of the reflective layer from a layer below and/or above the reflective layer. | 2016-03-24 |
20160087157 | TRANSPARENT CONDUCTIVE LAYER STRUCTURE OF LIGHT EMITTING DIODE - A transparent conductive layer structure for an LED is provided. The LED includes a reflecting layer, an N-type electrode, an N-type semiconductor layer, a light emitting layer, a P-type semiconductor layer, a current block layer, a transparent conductive layer and a P-type electrode that are stacked on a substrate. The current block layer is disposed between and separates the P-type electrode and the P-type semiconductor layer. The transparent conductive layer is disposed between the P-type electrode and the current block layer, and connects to the P-type electrode and the P-type semiconductor layer. At a region corresponding to the P-type electrode, a plurality of holes are disposed at the transparent conductive layer to reduce an area of and hence an amount of light absorbed by the transparent conductive layer, thereby increasing light extraction efficiency of excited light from the light emitting layer and enhancing light emitting efficiency of the LED. | 2016-03-24 |
20160087158 | LIGHT EMITTING DIODE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are a light emitting diode including a plurality of protrusions including zinc oxide and a method for manufacturing the same. According to an exemplary embodiment of the present disclosure, the light emitting diode includes: a substrate; a nitride light emitting structure disposed on the substrate; and a transparent electrode layer disposed on the nitride light emitting structure, wherein the transparent electrode layer includes a plurality of protrusions, the plurality of protrusions each have a lower portion and an upper portion, and a side of the lower portion and a side of the upper portion have different gradients. | 2016-03-24 |
20160087159 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes a light-emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer, and a selective transmission-reflection layer disposed on the light-emitting structure and including a plurality of dielectric layers having different optical thicknesses alternately stacked at least once. The sum of an optical thickness of a dielectric layer having a maximum optical thickness and an optical thickness of a dielectric layer having a minimum optical thickness is in the range of 0.75 to 0.80. | 2016-03-24 |
20160087160 | III-V PHOTONIC INTEGRATED CIRCUITS ON SILICON SUBSTRATE - A semiconductor device including a substrate structure including a semiconductor material layer that is present directly on a buried dielectric layer in a first portion of the substrate structure and an isolation dielectric material that is present directly on the buried dielectric layer in a second portion of the substrate structure. The semiconductor device further includes a III-V optoelectronic device that is present in direct contact with the isolation dielectric material in a first region of the second portion of the substrate structure. A dielectric wave guide is present in direct contact with the isolation dielectric material in a second region of the second portion of the substrate structure. | 2016-03-24 |
20160087161 | LIGHTING APPARATUS INCLUDING AN OPTOELECTRONIC COMPONENT - The invention relates to an illumination device ( | 2016-03-24 |
20160087162 | LIGHT EMITTING DEVICE AND TV BACK-LIGHT MODULE WITH WIDE COLOR GAMUT - The present invention provide an light emitting device (LED) with wide color gamut (high NTSC), and a LED backlight module with the light emitting device, the light emitting device includes at least one LED chip, wherein the LED chip is a blue or ultraviolet (UV) LED chip, the light-out surface of the LED chip is covered by a phosphor-converted layer which consists of phosphor converted materials and thermosetting colloid materials, the phosphor converted materials contain green-converted phosphor, red-converted phosphor and a special phosphor material that has strong light-absorbing properties in the wavelength range of 460-510 nm. The present invention can reduce the stringent requirements of phosphor FWHM that needs to meet for conventional high NTSC solution. | 2016-03-24 |
20160087163 | PHOSPHOR, METHOD FOR PRODUCING THE SAME, AND LIGHT-EMITTING DEVICE USING THE SAME - A present embodiment is to provide a phosphor that has favorable temperature characteristics, that can emit yellow light having excellent color rendering properties, and that has high quantum efficiency. The phosphor emits yellow light when excited with light having a luminescence peak in a wavelength range of 250 to 500 nm and has a crystal structure that is substantially identical to the crystal structure of Sr | 2016-03-24 |
20160087164 | LIGHT EMITTING DEVICE - A light emitting device includes a light emitting element adapted to emit blue light, quantum dots that absorb part of the blue light emitted from the light emitting element to emit green light, and at least one of a KSF phosphor adapted to absorb part of the blue light emitted from the light emitting element to emit red light and a MGF phosphor adapted to absorb part of the blue light emitted from the light emitting element to emit red light. | 2016-03-24 |