12th week of 2016 patent applcation highlights part 64 |
Patent application number | Title | Published |
20160087565 | DOOR OPENING/CLOSING DEVICE AND DOOR OPENING/CLOSING METHOD - A door opening/closing device includes: a motor; and a control unit that is configured to control a rotation rate of the motor by pulse-width modulation (PWM) control. The door opening/closing device opens and closes a door of a vehicle with power of the motor. The control unit is configured to perform the PWM control on the motor at a PWM frequency set so as to deviate from a resonance point of an installation body on which the motor is installed. | 2016-03-24 |
20160087566 | METHOD AND APPARATUS FOR CONTROLLING REACTIVE POWER OF GENERATOR IN POWER PLANT - A method and apparatus for controlling a reactive power of a generator in a power plant are provided. The method includes: S1, dividing a plurality of power plants into a plurality of plant-plant coordination groups; S2, dividing generators into a first generator and a second generator set; S3, calculating a deviation between a measured voltage and a preset voltage of a central bus; S4, comparing the deviation with a control dead band threshold; S5, establishing a reactive power tracking model if the deviation is greater than the control dead band threshold; S6, establishing a reactive power keeping model; and S7, obtaining sum reactive power adjustments of the generators according to the first reactive power adjustments and the second reactive power adjustments, and obtaining voltage adjustments of buses according to the sum reactive power adjustments. | 2016-03-24 |
20160087567 | NORMALIZATION OF MOTOR PHASE MEASUREMENTS - A method of normalizing phase measurements for a motor using a normalizing phase measurements (NPM) algorithm that a processor implements to cause a motor controller coupled to stator terminals of the phases to execute forcing a set of input current or voltage vectors (set of input vectors) including repeating the forcing after rotating the rotor through a full mechanical cycle to generate resulting current or voltage samples (resulting samples) of non-normalized phase A and phase B waveforms. The magnitude of the input vectors are sufficiently small to not move the rotor. A maximum value (x_max) and a minimum value (x_min) are determined for each of the non-normalized phase A and phase B waveforms. An offset value and normalization scale factor (NSF) are determined from the max and min values. The offsets and NSFs are applied to the non-normalized phase waveforms to generate normalized phase A and phase B waveforms. | 2016-03-24 |
20160087568 | INPUT VECTOR SET FOR POSITION DETECTION OF PM MOTORS - A method of determining angular position (A) of a rotor of an N-phase permanent magnet motor (PMM). A processor having an associated stored angular position determination (APD) algorithm is programmed to implement the algorithm to cause an associated motor controller to execute steps including forcing one vector at a time a phase vector set of current or voltage vectors to stator terminals of windings for the N-phases a positive and negative magnitude vector, wherein the vector magnitude is sufficiently small to not move the rotor, and a time duration for the forcing current or voltage vectors is essentially constant. The resulting stator current or voltage levels are measured for each current or voltage vector. An N-dimension current vector or voltage vector is generated from superposition of the resulting stator current levels or resulting stator voltage levels. The N-dimension current vector or voltage vector is used to determine angular position. | 2016-03-24 |
20160087569 | CONTROLLING AN ELECTRICALLY-DRIVEN ACTUATOR - In some aspects, an actuation system includes an electrical positioning driver and an electrically-driven actuator. A voltage boost converter in the electrical positioning driver receives an input voltage. The voltage boost converter passes the input voltage to a voltage bus in the electrical positioning driver. The voltage on the voltage bus is converted to an actuator power signal that controls the electrically-driven actuator. The voltage boost converter boosts the voltage on the voltage bus to control a mechanical output performance of the electrically-driven actuator. | 2016-03-24 |
20160087570 | System and Method to Control a Switched Reluctance Machine in Continuous Conduction - A control system for a switched reluctance (SR) machine is disclosed. The SR machine may have a rotor and a stator. The control system may have a converter circuit operatively coupled to the stator and including a plurality of gates in selective communication with each phase of the stator, and a controller in communication with each of the stator and the converter circuit. The controller may be configured to command a fixed dwell of a theta-on angle and a theta-off angle and a varying current command to the plurality of gates when the SR machine is in a continuous conduction mode. | 2016-03-24 |
20160087571 | CIRCUIT ARRANGEMENT HAVING REDUNDANT HALF BRIDGES FOR OPERATING AN ELECTRIC MACHINE - A circuit arrangement for operating an electric machine, which has a plurality of lines, each for one phase of an alternating current to the electric machine, each line having a plurality of series-connected switching elements that form a half bridge, the half bridge having a terminal between two switching elements, and the circuit arrangement being electrically couplable to the electric machine via the terminals of the half bridge. The circuit arrangement is characterized in that each line has a plurality of half bridges, which are electrically connected parallel to each other. | 2016-03-24 |
20160087572 | Motor Drive Device and Motor Drive Method for EPS System - A motor drive device includes an inverter that drives a motor, a power source smoothing capacitor of the inverter, and a control unit that controls the inverter to drive the motor. The control unit precharges the capacitor with a power source voltage, and calculates a capacity value of the capacitor, based on a ratio of the power source voltage and a voltage with which the capacitor is charged, or an amount of time taken until the voltage with which the capacitor is charged, after the passage of a predetermined amount of time from the start of the precharge, reaches a voltage corresponding to the power source voltage. The control unit performs torque limitation of the motor when the capacity value of the capacitor has decreased. | 2016-03-24 |
20160087573 | MULTI-FUNCTION FLOATING SOLAR POWER GENERATING SYSTEM - The present Invention relates to a multi-function floating solar power generating system, which uses buoys to form buoy sets. A convergence box is used as the center for forming a cross structure, on which solar cell modules installed at an inclination angle of 10 to 15 degrees are carried. According to the present invention, a water-pumping unit below the buoy set is used for pumping the fluid. Then a spray unit is used for spraying the fluid and driving the system to rotate counterclockwise or clockwise, hence achieving the effect of tracking the sun. Alternatively, the fluid can be filtered or used for cleaning the solar cell module. | 2016-03-24 |
20160087574 | PROTECTIVE COVERING FOR ROOF MOUNTED SYSTEMS - A protective covering helps to prevent fastener leaks from roof installed fasteners, which are used to mount roofing systems, such as a solar panel installation system, to roofs with a mounting bracket attached to the roof. The protective covering is a portion of flat, malleable waterproof material molded to form a cover, forming a rounded or peaked triangular-shaped structure when viewed from the side. The triangular shaped structure includes a base and a hypotenuse portion where the line of the roof acts as a side which is covered by at least the hypotenuse portion. The hypotenuse portion meets the roof at an angle. The covering is adapted for insertion under portions of a roof shingle, and extends back in a slight rise (downwardly with respect to the roof) to cover the fastener and L-shaped bracket, which the fastener fastens to the roof. | 2016-03-24 |
20160087575 | SUPPORT STRUCTURE FOR SOLAR MODULE - A solar module ( | 2016-03-24 |
20160087576 | PHOTOVOLTAIC MOUNTING SYSTEM FOR TILED ROOFS - A photovoltaic mounting system for tile roofs is disclosed. In one embodiment, mounting bracket is attached to a roof deck and passes through a flashing support and flexible flashing that mimics the contour of the adjacent roof tiles. In other embodiments, a tile hook passes through partial or full tile replacement flashing. A plug or other structure blocks the space around the tile hook preventing the ingress of pests and debris under the flashing and surrounding tiles. Additional photovoltaic module mounting hardware, including sections of rails and frame mounts are attached either the mounting bracket or tile hook. | 2016-03-24 |
20160087577 | FLEXIBLE SOLAR CELLS COMPRISING THICK AND THIN ABSORBER REGIONS - A solar cell includes a p-type semiconductor substrate including a plurality of thin absorption regions and a plurality of thick absorption regions. The plurality of thin absorption regions and the plurality of thick absorption regions are coplanar on a bottom side thereof. An n-type semiconductor layer is disposed over a top side of the p-type semiconductor substrate. The n-type semiconductor layer has a substantially uniform thickness. Metallurgy is disposed on top of the n-type semiconductor layer. The plurality of thin absorption regions are sufficiently thin to render the semiconductor substrate flexible. | 2016-03-24 |
20160087578 | Solar Panel Mechanical Connector And Frame - A design is described for solar panel that allows for modular installation and efficient removal of panels irrespective of the panel's relative location in an array arrangement. A system is provided that includes a plurality of modular panels (such as solar power panels). These panels are rimmed by frames featuring one or more exterior-facing, grooved channels. A first channel—which may be used to mount the panel, and which replaces traditional railing installation systems—and a second channel that is configured to allow movement of one or more panel splices used to secure the panels together. Integrated electrical connection interfaces are provided on opposite side surfaces of the frames to couple with the electrical connection interfaces of adjacent panels to establish an electrical path between them. A spacer component may be inserted between panels to provide access to the electrical connection interfaces; support and rigidity to the joined panels; a grounding path between the panels; and, when combined with the panel splices, to align the panels to prevent damage to the electrical connection interfaces. | 2016-03-24 |
20160087579 | SMART PHOTOVOLTAIC CELLS AND MODULES - A solar photovoltaic module laminate for electric power generation is provided. A plurality of solar cells are embedded within module laminate and arranged to form at least one string of electrically interconnected solar cells within said module laminate. A plurality of power optimizers are embedded within the module laminate and electrically interconnected to and powered with the plurality of solar cells. Each of the distributed power optimizers capable of operating in either pass-through mode without local maximum-power-point tracking (MPPT) or switching mode with local maximum-power-point tracking (MPPT) and having at least one associated bypass switch for distributed shade management. | 2016-03-24 |
20160087580 | SOLAR CELL MODULE AND METHOD OF FABRICATING THE SAME - A solar cell module according to the embodiment includes a support substrate having a single hole at a peripheral region of the support substrate; solar cells at an upper portion of the support substrate; a bus bar electrically connected to the solar cells; and a junction box connected to the bus bar, wherein the junction box includes an insertion part partially inserted in the single hole. | 2016-03-24 |
20160087581 | ELECTRONIC DEVICE, ELECTRONIC APPARATUS, AND MOVING OBJECT - An electronic device includes a resonator provided with a heating element, and a circuit component opposed to the heating element, and provided with at least an oscillating amplifier element, and a distance between the heating element and the circuit component is in a range not smaller than 0 mm and no larger than 1.5 mm. | 2016-03-24 |
20160087582 | RC OSCILLATOR - An oscillator includes an oscillating circuit having an input and an output configured to oscillate between a first state and a second state. The oscillating circuit includes a resistor-capacitor circuit configured to bias the oscillating circuit input towards a target voltage. The oscillating circuit is configured to transition the oscillating circuit output from the first state to the second state in response to the oscillating circuit input reaching a threshold voltage before it reaches the target voltage. Another oscillator includes an oscillating circuit having an input and an output configured to oscillate between the first state and the second state. The oscillating circuit is configured to transition the oscillating circuit output from the first state to the second state in response to the oscillating circuit input reaching a threshold voltage. A starting circuit is configured to set the oscillating circuit input to the threshold voltage to start the oscillating circuit. | 2016-03-24 |
20160087583 | Oscillator, Electronic Apparatus, and Moving Object - An oscillator includes a circuit board including a supporting substrate (base member), a first VCXO (a first oscillator circuit), a second VCXO (a second oscillator circuit), and a ground terminal (terminal for ground). The first VCXO and the second VCXO are configured such that a second output frequency that is output from the second VCXO is higher than a first output frequency that is output from the first VCXO. The second VCXO is placed closer to the ground terminal than the first VCXO. | 2016-03-24 |
20160087584 | OSCILLATOR, ELECTRONIC APPARATUS, AND MOVING OBJECT - An oscillator includes a first VCXO and a second VCXO which are capable of changing an output frequency by application of a control voltage, and a control voltage terminal to which the control voltage is applied, the first VCXO includes a variable-capacitance diode (first variable-capacitance diode) and a resistor (first resistor), the second VCXO includes a variable-capacitance diode (second variable-capacitance diode) and a resistor (second resistor), the cutoff frequency of the first variable-capacitance diode, the second variable-capacitance diode, the first resistor, and the second resistor is equal to the cutoff frequency of the first variable-capacitance diode and the first resistor, and the cutoff frequency of the second variable-capacitance diode and the second resistor. | 2016-03-24 |
20160087585 | Wideband Self-Envelope Tracking RF Power Amplifier - A wideband self-envelope tracking power amplifier (PA) can use more than a 40-MHz channel bandwidth and improves the envelope bandwidth limit of a self-envelope tracking PAs by ten times. The PA uses an envelope load network, which is based on a general multi-stage low-pass filter. The envelope load network located between an RF choke inductor and main DC power supply provides a dynamically modulated PA supply voltage without using a dedicated envelope amplifier. An input terminal of the network connects a main PA via an RF choke inductor to an input of low-pass filter. An output terminal is connected to the low-pass filter via an envelope choke inductor and to a direct current (DC) power supply. A DC blocker is connected between the output of the low-pass filter and ground by a termination resistor. | 2016-03-24 |
20160087586 | PACKAGED RF AMPLIFIER DEVICES AND METHODS OF MANUFACTURE THEREOF - An embodiment of a packaged radio frequency (RF) device includes a device substrate with a voltage reference plane, a first input lead coupled to the device substrate, a first output lead coupled to the device substrate, a first transistor die coupled to a top surface of the device substrate with a solder bond, a second die coupled to the top surface of the device substrate with a conductive epoxy that electrically couples at least one component of the second die to the voltage reference plane, and non-conductive molding compound over the top surface of the device substrate and encompassing the first transistor die, the second die, a portion of the first input lead, and a portion of the first output lead. | 2016-03-24 |
20160087587 | DUAL STAGE LOW NOISE AMPLIFIER FOR MULTIBAND RECEIVER - A dual stage LNA for use in multiband receivers is disclosed. In an exemplary embodiment, an apparatus includes a plurality of first stage amplifiers having a plurality of first stage output ports, respectively, to output first stage amplified voltage mode signals. The apparatus also includes a plurality of second stage amplifiers having a plurality of second stage input ports, respectively, and second stage output ports to output amplified current mode signals. The apparatus also includes a switch apparatus having input terminals connected to the first stage output ports and output terminals connected to the second stage input ports, the switch apparatus to connect selected second stage input ports to selected first stage output ports. | 2016-03-24 |
20160087588 | PACKAGED RF AMPLIFIER DEVICES WITH GROUNDED ISOLATION STRUCTURES AND METHODS OF MANUFACTURE THEREOF - An embodiment of a packaged RF amplifier device includes a device substrate, a transistor die coupled to the device substrate, and an isolation structure coupled to the transistor die. The transistor die has a top die surface, a bottom die surface, a semiconductor substrate, first and second transistors formed in the semiconductor substrate, a conductive structure at the top die surface and positioned between the first and second transistors, and a low resistance path that extends vertically through the semiconductor substrate between the conductive structure and the bottom die surface. The isolation structure is coupled to the conductive structure and extends into an area above the top die surface between the first and second transistors. The isolation structure may be a wirebond fence, a conductive wall, conductive pillars or vias, or a plated trench that extends vertically upward from the conductive structure. The device may be encapsulated with molding compound. | 2016-03-24 |
20160087589 | AMPLIFIER WITH BASE CURRENT REUSE - An RF amplifier module that has a plurality of amplifiers wherein at least one of the amplifiers is powered via an envelope tracking module. The biasing input of at least one of the amplifiers is provided to the first amplifier to power the first amplifier to reduce power consumption. The first amplifier may also be powered via fixed biasing to provide greater stability of the module. | 2016-03-24 |
20160087590 | Tunable Envelope Tracking - A novel method to provide power management to a radio frequency amplifier is described. The method makes use of a DC-AC resonant switching power converter, a resonant tunable network and a rectifier to track the envelope signal of a radio amplifier system. This system provides a fast, efficient and clean supply to the radio frequency amplifier. The resonant power converter may be implemented with a class E inverter. The resonant power converter may be operated efficiently by switching at zero voltage switching or zero current switching. By operating the resonant switching power converter at the same frequency of the radio frequency amplifier, the spectrum of the power converter is immune from undesired harmonics while meeting the bandwidth requirement. By adaptively tuning the tunable resonant network, the output voltage of the rectifier is controlled to track the envelope signal. | 2016-03-24 |
20160087591 | METHODS AND SYSTEMS FOR EFFICIENT AND ADAPTIVE OPERATION OF CONTINUOUS-WAVE AMPLIFIERS - Disclosed herein are methods and systems for efficient and adaptive operation of continuous-wave amplifiers. One embodiment takes the form of a method that includes adjusting an RF input power of an amplifier until an RF output power of the amplifier reaches a first target level. The method also includes adjusting a supply power of the amplifier until a power-added efficiency of the amplifier reaches a second target level. | 2016-03-24 |
20160087592 | SINGLE-END AMPLIFIER AND NOISE CANCELLING METHOD THEREOF - A single-end amplifier includes: a noise cancelling circuit, coupled to a power supply, configured to receive a power signal and to cancel a part of ripples and noises in the power signal to generate an initial signal; an amplifying circuit, configure to receive the initial signal at a first end of the amplifying signal, and to amplify the initial signal to generate a first signal at a second end; and a first transmitting circuit, configured to receive the power signal and to generate a second signal at the second end of the amplifying circuit. The first signal and the second signal are superimposed and outputted to cancel most part of the ripples and noises in the power signal. The noise cancelling circuit includes a first capacitor and a first choke coil. | 2016-03-24 |
20160087593 | Scalable Periphery Tunable Matching Power Amplifier - A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes. | 2016-03-24 |
20160087594 | ELECTRONIC DEVICE FOR A RADIOFREQUENCY SIGNAL RECEPTION CHAIN, COMPRISING A LOW-NOISE TRANSIMPEDANCE AMPLIFIER STAGE - An electronic device includes a transimpedance amplifier stage having an amplifier end stage of the class AB type and a preamplifier stage coupled between an output of a frequency transposition stage and an input of the amplifier end stage. A self-biased common-mode control stage is configured to bias the preamplifier stage. The preamplifier stage is formed by a differential amplifier with an active load that is biased in response to the self-biased common-mode control stage. | 2016-03-24 |
20160087595 | MULTI-STAGE AMPLIFIER - In an embodiment, an amplifier includes first, second, and third stages, and a feedback network. The first stage has a first passband and is configured to generate a first output signal in response to first and second input signals, and the second stage has a second passband that is higher in frequency than the first passband and is configured to generate a second output signal in response to third and fourth input signals. The third stage has a first input node coupled to receive the first output signal, a second input node coupled to receive the second output signal, and an output node. And the feedback network is coupled between the second input node and the output node of the third stage. For example, where the first, second, and third stages are respective operational-transconductance-amplifier stages, such an amplifier may be suitable for low-power applications. | 2016-03-24 |
20160087596 | DIGITAL MICROPHONE WITH ADJUSTABLE GAIN CONTROL - Approaches are provided for an apparatus that includes an input buffer, an analog-to-digital converter coupled to the input buffer, a decompress module coupled to the analog to digital converter, and a gain control module coupled to the input buffer and the decompress module. The input buffer has a first adjustable gain and operating in the analog domain. The analog-to-digital converter converts the input analog data received from the input buffer into digital data. The decompress module operates in the digital domain, and is configured to decompress the digital data received from the analog-to-digital converter. The decompress module has a second adjustable gain and produces an output digital signal. The gain control module determines when to compensate for changes in characteristics the input analog data by selectively controlling the first gain of the input buffer in the analog domain and the second gain of the decompress module in the digital domain. | 2016-03-24 |
20160087597 | AUTOMATIC VOLUME CONTROL FOR LAND MOBILE RADIO - The present disclosure provides a radio and method for automatically adjusting, in response to ambient noise, the volume setting of a radio. The radio comprises a microphone for receiving ambient audio and generating a microphone signal; a codec for receiving the microphone signal and generating a processor signal representative of the ambient audio; and processor circuitry operable to receive the processor signal, determine an ambient audio level in response to the processor signal, and determine an adjusted radio volume to generate a radio volume control signal, wherein the adjusted radio volume is determined by calculating a difference between a baseline volume level and ambient audio level and adding a current volume level setting, wherein the codec is also operable to receive the radio volume control signal and generate an output signal to adjust the radio volume setting to maintain a net difference between the adjusted radio volume and ambient audio. | 2016-03-24 |
20160087598 | INPUT/OUTPUT SYSTEMS AND DEVICES FOR USE WITH SUPERCONDUCTING DEVICES - Systems and devices for providing differential input/output communication with a superconducting device are described. Each differential I/O communication is electrically filtered using a respective tubular filter structure incorporating superconducting lumped element devices and high frequency dissipation by metal powder epoxy. A plurality of such tubular filter structures is arranged in a cryogenic, multi-tiered assembly further including structural/thermalization supports and a device sample holder assembly for securing a device sample, for example a superconducting quantum processor. The interface between the cryogenic tubular filter assembly and room temperature electronics is achieved using hermetically sealed vacuum feed-through structures designed to receive flexible printed circuit board cable. | 2016-03-24 |
20160087599 | SUPERCONDUCTING PHASE-SHIFT SYSTEM - One example includes a superconducting phase-shift system. The system includes an all-pass filter comprising at least one variable inductance element. The all-pass filter can be configured to receive an input signal and to provide the input signal as an output signal that is phase-shifted relative to the input signal based on a variable inductance provided by each of the at least one variable inductance element. The system can further include a phase controller configured to provide a phase-control current to control the variable inductance of the at least one variable inductance element based on a characteristic of the phase-control current. | 2016-03-24 |
20160087600 | NANOMECHANICAL RESONATOR ARRAY AND PRODUCTION METHOD THEREOF - In the present invention, a nanomechanical resonator array ( | 2016-03-24 |
20160087601 | FULLY ELECTRONICALLY PROGRAMMABLE COMPLEX FILTER - The fully electronically programmable complex filter employs a network of current amplifiers (CAs), each CA having differential pairs biased with different tail currents, the outputs being programmed by adjusting these tail currents. Each CA has an RC circuit at its input including a resistor R and a capacitor C, and a feedback path connecting one of its outputs to the RC circuit, thereby offering independent programmability of center frequency, pole frequency, and programmable gain. Optimal gain parameters set the electronically programmable pole frequency, gain and center frequency to accommodate Integrated Services Digital Broadcasting-Terrestrial (ISDB-T) and Terrestrial Digital Multimedia Broadcasting (T-DMB). | 2016-03-24 |
20160087602 | ADAPTIVE FEEDBACK FOR POWER DISTRIBUTION NETWORK IMPEDANCE BARRIER SUPPRESSION - An adaptive feedback circuit may include: a filter having a first terminal coupled to a first power supply line and a second terminal coupled to a second power supply line, the filter configured to output a high-frequency signal that is transmitted between the first and second power supply lines; an amplifier configured to receive the high-frequency signal output from the filter and generate an amplified high-frequency signal at an output of the amplifier; and a capacitor having a first terminal coupled to the first power supply line and a second terminal coupled to the output of the amplifier. The capacitor is configured to receive the amplified high-frequency signal, and the amplified high-frequency signal generated by the amplifier controls a voltage applied between the first terminal and the second terminal of the capacitor. | 2016-03-24 |
20160087603 | SIGNAL SEGMENTATION AND ANALYSIS - The present invention provides a system and method for representing quasi-periodic (“qp”) waveforms comprising, representing a plurality of limited decompositions of the qp waveform, wherein each decomposition includes a first and second amplitude value and at least one time value. In some embodiments, each of the decompositions is phase adjusted such that the arithmetic sum of the plurality of limited decompositions reconstructs the qp waveform. These decompositions are stored into a data structure having a plurality of attributes. Optionally, these attributes are used to reconstruct the qp waveform, or patterns or features of the qp wave can be determined by using various pattern-recognition techniques. Some embodiments provide a system that uses software, embedded hardware or firmware to carry out the above-described method. Some embodiments use a computer-readable medium to store the data structure and/or instructions to execute the method. | 2016-03-24 |
20160087604 | DIGITAL COMPENSATION FOR A NON-LINEAR ANALOG RECEIVER - Aspects and embodiments are directed to non-linear systems including a digital compensator structure, a method of digital compensation, and methods for designing digital compensator structures for analog receivers. A digital compensator is configured to substantially reduce the one or more nonlinear distortion components in the sampled digital output signal from the analog receiver to provide an output signal achieving a receiver linearity requirement for the combination of the analog receiver and a digital compensator. | 2016-03-24 |
20160087605 | ADAPTIVE CONTINUOUS-TIME FILTER ADJUSTMENT DEVICE - A device includes a controller and an adaptive continuous-time filter that includes a control input and a first array of elements. The controller generates a digital word responsive to a time constant and compares a select bit of the digital word to a corresponding reference word to generate a control bit. The controller includes a duplicate array of elements, and applies the control bit to an adjustable element of the duplicate array of elements to modify the time constant. The controller provides the output word to the control input of the adaptive continuous-time filter to generate a filter response that accounts for effects of semiconductor process variation in the first array of elements. | 2016-03-24 |
20160087606 | Packaged MEMS Device and Method of Calibrating a Packaged MEMS Device - A packaged MEMS device and a method of calibrating a packaged MEMS device are disclosed. In one embodiment a packaged MEMS device comprises a carrier, a MEMS device disposed on the substrate, a signal processing device disposed on the carrier, a validation circuit disposed on the carrier; and an encapsulation disposed on the carrier, wherein the encapsulation encapsulates the MEMS device, the signal processing device and the memory element. | 2016-03-24 |
20160087607 | Bias Circuit for Comparators - Pumping current into a regeneration latch of a comparator, including: a first transistor configured to receive a first constant current from a first constant current source; a first current mirror coupled to the first transistor and configured to provide a first bias current, wherein the first transistor substantially mirrors the first constant current into the first bias current in the first current mirror; a second transistor configured to receive a second constant current from a second constant current source; a second current mirror coupled to the second transistor and configured to provide a second bias current, wherein the second transistor substantially mirrors the second constant current into the second bias current in the second current mirror; and a third transistor configured to combine the first bias current and the second bias current, wherein the third transistor pumps the combined bias current into the regeneration latch. | 2016-03-24 |
20160087608 | POWER MANAGERS FOR AN INTEGRATED CIRCUIT - Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands where power consumption is independently controlled within each of the power islands. A power manager determines a target power level for one of the power islands. The power manager then determines an action to change a consumption power level of the one of the power islands to the target power level. The power manager performs the action to change the consumption power level of the one of the power islands to the target power level. | 2016-03-24 |
20160087609 | APPARATUS AND METHOD FOR OBTAINING POWER VOLTAGE FROM CONTROL SIGNALS - An power voltage generating unit for a radio frequency switch includes a first input and a second input respectively configured to receive a first control signal and a second control signal, wherein the first control signal and the second control signal are configured to control which one of a plurality of paths in the radio frequency switch is enabled, and at least one output, configured to output an auxiliary voltage, derived from at least one of the first control signal or the second control signal, that is used to operate the radio frequency switch. The power voltage may be a voltage used to power an inverting circuit used to enable a selected branch as an isolation branch or shunt branch. | 2016-03-24 |
20160087610 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first sampling circuit for outputting a data value and an edge value corresponding to odd-numbered data of data contained in an input signal, using multiphase sampling clocks including a plurality of sampling clocks having different phases by 90 degrees; and a second sampling circuit for outputting a data value and an edge value corresponding to even-numbered data of data contained in the input signal, using the multiphase sampling clocks. One piece of data is sampled in one sampling period, and two sampling periods are included in one cycle of the sampling clock, the first sampling circuit and the second sampling circuit each including a first data sampling circuit which adds a negative offset to a signal level of the input signal, samples the input signal, and outputs a first data value. | 2016-03-24 |
20160087611 | FAULT RESISTANT FLIP-FLOP - A flip-flop ( | 2016-03-24 |
20160087612 | SEMICONDUCTOR DEVICE - If an exclusive OR circuit itself, a component of a signal delay detecting circuit, has failed to operate properly, a signal delay cannot be detected accurately. A malfunction pre-detecting circuit | 2016-03-24 |
20160087613 | Fast Voltage Level Shifter Circuit - A voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a field-effect transistor (FET) switch with a gate attached to the input terminal, a drain attached to the output terminal and a source attached to a current changing mechanism. The current changing mechanism includes a current mirror circuit having an output connected between the source and an electrical earth. The output of the current mirror circuit is preferably adapted to change a current flowing between the drain and the source based on an input voltage applied to the gate. | 2016-03-24 |
20160087614 | SYSTEM FOR GENERATING AN ANALOGUE SIGNAL - The system has: a set of at least two electric current generators, at least one capacitor and activation/deactivation devices for the electric current generators; the electric current generator being connected in parallel with one another and the capacitor being connected in series with the electric current generators, the activation/deactivation devices controlling the generators by a digital stream allowing control of the intensity of the electric current entering the capacitor and generating a trapezoidal voltage signal at the terminals of the capacitor, the analog signal being reconstructed through interpolation of the trapezoidal signal. | 2016-03-24 |
20160087615 | Debounce Circuit with Dynamic Time Base Adjustment for a Digital System - A debounce circuit eliminates noise, glitches, or transient signal variations resulting from mechanical bounce occurring at a change of state of analog signals and provides a dynamic debounce period alteration and time base variation without loss of the current debounce state. The debounce circuit has a physical counter that is configured for being adjusted within a virtual counter such that the noise, glitches, or transient signal variations resulting from mechanical bounce occurring at an initiation of a change of state of an analog input signal from a source device are filtered by delaying a change of output state of the debounce circuit. The debounce circuit includes a strobe generator that produces a strobe signal that is a submultiple of a master clock that is determined by the location of the physical counter within the virtual counter that is used to increment the physical counter within the virtual counter. | 2016-03-24 |
20160087616 | PHASE CONTROL CIRCUIT AND RECEIVING DEVICE - A phase control circuit includes: a phase interpolation circuit including a first transistor connected between a power source and an output terminal, and configured to output an output signal from the output terminal by combining input signals having different phases with each other based on a ratio of input bias currents; a bias circuit configured to control an ON-resistance of the first transistor by adjusting a gate voltage of the first transistor based on a total amount of the input bias currents, and to maintain an output common voltage of the phase interpolation circuit regardless of the total amount; and a current controller configured to control a through rate of the output signal with respect to the input signals by adjusting the total amount. | 2016-03-24 |
20160087617 | SEMICONDUCTOR INTEGRATED CIRCUIT, APPARATUS INCLUDING SEMICONDUCTOR INTEGRATED CIRCUIT, AND METHOD FOR CONTROLLING CLOCK SIGNAL IN SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a first generation unit configured to generate a fixed frequency division clock signal (first signal) from an output clock signal of a clock source, a fixed frequency division state monitoring unit configured to monitor the first signal, a second generation unit configured to generate a variable frequency division clock signal (second signal) from the output signal, and a variable frequency division state monitoring unit configured to monitor the second signal. In a case where the frequency of the second signal is returned from a reduced frequency to normal, when the variable frequency division state monitoring unit determines that the second signal becomes high in a next cycle, output of the second signal is stopped, and when the fixed frequency division state monitoring unit determines, after the output is stopped, that the first signal becomes high in a next cycle, the output is resumed. | 2016-03-24 |
20160087618 | SEMICONDUCTOR INTEGRATED CIRCUIT, APPARATUS WITH SEMICONDUCTOR INTEGRATED CIRCUIT, AND CLOCK CONTROL METHOD IN SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes, a fixed frequency-division clock generation unit configured to generate a fixed frequency-division clock with a fixed frequency based on an output clock of a clock source, a variable frequency-division clock generation unit configured to generate a variable frequency-division clock with a variable frequency based on the output clock of the clock source, and a data path selection unit configured to select a data path. The data path selection unit selects a data path with or without a synchronization unit for converting the data into clock-synchronous data on a receiving side according to whether the variable frequency-division clock is or is not, respectively, generated by the variable frequency-division clock generation unit. | 2016-03-24 |
20160087619 | Zero-Crossing Voltage Detection Circuit and Method Thereof - A zero-crossing voltage detection circuit for detecting a phase voltage of a converter includes a comparator, a first transistor and a second transistor. The first transistor has a first base, a first collector and a first emitter. The first base couples with the first collector. The first emitter receives the phase voltage. The first collector provides a first voltage to a first terminal of the comparator. The second transistor has a second base, a second collector and a second emitter. The second base couples with the first base. The second base couples with the second collector. The second emitter receives a ground voltage. The second collector provides a second voltage to a second terminal of the comparator. The comparator compares the first voltage with the second voltage to generate a zero-crossing voltage signal. | 2016-03-24 |
20160087620 | APPARATUS FOR MANAGING CLOCK DUTY CYCLE CORRECTION (DCC) - Embodiments of the present invention disclose an apparatus for managing clock duty cycle. The apparatus comprises a Duty Cycle Control Circuit (DCCC) for receiving at least an input clock signal and generating an output clock signal with adjustable duty cycle, a first Low-Pass Filter with Pull-Up Resistor (LPFPR) for receiving the output clock signal with adjustable duty cycle and simultaneously averaging and raising the common mode of the output thereof, a frequency divider for generating a signal with a 50% duty cycle, a second LPFPR for receiving the generated signal with 50% duty cycle and simultaneously averaging and raising the common mode of the output thereof and an OPAMP for receiving the outputs of the first and second LPFPRs for generating an equivalent reference signal to be fed to the DCCC as a control input, thereby facilitating correction of the duty cycle of the input clock signal. | 2016-03-24 |
20160087621 | INTEGRATED MAGNETIC FIELD SENSOR-CONTROLLED SWITCH DEVICES - Embodiments relate to integrated magnetic field sensor-controlled switch devices, such as transistors, current sources, and power switches, among others. In an embodiment, a magnetic switch and a load switch are integrated in a single integrated circuit device. In embodiments, the device can also include integrated load protection and load diagnostics. Embodiments can provide load switching and optional simultaneous logic signaling, for example to update a microcontroller or electronic control unit (ECU), while reducing space and complexity and thereby cost. | 2016-03-24 |
20160087622 | SEMICONDUCTOR DEVICE - The semiconductor device according to one embodiment includes a power transistor and a sense transistor connected in parallel with each other, a first operational amplifier having a non-inverting input terminal connected to an emitter of the sense transistor and an inverting input terminal connected to an emitter of the power transistor, a resistor element having one end connected to the emitter of the sense transistor and another end connected to a first node, and an adjustment transistor placed between the first node and a low-voltage power supply. The first operational amplifier adjusts a current flowing through the adjustment transistor so that an emitter voltage of the power transistor and an emitter voltage of the sense transistor are substantially the same. | 2016-03-24 |
20160087623 | GATE DRIVER - In a gate driver for driving a first transistor, the gate driver includes first, second and third push-pull circuits, in each of the push-pull circuits, two transistors are connected in series, an output terminal of the first push-pull circuit is connected to the gate of the first transistor, an output terminal of the second push-pull circuit is connected to the gate of a second transistor included in the first push-pull circuit and an output terminal of the third push-pull circuit is connected to the gate of a third transistor included in the first push-pull circuit. | 2016-03-24 |
20160087624 | HIGH FREQUENCY SWITCH CIRCUIT - A high frequency switch circuit including a first terminal, a second terminal, a bias terminal, n (n is an integer more than one) number of transistors connected in series in an order from a first transistor to an nth transistor from said first terminal to said second terminal, first to nth nodes respectively connected to back gates of said first to nth transistors, and n number of resistance elements connected in series in an order from a first resistance element to an nth resistance element from said bias terminal to said nth node, wherein said first resistance element is connected between said bias terminal and said first node, and a kth resistance element (k=2 to n) is connected between said (k−1)th node and said kth node. | 2016-03-24 |
20160087625 | GATE CONTROL DEVICE, SEMICONDUCTOR DEVICE, AND METHOD FOR CONTROLLING SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiments controls a gate voltage to be applied to a gate electrode of a junction field effect transistor including a source electrode, a drain electrode, and the gate electrode, the transistor having a first threshold voltage at which the transistor is turned on, and a second threshold at which conductivity modulation occurs in the transistor so as to make the gate voltage equal to or higher than the second threshold voltage when a forward current in a direction from the drain electrode toward the source electrode flows, and so as to make the time variation in gate voltage have a point from which the rate of the time variation starts decreasing at a voltage between the second threshold voltage and the first threshold voltage when the forward current to be shut down. | 2016-03-24 |
20160087626 | POWER CONTROL CIRCUIT - A power control circuit according to one embodiment includes an H-bridge circuit formed using a plurality of power transistors. The power transistors are respectively connected to current measurement circuits that measure currents flowing through the power transistors. Each of the power transistors includes a main emitter and a sense emitter through which a current corresponding to a current flowing through the main emitter flows. Each of the current measurement circuits measures a current flowing through each of the power transistors by using a current flowing through the sense emitter included in the power transistor. A control circuit controls the power transistors based on current values respectively measured by the current measurement circuits. | 2016-03-24 |
20160087627 | Output Buffer, and Source Driver and Display Device Including the Same - Disclosed is an output buffer. The output buffer includes a first amplifier configured to amplify an input signal, and output first to fourth amplified signals according to results of the amplification, a first transistor to receive the first amplified signal, a second transistor to receive the second amplified signal, a third transistor to receive the third amplified signal, a fourth transistor to receive the fourth amplified signal, a first node, connected to drains of the first and second transistors, a second node, connected to drains of the third and fourth transistors, an output node connected to the first and second nodes, and a first controller configured to selectively supply a control voltage to the gates of the first to fourth transistors in response to a control signal. | 2016-03-24 |
20160087628 | Device and Method for Micro-Electro-Mechanical-System Photonic Switch - In one embodiment, a method includes reflecting, by a first mirror of a first mirror array of a micro-electro-mechanical system (MEMS) photonic switch, an optical control beam to produce an optical control beam spot on a second mirror array of the MEMS photonic switch and cyclic dithering of the first mirror to effective enlargement of a size of the optical control beam spot. The method also includes detecting, by a first photodiode having a first location on the second mirror array, a first intensity of the optical control beam spot. | 2016-03-24 |
20160087629 | CONTACT SENSING DEVICE - A contact sensing device includes: a first electrode and a second electrode facing each other, a drive detection circuit of an electrostatic capacitance type, a first switching circuit that implements switching between connection and disconnection between the first electrode and ground, and a second switching circuit that implements switching between connection and disconnection between the first electrode and the second electrode. The drive detection circuit implements switching between a first state and a second state and detects an electrostatic capacitance change in the first state and an electrostatic capacitance change in the second state. | 2016-03-24 |
20160087630 | STORAGE CONTROLLERS, METHODS OF OPERATING THE SAME AND SOLID STATE DISKS INCLUDING THE SAME - A storage controller includes a first on-die termination (ODT) circuit, a second ODT circuit and an ODT control circuit. The first ODT circuit provides a first termination resistance with a strobe signal line transferring a data strobe signal. The second ODT circuit provides a second termination resistance with at least one data line transferring data. The ODT control circuit individually controls activation and deactivation of the first ODT circuit and the second ODT circuit. | 2016-03-24 |
20160087631 | MAGNETIC LOGIC DEVICE, MAGNETIC LOGIC CIRCUIT, AND MAGNETIC MEMORY - One embodiment provides a magnetic logic device including: a first conductive thin wire; a second conductive thin wire; and a third conductive thin wire that electrically connects the first conductive thin wire and the second conductive thin wire. The first to third conductive thin wires commonly includes: a first non-magnetic metal layer; a second non-magnetic metal layer; and a magnetic metal layer sandwiched between the first non-magnetic metal layer and the second non-magnetic metal layer. | 2016-03-24 |
20160087632 | CURRENT AMPLIFIER AND TRANSMITTER USING THE SAME - A current amplifier and a transmitter using the same. The current amplifier has a first and second transistor and a voltage level shifting unit. The first transistor has a gate receiving an input current and a drain receiving a driving current. The voltage level shifting unit providing a voltage shift is coupled between the drain of the first transistor and the gate of the second transistor. An output current is generated at the drain of the second transistor. | 2016-03-24 |
20160087633 | DIFFERENTIAL DRIVER WITH PULL UP AND PULL DOWN BOOSTERS - A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground. | 2016-03-24 |
20160087634 | RECONFIGURABLE LOGIC GATES USING CHAOTIC DYNAMICS - The present invention provides apparatuses and methods for chaos computing. For example, a chaos-based logic block comprises an encoding circuit block, at least one chaotic circuit block, a bias voltage generating circuit block, and a threshold circuit block. The encoding circuit block converts a plurality of digital inputs to an analog output. The plurality of digital inputs may comprise at least one data input and at least one control input. At least one chaotic circuit block is configured to iterate converting an input signal to an output signal by feeding the output signal to at least one chaotic circuit as the input signal at each iteration. The bias voltage generating circuit block converts a plurality of binary control inputs to a bias voltage. The threshold circuit block compares the output signal with a predetermined threshold, thereby generating a digital signal. | 2016-03-24 |
20160087635 | Operational Time Extension - Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time. Some embodiments provide a method of designing a reconfigurable IC that has several reconfigurable circuits, each having several configurations and operating in several reconfiguration cycles. The method identifies a signal path through the IC that does not meet a timing constraint. The signal path includes several circuits, one of which is a particular reconfigurable circuit. The method then maintains a configuration of the particular reconfigurable circuit constant over at least two contiguous reconfiguration cycles in order to reduce signal delay through the signal path and thereby satisfy the timing constraint. | 2016-03-24 |
20160087636 | CLOCK GENERATING APPARATUS AND FRACTIONAL FREQUENCY DIVIDER THEREOF - A clock generating apparatus and a fractional frequency divider thereof are provided. The fractional frequency divider includes a frequency divider (FD), a plurality of samplers, a selector and a control circuit. An input terminal of the FD is coupled to an output terminal of a multi-phase-frequency generating circuit. Input terminals of the samplers are coupled to an output terminal of the FD. Trigger terminals of the samplers receive the sampling clock signals. The input terminals of the selector are coupled to output terminals of the samplers. An output terminal of the selector is coupled to a feedback terminal of the multi-phase-frequency generating circuit. The control circuit provides a fraction code to a control terminal of the selector, so as to control the selector for selectively coupling the output terminal of one of the samplers to the feedback terminal of the multi-phase-frequency generating circuit. | 2016-03-24 |
20160087637 | DEVICE AND METHOD FOR ADJUSTING AN OSCILLATION FREQUENCY OF A VCTCXO OSCILLATOR | 2016-03-24 |
20160087638 | MULTI-CHANNEL DELAY LOCKED LOOP - A multi-channel delay locked loop includes a global delay locked loop and a plurality of local delay locked loops. The global delay locked loop is configured to lock an input clock signal and output a global delay control signal corresponding to a delay amount of the input clock signal during a locking operation. Each of the plurality of local delay locked loops is configured to output a channel clock signal by locking the input clock signal, and initialize the delay amount of the input clock signal according to the global delay control signal. | 2016-03-24 |
20160087639 | PHASE TRACKER FOR A PHASE LOCKED LOOP - A phase locked loop includes a feedforward path receiving a reference signal having a reference frequency and outputting an output signal having an output frequency that is a function of the reference signal and a feedback signal. The phase locked loop further includes a feedback path having a divider circuit associated therewith that is configured to receive the output signal and generate the feedback signal having a reduced frequency based on a divide value of the divider circuit. The feedback signal is supplied to the feedforward path. The phase locked loop also includes a modulator circuit configured to receive modulation data and provide a divider control signal to the divider circuit to control the divide value thereof, and a phase tracker circuit configured to determine an amount of phase drift from an initial phase value of the output signal due to an interruption in a locked state of the phase locked loop. | 2016-03-24 |
20160087640 | PLL-VCO BASED INTEGRATED CIRCUIT AGING MONITOR - A PLL-VCO based integrated circuit aging monitor, including: a control circuit, a monitoring circuit, and an output circuit. The monitoring circuit includes a reference circuit, an aging generation circuit, and a comparison circuit. The reference circuit is a PLL circuit insensitive to a parameter error caused by the aging of circuit. The aging generation circuit is a VCO circuit sensitive to the parameter error. The control circuit is connected to the PLL circuit, the VCO circuit, the comparison circuit, and the output circuit. The output end of the PLL circuit is connected to a first input end of the comparison circuit, and the output end of the VCO circuit is connected to a second input end of the comparison circuit. The output end of the comparison circuit is connected to the input end of the output circuit. The input end of the PLL circuit inputs a reference clock signal. | 2016-03-24 |
20160087641 | DIGITAL PHASE-LOCKED LOOP SUPPLY VOLTAGE CONTROL - Some embodiments include apparatuses and methods having a digitally controlled oscillator (DCO) in a digital phase-locked loop (PLL) and a control loop. The DCO can generate an output signal having a frequency based on a value of a digital information. The control loop can adjust a value of a supply voltage of the DCO based on the value the digital information. Additional apparatuses and methods are described. | 2016-03-24 |
20160087642 | DITHER-LESS ERROR FEEDBACK FRACTIONAL-N FREQUENCY SYNTHESIZER SYSTEMS AND METHODS - A fractional-N divider of a frequency synthesizer is driven by a dither-less error feedback modulator to alleviate fractional spurious tones introduced by the cyclic train of division ratios from delta-sigma modulators. A first feedback loop generates the feedback signal. A second feedback loop disrupts fractional spurious tones and a third feedback loop provides approximately zero static error. | 2016-03-24 |
20160087643 | ANALOG-TO-DIGITAL CONVERTER AND SEMICONDUCTOR INTEGRATED CIRCUIT - A time-interleaved analog-to-digital converter that samples an analog input signal at a sampling frequency and converts the analog input signal into a digital output signal is enabled to perform correction processing on an error by: converting the analog input signal into the digital output signal by a plurality of analog-to-digital conversion circuits in a time-interleaved manner; and performing gain correction processing and skew correction processing with respect to the analog-to-digital conversion circuit, on the basis of a mixed signal, the mixed signal being obtained by mixing an output signal from the analog-to-digital conversion circuit with a signal made by shifting a phase of the output signal by π/2. | 2016-03-24 |
20160087644 | Asynchronous Low-Power Analog-to-Digital Converter Circuit With Configurable Thresholds - An analog-to-digital converter circuit is described that includes register space to keep one or more values to establish upper and lower thresholds of the analog-to-digital converter. The analog-to-digital converter circuit also includes first and second comparators to compare an analog input signal against the upper and lower thresholds and to trigger an analog-to-digital conversion process in response to the analog input signal crossing one of the thresholds. The analog-to-digital converter circuit also includes first logic circuitry to discard a result of the analog-to-digital conversion process if the result is within a prior analog-to-digital conversion process's thresholds. The analog-to-digital converter circuit also includes second logic circuitry to provide the result as an output and generate an interrupt if the result is not within the prior analog-to-digital conversion process's thresholds. | 2016-03-24 |
20160087645 | Apparatus and Method for Digital to Analog Conversion with Current Mirror Amplification - A DAC using current mirrors suitable for use in a modulator. Embodiments include a current-generating circuit to provide an information signal; a bias current source; a current mirror having a mirror input transistor connected to the current generating circuit and the bias current source, and being driven by the bias current and the varying current signal and having a corresponding varying voltage signal at a control terminal; a signal shaping filter interposed between the mirror input transistor and an output mirror transistor configured to limit a bandwidth of the varying voltage signal; the output mirror transistor configured to generate a band-limited varying current signal and a mirrored bias current; and, a mirrored bias current reduction circuit connected to the output mirror transistor configured to reduce the mirrored bias current. | 2016-03-24 |
20160087646 | APPARATUS AND METHOD FOR MAPPING BINARY TO TERNARY AND ITS REVERSE - Described is an apparatus for converting binary data to ternary and back such that the apparatus comprises: a first look-up table (LUT) having a mapping of 19 binary bits to 12 ternary trits; and a first logic to receive a binary input and to convert the binary input to a ternary output according to the first LUT. | 2016-03-24 |
20160087647 | Data Compression Using Entropy Encoding - Data values can be entropy encoded, as part of a data compression process, according to a predetermined variable-length entropy coding scheme (e.g. based on exponential Golomb coding) such that they have ≧1 prefix bits and ≧0 suffix bits. A corresponding entropy decoding process can be performed, whereby the prefix bits are analysed to determine bit-boundaries between the received entropy encoded data values. The suffix bits and the determined bit-boundaries are used to decode the entropy encoded data values. In this way, multiple bit-boundaries can be found during the same clock cycle, e.g. by analysing the prefix bits in parallel decode units, thereby allowing for multiple entropy encoded data values (encoded using a variable-length coding scheme) to be decoded in the same clock cycle. | 2016-03-24 |
20160087648 | Puncture-aware low density parity check (LDPC) decoding - A communication device or device includes a processor that generates and interprets signals that are transmitted and received via a communication interface. The processor receives an LDPC coded signal, via the communication interface, that is generated by puncturing at least one parity bit from another LDPC coded signal that is generated based on an LDPC code characterized by a first LDPC matrix. The processor operates on the first LDPC matrix to generate a second LDPC matrix by excluding at least one column and at least one row from the first LDPC matrix. The number of columns and rows excluded from the first LDPC matrix is based on the number of bits punctured from the other LDPC coded signal to generate the LDPC coded signal. The processor then decodes the LDPC coded signal using the second LDPC matrix to make estimates of information bits encoded within the LDPC coded signal. | 2016-03-24 |
20160087649 | Digital television broadcasting system using coded orthogonal frequency-division modulation with multilevel low-density-parity-check coding - In transmitter apparatus for a digital television broadcasting system, internet-protocol (IP) packets of digital television information are subjected to multilevel coding (MLC) before being Gray-mapped to quadrature-amplitude-modulation (QAM) constellations. The constituent codes of the MLC comprise respective low-density parity-check (LDPC) inner coding. Preferably, the LDPC inner coding is LDPC convolutional coding. The QAM constellations are used in coded orthogonal frequency-division modulation (COFDM) of plural carrier waves up-converted to a radio-frequency broadcast television channel. In receiver apparatus for the digital television broadcasting system the results of de-mapping QAM constellations recovered from demodulating the COFDM carrier waves are de-interleaved, and the LDPC constituent codes of the MLC are independently decoded in parallel with decoding results time-interleaved to recover the IP packets of digital television information. | 2016-03-24 |
20160087650 | BCH DECODING METHOD AND DECODER THEREOF - The present disclosure illustrates a BCH decoding method and a decoder thereof. In this BCH decoding method, the BCH decoder receives an encode data at first, then calculates a syndrome of the encode data. After calculating the syndrome of the encode data, the BCH decoder calculates at least one error location of the encode data in response to the syndrome. Next, the BCH decoder detects at least one determining bit which a first bit string of the encode data comprises. Finally, an error correction is then performed based upon the error location, such that the BCH decoder outputs decode data. | 2016-03-24 |
20160087651 | SYSTEM AND METHOD FOR DECODING VARIABLE LENGTH CODES - A method for decoding a variable length coded input including a plurality of binary code symbols into an output symbol includes: setting, by a decoder including a processor and memory storing a lookup table including a plurality of states, a current state to an initial state and a current branch length to an initial branch length; and identifying, by the decoder using the lookup table, a next state or a symbol of the output symbols based on a current state, a current branch length, and a next binary code symbol of the variable length coded input. | 2016-03-24 |
20160087652 | Apparatus and Method for Transmitting/Receiving Signal in Communication System Supporting Bit-Interleaved Coded Modulation with Iterative Decoding Scheme - The present disclosure relates to a pre-5 | 2016-03-24 |
20160087653 | Decoder With Targeted Symbol Flipping Recovery Of Miscorrected Codewords - An apparatus for decoding data includes a decoder circuit operable to apply a decoding algorithm to a decoder input to yield a codeword, a convergence detection circuit operable to determine whether parity checks are satisfied by the decoder input and to identify unsatisfied parity checks in the decoder circuit, and a symbol flipping controller operable to change values of at least one symbol in the decoder input based on information about the unsatisfied parity checks. The decoder circuit is restarted to process the decoder input with the changed values. The information about the unsatisfied parity checks is obtained at each of a number of local decoding iterations in the decoder circuit. | 2016-03-24 |
20160087654 | SLIDING WINDOW LIST DECODER FOR ERROR CORRECTING CODES - A system for hardware error-correcting code (ECC) detection or correction of a received codeword from an original codeword includes an error-detecting circuit configured to process a selection of symbols of the received codeword using a set of factors, the original codeword being recomputable from a corresponding said selection of symbols of the original codeword using the set of factors. The error-detecting circuit includes a hardware multiplier and accumulator configured to use the set of factors and the selection of symbols of the received codeword to recompute remaining symbols of the original codeword, and a hardware comparator configured to compare the recomputed remaining symbols of the original codeword with corresponding said remaining symbols of the received codeword and to output first results of this comparison. | 2016-03-24 |
20160087655 | METHOD AND APPARATUS FOR CONTROLLING ANTENNAS IN VEHICLE COMMUNICATION SYSTEM - A method for controlling antennas in a vehicle having an external antenna and an internal antenna includes triggering an eCall service function upon sensing an accident occurrence event, measuring a quality of one or more wireless signals received through the external antenna, comparing the measured quality of the wireless signals with a reference quality value, and selecting one of the external antenna and the internal antenna to be used in the eCall service function based on the results of the step of comparing the measured quality of the wireless signals with the reference quality value. A system of emergency communication of a vehicle is also provided. | 2016-03-24 |
20160087656 | TRANSMITTER AND METHOD OF PROCESSING TRANSMISSION SIGNALS - A transmitter and method are provided for processing a transmission signal. The transmitter includes an FEM that switches a plurality of band signals for a first and second communication scheme, wherein the band signals for the first communication scheme include a first HB signal, a second HB signal, a first LB signal, and a second LB signal, and the band signals for the second communication scheme include a third LB and a third HB signal; a first PAM including a first power amplifier that amplifies the third HB signal, a second power amplifier that amplifies the first HB signal, and a third power amplifier that amplifies the first LB signal; and a second PAM including a fourth power amplifier that amplifies the third LB signal, a fifth power amplifier that amplifies the second HB signal, and a sixth power amplifier that amplifies the second LB signal. | 2016-03-24 |
20160087657 | Adaptively Controlled Pre-Distortion Circuits for RF Power Amplifiers - A system includes a crest-factor reduction circuit, a signal analyzer, and a pre-distortion circuit. The crest-factor reduction circuit reduces a crest factor of a baseband signal and generates a feedforward signal. The signal analyzer generates parameters based on the feedforward signal and an output signal from a power amplifier. The pre-distortion circuit generates a pre-distorted baseband signal based on the parameters for input to the power amplifier. | 2016-03-24 |
20160087658 | NOISE CANCELER FOR USE IN A TRANSCEIVER - A noise canceler for use in a transceiver is disclosed. In an exemplary embodiment, an apparatus includes a split amplifier to output an amplified transmit signal, the split amplifier providing a first noise attenuation factor in a receive band. The apparatus also includes a transmit antenna to transmit the amplified transmit signal, the transmit antenna being isolated from a receive antenna by an antenna isolation factor that provides a second noise attenuation factor in the receive band. The apparatus also includes a noise canceler configured to subtract a detection signal from a received signal to obtain an adjusted received signal, wherein subtraction of the detection signal provides a third noise attenuation factor in the receive band, and wherein the first, second, and third noise attenuation factors combine to provide a selected amount of noise attenuation in the receive band. | 2016-03-24 |
20160087659 | METHODS, SYSTEMS, AND NON-TRANSITORY COMPUTER READABLE MEDIA FOR WIDEBAND FREQUENCY AND BANDWIDTH TUNABLE FILTERING - Methods, systems, and computer readable media for wideband frequency and bandwidth tunable filtering are disclosed. According to one aspect, the subject matter described herein includes a wideband frequency and bandwidth tunable filter that splits a filter input signal into first and second input signals, modifies the first input signal to produce a first output signal, modifies the second input signal to produce a second output signal having an intermediate frequency response, and combines the first and second output signals while adjusting their relative phases and/or amplitudes to produce a filter output signal with the target frequency response. Adjustment includes splitting the second input signal into third and fourth input signals, which are modified and then combined to produce the second output signal having the intermediate frequency response. | 2016-03-24 |
20160087660 | METHOD AND SYSTEM FOR EXTENDING DYNAMIC RANGE OF RECEIVER BY COMPENSATING FOR NON-LINEAR DISTORTION - A method is provided for extending dynamic range of a receiver. The method includes receiving a known input signal at the receiver, detecting a first output signal in response to the known input signal, and determining a correction function based on the first output signal and the known input signal for compensating for non-linear distortion introduced by the receiver. The method further includes receiving an unknown input signal at the receiver, detecting a second output signal in response to the unknown input signal, and applying the correction function to the second output signal in a time domain to recover the unknown input signal. | 2016-03-24 |
20160087661 | Radio Receiver - An AM/FM radio receiver includes an AM/FM demodulation circuit that is configured to demodulate a signal that is received; a mute circuit that is configured to perform, on the signal demodulated by the demodulation unit, a mute process with a characteristic corresponding to an electric field strength of the signal that is received; a volume balance optimizing circuit configured to control a volume level of the signal after the mute process to be constant when the volume level of the signal is within a predetermined range; and a low-input attenuation circuit configured to receive an input signal of which the volume level has been controlled by the volume balance optimizing circuit and to attenuate the input signal when the volume level is lower than a predetermined level. | 2016-03-24 |
20160087662 | SIGNAL PROCESSING DEVICE, SIGNAL PROCESSING METHOD, AND PROGRAM - In the signal processing device, which is capable of performing an FFT and performing a window function process as preprocessing before the FFT and achieves OFDM demodulation, the window function process is skipped to perform an FFT on a received signal if the frequency of narrow-band noise included in the received signal coincides with the subcarrier frequency of OFDM within a predetermined range. If the frequencies do not coincide with each other, the FFT is performed after the window function process is performed on the received signal. The signal processing device includes an NBN detection/determination section, which determines whether narrow-band noise is included in a subcarrier, and a window function determination section, which determines, in accordance with the degree of coincidence between the frequency of narrow-band noise and the frequency of a subcarrier, whether or not to perform the window function process. | 2016-03-24 |
20160087663 | WIRELESS COMMUNICATION DEVICE - A wireless communication device is provided. The wireless communication device includes a first wireless communication protocol transceiver, a second wireless communication protocol transceiver, a signal frequency splitter and a signal filter. The first wireless communication protocol transceiver accesses data with a first wireless communication protocol. The signal frequency splitter splits a receiving signal received by a second antenna and a transmitting signal transmitted by the second antenna according to a receiving frequency band and a transmitting frequency band of a second wireless communication protocol. The signal filter coupled to the signal frequency splitter and a receiving terminal of the second wireless communication protocol transceiver filters a signal in a receiving frequency band of the first wireless communication protocol and the receiving frequency band of the second wireless communication protocol. | 2016-03-24 |
20160087664 | ALTERNATE USER INTERFACES FOR MULTI TUNER RADIO DEVICE - A method, device, system, and media are directed to controlling a multi-tuner radio. A voice command may be received and/or filtered. An operation of the radio may be modified based on the voice command. A gesture input may be received through a gesture pad. Another operation of the multi-tuner radio may be modified based on the received gesture input. A fingerprint may be recognized with a gesture pad. A user may be authenticated based on the recognized fingerprint. The operation or the other operation may be personalized based on the fingerprint. User training may be provided for the gesture input. | 2016-03-24 |