12th week of 2022 patent applcation highlights part 65 |
Patent application number | Title | Published |
20220093503 | DUAL-TRACK BITLINE SCHEME FOR 6T SRAM CELLS | 2022-03-24 |
20220093504 | FOLDED CELL LAYOUT FOR 6T SRAM CELL | 2022-03-24 |
20220093505 | VIA CONNECTIONS FOR STAGGERED INTERCONNECT LINES | 2022-03-24 |
20220093506 | SEMICONDUCTOR STRUCTURE | 2022-03-24 |
20220093507 | STACKED CAPACITOR | 2022-03-24 |
20220093508 | VIA STRUCTURES OF PASSIVE SEMICONDUCTOR DEVICES | 2022-03-24 |
20220093509 | CONTACT WINDOW STRUCTURE, METAL PLUG AND FORMING METHOD THEREOF, AND SEMICONDUCTOR STRUCTURE | 2022-03-24 |
20220093510 | SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE CONTACT HAVING TAPERING PROFILE AND METHOD FOR PREPARING THE SAME | 2022-03-24 |
20220093511 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | 2022-03-24 |
20220093512 | SEMICONDUCTOR DEVICES WITH BACKSIDE POWER RAIL AND METHODS OF FABRICATION THEREOF | 2022-03-24 |
20220093513 | METHOD OF FORMING POWER GRID STRUCTURES | 2022-03-24 |
20220093514 | DEPOSITION OF GRAPHENE ON A DIELECTRIC SURFACE FOR NEXT GENERATION INTERCONNECTS | 2022-03-24 |
20220093515 | EMBEDDED MULTI-DIE INTERCONNECT BRIDGE HAVING A MOLDED REGION WITH THROUGH-MOLD VIAS | 2022-03-24 |
20220093516 | POWER DELIVERY FOR EMBEDDED BRIDGE DIE UTILIZING TRENCH STRUCTURES | 2022-03-24 |
20220093517 | DIRECT BONDING IN MICROELECTRONIC ASSEMBLIES | 2022-03-24 |
20220093518 | ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF | 2022-03-24 |
20220093519 | INTERPOSERS AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME | 2022-03-24 |
20220093520 | CONDUCTIVE ROUTE PATTERNING FOR ELECTRONIC SUBSTRATES | 2022-03-24 |
20220093521 | INTERCONNECTION STRUCTURE OF A SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE INTERCONNECTION STRUCTURE | 2022-03-24 |
20220093522 | PACKAGE INTEGRATION USING FANOUT CAVITY SUBSTRATE | 2022-03-24 |
20220093523 | MULTIPLE COMPONENT INTEGRATION IN FANOUT PACKAGE WITH DIFFERENT BACK SIDE METALLIZATION AND THICKNESSES | 2022-03-24 |
20220093524 | LOGIC DRIVE BASED ON MULTICHIP PACKAGE COMPRISING STANDARD COMMODITY FPGA IC CHIP WITH COOPERATING OR SUPPORTING CIRCUITS | 2022-03-24 |
20220093525 | THERMALLY-CONDUCTIVE ELECTROMAGNETIC INTERFERENCE (EMI) ABSORBERS | 2022-03-24 |
20220093526 | SEMICONDUCTOR PACKAGE WITH REDISTRIBUTION STRUCTURE AND MANUFACTURING METHOD THEREOF | 2022-03-24 |
20220093527 | INTEGRATED CIRCUIT CHIP, INTEGRATED CIRCUIT PACKAGE AND DISPLAY APPARATUS INCLUDING THE INTEGRATED CIRCUIT CHIP | 2022-03-24 |
20220093528 | PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME | 2022-03-24 |
20220093529 | Multitier Arrangements of Integrated Devices, and Methods of Protecting Memory Cells During Polishing | 2022-03-24 |
20220093530 | SELF-ERASABLE AND REWRITABLE OPTOEXCITONIC PLATFORM FOR ANTI-TAMPER HARDWARE | 2022-03-24 |
20220093531 | PACKAGE-INTEGRATED BISTABLE SWITCH FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION | 2022-03-24 |
20220093532 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF | 2022-03-24 |
20220093533 | METHOD FOR PREPARING SEMICONDUCTOR DEVICE STRUCTURE WITH AIR GAP STRUCTURE | 2022-03-24 |
20220093534 | ELECTRONIC SUBSTRATES HAVING EMBEDDED INDUCTORS | 2022-03-24 |
20220093535 | ELECTRONIC SUBSTRATES HAVING EMBEDDED INDUCTORS | 2022-03-24 |
20220093536 | MAGNETIC CORE INDUCTORS IN INTERPOSER | 2022-03-24 |
20220093537 | PLANAR MAGNETIC RADIAL INDUCTORS TO ENABLE VR DISAGGREGATION | 2022-03-24 |
20220093538 | ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF | 2022-03-24 |
20220093539 | FAN-OUT ANTENNA PACKAGING STRUCTURE AND PACKAGING METHOD | 2022-03-24 |
20220093540 | DRIVING BACKPLANE AND DISPLAY APPARATUS | 2022-03-24 |
20220093541 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH GRAPHENE LAYERS | 2022-03-24 |
20220093542 | SEMICONDUCTOR DEVICE | 2022-03-24 |
20220093543 | SEMICONDUCTOR PACKAGE | 2022-03-24 |
20220093544 | SEMICONDUCTOR DEVICE | 2022-03-24 |
20220093545 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH SLANTED CONDUCTIVE LAYERS | 2022-03-24 |
20220093546 | MICROELECTRONIC ASSEMBLIES WITH INDUCTORS IN DIRECT BONDING REGIONS | 2022-03-24 |
20220093547 | MICROELECTRONIC ASSEMBLIES WITH INDUCTORS IN DIRECT BONDING REGIONS | 2022-03-24 |
20220093548 | SEMICONDUCTOR PACKAGE | 2022-03-24 |
20220093549 | HYBRID BONDING STRUCTURES, SEMICONDUCTOR DEVICES HAVING THE SAME, AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES | 2022-03-24 |
20220093550 | METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE | 2022-03-24 |
20220093551 | ELECTRONIC DEVICE | 2022-03-24 |
20220093552 | SEMICONDUCTOR MODULE | 2022-03-24 |
20220093553 | JOINED STRUCTURE | 2022-03-24 |
20220093554 | SEMICONDUCTOR MODULE | 2022-03-24 |
20220093555 | BONDED ASSEMBLY INCLUDING INTERCONNECT-LEVEL BONDING PADS AND METHODS OF FORMING THE SAME | 2022-03-24 |
20220093556 | ASYMMETRIC DIE BONDING | 2022-03-24 |
20220093557 | CHIP-TRANSFERRING SYSTEM AND CHIP-TRANSFERRING METHOD | 2022-03-24 |
20220093558 | METHOD OF MANUFACTURING ELECTRONIC DEVICE | 2022-03-24 |
20220093559 | REDUCING KEEP-OUT-ZONE AREA FOR A SEMICONDUCTOR DEVICE | 2022-03-24 |
20220093560 | INTEGRATED CIRCUIT PACKAGES AND METHODS OF FORMING THE SAME | 2022-03-24 |
20220093561 | DIRECT BONDING IN MICROELECTRONIC ASSEMBLIES | 2022-03-24 |
20220093562 | SEMICONDUCTOR DEVICE | 2022-03-24 |
20220093563 | CHIP-ON-FILM STRUCTURE, DISPLAYING BASE PLATE AND DISPLAYING DEVICE | 2022-03-24 |
20220093564 | DIE STACK STRUCTURE AND MANUFACTURING METHOD THEREOF | 2022-03-24 |
20220093565 | STACKED DIE AND VR CHIPLET WITH DUAL-SIDED AND UNIDIRECTIONAL CURRENT FLOW | 2022-03-24 |
20220093566 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF | 2022-03-24 |
20220093567 | SEMICONDUCTOR PACKAGES | 2022-03-24 |
20220093568 | FILM IN SUBSTRATE FOR RELEASING Z STACK-UP CONSTRAINT | 2022-03-24 |
20220093569 | MONOLITHIC CHIP STACKING USING A DIE WITH DOUBLE-SIDED INTERCONNECT LAYERS | 2022-03-24 |
20220093570 | BALL GRID ARRAY SUBSTRATE | 2022-03-24 |
20220093571 | BACKSIDE CONTACT FOR THERMAL DISPLACEMENT IN A MULTI-WAFER STACKED INTEGRATED CIRCUIT | 2022-03-24 |
20220093572 | SEMICONDUCTOR DEVICE | 2022-03-24 |
20220093573 | SEMICONDUCTOR MODULE | 2022-03-24 |
20220093574 | LED Display Screen Layout Method | 2022-03-24 |
20220093575 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH ACTIVE INTERPOSER | 2022-03-24 |
20220093576 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES | 2022-03-24 |
20220093577 | LIGHT EMITTING ARRAY STRUCTURE AND DISPLAY | 2022-03-24 |
20220093578 | LIGHT EMITTING ARRAY STRUCTURE AND DISPLAY | 2022-03-24 |
20220093579 | MICRO LED DEVICE AND METHOD FOR MANUFACTURING SAME | 2022-03-24 |
20220093580 | FAN-OUT LED PACKAGING STRUCTURE AND METHOD | 2022-03-24 |
20220093581 | IC PACKAGE PROVIDING ISOLATED FILTER ON LEAD-FRAME | 2022-03-24 |
20220093582 | SEMICONDUCTOR PACKAGE | 2022-03-24 |
20220093583 | EPITAXIAL STRUCTURE OF GA-FACE GROUP III NITRIDE, ACTIVE DEVICE, AND GATE PROTECTION DEVICE THEREOF | 2022-03-24 |
20220093584 | RESISTOR AND RESISTOR-TRANSISTOR-LOGIC CIRCUIT WITH GAN STRUCTURE AND METHOD OF MANUFACTURING THE SAME | 2022-03-24 |
20220093585 | RC IGBT, Method of Producing an RC IGBT and Method of Controlling a Half Bridge Circuit | 2022-03-24 |
20220093586 | THREE-DIMENSIONAL INTEGRATED CIRCUITS (3DICS) INCLUDING BOTTOM GATE MOS TRANSISTORS WITH MONOCRYSTALLINE CHANNEL MATERIAL | 2022-03-24 |
20220093587 | INTEGRATED CIRCUIT LAYOUT AND METHOD THEREOF | 2022-03-24 |
20220093588 | ADJACENT GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING NON-MERGED EPITAXIAL SOURCE OR DRAIN REGIONS | 2022-03-24 |
20220093589 | FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ADJACENT ISLAND STRUCTURES | 2022-03-24 |
20220093590 | SELECTIVE GROWTH SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITHOUT FIN END GAP | 2022-03-24 |
20220093591 | SEMICONDUCTOR STRUCTURE WITH GATE-ALL-AROUND DEVICES AND STACKED FINFET DEVICES | 2022-03-24 |
20220093592 | FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING PRE-SPACER DEPOSITION CUT GATES | 2022-03-24 |
20220093593 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | 2022-03-24 |
20220093594 | FIELD-EFFECT TRANSISTORS (FET) CIRCUITS EMPLOYING TOPSIDE AND BACKSIDE CONTACTS FOR TOPSIDE AND BACKSIDE ROUTING OF FET POWER AND LOGIC SIGNALS, AND RELATED COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) CIRCUITS | 2022-03-24 |
20220093595 | SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME | 2022-03-24 |
20220093596 | FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING COMMON METAL GATES AND HAVING GATE DIELECTRICS WITH A DIPOLE LAYER | 2022-03-24 |
20220093597 | FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING MOLYBDENUM NITRIDE METAL GATES AND GATE DIELECTRICS WITH A DIPOLE LAYER | 2022-03-24 |
20220093598 | FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ADDITIVE METAL GATES | 2022-03-24 |
20220093599 | METHOD FOR MANUFACTURING FIN FIELD-EFFECT TRANSISTOR AND FIN FIELD-EFFECT TRANSISTOR STRUCTURE | 2022-03-24 |
20220093600 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE INCLUDING THE SEMICONDUCTOR DEVICE | 2022-03-24 |
20220093601 | MEMORY DEVICE | 2022-03-24 |
20220093602 | SEMICONDUCTOR DIE WITH DECOUPLING CAPACITOR AND MANUFACTURING METHOD THEREOF | 2022-03-24 |