13th week of 2015 patent applcation highlights part 67 |
Patent application number | Title | Published |
20150089116 | Merged TLB Structure For Multiple Sequential Address Translations - A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. | 2015-03-26 |
20150089117 | COMPUTER SYSTEM, MEMORY MANAGEMENT METHOD AND PROGRAM THEREOF - A computer system, having a non-volatile storage unit ( | 2015-03-26 |
20150089118 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR PARTITION AND CACHE RESTORE - Methods, systems, and computer readable media for partition and cache restore are disclosed. According to one aspect, a method for partition and cache restore includes, in a computing platform having a mass storage device and a non-volatile cache storage device that operates as a cache for the mass storage device: providing, in a first location within the mass storage device, a first image of data; providing, in a second location within the mass storage device, a second image of data; copying the first image of data from the first location within the mass storage device to a third location within the mass storage device; and copying the second image of data from the second location within the mass storage device into the non-volatile cache storage device. | 2015-03-26 |
20150089119 | COMMAND EXECUTION USING EXISTING ADDRESS INFORMATION - Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a plurality of solid-state non-volatile memory cells. A controller communicates a first command having address information and a first operation code. The first operation code identifies a first action to be taken by the memory module in relation to the address information. The controller subsequently communicates a second command having a second operation code without corresponding address information. The memory module takes a second action identified by the second command using the address information from the first command. | 2015-03-26 |
20150089120 | REFRESH OF DATA STORED IN A CROSS-POINT NON-VOLATILE MEMORY - Embodiments including systems, methods, and apparatuses associated with refreshing memory cells are disclosed herein. In embodiments, a memory controller may be configured to perform a read operation on one or more memory cells in a cross-point non-volatile memory such as a phase change memory (PCM). The one or more memory cells may have voltage values respectively set to a first threshold voltage or a second threshold voltage. Based on the read, the memory controller may identify the memory cells in the cross-point non-volatile memory that are set to the second threshold voltage, and refresh the voltage values of those cells without altering the voltage values of the memory cells in the cross-point non-volatile memory that are set to the first threshold voltage. Other embodiments may be described or claimed. | 2015-03-26 |
20150089121 | Managing A Cache On Storage Devices Supporting Compression - Flash memory on a flash memory device is virtualized using compression that is native to the flash memory device. Through compression, the flash memory device is used to logically store more data in a virtual address space that is larger than the physical address space of the flash memory device. Physical storage capacity of a flash memory device may prevent further storage of data even when the virtual address space is not fully populated. Because compressibility may vary, the extent to which the virtual address space may be populated before physical storage capacity is reached varies. The approaches for virtual memory described herein rely on the memory device client to monitor when this point is reached. In addition, the memory device client is responsible for freeing space as needed to accommodate subsequent requests to store data in the flash memory. | 2015-03-26 |
20150089122 | APPARATUS, CONTROL APPARATUS, CONTROL METHOD AND STORAGE MEDIUM - An apparatus, when a storage unit is initialized, writes dummy data to an area of the storage unit, and when actual data is written to the storage unit, releases the dummy data written in the area of the storage unit, and writes the actual data in the released area, and also when the actual data is deleted from the storage unit, writes dummy data to an area in which the actual data is written. | 2015-03-26 |
20150089123 | COMPUTER SYSTEM WITH PHYSICALLY-ADDRESSABLE SOLID STATE DISK (SSD) AND A METHOD OF ADDRESSING THE SAME - A storage system includes a Central Processing Unit (CPU) that has a physically-addressed solid state disk (SSD), addressable using physical addresses associated with user data and provided by a host. The user data is to be stored in or retrieved from the physically-addressed SSD in blocks. Further, a non-volatile memory module is coupled to the CPU and includes flash tables used to manage blocks in the physically addressed SSD. The flash tables have tables that are used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. The flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption. | 2015-03-26 |
20150089124 | DATA ACCESSING METHOD FOR FLASH MEMORY STORAGE DEVICE HAVING DATA PERTURBATION MODULE, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module. | 2015-03-26 |
20150089125 | FRAMEWORK FOR NUMA AFFINITIZED PARALLEL QUERY ON IN-MEMORY OBJECTS WITHIN THE RDBMS - Techniques are provided for performing parallel processing on in-memory objects within a database system. In one embodiment, a plurality of in-memory chunks are maintained on a plurality of non-uniform memory access (NUMA) nodes. In response to receiving a query, a set of clusters is determined for the plurality of in-memory chunks. Each respective cluster in the set of clusters corresponds to a particular NUMA node of the plurality of NUMA nodes and includes a set of one or more in-memory chunks from the plurality of in-memory chunks. For each respective cluster in the set of clusters, a query coordinator assigns, to the respective cluster, a set of one or more processes associated with the particular NUMA node that corresponds to the respective cluster. | 2015-03-26 |
20150089126 | Data Compression In Processor Caches - In an embodiment, a processor includes a cache data array including a plurality of physical ways, each physical way to store a baseline way and a victim way; a cache tag array including a plurality of tag groups, each tag group associated with a particular physical way and including a first tag associated with the baseline way stored in the particular physical way, and a second tag associated with the victim way stored in the particular physical way; and cache control logic to: select a first baseline way based on a replacement policy, select a first victim way based on an available capacity of a first physical way including the first victim way, and move a first data element from the first baseline way to the first victim way. Other embodiments are described and claimed. | 2015-03-26 |
20150089127 | MEMORY BROADCAST COMMAND - Apparatus, systems, and methods to broadcast a memory command are described. In one embodiment, a memory controller comprising logic to insert a first predetermined value into an all ranks parameter in a memory command, and transmit the memory command to a memory device. Other embodiments are also disclosed and claimed. | 2015-03-26 |
20150089128 | Reordering the Output of Recirculated Transactions Within a Pipeline - A mechanism is provided for recirculating transactions within a pipeline while reordering outputs. A set of transactions associated with a block of data is received and each transaction in the set of transactions is processed via the pipeline. For each transaction processed via the pipeline, responsive to the transaction exiting the pipeline, a determination is made as to whether the transaction needs further processing. Responsive to the transaction needing further processing, the transaction is re-circulated via the pipeline forming a recirculated transaction. | 2015-03-26 |
20150089129 | COMPUTER SYSTEM AND STORAGE MANAGEMENT METHOD - A storage management system, where when adding a specified area of storage media to a storage tiered in response to a request from a host computer, a management computer: obtains storage media information, including I/O frequency of a data storage area of a volume(s) as well as performance information and structure information of the storage media, from the storage apparatus; identifies one or more storage media, which have not been allocated to any of the volumes with the I/O performance in excess of the I/O frequency, on the basis of the structure information of the storage media so that the data storage area of the volume(s), to which a specified storage in the storage tiered is allocated, would achieve a specified I/O performance target; and issues an instruction to the storage apparatus to create a storage tiered by using the identified storage media. | 2015-03-26 |
20150089130 | DYNAMICALLY ALLOCATING TEMPORARY REPLACEMENT STORAGE FOR A DRIVE IN A RAID ARRAY - One embodiment provides a system, including: one or more processors; a network interface for communication with a remote bank of available storage; a redundant array of independent disks (RAID) operatively coupled to the one or more processors; and a memory operatively coupled to the one or more processors and storing instructions executable by the one or more processors to: ascertain at least one unavailable hard disk drive (HDD) of the RAID; determine an available remote storage target; dynamically update a storage destination for data to be stored from the at least one unavailable HDD of the RAID to the available remote storage target; and send the data over the network interface to the available remote storage target. Other embodiments are described and claimed. | 2015-03-26 |
20150089131 | DATA STORAGE UNIT WITH INTERNAL STORAGE AREA NETWORK SWITCH MODULE AND REDUNDANT DATA STORAGE SYSTEM INCLUDING SUCH DATA STORAGE UNIT - The invention discloses a data storage unit and a redundant data storage system including such data storage unit. The data storage unit of the invention includes an internal storage area network (SAN) switch module, a storage server module and a storage device. The internal SAN switch module includes a first external transmission interface and a first internal transmission interface. The storage server module includes a second external transmission interface and a second internal transmission interface. The storage server module is respectively connected to the storage device and the first internal transmission interface through the second internal transmission interface. The internal SAN switch module is connected to the storage device through the first internal transmission interface. | 2015-03-26 |
20150089132 | DYNAMIC STORAGE VOLUME CONFIGURATION BASED ON INPUT/OUTPUT REQUESTS - A storage system includes a plurality hard disk drives and a plurality of solid-state drives and a storage controller operable to manage the hard disk drives and solid-state drives as a plurality of logical volumes, and categorize input/output requests to the logical volumes into types based on sizes of the input/output requests (e.g., smaller and larger). The storage controller is also operable to reconfigure the logical volumes from the hard disk drives and the solid-state drives based on the types of the input/output requests to the logical volumes. A first of the reconfigured logical volumes occupies a first portion of at least one of the solid-state drives and a first portion of at least one of the hard disk drives. The storage controller is further operable to direct the first type of the input/output requests to the first portion of the solid-state drive occupied by the first reconfigured logical volume. | 2015-03-26 |
20150089133 | DATA STORAGE SYSTEM AND CONTROL METHOD THEREOF - The present disclosure discloses a data storage system and a control method thereof. The data storage system includes a plurality of data storage devices, a temporary memory device and an expander. The control method includes: detecting, by the expander, if a flag is in a first status after the expander is restarted; sending, by the expander, a first command to all the data storage devices if the first status is detected. The first status indicates that all the data storage devices are ready for linking and operation. | 2015-03-26 |
20150089134 | CORE IN-MEMORY SPACE AND OBJECT MANAGEMENT ARCHITECTURE IN A TRADITIONAL RDBMS SUPPORTING DW AND OLTP APPLICATIONS - Techniques are provided for managing in-memory space and objects. In one embodiment, a set of in-memory objects are maintained within an area in volatile memory that is accessible to a database server. An in-memory object in this context includes a set of one or more in-memory segments where each respective in-memory segment includes a set of in-memory extents and each respective in-memory extent is a contiguous chunk of memory from the area in volatile memory that is accessible to the database server. The area in volatile memory is managed as a set of stripes, where each stripe is a contiguous chunk of in-memory extents. Stripe control blocks are used to locate free in-memory extents for allocation and registration with an in-memory segment. | 2015-03-26 |
20150089135 | INFORMATION PROCESSING SYSTEM AND METHOD FOR CONTROLLING DATA ACCESS TO STORAGE DEVICES - An information processing system includes a plurality of storage devices and an information processing device. Each of the plurality of storage devices is configured to store therein both of block data and meta data. The information processing device includes a first processor. The first processor is configured to write first meta data to a first storage device from among the plurality of storage devices. The first processor is configured to write first block data corresponding to the first meta data to a second storage device from among the plurality of storage devices. The second storage device is different from the first storage device. | 2015-03-26 |
20150089136 | INTERFACE FOR MANAGEMENT OF DATA MOVEMENT IN A THIN PROVISIONED STORAGE SYSTEM - A computational device receives a request to copy a source logical block of a thin provisioned source logical unit to a target logical block of a thin provisioned target logical unit, wherein in thin provisioned logical units physical storage space is allocated in response to a write operation being performed but not during creation of the thin provisioned logical units. The computational device generates metadata that stores a correspondence between the source logical block and the target logical block, while avoiding allocating any physical storage space for the target logical block in the thin provisioned target logical unit. | 2015-03-26 |
20150089137 | Managing Mirror Copies without Blocking Application I/O - Mechanisms, in a data processing system comprising a processor and an address translation cache, for caching address translations in the address translation cache are provided. The mechanisms receive an address translation from a server computing device to be cached in the data processing system. The mechanisms generate a cache key based on a current valid number of mirror copies of data maintained by the server computing device. The mechanisms allocate a buffer of the address translation cache, corresponding to the cache key, for storing the address translation and store the address translation in the allocated buffer. Furthermore, the mechanisms perform an input/output operation using the address translation stored in the allocated buffer. | 2015-03-26 |
20150089138 | Fast Data Initialization - A method and system for fast file initialization is provided. An initialization request to create or extend a file is received. The initialization request comprises or identifies file template metadata. A set of allocation units are allocated, the set of allocation units comprising at least one allocation unit for the file on a primary storage medium without initializing at least a portion of the file on the primary storage medium. The file template metadata is stored in a cache. The cache resides in at least one of volatile memory and persistent flash storage. A second request is received corresponding to a particular allocation unit of the set of allocation units. Particular file template metadata associated with the particular allocation unit is obtained. In response to the second request, at least a portion of a new allocation unit is generated. | 2015-03-26 |
20150089139 | METHOD AND APPARATUS FOR CACHE OCCUPANCY DETERMINATION AND INSTRUCTION SCHEDULING - An apparatus and method for determining whether data needed for one or more operations is stored in a cache and scheduling the operations for execution based on the determination. For example, one embodiment of a processor comprises: a hierarchy of cache levels for caching data including at least a level 1 (L1) cache; cache occupancy determination logic to determine whether data associated with one or more subsequent operations is stored in one of the cache levels; and scheduling logic to schedule execution of the subsequent operations based on the determination of whether data associated with the subsequent operations is stored in the cache levels. | 2015-03-26 |
20150089140 | Movement Offload To Storage Systems - In a write by-peer-reference, a storage device client writes a data block to a target storage device in the storage system by sending a write request to the target storage device, the write request specifying information used to obtain the data block from a source storage device in the storage system. The target storage device sends a read request to the source storage device for the data block. The source storage device sends the data block to the target storage device, which then writes the data block to the target storage device. The data block is thus written to the target storage device without the storage device client transmitting the data block itself to the target storage device. | 2015-03-26 |
20150089141 | MICROPROCESSOR AND METHOD FOR USING AN INSTRUCTION LOOP CACHE THEREOF - A microprocessor is provided, which includes a processor core and an instruction loop cache. The processor core provides a fetch address of an instruction stream. The fetch address includes a tag and an index. The instruction loop cache receives the fetch address from the processor core. The instruction loop cache includes a cache array and a tag storage. The cache array stores multiple cache entries. Each cache entry includes a tag identification (ID). The cache array outputs the tag ID of the cache entry indicated by the index of the fetch address. The tag storage stores multiple tag values and output the tag value indicated by the tag ID output by the cache array. The instruction loop cache determines whether a cache hit or a cache miss occurs based on a bitwise comparison between the tag of the fetch address and the tag value output by the tag storage. | 2015-03-26 |
20150089142 | MICROPROCESSOR WITH INTEGRATED NOP SLIDE DETECTOR - A microprocessor includes an instruction cache and a hardware state machine configured to detect a continuous sequence of N no operation (NOP) instructions within a stream of instruction bytes fetched from the instruction cache, wherein N is greater than zero. The microprocessor is configured to suspend fetching and executing instructions from the instruction cache in response to detecting the continuous sequence of N NOP instructions. | 2015-03-26 |
20150089143 | Method and Apparatus for Saving Power by Efficiently Disabling Ways for a Set-Associative Cache - A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and determine if an access to some ways are to be disabled to save power, based upon way power signals having a logical state representing a predicted miss to the way. One or more counters associated with the ways count accesses, wherein a power signal is set to the logical state representing a predicted miss when one of said one or more counters reaches a saturation value. Control logic adjusts said one or more counters associated with the ways according to the accesses. | 2015-03-26 |
20150089144 | METHOD AND SYSTEM FOR AUTOMATIC SPACE ORGANIZATION IN TIER2 SOLID STATE DRIVE (SSD) CACHE IN DATABASES FOR MULTI PAGE SUPPORT - A system and method for adjusting space allocated for different page sizes on a recording medium includes dividing the recording medium into multiple blocks such that a block size of the multiple blocks supports a largest page size, and such that each of the multiple blocks is used for a single page size, and assigning an incoming page to a block based on a temperature of the incoming page. | 2015-03-26 |
20150089145 | MULTIPLE CORE PROCESSING WITH HIGH THROUGHPUT ATOMIC MEMORY OPERATIONS - A processor comprising multiple processor cores and a bus for exchanging data between the multiple processor cores is disclosed. Each of the multiple processor cores includes: at least one processor register; a cache for storing at least one cache line of memory; a load store unit for executing a memory command to exchange data between the cache and the at least one processor register; an atomic memory operation unit for executing an atomic memory operation on the at least one cache line of memory; and a high throughput register for storing a status indicating a high throughput or a normal status. The load store unit is operable to transfer the atomic memory operation to the atomic memory operation unit of a designated processor core if the atomic memory operation status is the high throughput status using the bus. | 2015-03-26 |
20150089146 | CONDITIONAL PAGE FAULT CONTROL FOR PAGE RESIDENCY - The present disclosure provides for systems and methods to process a non-resident page that may include attempting to access the non-resident page, an address for the non-resident page pointing to a memory page containing default values, determining that the non-resident page should not cause a page fault based on an indicator indicating that a particular non-resident page should not generate a page fault, returning an indication that a memory read did not translate and returning the default value when the access of the non-resident page is a read and the non-resident page should not cause a page fault. Another example may discontinue a write when the access of the non-resident page is a write and the non-resident page should not cause a page fault. | 2015-03-26 |
20150089147 | Maintenance Of Cache And Tags In A Translation Lookaside Buffer - A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB is an additional cache storing collapsed translations derived from the MTLB. Entries in the MTLB, the collapsed TLB, and other caches can be maintained for consistency. | 2015-03-26 |
20150089148 | MEMORY MANAGEMENT UNIT - A data processing apparatus is provided comprising a plurality of master devices configured to issue memory access requests including virtual addresses. A memory management unit is configured to receive memory access requests and to translate a virtual address included in a memory access request from a requesting master device into a physical address indicating a storage location in memory. The memory management unit has an internal storage unit having a plurality of entries wherein indications of corresponding virtual address portions and physical address portions are stored. The memory management unit is configured to select an entry of the internal storage unit in dependence on the virtual address and an identifier of the requesting master device. Conflict between the master devices in their usage of the internal storage unit is thus avoided. | 2015-03-26 |
20150089149 | ARITHMETIC PROCESSING DEVICE AND CONTROL METHOD FOR ARITHMETIC PROCESSING DEVICE - An arithmetic processing device includes: a cache memory configured to store data in a plurality of cache lines; a hardware prefetch circuit configured to prefetch data to a cache line subsequent to a cache line in which cache misses occur when the cache misses occur in cache lines whose number is p at successive addresses in the cache memory; and a controller configured to change values whose number is p in the hardware prefetch circuit when a number-of-cache-misses specifying instruction is input. | 2015-03-26 |
20150089150 | Translation Bypass In Multi-Stage Address Translation - A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Lookups to the caches of the MTLB can be selectively bypassed based on a control configuration and the attributes of a received address. | 2015-03-26 |
20150089151 | SURFACE RESOURCE VIEW HASH FOR COHERENT CACHE OPERATIONS IN TEXTURE PROCESSING HARDWARE - Techniques are disclosed for performing memory access operations. A texture unit receives a memory access operation that includes a tuple associated with a first view in a plurality of views. The texture unit retrieves a first hash value associated with a first texture header in a plurality of texture headers, where the first texture header is related to the first view. The texture unit retrieves a second hash value associated with a second texture header in the plurality of texture headers, where the second texture header is related to a second view. The texture unit determines whether the first view is potentially aliased with the second view, based on the first and second hash values. If so, then the texture unit invalidates a cache entry in a cache memory associated with the second texture header. Otherwise, the texture unit maintains the cache entry. | 2015-03-26 |
20150089152 | MANAGING HIGH-CONFLICT CACHE LINES IN TRANSACTIONAL MEMORY COMPUTING ENVIRONMENTS - Cache lines in a computing environment with transactional memory are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. When a transaction accessing a cache line in full-line coherency mode results in a transactional abort, the cache line may be placed in sub-line coherency mode if the cache line is a high-conflict cache line. The cache line may be associated with a counter in a conflict address detection table that is incremented whenever a transaction conflict is detected for the cache line. The cache line may be a high-conflict cache line when the counter satisfies a high-conflict criterion, such as reaching a threshold value. The cache line may be returned to full-line coherency mode when a reset criterion is satisfied. | 2015-03-26 |
20150089153 | IDENTIFYING HIGH-CONFLICT CACHE LINES IN TRANSACTIONAL MEMORY COMPUTING ENVIRONMENTS - Cache lines in a computing environment with transactional memory are configurable with a coherency mode and are associated with a high-conflict indicator. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. A cache line is placed in sub-line coherency mode based on examining the high-conflict indicator. A transaction accessing a memory address in a cache line in sub-line coherency mode marks only the sub-cache line portion associated with the memory address as transactionally accessed. The high-conflict indicator may be included in a set of descriptive bits associated with the cache line. A copy of the high-conflict indicator for a cache line in a first cache may be updated with the high-conflict indicator for the cache line in a second cache. | 2015-03-26 |
20150089154 | MANAGING HIGH-COHERENCE-MISS CACHE LINES IN MULTI-PROCESSOR COMPUTING ENVIRONMENTS - Cache lines in a multi-processor computing environment are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. A high-coherence-miss cache line may be placed in sub-line coherency mode. A cache line may be associated with a counter in a coherence miss detection table that is incremented whenever an access of the cache line results in a coherence request. The cache line may be a high-coherence-miss cache line when the counter satisfies a high-coherence-miss criterion, such as reaching a threshold value. The cache line may be returned to full-line coherency mode when a reset criterion is satisfied. | 2015-03-26 |
20150089155 | CENTRALIZED MANAGEMENT OF HIGH-CONTENTION CACHE LINES IN MULTI-PROCESSOR COMPUTING ENVIRONMENTS - Cache lines in a multi-processor computing environment are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. Communications detected on a coherence interconnect may indicate that a cache line is associated with performance-reducing events. A high-contention cache line may be placed in sub-line coherency mode. Caches accessing the cache line are notified that the cache line is in sub-line coherency mode. The cache line may be associated with a counter in a centralized detection table that is incremented based on detecting the communications. The cache line may be a high-contention cache line when the counter satisfies a high-contention criterion, such as reaching a threshold value. The cache line may be returned to full-line coherency mode when a reset criterion is satisfied. | 2015-03-26 |
20150089156 | Atomic Memory Update Unit & Methods - In an aspect, an update unit can evaluate condition(s) in an update request and update one or more memory locations based on the condition evaluation. The update unit can operate atomically to determine whether to effect the update and to make the update. Updates can include one or more of incrementing and swapping values. An update request may specify one of a pre-determined set of update types. Some update types may be conditional and others unconditional. The update unit can be coupled to receive update requests from a plurality of computation units. The computation units may not have privileges to directly generate write requests to be effected on at least some of the locations in memory. The computation units can be fixed function circuitry operating on inputs received from programmable computation elements. The update unit may include a buffer to hold received update requests. | 2015-03-26 |
20150089157 | SPECULATIVE READ IN A CACHE COHERENT MICROPROCESSOR - A cache coherence manager, disposed in a multi-core microprocessor, includes a request unit, an intervention unit, a response unit and an interface unit. The request unit receives coherent requests and selectively issues speculative requests in response. The interface unit selectively forwards the speculative requests to a memory. The interface unit includes at least three tables. Each entry in the first table represents an index to the second table. Each entry in the second table represents an index to the third table. The entry in the first table is allocated when a response to an associated intervention message is stored in the first table but before the speculative request is received by the interface unit. The entry in the second table is allocated when the speculative request is stored in the interface unit. The entry in the third table is allocated when the speculative request is issued to the memory. | 2015-03-26 |
20150089158 | NAVIGATION SYSTEM WITH GEOCACHING MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a navigation system includes: identifying a geocache at a geocache-location; determining an external association for representing the geocache associated with an entity, an event, or a combination thereof; determining an external status for identifying the external status of the entity, the event, or a combination thereof; and generating a cache status based on the external status for displaying on a device. | 2015-03-26 |
20150089159 | MULTI-GRANULAR CACHE MANAGEMENT IN MULTI-PROCESSOR COMPUTING ENVIRONMENTS - Cache lines in a multi-processor computing environment are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. Each cache is associated with a directory having a number of directory entries and with a side table having a smaller number of entries. The directory entry for a cache line associates the cache line with a tag and a set of full-line descriptive bits. Creating a side table entry for the cache line places the cache line in sub-line coherency mode. The side table entry associates each of the sub-cache line portions of the cache line with a set of sub-line descriptive bits. Removing the side table entry may return the cache line to full-line coherency mode. | 2015-03-26 |
20150089160 | METHOD AND APPARATUS FOR COPYING DATA USING CACHE - A cache and a method for performing data copying are provided. The cache includes a copy logic and be connected to a processor through a first bus and to a memory controller through a second bus, which is different from the first bus. Moreover, the copy logic may perform data copying through the second bus based on a data copy command received from the processor. | 2015-03-26 |
20150089161 | HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL - A coherence protocol message is sent corresponding to a particular cache line. A potential conflict involving the particular cache line is identified and a forward request is sent to a home agent to identify the potential conflict. A forward response can be received in response to the forward request from the home agent and a response to the conflict can be determined. | 2015-03-26 |
20150089162 | DISTRIBUTED MEMORY OPERATIONS - A technology for implementing a method for distributed memory operations. A method of the disclosure includes obtaining distributed channel information for an algorithm to be executed by a plurality of spatially distributed processing elements. For each distributed channel in the distributed channel information, the method further associates one or more of the plurality of spatially distributed processing elements with the distributed channel based on the algorithm. | 2015-03-26 |
20150089163 | Memory Controller For Selective Rank Or Subrank Access - A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands. | 2015-03-26 |
20150089164 | HIGH CAPACITY MEMORY SYSTEMS - In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends. | 2015-03-26 |
20150089165 | TRANSACTIONAL MEMORY THAT SUPPORTS A GET FROM ONE OF A SET OF RINGS COMMAND - A transactional memory (TM) includes a control circuit pipeline and an associated memory unit. The memory unit stores a plurality of rings. The pipeline maintains, for each ring, a head pointer and a tail pointer. A ring operation stage of the pipeline maintains the pointers as values are put onto and are taken off the rings. A put command causes the TM to put a value into a ring, provided the ring is not full. A get command causes the TM to take a value off a ring, provided the ring is not empty. A put with low priority command causes the TM to put a value into a ring, provided the ring has at least a predetermined amount of free buffer space. A get from a set of rings command causes the TM to get a value from the highest priority non-empty ring (of a specified set of rings). | 2015-03-26 |
20150089166 | REDUCING MEMORY ACCESSES FOR ENHANCED IN-MEMORY PARALLEL OPERATIONS - A memory storage system is that includes a memory element having a memory address for a physical memory. A memory controller receives a command for accessing the memory element using a program-generated address and dynamically transforms the program-generated address into the memory address for the physical memory using a rotation module and configuration information. A data word accessed by the physical address is then provided to a set of arithmetic logic units (ALUs) where multiple computations are performed simultaneously so as top reduce program execution time and energy. The configuration information provided to the rotation unit configures the set of ALUs. | 2015-03-26 |
20150089167 | TRACKING OWNERSHIP OF MEMORY IN A DATA PROCESSING SYSTEM THROUGH USE OF A MEMORY MONITOR - Ownership of a memory unit in a data processing system is tracked by assigning an identifier to each software component in the data processing system that can acquire ownership of the memory unit. An ownership variable is updated with the identifier of the software component that acquires ownership of the memory unit whenever the memory unit is acquired. | 2015-03-26 |
20150089168 | NESTED CHANNEL ADDRESS INTERLEAVING - A system and method for mapping an address space to a non-power-of-two number of memory channels. Addresses are translated and interleaved to the memory channels such that each memory channel has an equal amount of mapped address space. The address space is partitioned into two regions, and a first translation function is used for memory requests targeting the first region and a second translation function is used for memory requests targeting the second region. The first translation function is based on a first set of address bits and the second translation function is based on a second set of address bits. | 2015-03-26 |
20150089169 | DYNAMIC REUSE AND RECONFIGURATION OF LOGICAL DATA OBJECTS IN A VIRTUAL TAPE SYSTEM - A method according to one embodiment includes selecting, by a processor, one of a WORM logical data object and a read-write logical data object for reuse as a new WORM logical data object, said processor maintaining data attributes bound to said selected logical data object until it is determined that said selected logical data object is available for reuse. At least one temporary data attribute is assigned to said selected logical data object while maintaining said data attributes bound to said selected logical data object The selected logical data object is mounted and a write command to beginning of logical data object is received to bind at least one data attribute to said selected logical data object to replace data attributes and data associated with said selected logical data object to reuse said selected logical data object as said new WORM logical data object. | 2015-03-26 |
20150089170 | METHOD AND APPARATUS FOR MANAGING MEMORY - An apparatus for managing a memory including a working region and a compression region is provided. The working region stores uncompressed data. The apparatus includes a management module and a compression/decompression module. According to a recent used index and a compression ratio of a set of target data stored in the working region, the management module determines whether to transfer the target data to the compression region. When the management module determines to transfer the target data to the compression region, the compression/decompression module compresses the target data and transfers the compressed target data to the compression region. | 2015-03-26 |
20150089171 | STORAGE CONTROL APPARATUS, CONTROL METHOD, AND COMPUTER PRODUCT - A storage control apparatus controls storage units in a storage apparatus and includes a memory unit that stores group information identifying a copy-source volume group belonging to a consistency group; and a control unit that creates based on the group information, snapshots of respective volumes of the volume group for a given time point; creates respective difference storage areas to store, as difference data, update data for the respective volumes after the given time point; and transfers to a copy-destination storage apparatus, data of the snapshots of the respective volumes. The control unit further creates snapshots of the respective volumes at an arbitrary time point after the given time point; creates respective difference storage areas to store, as difference data, update data for the respective volumes after the arbitrary time point; and transfers to the copy-destination storage apparatus, the difference data of the respective volumes for the arbitrary time point. | 2015-03-26 |
20150089172 | COMPOSING A VIRTUAL DISK USING APPLICATION DELTA DISK IMAGES - According to a system and method, for composing a virtual disk for a virtual desktop, the virtual desktop is booted from a virtual disk comprised of a base disk image and a user delta disk image that receives all disk writes to the virtual disk. Disk space is allocated on the virtual disk for a file associated with a selected application to be provided to a user of the virtual desktop. Then the virtual desktop is recomposed offline by linking the bass disk image, an application delta disk image including the file associated with the selected application, and the user delta disk image. The recomposing includes modifying meta data of the application delta disk and the user delta disk so that the file associated with the selected application is mapped to the disk space previously allocated. | 2015-03-26 |
20150089173 | SECURE MEMORY REPARTITIONING - Secure memory repartitioning technologies are described. A processor includes a processor core and a memory controller coupled between the processor core and main memory. The main memory includes a memory range including a section of convertible pages are convertible to secure pages or non-secure pages. The processor core, in response to a page conversion instruction, is to determine from the instruction a convertible page in the memory range to be converted and convert the convertible page to be at least one of a secure page or a non-secure page. The memory range may also include a hardware reserved section are convertible in response to a section conversion instruction. | 2015-03-26 |
20150089174 | DATA ACCESS SYSTEM AND INSTRUCTION MANAGEMENT DEVICE THEREOF - A data access system includes a storage device, an instruction management device, and a host device. The host device is configured to transmit an access instruction associated with an access operation directed to an intended physical address of the storage device to the instruction management device, which compares the access instruction with a specified instruction list. When the instruction management device determines that the access instruction conforms with an instruction included in the specified instruction list, the instruction management device is configured to generate a modified access instruction associated with an access operation directed to a target physical address that is different from the intended physical address of the storage device. | 2015-03-26 |
20150089175 | BUS SYSTEM AND METHOD OF PROTECTED MEMORY ACCESS - A bus system includes a functional unit to which a unit identifier is assigned, a memory module for storage of data that has a storage region, and a bus. The functional unit is connected to the memory module via the bus. The storage region is configured such that one or more multiple global authorized identifiers are assigned thereto, so that the functional unit only has reading or writing access to the storage region if the unit identifier assigned to the functional unit corresponds to one of the global authorized identifiers assigned to the storage region. | 2015-03-26 |
20150089176 | GNSS SERVICES ON LOW POWER HUB - In one embodiment an controller comprises logic, at least partially including hardware logic, configured to logic, at least partially including hardware logic, configured to receive location data from a location measurement apparatus, buffer the location data in a local memory, and release the location data from the local memory to a remote processor in response to one or more trigger conditions. Other embodiments may be described. | 2015-03-26 |
20150089177 | MANAGING AN ANALYTIC FUNCTION TO BE PERFORMED ON DATA STORED IN AN INPUT BLOCK - In an example, an analytic function to be performed on data stored in an input block is managed through an interface to a framework through which a user is to define the analytic function. The framework is to buffer batches of the data into a memory through implementation of a Reader, a Writer, a PreReader, and a PreWriter on the data stored in the input block when the user-defined analytic function is performed, and wherein the Reader, the Writer, the PreReader, and the PreWriter are individually movable with respect to each other in the input block. In addition, the user-defined analytic function is received through the interface. | 2015-03-26 |
20150089178 | Management Of A Memory - A method for managing a memory pool in a memory heap partitioned into consecutive memory segments includes deleting a specific memory segment by: receiving an identification key for the specific memory segment, determining a start address and a size of the specific memory segment from a translation table based on the identification key, and moving memory segments, which are allocated behind the start address of the specific memory segment in the memory heap, towards the beginning of the memory heap by the size of the specific memory segment, such that the memory pool consists of a first section, which is continuously allocated, and a second section, which is continuously unallocated. | 2015-03-26 |
20150089179 | STORAGE SYSTEM - According to one embodiment, a storage system includes a plurality of memory nodes that are connected to each other in two or more different directions and a connection unit. The connection unit issues a command in response to a request from the outside. In the storage system, a plurality of logical memory nodes are constructed by allocating, to one logical memory node, memory nodes including at least one first memory node which stores data to be accessed by the command and a second memory node which stores redundant data of the data stored in the first memory node. The command includes a first address which designates one of the plurality of logical memory nodes and a second address which designates a storage position in a memory space allocated to each logical memory node. | 2015-03-26 |
20150089180 | ARITHMETIC PROCESSING DEVICE, INFORMATION PROCESSING DEVICE, CONTROL METHOD FOR INFORMATION PROCESSING DEVICE, AND CONTROL PROGRAM FOR INFORMATION PROCESSING DEVICE - An arithmetic processing device having an allocation unit configured to reserve a memory allocation area in a memory and register address range information indicating an address range of the memory allocation area in an address range table, in response to an execution of a memory area allocation function requesting memory area allocation, and a determination unit configured to refer to the address range table and perform determination processing as to whether or not an access destination address of a memory access instruction is within an address range indicated by the address range information registered in the address range table, in response to an execution of the memory access instruction relating to the memory allocation area. | 2015-03-26 |
20150089181 | Use of wireless devices external storage - To meet the needs for storing larger volume personal information for user of wireless device, it is desire to provide extra storage space to the wireless device such as for cell phone etc due to the limited storage space that the wireless device has. Instant application disclosed a system and method for the wireless device to efficiently and effectively use remotely located storage space provided by a server. | 2015-03-26 |
20150089182 | AUTOMATICALLY ALIGNING VIRTUAL BLOCKS TO PHYSICAL BLOCKS - Automatically aligning virtual blocks of partitions to blocks of underlying physical storage is disclosed. In some embodiments, a starting offset of a partition included in a logical container is detected. In some embodiments, a misalignment correction amount for a partition included in a logical container is detected. In some embodiments, a misalignment associated with a partition included in a logical container is corrected. | 2015-03-26 |
20150089183 | MAPPING A PHYSICAL ADDRESS DIFFERENTLY TO DIFFERENT MEMORY DEVICES IN A GROUP - A memory subsystem includes a group of memory devices connected to an address bus. The memory subsystem includes logic to uniquely map a physical address of a memory access command to each memory device of the group. Thus, each physical address sent by an associated memory controller uniquely accesses a different row of each memory device, instead of being mapped to the same or corresponding row of each memory device. | 2015-03-26 |
20150089184 | Collapsed Address Translation With Multiple Page Sizes - A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB. | 2015-03-26 |
20150089185 | Managing Mirror Copies without Blocking Application I/O - Mechanisms, in a data processing system comprising a processor and an address translation cache, for caching address translations in the address translation cache are provided. The mechanisms receive an address translation from a server computing device to be cached in the data processing system. The mechanisms generate a cache key based on a current valid number of mirror copies of data maintained by the server computing device. The mechanisms allocate a buffer of the address translation cache, corresponding to the cache key, for storing the address translation and store the address translation in the allocated buffer. Furthermore, the mechanisms perform an input/output operation using the address translation stored in the allocated buffer. | 2015-03-26 |
20150089186 | STORE ADDRESS PREDICTION FOR MEMORY DISAMBIGUATION IN A PROCESSING DEVICE - A processing device implementing store address prediction for memory disambiguation in a processing device is disclosed. A processing device of the disclosure includes a store address predictor to predict an address for store operations that store data to a memory hierarchy. The processing device further includes a store buffer for buffering the store operations prior to completion, the store buffer to comprise the predicted address for each of the store operations. The processing device further includes a load buffer to buffer a load operation, the load operation to reference the store buffer to, based on the predicted addresses, determine whether to speculatively execute ahead of each store operation and to determine whether to speculatively forward data from one of the store operations. | 2015-03-26 |
20150089187 | Hazard Check Instructions for Enhanced Predicate Vector Operations - A hazard check instruction has operands that specify addresses of vector elements to be read by first and second vector memory operations. The hazard check instruction outputs a dependency vector identifying, for each element position of the first vector corresponding to the first vector memory operation, which element position of the second vector that the element of the first vector depends on (if any). In an embodiment, at least one of the vector memory operations has addresses specified using a scalar address in the operands (and a vector attribute associated with the vector). In an embodiment, the operands may include predicates for one or both of the vector memory operations, indicating which vector elements are active. The dependency vector may be qualified by the predicates, indicating dependencies only for active elements. | 2015-03-26 |
20150089188 | Vector Hazard Check Instruction with Reduced Source Operands - In an embodiment, a processor may implement a vector hazard check instruction to detect dependencies between vector memory operations based on the addresses of the vectors accessed by the vector memory operations. The addresses may be specified via a base address and a vector of indexes for each vector. In an embodiment, one of the base addresses may be an implied (or assumed) zero address, reducing the number of operands of the hazard check instruction. | 2015-03-26 |
20150089189 | Predicate Vector Pack and Unpack Instructions - In an embodiment, a processor may implement a vector instruction set including predicate vectors and multiple vector element sizes. The vector instruction set may include predicate vector pack and unpack instructions. Responsive to the predicate vector pack instruction, the processor may pack predicates from multiple predicate vector source registers into a destination predicate vector register. Responsive to the predicate vector unpack instruction, the processor may select a portion of a source predicate vector register and write the result to a destination predicate vector register. Additionally, the predicate vector register may store one or more vector attributes associated with the corresponding vector. The processor may modify the attribute as part of the pack/unpack operation (e.g. based on a pack/unpack factor). Additionally, vector pack/unpack instructions that are controlled by the attribute in a corresponding predicate vector register may be implemented. | 2015-03-26 |
20150089190 | Predicate Attribute Tracker - In an embodiment, a processor includes a register attribute tracker configured to track one or more attributes corresponding to registers. The register attribute tracker may track the attributes associated with the registers when those registers are used as output registers of instructions that explicitly define the attributes and, if the register attribute tracker has a tracked attribute associated with an input register of an instruction that does not explicitly define the attribute, the register attribute tracker may annotate the instruction with an attribute and/or associate an attribute with the output register of the instruction in the register attribute tracker. | 2015-03-26 |
20150089191 | Early Issue of Null-Predicated Operations - In an embodiment, a processor includes an issue circuit configured to issue instruction operations for execution. The issue circuit may be configured to monitor the source operands of the instruction operations, and to issue instruction operations for which the source operands (including predicate operands, as appropriate) are resolved. Additionally, the issue circuit may be configured to detect a null predicate that indicates that none of the vector elements will be modified by a corresponding instruction operation. The issue circuit may be configured to issue the corresponding instruction operation with the null predicate even if other source operands are not yet resolved. | 2015-03-26 |
20150089192 | Dynamic Attribute Inference - In an embodiment, a processor may be configured to dynamically infer one or more attributes of input and/or output registers of an instruction, given the attributes corresponding to at least one input registers. The inference may be made at the issue circuit/stage of the processor, for those registers that do not have attribute information at the issue circuit/stage. In an embodiment, the processor may also include a register attribute tracker configured to track attributes of registers prior to the issue stage of the processor pipeline. The processor may feed back, to the register attribute tracker, inferred attributes and the register addresses of the registers to which the inferred attributes apply. The register attribute tracker may be configured to may associate the inferred attribute with the identified register attribute tracker may also be configured to infer input register attributes from other input register attributes. | 2015-03-26 |
20150089193 | PREDICTIVE FETCHING AND DECODING FOR SELECTED RETURN INSTRUCTIONS - Predictive fetching and decoding for selected instructions. A determination is made as to whether an instruction to be executed in a pipelined processor is a selected return instruction, the pipelined processor having a plurality of stages including an execute stage. Based on the instruction being the selected return instruction, obtaining from a data structure a predicted return address, the predicted return address being an address of an instruction to which it is predicted that processing is to be returned. Additionally, based on the instruction being the selected return instruction, operating state for the instruction at the predicted return address is predicted. The instruction is fetched at the predicted return address, prior to the selected return instruction reaching the execute stage, and decoding of the fetched instruction is initiated based on the predicted operating state. | 2015-03-26 |
20150089194 | PREDICTIVE FETCHING AND DECODING FOR SELECTED INSTRUCTIONS - Predictive fetching and decoding for selected instructions (e.g., operating system instructions, hypervisor instructions or other such instructions). A determination is made that a selected instruction, such as a system call instruction, an asynchronous interrupt, a return from system call instruction or return from asynchronous interrupt, is to be executed. Based on determining that such an instruction is to be executed, a predicted address is determined for the selected instruction, which is the address to which processing transfers in order to provide the requested services. Then, fetching of instructions beginning at the predicted address prior to execution of the selected instruction is commenced. Further, speculative state relating to a selected instruction, including, for instance, an indication of the privilege level of the selected instruction or instructions executed on behalf of the selected instruction, is predicted and maintained. | 2015-03-26 |
20150089195 | METHOD AND APPARATUS FOR PERFORMING A SHIFT AND EXCLUSIVE OR OPERATION IN A SINGLE INSTRUCTION - Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value. | 2015-03-26 |
20150089196 | METHOD AND APPARATUS FOR PERFORMING A SHIFT AND EXCLUSIVE OR OPERATION IN A SINGLE INSTRUCTION - Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value. | 2015-03-26 |
20150089197 | METHOD AND APPARATUS FOR PERFORMING A SHIFT AND EXCLUSIVE OR OPERATION IN A SINGLE INSTRUCTION - Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value. | 2015-03-26 |
20150089198 | TECHNIQUE FOR REDUCING VOLTAGE DROOP BY THROTTLING INSTRUCTION ISSUE RATE - An issue control unit is configured to control the rate at which an instruction issue unit issues instructions to an execution pipeline in order to avoid spikes in power drawn by that execution pipeline. The issue control unit maintains a history buffer that reflects, for N previous cycles, the number of instructions issued during each of those N cycles. If the total number of instructions issued during the N previous cycles exceeds a threshold value, then the issue control unit throttles the instruction issue unit from issuing instructions during a subsequent cycle. In addition, the issue control unit increases the threshold value in proportion to the number of previously issued instructions and based on a variety of configurable parameters. Accordingly, the issue control unit maintains granular control over the rate with which the instruction issue unit “ramps up” to a maximum instruction issue rate. | 2015-03-26 |
20150089199 | ROTATE INSTRUCTIONS THAT COMPLETE EXECUTION EITHER WITHOUT WRITING OR READING FLAGS - A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag. | 2015-03-26 |
20150089200 | ROTATE INSTRUCTIONS THAT COMPLETE EXECUTION EITHER WITHOUT WRITING OR READING FLAGS - A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag. | 2015-03-26 |
20150089201 | ROTATE INSTRUCTIONS THAT COMPLETE EXECUTION EITHER WITHOUT WRITING OR READING FLAGS - A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag. | 2015-03-26 |
20150089202 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING MULTI-CYCLE REGISTER FILE BYPASS - A system, method, and computer program product are provided for implementing a multi-cycle register file bypass mechanism. The method includes the steps of receiving a set of control bits, combining the set of control bits with a set of valid bits associated with previously issued instructions, and enabling a bypass path for each thread based on the set of control bits and the set of valid bits. Each valid bit in the set of valid bits indicates whether execution of an instruction of the previously issued instructions was enabled for a thread in a thread block. | 2015-03-26 |
20150089203 | LATENCY REDUCTION IN DISTRIBUTED COMPUTING ENVIRONMENTS - Systems and methods that facilitate anticipatory execution and provision of possible instructions receivable by a computing environment are described herein. A state management component identifies the possible instructions, and defines a prediction space. A predictor component selects one or more possible instructions to be executed by a processor module. In one embodiment, a portion of a computing environment is hosted at a data center, and a user interacts with the computing environment via a terminal computing device. A possible instruction receivable by the terminal is identified and executed before such instruction is issued, and resulting information is preemptively delivered to the terminal computing device, which accesses the information when such instruction is issued. | 2015-03-26 |
20150089204 | DYNAMICALLY RECONFIGURABLE MICROPROCESSOR - A microprocessor includes a plurality of dynamically reconfigurable functional units, a fingerprint, and a fingerprint unit. As the plurality of dynamically reconfigurable functional units execute instructions according to a first configuration setting, the fingerprint unit accumulates information about the instructions according to a mathematical operation to generate a result. The microprocessor also includes a reconfiguration unit that reconfigures the plurality of dynamically reconfigurable functional units to execute instructions according to a second configuration setting in response to an indication that the result matches the fingerprint. | 2015-03-26 |
20150089205 | CONVERT FROM ZONED FORMAT TO DECIMAL FLOATING POINT FORMAT - Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location. | 2015-03-26 |
20150089206 | CONVERT TO ZONED FORMAT FROM DECIMAL FLOATING POINT FORMAT - Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location. | 2015-03-26 |
20150089207 | TECHNIQUE FOR COUNTING VALUES IN A REGISTER - A parallel counter accesses data generated by an application and stored within a register. The register includes different segments that include different portions of the application data. The parallel counter is configured to count the number of values within each segment that have a particular characteristic in a parallel fashion. The parallel counter may then return the individual segment counts to the application, or combine those segment counts and return a register count to the application. Advantageously, applications that rely on population count operations may be accelerated. Further, increasing the number of segments in a given register may reduce the time needed to count the values in that register, thereby providing a scalable solution to population counting. Additionally, the architecture of the parallel counter is sufficiently flexible to allow both register counting and segment counting, thereby combining two separate functionalities into just one hardware unit. | 2015-03-26 |
20150089208 | PREDICTOR DATA STRUCTURE FOR USE IN PIPELINED PROCESSING - A predictor data structure is used for pipelined processing by a pipelined processor. The predictor data structure includes a predicted address to be used in return from execution of a selected instruction, and a predicted operating state associated with the predicted address. Based on determining a selected return instruction is to be executed, the predicted address to which processing is to be returned is obtained from the predictor data structure. Further, based on determining the selected return instruction is to be executed, a transitional operating state to be entered based on the predicted operating state stored in the predictor data structure is predicted, wherein at least one of the predicted address and the predicted transitional operating state are to be used to validate execution of the selected return instruction. | 2015-03-26 |
20150089209 | Synchronization of UEFI Secure Boot Variables on a Managed Server - Techniques are provided for actively managing secure boot variables. Such techniques include receiving a request from an entity to modify a portion of a basic input/output system (BIOS), the request including a data segment, and verifying that the requesting entity is authorized to modify a portion of the BIOS. In response to verifying that the requesting entity is authorized, the portion of the BIOS is modified based on the received request and the data segment, and a copy of the data segment is stored in a file on a physical memory that is communicatively coupled to the BIOS. If the BIOS is updated, thereby erasing part or all of the secure boot variables that are stored in the BIOS, the record of changes of the secure boot variables along with default authenticated variables may be used to restore the secure boot variables to a state prior to the BIOS update. | 2015-03-26 |
20150089210 | ELECTRONIC DEVICE AND LOW BATTERY BOOT-UP METHOD - In a low battery boot-up method executed in an electronic device, boot configurations of the electronic device for low battery boot-up are set and stored in a storage device. When a user command to turn on the electronic device is received after the electronic device has shut down automatically due to low battery, the boot configurations are read from the storage device. The electronic device is controlled to boot-up according to the boot configurations and enter a low battery power-on state. | 2015-03-26 |
20150089211 | SYSTEM AND METHOD FOR CLIENT POLICY ASSIGNMENT IN A DATA STORAGE SYSTEM - A system and method for property assignment in a data storage system is presented. A data storage system defines a client configuration profile comprising a set of storage operation properties, wherein the storage operation properties regulate criteria for performing storage operations by the data agent on client devices that are associated with the client configuration profile. A storage management system associates a first client device to the client configuration profile; and communicates the set of properties of the client configuration profile to property tables of corresponding objects in the first client device. | 2015-03-26 |
20150089212 | Systems and Methods For Utilizing IMS Data Security Mechanisms in a Circuit Switched Network - Aspects of the present invention provide a mechanism to utilize IMS media security mechanisms in a CS network and, thereby, provide end-to-end media security in the case where the media traffic travels across both a CS network and a PS network. | 2015-03-26 |
20150089213 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, an information processing apparatus includes a main processor, a secure operating system (OS) module, a non-secure OS module, a secure monitor memory setting module, a timer, and an address space controller. When receiving a notification of an interrupt from the timer, a secure monitor instructs the secure OS module to execute certain processing. The secure OS module is configured to execute certain processing instructed by the secure monitor and store data of a result of the processing in a first memory area. | 2015-03-26 |
20150089214 | ENHANCED AUTHENTICATION AND/OR ENHANCED IDENTIFICATION OF A SECURE ELEMENT OF A COMMUNICATION DEVICE - A method for enhanced authentication and/or enhanced identification of a secure element of a user equipment includes: transmitting a first message to a secure element; receiving a second message, from the secure element at a first server entity, the second message including at least the signed public key and a signature information, wherein the signing message content includes at least one information element that is omitted in the second message; transmitting a third message, to the second server entity, the third message including at least the signed public key and the signature information, wherein the signing message content is accessible to or derivable by the second server entity in view of a verification of the signature information contained in the second message for authentication and/or identification purposes. | 2015-03-26 |
20150089215 | SYSTEM, APPARATUS, APPLICATION AND METHOD FOR BRIDGING CERTIFICATE DEPLOYMENT - An apparatus, system and method is provided for bridging (i) a certificate registration apparatus that communicates with a certificate deployment target based on a specific certificate deployment protocol and (ii) a target deployment device that is not configured to conform to the specific certificate deployment protocol, within a public key infrastructure (PKI). | 2015-03-26 |