13th week of 2014 patent applcation highlights part 48 |
Patent application number | Title | Published |
20140087509 | MEMS-BASED CANTILEVER ENERGY HARVESTER - The claimed invention is directed to integrated energy-harvesting piezoelectric cantilevers. The cantilevers are fabricated using sol-gel processing using a sacrificial poly-Si seeding layer. Improvements in film microstructure and electrical properties are realized by introducing a poly-Si seeding layer and by optimizing the poling process. | 2014-03-27 |
20140087510 | Manufacturing Method Of An Amorphous-Silicon Flat-Panel X-Ray Sensor - An embodiment of the present invention provides a manufacturing method of an amorphous-silicon flat-panel X-ray sensor; the method reduces the number of mask plates to be used, simplifies the production processes, saves production costs, while also improving the product yield. The manufacturing method comprises: on a substrate, after a gate scan line is formed, forming a data line, a TFT switch element and a photosensitive element through one patterning process, wherein on the mask plate used in the patterning process, a region corresponding to a channel of the TFT switch element is semi-transmissive, whereas regions respectively corresponding to the data line, the photosensitive element and the portion of the TFT switch element other than the channel thereof are non-transmissive; thereafter, on the substrate formed with the TFT switch element and the photosensitive element, a passivation layer and a bias line are formed. | 2014-03-27 |
20140087511 | METHOD FOR PRODUCING A PHOTOVOLTAIC CELL HAVING A SELECTIVE EMITTER - A method for manufacturing a photovoltaic cell with a selective emitter, including the steps of: depositing an antireflection layer including n-type dopants on an n- or p-type silicon substrate, said deposition being, performed in the presence of a chemical compound that accelerates the diffusion of n-type dopant atoms in said substrate; overdoping at least one area of the substrate to form at least one n | 2014-03-27 |
20140087512 | LIQUID PRECURSOR FOR DEPOSITION OF COPPER SELENIDE AND METHOD OF PREPARING THE SAME - Liquid precursors containing copper and selenium suitable for deposition on a substrate to form thin films suitable for semiconductor applications are disclosed. Methods of preparing such liquid precursors and methods of depositing a precursor on a substrate are also disclosed. | 2014-03-27 |
20140087513 | EMBEDDED JUNCTION IN HETERO-STRUCTURED BACK-SURFACE FIELD FOR PHOTOVOLTAIC DEVICES - A photovoltaic device and method include a crystalline substrate and an emitter contact portion formed in contact with the substrate. A back-surface-field junction includes a homogeneous junction layer formed in contact with the crystalline substrate and having a same conductivity type and a higher active doping density than that of the substrate. The homogeneous junction layer includes a thickness less than a diffusion length of minority carriers in the homogeneous junction layer. A passivation layer is formed in contact with the homogeneous junction layer opposite the substrate, which is either undoped or has the same conductivity type as that of the substrate. | 2014-03-27 |
20140087514 | PHOTOELECTRIC CONVERTER, METHOD OF MANUFACTURING PHOTOELECTRIC CONVERTER AND IMAGING DEVICE - A photoelectric converter includes a pair of electrodes and a plurality of organic layers. The pair of electrodes is provided above a substrate. The plurality of organic layers is interposed between the pair of electrodes and includes a photoelectric conversion layer and a given organic layer being formed on one electrode of the pair of electrodes. The one electrode is one of pixel electrodes arranged two-dimensionally. The given organic layer has a concave portion that is formed in a corresponding position located above a step portion among the arranged pixel electrodes. An angle θ of the concave portion is less than 50°, where an inclination angle of a tangent plane at a given point on the concave portion to a surface plane of the substrate is defined as θ. | 2014-03-27 |
20140087515 | METHOD FOR THE CONTACT SEPARATION OF ELECTRICALLY-CONDUCTING LAYERS ON THE BACK CONTACTS OF SOLAR CELLS AND CORRESPONDING SOLAR CELL - A method for fabricating a solar cell including a semiconductor substrate is proposed where electrical contacting is made on the back side of the semiconductor substrate. The back side of the semiconductor substrate has locally doped regions. The adjacent regions exhibit different doping from the region. The two regions are initially coated with electrically conductive material over the entire area. So that the conductive material does not short-circuit the solar cell, the two regions are covered with a thin electrically insulating layer at least at the region boundaries. The electrically conductive layer is separated by applying an etch barrier layer over the entire surface which is then removed free from masking and selectively e.g. by laser ablation, locally above the insulating layer. The conductive layer is locally removed in the area of the openings of the etch barrier layer by subsequent action of an etching solution. | 2014-03-27 |
20140087516 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object to provide a material suitably used for used for a semiconductor included in a transistor, a diode, or the like, with the use of a sputtering method. Specifically, an object is to provide a manufacturing process an oxide semiconductor film having high crystallinity. By intentionally adding nitrogen to the oxide semiconductor, an oxide semiconductor film having a wurtzite crystal structure that is a hexagonal crystal structure is formed. In the oxide semiconductor film, the crystallinity of a region containing nitrogen is higher than that of a region hardly containing nitrogen or a region to which nitrogen is not intentionally added. The oxide semiconductor film having high crystallinity and having a wurtzite crystal structure is used as a channel formation region of a transistor. | 2014-03-27 |
20140087517 | SEMICONDUCTOR DEVICE - An object is to prevent an impurity such as moisture and oxygen from being mixed into an oxide semiconductor and suppress variation in semiconductor characteristics of a semiconductor device in which an oxide semiconductor is used. Another object is to provide a semiconductor device with high reliability. A gate insulating film provided over a substrate having an insulating surface, a source and a drain electrode which are provided over the gate insulating film, a first oxide semiconductor layer provided over the source electrode and the drain electrode, and a source and a drain region which are provided between the source electrode and the drain electrode and the first oxide semiconductor layer are provided. A barrier film is provided in contact with the first oxide semiconductor layer. | 2014-03-27 |
20140087518 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: supplying a supercritical fluid mixed with an under-fill material to a stacked unit, which has a plurality of stacked semiconductor chips; and filling the under-fill material in the space between the plurality of the semiconductor chips, by heating the stacked unit placed in the inside of the high-pressure vessel and curing the under-fill material flowing in the space between the plurality of the semiconductor chips by a polymerization reaction, while the supercritical fluid is being supplied. | 2014-03-27 |
20140087519 | PACKAGE PROCESS AND PACKAGE STRUCTURE - A package process is provided. An adhesive layer is disposed on a carrier board and then plural first semiconductor devices are disposed on the adhesive layer. A first molding compound formed on the carrier board covers the sidewalls of the first semiconductor devices and fills the gaps between the first semiconductor devices so as to form a chip array board constructed by the first semiconductor devices and the first molding compound. Next, plural second semiconductor devices are flip-chip bonded to the first semiconductor devices respectively. Then, a second molding compound formed on the chip array board at least covers the sidewalls of the second semiconductor devices and fills the gaps between the second semiconductor devices. Subsequently, the chip array board is separated from the adhesive layer. Then, the first and the second molding compound are cut along the gaps between the second semiconductor devices. | 2014-03-27 |
20140087520 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the lead frame, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region). | 2014-03-27 |
20140087521 | WAFER LEVEL CHIP SCALE PACKAGING - An improved wafer level chip scale packaging technique is described which does not use an encapsulated via to connect between a redirection layer and a pad within the pad ring on the semiconductor die. In an embodiment, a first dielectric layer is formed such that it terminates on each die within the die's pad ring. Tracks are then formed in a conductive layer which contact one of the pads and run over the edge of an opening onto the surface of the first dielectric layer. These tracks may be used to form an electrical connection between the pad and a solder ball. | 2014-03-27 |
20140087522 | Reducing Delamination Between an Underfill and a Buffer Layer in a Bond Structure - A die includes a metal pad, a passivation layer, and a patterned buffer layer over the passivation layer. The patterned buffer layer includes a plurality of discrete portions separated from each other. An under-bump-metallurgy (UBM) is formed in an opening in the patterned buffer layer and an opening in the passivation layer. A metal bump is formed over and electrically coupled to the UBM. | 2014-03-27 |
20140087523 | STACKED NANOWIRE FIELD EFFECT TRANSISTOR - A method for fabricating a nanowire field effect transistor device includes depositing a first sacrificial layer on a substrate, depositing a first layer of a semiconductor material on the first sacrificial layer, depositing a second sacrificial layer on the first layer of semiconductor material, depositing a second layer of the semiconductor material on the second sacrificial layer, pattering and removing portions of the first sacrificial layer, the first semiconductor layer, the second sacrificial layer, and the second semiconductor layer, patterning a dummy gate stack, removing the dummy gate stack, removing portions of the sacrificial layer to define a first nanowire including a portion of the first semiconductor layer and a second nanowire including a portion of the second semiconductor layer, and forming gate stacks about the first nanowire and the second nanowire. | 2014-03-27 |
20140087524 | METHOD FOR PRODUCING A FIELD EFFECT TRANSISTOR WITH IMPLANTATION THROUGH THE SPACERS - The substrate successively includes a support substrate, an electrically insulating layer, a semiconductor material layer, and a gate pattern. The semiconductor material layer and gate pattern are covered by a covering layer. A first doping impurity is implanted in the semiconductor material layer through the covering layer so as to place the thickness of maximum concentration of the first doping impurity in the first layer. The covering layer is partly eliminated so as to form lateral spacers leaving source/drain electrodes free. | 2014-03-27 |
20140087525 | COMPLEMENTARY METAL OXIDE SEMICONDUCTOR TRANSISTOR AND FABRICATING METHOD THEREOF - A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain. | 2014-03-27 |
20140087526 | MULTI-GATE FIELD EFFECT TRANSISTOR DEVICES - A method for fabricating a field effect transistor device includes patterning a semiconductor fin on a substrate insulator layer, the substrate insulator layer arranged on a substrate, patterning a dummy gate stack over a portion of the fin, forming spacers adjacent to the dummy gate stack, removing the dummy gate stack to form a cavity that exposes portions of the substrate insulator layer and the fin, removing exposed portions of the substrate insulator layer to increase a depth of the cavity, removing a region of the substrate insulator layer from beneath the fin to suspend a portion of the fin above the substrate insulator layer, forming a gate stack in the cavity, removing a portion of the gate stack in the cavity to expose a portion of a dielectric layer arranged on the fin, and depositing an insulator material in the cavity. | 2014-03-27 |
20140087527 | METHOD OF FORMING THIN FILM POLY SILICON LAYER AND METHOD OF FORMING THIN FILM TRANSISTOR - A method of forming a thin film poly silicon layer includes following steps. Firstly, a substrate is provided. A thin film silicon layer is then formed on the substrate by a silicon thin film deposition process. A heating treatment is then applied to the substrate so as to convert the thin film silicon layer into a thin film poly silicon layer. A method of forming a thin film transistor includes following steps. A first patterning process is performed on the thin film poly silicon layer on the substrate to form a semiconductor pattern. Subsequently, a gate insulation layer, a gate electrode, a source electrode and a drain electrode are formed. | 2014-03-27 |
20140087528 | Printed Material Constrained By Well Structures And Devices Including Same - A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g., an operative transistor. | 2014-03-27 |
20140087529 | POWER DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided is a power device. The power device may include a two-dimensional electron gas (2-DEG) layer in a portion corresponding to a gate electrode pattern since a second nitride layer is further formed on a lower portion of the gate electrode pattern after a first nitride layer is formed and thus, may be capable of performing a normally-OFF operation. Accordingly, the power device may adjust generation of the 2-DEG layer based on a voltage of a gate, and may reduce power consumption. The power device may regrow only the portion corresponding to the gate electrode pattern or may etch a portion excluding the portion corresponding to the gate electrode pattern and thus, a recess process may be omissible, a reproducibility of the power device may be secured, and a manufacturing process may be simplified. | 2014-03-27 |
20140087530 | Field Controlled Diode With Positively Biased Gate - An integrated circuit containing a field controlled diode which includes a p-type channel region between an upper gate and a lower n-type depletion gate, a p-type anode in a p-type anode well abutting the channel region, and an n-type cathode in a p-type anode well abutting the channel region opposite from the anode well. An n-type lower gate link connects the lower gate to the surface of the substrate. A surface control element is located at the surface of the channel region between the cathode and the upper gate. A process of forming the integrated circuit containing the field controlled diode is described. | 2014-03-27 |
20140087531 | Two Step Poly Etch LDMOS Gate Formation - A method of making a transistor includes etching a first side of a gate, the gate including an oxide layer formed over a substrate and a conductive material formed over the oxide layer, the etching removing a first portion of the conductive material, implanting an impurity region into the substrate such that the impurity region is self-aligned, and etching a second side of the gate to remove a second portion of the conductive material. | 2014-03-27 |
20140087532 | CMOS TRANSISTOR AND METHOD FOR FABRICATING THE SAME - The invention provides a method for fabricating a CMOS transistor and a method for fabricating an array substrate. The method for fabricating a CMOS transistor comprises a step of forming channels, which comprises: depositing an amorphous silicon layer on a substrate, and crystallizing the amorphous silicon layer into a poly-silicon layer; implanting boron atoms into the poly-silicon layer and then forming an N channel region and a P channel region by etching the poly-silicon layer implanted with the boron atoms; forming a photoresist-partially-retained region corresponding to the N channel region and a photoresist-completely-retained region corresponding to the P channel region through a single patterning process; and removing the photoresist in the photoresist-partially-retained-region and retaining a part of the photoresist in the photoresist-completely-retained region using an ashing process, implanting phosphorus atoms through ion implantation thereby forming an N channel and a P channel. | 2014-03-27 |
20140087533 | METHODS OF FORMING TRANSISTORS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING THE TRANSISTORS - A method of forming a transistor is provided. An upper portion of a substrate is partially removed forming a trench. An isolation layer partially fills the trench, forming active patterns of the substrate. The isolation layer has a void therein. A photoresist pattern is formed on the active patterns and the isolation layer. The active patterns and the isolation layer are partially removed using the photoresist pattern as an etching mask, thus forming a recess. A plasma treatment process is performed, removing the photoresist pattern and filling the void. A gate insulation layer and a gate electrode fill the recess. | 2014-03-27 |
20140087534 | METHODS OF MANUFACTURING VERTICAL STRUCTURE NONVOLATILE MEMORY DEVICES - A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a plurality of transistors that are disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer. At least one of the plurality of transistors includes at least one recess in a gate of the transistor into which at least one protrusion, which includes the channel layer, extends. | 2014-03-27 |
20140087535 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region. | 2014-03-27 |
20140087536 | SEMICONDUCTOR STRUCTURE THAT REDUCES THE EFFECTS OF GATE CROSS DIFFUSION AND METHOD OF FORMING THE STRUCTURE - Gate cross diffusion in a semiconductor structure is substantially reduced or eliminated by forming multiple n-type gate regions with different dopant concentrations and multiple p-type gate regions with different dopant concentrations so that the n-type gate region with the lowest dopant concentration touches the p-type gate region with the lowest dopant concentration. | 2014-03-27 |
20140087537 | SEMICONDUCTOR DEVICES INCLUDING MULTILAYER SOURCE/DRAIN STRESSORS AND METHODS OF MANUFACTURING THE SAME - A semiconductor device including source drain stressors and methods of manufacturing the same are provided. The methods may include forming a recess region in the substrate at a side of a gate pattern, and an inner surface of the recess region may include a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes. The method may further include performing a first selective epitaxial growth (SEG) process to form a base epitaxial pattern on the inner surface of the recess region at a process pressure in a range of about 50 Torr to about 300 Torr. The method may also include performing a second selective epitaxial growth (SEG) process to form a bulk epitaxial pattern on the base epitaxial pattern. | 2014-03-27 |
20140087538 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is disclosed. In one embodiment, the method comprises: forming a gate stack on a substrate, wherein the gate stack comprises a gate dielectric layer and a gate conductor layer; selectively etching end portions of the gate dielectric layer to form gaps; and filling a material for the gate dielectric layer into the gaps. | 2014-03-27 |
20140087539 | PROCESS FOR MANUFACTUIRNG SUPER-BARRIER RECTIFIERS - A process for manufacturing a semiconductor device, wherein a semiconductor layer is formed on a body of semiconductor material; a first mask is formed on the semiconductor layer; a first conductive region is implanted in the body using the first mask; a second mask is formed laterally and complementarily to the first mask, at least in a projection in a plane parallel to the surface of the body; a second conductive region is implanted in the body using the second mask, in an adjacent and complementary position to the first conductive region; spacers are formed on the sides of the second mask region, to form a third mask aligned to the second mask; and, using the third mask, portions of the semiconductor layer are removed to form a gate region. | 2014-03-27 |
20140087540 | METHOD FOR FORMING TRENCH ISOLATION - A trench isolation method is disclosed. A substrate having thereon a pad layer and a hard mask is provided. An opening is formed in the hard mask. The substrate is etched through the opening to thereby form a first trench. A spacer is formed on a sidewall of the first trench. A second trench is then etched into the substrate through the first trench by using the spacer as an etching hard mask. The substrate within the second trench is then oxidized by using the spacer as an oxidation protection layer, thereby forming an oxide layer that fills the second trench. The spacer is then removed to reveal the sidewall of the first trench. A liner layer is then formed on the revealed sidewall of the first trench. A chemical vapor deposition process is then performed to deposit a dielectric layer that fills the first trench. | 2014-03-27 |
20140087541 | Method for Manufacturing a Semiconductor Substrate, and Method for Manufacturing Semiconductor Devices Integrated in a Semiconductor Substrate - A method of manufacturing a semiconductor substrate includes providing a semiconductor wafer having a first surface and a second surface opposite the first surface, and forming, when seen in a cross-section perpendicular to the first surface, cavities in the semiconductor wafer at a first distance from the first surface. The cavities are laterally spaced from each other by partition walls formed by semiconductor material of the wafer. The cavities form a separation region. The method further includes forming a semiconductor layer on the first surface of the semiconductor wafer, and breaking at least some of the partition walls by applying mechanical impact to the partition walls to split the semiconductor wafer along the separation region. | 2014-03-27 |
20140087542 | SEMICONDUCTOR DIE SINGULATION APPARATUS AND METHOD - In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer. | 2014-03-27 |
20140087543 | METHOD FOR MANUFACTURING SOI SUBSTRATE AND SEMICONDUCTOR DEVICE - It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is another object of the present invention to provide a method for manufacturing a thin semiconductor device using such an SOI substrate with high yield. When a single-crystal semiconductor substrate is bonded to a flexible substrate having an insulating surface and the single-crystal semiconductor substrate is separated to manufacture an SOI substrate, one or both of bonding surfaces are activated, and then the flexible substrate having an insulating surface and the single-crystal semiconductor substrate are attached to each other. | 2014-03-27 |
20140087544 | TIN PRECURSORS FOR VAPOR DEPOSITION AND DEPOSITION PROCESSES - Sn-containing precursors for deposition of Sn-containing films and methods of using are provided herein. In some embodiments, Sn-containing precursors are methylated and/or hydrogenated and/or deuteriated. In some embodiments, methods of chemical vapor deposition are provided. | 2014-03-27 |
20140087545 | METHOD FOR PRODUCING A GROUP III NITRIDE SEMICONDUCTOR - The surface of a sapphire substrate having a c-plane main surface is patterned by ICP dry etching. The patterned sapphire substrate is thermally treated in a hydrogen or nitrogen atmosphere at a temperature of less than 700° C. or at a temperature of more than 800° C. to 1100° C. An AlN buffer layer is formed by magnetron sputtering on the surface on the patterned side of the sapphire substrate heated at a temperature of 200° C. to less than 700° C. On the buffer layer, a Group III nitride semiconductor layer having a c-plane main surface is formed so as to have a thickness of 1 μm to 10 μm by MOCVD. | 2014-03-27 |
20140087546 | Method and device for coating substrates - The invention relates to a method and device for coating plate-shaped substrates, in particular glass substrates for solar cell production. The method includes heating the substrates, which are moved on transporting shafts through heating and coating chambers, by a different amount on the upper and lower sides, so that the coating temperature can be increased without the substrates becoming too soft to handle. A device is described which is suitable for carrying out the method and has heating and coating chambers, which have independent heating systems, as well as a transport system. | 2014-03-27 |
20140087547 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ANNEALING DEVICE, AND ANNEALING METHOD - According to one embodiment, the manufacturing method for the semiconductor device according to the embodiment includes carrying out ion implantation to the semiconductor layer and forming an amorphous layer on the surface of the semiconductor layer, and a heat treatment process using microwave annealing at a temperature higher than or equal to 200° C. and lower than or equal to 700° C. and single crystallizes the amorphous layer. | 2014-03-27 |
20140087548 | METHOD OF SHIELDING THROUGH SILICON VIAS IN A PASSIVE INTERPOSER - A method of shielding through silicon vias (TSVs) in a passive interposer includes doping a substrate with positive ions, and implanting positive ions in an upper portion of the substrate, such that the substrate has at least a p-doped portion and a heavily p-doped upper portion. The method further includes forming an interlayer dielectric (ILD) above the heavily p-doped upper portion. The method further includes forming a plurality of through silicon vias (TSVs) through the ILD and the substrate, such that the passive interposer is configured to electrically couple at least one structure above and below the passive interposer. The method further includes forming, between pairs of TSVs of the plurality of TSVs, a plurality of shielding lines through the interlayer dielectric, the shielding lines configured to electrically couple the heavily p-doped upper portion of the substrate and at least one interconnect structure above the ILD. | 2014-03-27 |
20140087549 | METHOD FOR FORMING PATTERNED DOPING REGIONS - A method for forming doping regions is disclosed, including providing a substrate, forming a first-type doping material on the substrate and forming a second-type doping material on the substrate, wherein the first-type doping material is separated from the second-type doping material by a gap; forming a covering layer to cover the substrate, the first-type doping material and the second-type doping material; and performing a thermal diffusion process to diffuse the first-type doping material and the second-type doping material into the substrate. | 2014-03-27 |
20140087550 | METHODS OF MAKING SEMICONDUCTOR DEVICES WITH LOW LEAKAGE SCHOTKYCONTACTS - Embodiments include methods of making semiconductor devices with low leakage Schottky contacts. An embodiment includes providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced. | 2014-03-27 |
20140087551 | ETCHING POLYSILICON - Methods and compositions for etching polysilicon including aqueous compositions containing nitric acid and ammonium fluoride, and apparatus formed thereby. | 2014-03-27 |
20140087552 | METHOD OF FORMING A CONDUCTIVE POLYMER MICROSTRUCTURE - The present disclosure relates to microstructure devices, in which a conductive pattern is formed on the basis of a conductive polymer material. In order to avoid the deposition and processing of the sacrificial materials and reduce a negative influence of the lithography process on sensitive conductive polymer materials a one-layer patterning sequence is proposed, in which a trench pattern is formed in a dielectric material that is subsequently filled with the conductive polymer material. | 2014-03-27 |
20140087553 | Fabricating a Wafer Level Semiconductor Package Having a Pre-formed Dielectric Layer - There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process. | 2014-03-27 |
20140087554 | METHODS FOR FORMING ARRAYS OF SMALL, CLOSELY SPACED FEATURES - Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed patterns of crossing elongate features with pillars at the intersections. Spacers are simultaneously applied to sidewalls of both sets of crossing lines to produce a pitch-doubled grid pattern. The pillars facilitate rows of spacers bridging columns of spacers. | 2014-03-27 |
20140087555 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including a cell region and a core region adjacent to the cell region, active regions in the cell region and the core region, an interlayer insulating layer covering the active regions, upper cell contacts penetrating the interlayer insulating layer in the cell region, the upper cell contacts being adjacent to each other along a first direction and being electrically connected to the active regions, and core contacts penetrating the interlayer insulating layer in the active regions of the core region, the core contacts being adjacent to each other along the first direction and including upper connection core contacts electrically connected to the active regions, and dummy contacts adjacent to the upper connection core contacts, the dummy contacts being insulated from the active regions. | 2014-03-27 |
20140087556 | METHOD OF MANUFACTURING WIRING SUBSTRATE - A method of manufacturing a wiring substrate, includes, forming an etching stop layer and a first wiring layer on a supporting member, forming a first insulating layer on the first wiring layer, forming a via hole reaching the first wiring layer, and forming the wiring layers of an n-layer and the insulating layers of an n-layer, removing the supporting member and the etching stop layer, thereby forming a build-up intermediate body, forming a second insulating layer on the wiring layer of an n-th layer, and forming a third insulating layer on first wiring layer, forming a via hole reaching the wiring layer of the n-th layer, and forming a via hole reaching the first wiring layer, forming a roughened face to the third insulating layer, and forming a second wiring layer connected to the wiring layer, and forming a third wiring layer connected to the first wiring layer. | 2014-03-27 |
20140087557 | THROUGH SILICON VIA WAFER, CONTACTS AND DESIGN STRUCTURES - Disclosed herein are through silicon vias (TSVs) and contacts formed on a semiconductor material, methods of manufacturing, and design structures. The method includes forming a contact hole in a dielectric material formed on a substrate. The method further includes forming a via in the substrate and through the dielectric material. The method further includes lining the contact hole and the dielectric material with a metal liner using a deposition technique that will avoid formation of the liner in the viaformed in the substrate. The method further includes filling the contact hole and the via with a metal such that the metal is formed on the liner in the contact hole and directly on the substrate in the via. | 2014-03-27 |
20140087558 | Methods of Forming Memory Cells; and Methods of Forming Vertical Structures - Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions. | 2014-03-27 |
20140087559 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME - A method for forming a semiconductor structure and a method for patterning a dielectric layer are provided. The method comprises following steps. An upper cap layer is formed on and physically contacted with a dielectric layer. The dielectric layer has a dielectric thickness having a range of 1000 Ř5000 Å. A patterned mask layer is formed on and physically contacted with the upper cap layer. A part of the upper cap layer is removed to form a patterned upper cap layer by using the patterned mask layer as an etching mask. A part of the dielectric layer is removed to form a dielectric opening in the dielectric layer by using the patterned upper cap layer as an etching mask. | 2014-03-27 |
20140087560 | METHOD OF DEPOSITING METALLIC LAYERS BASED ON NICKEL OR COBALT ON A SEMICONDUCTING SOLID SUBSTRATE; KIT FOR APPLICATION OF SAID METHOD - The present invention relates to a kit intended for the deposition of nickel or cobalt in the cavities of a semiconductor substrate intended to form through-silicon vias (TSV) for making interconnections in integrated circuits in three dimensions. | 2014-03-27 |
20140087561 | METHOD AND APPARATUS FOR SUBSTRATE TRANSFER AND RADICAL CONFINEMENT - Embodiments of the present invention provide an apparatus for transferring substrates and confining a processing environment in a chamber. One embodiment of the present invention provides a hoop assembly for using a processing chamber. The hoop assembly includes a confinement ring defining a confinement region therein, and three or more lifting fingers attached to the hoop. The three or more lifting fingers are configured to support a substrate outside the inner volume of the confinement ring. | 2014-03-27 |
20140087562 | METHOD FOR PROCESSING SILICON SUBSTRATE AND METHOD FOR PRODUCING CHARGED-PARTICLE BEAM LENS - A method for processing a silicon substrate includes forming a mask layer on the silicon substrate; forming a hole is farmed in the silicon substrate by alternately repeating (i) an etching step in which plasma etching is performed in a thickness direction of the silicon substrate using the mask layer as a mask and (ii) a deposition step in which a protection film is deposited on an inner wall of the hole formed in the etching step; removing the protection film; and a planarizing a side wall of the hole by etching the inner wall of the hole from which the protection film has been removed. The mask layer includes a material that withstands the removal step. In the planarization step, the inner wall of the hole is etched using the mask layer as a mask. | 2014-03-27 |
20140087563 | METHOD FOR POSITIONING SPACERS IN PITCH MULTIPLICATION - Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed. | 2014-03-27 |
20140087564 | PLASAMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - Provided is a plasma processing apparatus, which includes a table unit installed within a processing vessel and configured to place a substrate thereon, a purge gas supply unit configured to supply a process gas into the processing vessel, a plasma generating unit configured to turn the process gas to plasma, a magnetic field forming mechanism installed at a lateral side of the table unit and configured to form magnetic fields in a processing atmosphere in order to move electrons existing in the plasma of the process gas along a surface of the substrate; and an exhaust mechanism configured to exhaust gas from the interior of the processing vessel. The magnetic fields are opened at at-least one point in a peripheral edge portion of the substrate such that a loop of magnetic flux lines surrounding the peripheral edge portion of the substrate is not formed. | 2014-03-27 |
20140087565 | Method of Manufacturing Semiconductor Device, Substrate Processing Apparatus, and Non-Transitory Computer Readable Recording Medium - A method of manufacturing a semiconductor device includes forming thin films on substrates by performing a cycle a predetermined number of times. The cycle includes: supplying a process gas into a process container and confining the gas in the container including an outer reaction tube and an inner reaction tube having a flat top inner surface at an upper end portion covering a portion of a top surface of the support arranging and supporting the substrates and including a communication section connecting an inside of the inner reaction tube to an inside of the outer reaction tube, wherein the communication section is disposed at a region other than a region horizontally encompassing a substrate arrangement region; maintaining a state where the gas is confined in the container; and exhausting the gas from the container via the communication section and a space between the inner and outer reaction tubes. | 2014-03-27 |
20140087566 | PATTERN FORMATION METHOD - A pattern formation method comprises a process of forming a resist pattern with an opening that exposes a first region of a glass film arranged on a substrate through a base film; a process of forming a neutralization film above the glass film; a process of forming a directed self-assembly material layer containing a first segment and a second segment above the glass film; a process of microphase separating the directed self-assembly material layer to form a directed self-assembly pattern containing a first part that includes the first segment and a second part that includes the second segment; and a process of removing either the first part or the second part and using the other as a mask to process the base film. | 2014-03-27 |
20140087567 | SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a substrate processing apparatus including: a substrate mounting portion provided in a process chamber and capable of mounting a plurality of substrates in a circumferential direction; a rotating mechanism that rotates the substrate mounting portion at a predetermined angular velocity; dividing structures provided in a radial form from a center of a lid of the process chamber so as to divide the process chamber into a plurality of areas; and gas supply areas disposed between the adjacent dividing structures, wherein an angle between the adjacent dividing structures with one gas supply area interposed is set to an angle corresponding to the angular velocity and a period in which a portion of the substrate mounting portion passes through the gas supply area. | 2014-03-27 |
20140087568 | METHOD OF CLEANING, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - A method of cleaning an interior of a process chamber by supplying a cleaning gas into the process chamber after a process of forming a thin film on a substrate in the process chamber is performed, including alternately repeating changing a pressure in the process chamber from a first pressure range to a second pressure range, and changing the pressure in the process chamber from the second pressure range to the first pressure range. In this method, when the pressure in the process chamber is changed to the first pressure range, the pressure in the process chamber is changed to the first pressure range without being maintained at the second pressure range, and when the pressure in the process chamber is changed to the second pressure range, the pressure in the process chamber is changed to the second pressure range without being maintained at the first pressure range. | 2014-03-27 |
20140087569 | MAGNETIC-ENABLED CONNECTOR DEVICE - An electrical connector, which may be a multi-pin connector, includes magnetic elements and mechanical alignment elements which provide connective forces and precision alignment and orientation. The magnetic elements permit a user to bring male and female connector portions only into “rough” alignment before magnetic forces bring the portions into the correct position. Pin contacts on the connector portions extend only a small amount beyond respective protective annular openings and are thereby protected. Spring-biased pin elements may be included on one of the connector portions to bias the contact pins into engagement and create conductive paths when the portions are in a connected position. Paramagnetic or non-magnetic sheaths may surround the magnetic elements to focus, or distribute, magnetic forces. | 2014-03-27 |
20140087570 | CABLE EXIT METHODS FOR PCIE CARDS - The present disclosure is directed to an apparatus configured for providing a plurality of exit routes to a single type of cable. The apparatus includes a board configured to have a notch. The notch is dimensioned to have a first predetermined distance from a lowest edge of the notch to a pin A1 location on the board and a second predetermined distance from an edge of the board to the pin A1 location. The apparatus also includes a plurality of connectors configured for receiving a cable of the plurality of the single type of cable. Each cable is inserted into a respective connector, and each cable exits the board through the notch. The cable may exit the board through a plurality of routes without requiring changes to the dimension of the board or placement of the connectors. | 2014-03-27 |
20140087571 | CONNECTOR OF A LIGHT-EMITTING-DIODE LAMP TUBE - By a simple insertion operation, a connector forms electric conduction by contact, and is therefore applied to a fluorescent lamp tube, a power-saving lamp tube or a similar lamp tube. A light-emitting-diode lamp tube of the present invention includes a light module and two end caps. The connector connects the two end caps at two ends of the light module, and is composed of an insulator body, a conductive plate and a connection terminal. The insulator body includes an insertion slot, the connection terminal is disposed in the insertion slot to connect with the conductive plate, and includes two elastic terminal units. By inserting directly a conductive terminal of the end cap into the connector, and forming electric conduction by contact with each elastic terminal unit, electricity is transmitted, thereby constituting a structure that can be assembled easily, and parts thereof can be replaced and repaired by an ordinary person. | 2014-03-27 |
20140087572 | PLUG CONNECTOR FOR DIRECT CONTACTING ON A CIRCUIT BOARD - A plug connector for direct electrical contacting of contact surfaces on a circuit board includes at least one electrical end contact of an electric line inserted into the plug connector housing in a plug-in direction and at least one separate electrical contact element, which protrudes elastically beyond one housing side of the plug connector housing transversely to the end contact for electrical contacting of a contact surface of the circuit board and is in electrically conductive contact with the end contact, at least when the contact surface has been contacted. | 2014-03-27 |
20140087573 | Leading ground contact with the aid of a spring element - A plug connector for connecting to a complementary plug connector includes: at least one electrical contact element for connecting to an electrical contact element of the complementary plug connector; and a spring element electrically connected to a ground line of the plug connector. The plug connector is configured in such a way that during the connection of the plug connector to the complementary plug connector, the spring element electrically contacts a ground contact element of the complementary plug connector, before the electrical contact element of the plug connector contacts the electrical contact element of the complementary plug connector. | 2014-03-27 |
20140087574 | CONNECTOR HAVING A NUT-BODY CONTINUITY ELEMENT AND METHOD OF USE THEREOF - A connector having a nut-body continuity element is provided, wherein the nut-body continuity element electrically couples a nut and a connector body, thereby establishing electrical continuity between the nut and the connector body. Furthermore, the nut-body continuity element facilitates grounding through the connector, and renders an electromagnetic shield preventing ingress of unwanted environmental noise. | 2014-03-27 |
20140087575 | ELECTRICAL CONNECTOR WITH FLAME-RESISTANT INSERTS - An electrical connector includes at least one insert ( | 2014-03-27 |
20140087576 | ELECTRICAL CONNECTOR - An electrical connector, comprises: an insulative housing; a plurality of contacts received into the insulative housing and having a plurality of soldering portion extending rearwardly and beyond a rear surface of the insulative housing; a metallic shell enclosing the insulative housing; and a cover formed on a rear end of the insulative housing and the metallic shell and sealed the rear surface of the insulative housing. | 2014-03-27 |
20140087577 | PLUGGABLE SYSTEM AND OPTICAL TRANSCEIVER APPLICABLE TO PLUGGABLE SYSTEM - An optical transceiver and a pluggable system to enhance the reliability of the communication between the optical transceiver and the host system are disclosed. The rear of the housing of the transceiver provides a periodic structure, a plurality of hollows or a plurality of projections, arranged along the gasket provided in the host connector. Only portions of the periodic structure come in contact with the gasket, and the repulsive force caused by the gasket is consequently weakened to enhance the reliability of the mating of the plug in the optical transceiver with the host connector. The width of the hollows, or the pitch of the projections is set to be shorter than a quarter wavelength of a signal transmitted between the transceiver and the host system to reduce the EMI radiation leaking from the end of the transceiver. | 2014-03-27 |
20140087578 | CONNECTOR HAVING A NUT-BODY CONTINUITY ELEMENT AND METHOD OF USE THEREOF - A connector having a nut-body continuity element is provided, wherein the nut-body continuity element electrically couples a nut and a connector body, thereby establishing electrical continuity between the nut and the connector body. Furthermore, the nut-body continuity element facilitates grounding through the connector, and renders an electromagnetic shield preventing ingress of unwanted environmental noise. | 2014-03-27 |
20140087579 | CONNECTOR COMPONENT AND PORTABLE ELECTRONIC DEVICE HAVING THEREOF - A connector component that is used for connecting a first electronic device and a second electronic device via the connector component is provided. The connector component includes a first connection component, a second connection component and fixing element. The first connection component electronically extends from the first electronic device and has a fastening portion. The second connection component is disposed in the second electronic device. The fixing element is disposed in the second electronic device and is located next to the second connection component. When the first connection component is coupled to the second connection component, the fixing element is fastened with the fixing portion, so as to fix the first connection component to the second connection component. | 2014-03-27 |
20140087580 | CONNECTOR - Protection walls ( | 2014-03-27 |
20140087581 | POWER CONNECTOR - A power and data connector includes an extension that protrudes from a lip surface. The extension is configured to mate with an electronic device. A connection surface at a terminal end of the extension separately surrounds openings, through which power interfaces extend. | 2014-03-27 |
20140087582 | CONTACT HOUSING WITH POSITIONING MEANS FOR FIXING THE POSITION OF A CABLE THAT IS PRONE TO KINKING - A contact housing for a connector of a connector assembly extends through a wall and includes a contact region having a contact seat for receiving a contact-side end of a kink-prone cable. The connector may be for a sealed connector assembly that includes an outer housing, which has a cable inlet opening and an interior space, at least sections of which form a mating-connector receptacle for a mating connector that is complementary to the connector. At least sections of the contact housing of the connector are arranged in the interior space. The contact housing, which has the contact region having the contact seat for holding the contact-side end of the kink-prone cable, facilitates assembly of the connector and prevents damage to the kink-prone cable, and includes positioning means for fixing the position of a laced section of the kink-prone cable. | 2014-03-27 |
20140087583 | WIRE HOLDER SUPPORT - A wire holder ( | 2014-03-27 |
20140087584 | ELECTRICAL CONTACTOR ARRANGEMENT WITH THERMAL MANAGEMENT - A power distribution contactor mount, and a power distribution system incorporating the same, include a plurality of electrically and thermally conductive contactor posts operable to connect a contactor lead to a bus bar, a mounting panel face, wherein each of the contactor posts is received in the mounting panel face and extends through the mounting panel face, and a first heat dissipation component mounted on the mounting panel face and thermally connected to each of the contactor posts. The thermal connection is via a thermally conductive and electrically insulative polymer insert, and each of the posts protrudes through the first heat dissipation component. | 2014-03-27 |
20140087585 | GENERATING A SYNTHETIC TACTILE SENSATION IN A CONNECTOR - A method and apparatus are described for generating a synthetic tactile sensation in a connector in an electronic device. In the described embodiments, a sensor is coupled to a receptacle for the connector and configured to sense a mating of the receptacle and a plug for the connector. An actuator is coupled to the receptacle, and a processing subsystem is coupled to the sensor and the actuator and configured to use the actuator to generate a synthetic tactile sensation based on information received from the sensor. | 2014-03-27 |
20140087586 | SECURING OPPOSING COMPONENTS TO A CIRCUIT BOARD - According to embodiments of the invention, an assembly having first and second components may be provided. The first component may include one or more connectors corresponding to one or more through-holes of a circuit board. The second component may include one or more receptacles to fixedly receive the connectors, wherein the first and second components are adapted to be located on opposing sides of the circuit board in an assembled position. In some embodiments, the first and second components may include electrical connectors soldered to the circuit board. In some embodiments, the connectors may include one or more pawls and the receptacles may include one or more ratchets. In other embodiments, the connectors may be threaded members and the receptacles may be threaded apertures. | 2014-03-27 |
20140087587 | High Temperature Electrode Connections - Embodiments include a high temperature electrode connection assembly for a wafer-processing pedestal. The high temperature electrode connection assembly includes an electrode rod having a cup that mounts to a stud embedded in the pedestal and a plate adapter portion. The assembly also includes a floating plate having an outer surface and an aperture for receiving the electrode rod. The floating plate contacts an inner surface of the pedestal to resist lateral movement of the electrode rods. The assembly also includes an anti-rotation retainer ring that frictionally engages the electrode rod and an anti-rotation post extending from the outer surface of the floating plate. The anti-rotation post limits rotation of the electrode rod with respect to the floating plate. | 2014-03-27 |
20140087588 | CONNECTOR HAVING A NUT-BODY CONTINUITY ELEMENT AND METHOD OF USE THEREOF - A connector having a nut-body continuity element is provided, wherein the nut-body continuity element electrically couples a nut and a connector body, thereby establishing electrical continuity between the nut and the connector body. Furthermore, the nut-body continuity element facilitates grounding through the connector, and renders an electromagnetic shield preventing ingress of unwanted environmental noise. | 2014-03-27 |
20140087589 | ELECTRICAL CONNECTOR - An electrical connector ( | 2014-03-27 |
20140087590 | Vertical Contact for Shielded Sockets - A conductive contact includes a hollow cylinder, a spring strip and a contact head. | 2014-03-27 |
20140087591 | BUSBAR PLATE - A busbar plate includes a busbar plate main body and total plus/minus terminal blocks. The busbar plate main body includes a terminal accommodating chamber part having a plurality of terminal accommodating chambers. The total plus/minus terminal blocks are externally attached to terminal accommodating chambers at two ends of the busbar plate respectively, and are formed of terminal block main bodies and busbars. One ends of the busbars are fastened to total plus/minus terminals in the terminal accommodating chambers at the two ends, the other ends of the busbars are fastened to an adjacent module or a connecting busbar of an external equipment. Flexible resin material is used for the busbar plate main body, and high strength resin material is used for the terminal block main bodies. | 2014-03-27 |
20140087592 | CONNECTOR TERMINAL - A connector terminal includes a first contact at one end, a second contact at the other end, and a buffer portion, the connector terminal electrically connecting a first object connected to the first contact to a second object connected to the second object, the buffer portion being bent in accordance with a positional gap between the first and second objects, the buffer portion having a cross-sectional area smaller than the same of the first and second contacts. | 2014-03-27 |
20140087593 | ELECTRICAL CONNECTOR - Electrical connectors are disclosed. One electrical connector comprises a receptacle component and a plug component. The receptacle component includes a receptacle body portion having a pair of opposed walls defining a gap therebetween. The pair of opposed walls each having one or more openings in their respective ends. | 2014-03-27 |
20140087594 | ELECTRICAL CONNECTOR HAVING A CONNECTOR STANDOFF - An electrical connector comprises a connector body. The connector body includes an insulative housing and a contact module received in the insulative housing. The contact module includes a spacer and a plurality of contacts received in the spacer. Each of the contacts have a foot portion for being mounted onto an external printed circuit board. The insulative housing has a plurality of mating ports defined in a vertical front face. The electrical connector also includes a connector standoff assembled under the connector body to support the connector body. The connector standoff includes a base portion and four locking arms extending from the base portion along a down-to-up direction, and two of the locking arms engage with the spacer. The foot portion extends downwardly through the connector standoff | 2014-03-27 |
20140087595 | ELECTRICAL CONNECTOR - Electrical connectors are disclosed. A component for an electrical connector includes a body portion, a pair of first metal contacts, and a second metal contact. The pair of first metal contacts are coupled to the body portion. The first metal contacts each have first ends extending in a first direction and second ends extending from the body portion in a direction opposite the first direction. The second metal contact is coupled to the body portion. The second metal contact has a first end extending in the first direction and a pair of second ends extending from the body portion in the direction opposite the first direction. Each second end of the second metal contact is aligned with a respective second end of the first metal contacts in a direction perpendicular to the first direction. The component may be configured as a plug component or as a receptacle component. | 2014-03-27 |
20140087596 | ANTENNA MOUNT AND ITS PROTECTIVE MODULE - An antenna mount includes a main member, a first contacting member, a second contacting member, and a driving member. The main member has a chamber therein to receive the first contacting member, the second contacting member and the driving member. The first contacting member electrically connects to a signal wire of a cable for signal transmission, and the main member electrically connects to a ground wire of the cable. Two ends of the second contacting member are respectively connected to the main member and contacted with the first contacting member, wherein the second contacting member has a predetermined resistance. Once a connector of an antenna is engaged, the driving member is moved to separate the second contacting member and the first contacting member; and when the connector of the antenna is disengaged, the second contacting member contacts with the first contacting member again as a protective circuit. | 2014-03-27 |
20140087597 | CONNECTION TERMINAL AND METHOD FOR MANUFACTURING CONNECTION TERMINAL - A connection terminal includes a terminal connection portion to be connected with a partner terminal, a wire connection portion connected with a wire, a neck portion connecting the terminal connection portion and the wire connection portion, and a resin covering portion covering a connection portion of the wire connection portion and the wire. The neck portion has a bottom wall and a pair of side walls installed upright from both sides of the bottom wall and having parallel wall portions equally spaced from each other. | 2014-03-27 |
20140087598 | Split Bolt Electrical Connector Assembly - An electrical connector includes a split bolt having a base and first and second outwardly extending legs. A conductor receiving channel is formed between the legs. A nut threadably engages the legs and has upper and lower surfaces and an opening through it. A pressure bar member is movably received in the conductor receiving channel. A head of the pressure bar member contacts the lower surface of the nut and a body of the pressure bar member extends through the opening in the nut. A spacer is disposed in the conductor receiving channel between the base and the head of the pressure bar member. | 2014-03-27 |
20140087599 | FIELD DEVICE WITH IMPROVED TERMINATIONS - A field device is provided. The field device includes field device electronics configured to couple to a transducer. A plurality of terminals is coupled to the field device electronics and is configured to couple the field device to a process communication loop to allow the field device to communicate over the process communication loop. Each of the plurality of terminals is configured to support multiple conductor attachment types. | 2014-03-27 |
20140087600 | FUSE HOLDER AND FUSE CLIP ASSEMBLY WITH DUAL DIRECTIONAL BIAS ELEMENT SUPPORT - Fuse holders having a fuse clip assembly configured to support resilient fuse clip arms when subjected to a compression force and also configured to support the resilient fuse clip arms when subject to an expansion force. The bias element is movable relative to the fuse clip arms between first and second positions and prevents deformation of the fuse clip arms. | 2014-03-27 |
20140087601 | ELECTRICAL TERMINAL - An electrical terminal includes a contact portion having a contact portion base with at least three sides forming a generally polyhedron structure. The contact portion has a plurality of contact arms, with at least one of the contact arms extending from at least some of the sides. The contact arms are arranged to receive a mating electrical component such that the mating electrical component contacts at least one of the contact arms associated with each side. A spring arrangement includes a plurality of spring arms, each having a spring head in contact with at least one respective contact arm near a distal end of the contact portion for applying a force thereto in a direction toward a central axis of the terminal, thereby increasing the retention force applied to the mating electrical component. | 2014-03-27 |
20140087602 | ELECTRICAL TERMINAL - An electrical terminal includes a contact portion having a contact portion base with at least three sides forming a generally polyhedron structure. At least one contact arm extends from at least some of the sides, and are arranged to receive a mating electrical component. A spring arrangement includes a plurality of spring arms extending from a spring base. Each of the spring arms includes a spring head in contact with at least one respective contact arm near a distal end of the contact portion for applying a force thereto in a direction toward a central axis of the terminal. The spring base includes a support structure configured to support the mating electrical component. | 2014-03-27 |
20140087603 | HERMAPHRODITIC ELECTRICAL CONNECTOR FOR TERMINATING ELECTRICAL CONDUCTORS - An electrical connector provides for terminating an electrical conductor. The connector includes an elongate connector body having an elongate barrel portion for accommodating one end of an electrical conductor. A transition portion extends from the barrel portion. A connection portion extends from the transition portion. The connection portion has an elongate aperture therethrough and an extending projection adjacent the aperture. The projection of one connector body is insertable into the aperture of another identically formed connector body so as to place the one connector body in electrical engagement with the other connector body. | 2014-03-27 |
20140087604 | Single Core Electric Wire and Terminal Crimping Structure of Single Core Electric Wire - Herein disclosed is a technique that suppresses the decrease of a contact pressure due to creep in a crimping part of a single core electric wire and a terminal. A single core electric wire | 2014-03-27 |
20140087605 | CONTACT MEMBER - A contact member includes first and second bent portions provided between a joining part to be joined to a first board and a contacting part to come into contact with a second board, a first contact part to come into contact with the second bent portion when the first bent portion is caused to bend by the pressing of the contacting part by the second board, a second contact part to come into contact with the first bent portion when the second bent portion is caused to bend by the pressing of the contacting part by the second board after the first contact part comes into contact with the second bent portion, and a third contact part to come into contact with the first board by the pressing of the contacting part by the second board after the second contact part comes into contact with the first bent portion. | 2014-03-27 |
20140087606 | COPPER ALLOY FOR ELECTRONIC/ELECTRIC DEVICE, COPPER ALLOY THIN PLATE FOR ELECTRONIC/ELECTRIC DEVICE, METHOD OF PRODUCING COPPER ALLOY FOR ELECTRONIC/ELECTRIC DEVICE, CONDUCTIVE COMPONENT FOR ELECTRONIC/ELECTRIC DEVICE AND TERMINAL - What is provided is a copper alloy for electronic/electric device comprising: in mass %, more than 2% and 36.5% or less of Zn; 0.1% or more and 0.9% or less of Sn; 0.05% or more and less than 1.0% of Ni; 0.001% or more and less than 0.10% of Fe; 0.005% or more and 0.10% or less of P; and the balance Cu and inevitable impurities, wherein a content ratio of Fe to Ni, Fe/Ni satisfies 0.002≦Fe/Ni<1.5, a content ratio of a sum of Ni and Fe, (Ni+Fe), to P satisfies 3<(Ni+Fe)/P<15, a content ratio of Sn to a sum of Ni and Fe, (Ni+Fe) satisfies 0.32014-03-27 | |
20140087607 | TERMINAL FITTING - Provided is a terminal fitting capable of making an electric contact portion and a cap member retained at the electric contact portion to be reliably engaged together. A terminal fitting includes an electric contact portion provided at one end side and formed into a tube-like shape such that a mating terminal is fitted thereto, an electric wire connection portion provided at the other end side and arranged to fasten an electric wire, and a cap member fitted to a distal end of the electric contact portion and retained at the distal end. A first engagement portion arranged to engage with the cap member is provided at the distal end of the electric contact portion, and the cap member is provided with a second engagement portion arranged to engage with the first engagement portion. | 2014-03-27 |
20140087608 | PROP SHAFT HOLDER FOR OUTBOARD MOTOR - A prop shaft holder for an outboard motor includes a forward end for engaging a gear casing of the outboard motor and a rearward end axially spaced apart from the forward end. The rearward end includes an inner radial surface for engaging an outer radial surface of a propeller. The prop shaft holder further includes a tapered surface extending from the forward end to the rearward end. The tapered surface includes a surface feature for inducing turbulent flow to water passing thereover. | 2014-03-27 |