13th week of 2013 patent applcation highlights part 16 |
Patent application number | Title | Published |
20130075739 | METHOD OF MANUFACTURING ELECTRONIC DEVICES ON BOTH SIDES OF A CARRIER SUBSTRATE AND ELECTRONIC DEVICES THEREOF - Some embodiments include a method of manufacturing electronic devices on both sides of a carrier substrate and electronic devices thereof. Other embodiments of related methods and structures are also disclosed. | 2013-03-28 |
20130075740 | P-TYPE OXIDE ALLOYS BASED ON COPPER OXIDES, TIN OXIDES, TIN-COPPER ALLOY OXIDES AND METAL ALLOY THEREOF, AND NICKEL OXIDE, WITH EMBEDDED METALS THEREOF, FABRICATION PROCESS AND USE THEREOF - The present invention relates to thin films comprising non-stoichiometric monoxides of: copper (OCu | 2013-03-28 |
20130075741 | Lateral PNP Bipolar Transistor Formed with Multiple Epitaxial Layers - A lateral bipolar transistor with deep emitter and deep collector regions is formed using multiple epitaxial layers of the same conductivity type. Deep emitter and deep collector regions are formed without the use of trenches. Vertically aligned diffusion regions are formed in each epitaxial layer so that the diffusion regions merged into a contiguous diffusion region after annealing to function as emitter or collector or isolation structures. In another embodiment, a lateral trench PNP bipolar transistor is formed using trench emitter and trench collector regions. In yet another embodiment, a lateral PNP bipolar transistor with a merged LDMOS transistor is formed to achieve high performance. | 2013-03-28 |
20130075742 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes: a stacked body including a plurality of electrode layers and a plurality of insulating layers, which are alternately stacked, and diffusion suppressing layers each provided between each of the plurality of electrode layers and each of the plurality of insulating layers; and a memory film provided on a side wall of a hole penetrating the stacked body in a stacking direction. Each of the plurality of electrode layers is a first semiconductor layer containing a first impurity element. The diffusion suppressing layer is a second semiconductor layer containing a second impurity element which is different from the first impurity element. The diffusion suppressing layer is a film having an effect of suppressing diffusion of the first impurity element. | 2013-03-28 |
20130075743 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first device isolation insulating film defining a first region, a first conductive layer of a first conductivity type formed in the first region, a semiconductor layer formed above the semiconductor substrate and including a second conductive layer of the first conductivity type connected to the first conductive layer and a third conductive layer of the first conductivity type connected to the first conductive layer, a second device isolation insulating film formed in the semiconductor layer and isolating the second conductive layer and the third conductive layer from each other, a gate insulating film formed above the second conductive layer, and a gate electrode formed above the gate insulating film and electrically connected to the first conductive layer via the third conductive layer. | 2013-03-28 |
20130075744 | DISPLAY APPARATUS - Provided is a display apparatus using an organic EL device in which blur in a display image to be a problem for the display apparatus is reduced while propagating light propagating through a high-refractive-index transparent layer is efficiently extracted outside. The display apparatus has a configuration in which a high-refractive-index transparent layer is provided on a light exit side of the organic EL device, a light extraction structure is provided on the high-refractive-index transparent layer so as to surround each of subpixels, a visible light absorbing member is arranged between pixels adjacent to each other, and the visible light absorbing member is not arranged in a region between subpixels adjacent to each other within a pixel. | 2013-03-28 |
20130075745 | THIN-FILM SEMICONDUCTOR DEVICE, DISPLAY APPARATUS, AND METHOD FOR MANUFACTURING THIN-FILM SEMICONDUCTOR DEVICE - A thin-film semiconductor device includes: a first gate line; a metal line; a first gate electrode extending from the first gate line; a second gate electrode on the first gate electrode; an insulating layer provided in a crossing area where the first gate line and the metal line cross; and a second gate line formed in the same layer as the second gate electrode, and on the first gate line in other than the crossing area, wherein the metal line is on the insulating layer, the second gate line and the second gate electrode are thicker than the first gate line and the first gate electrode, and an interface between the metal line and the insulating layer is positioned above a top surface of the second gate electrode, in a cross section in a direction in which the first and second gate lines extend. | 2013-03-28 |
20130075746 | Lateral PNP Bipolar Transistor with Narrow Trench Emitter - A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches. | 2013-03-28 |
20130075747 | ESD PROTECTION USING LOW LEAKAGE ZENER DIODES FORMED WITH MICROWAVE RADIATION - Semiconductor devices and methods for making such devices are described. These devices contain a semiconductor substrate with a first portion containing an integrated circuit device connected to a gate pad in an upper portion of the substrate and a second portion containing a Zener diode having a ESD rating up to about 10000 Volts, where the Zener diode is located around the periphery of the substrate. MW radiation can be used to form a single crystal Si material in a trench of the Zener diode | 2013-03-28 |
20130075748 | METHOD AND SYSTEM FOR DIFFUSION AND IMPLANTATION IN GALLIUM NITRIDE BASED DEVICES - A method of forming a doped region in a III-nitride substrate includes providing the III-nitride substrate and forming a masking layer having a predetermined pattern and coupled to a portion of the III-nitride substrate. The III-nitride substrate is characterized by a first conductivity type and the predetermined pattern defines exposed regions of the III-nitride substrate. The method also includes heating the III-nitride substrate to a predetermined temperature and placing a dual-precursor gas adjacent the exposed regions of the III-nitride substrate. The dual-precursor gas includes a nitrogen source and a dopant source. The method further includes maintaining the predetermined temperature for a predetermined time period, forming p-type III-nitride regions adjacent the exposed regions of the III-nitride substrate, and removing the masking layer. | 2013-03-28 |
20130075749 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An embodiment of a compound semiconductor device includes: a substrate; an electron channel layer and an electron supply layer formed over the substrate; a gate electrode, a source electrode and a drain electrode formed on or above the electron supply layer; a first p-type semiconductor layer formed between the electron supply layer and the gate electrode; and a second p-type semiconductor layer formed between the electron supply layer and at least one of the source electrode and the drain electrode. The one of the source electrode and the drain electrode on the second p-type semiconductor layer includes: a first metal film; and a second metal film Which contacts the first metal film on the gate electrode side of the first metal film, and a resistance of which is higher than that of the first metal film. | 2013-03-28 |
20130075750 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer formed on a substrate; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; a gate electrode formed on the third semiconductor layer; and a source electrode and a drain electrode formed on the second semiconductor layer. The third semiconductor layer is formed with a semiconductor material doped with a p-type impurity element. In the third semiconductor layer, a p-type area is formed immediately below the gate electrode, and a high resistance area having a higher resistance than the p-type area is formed in an area other than the p-type area. | 2013-03-28 |
20130075751 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An embodiment of a compound semiconductor device includes: a substrate; an electron channel layer and an electron supply layer formed over the substrate; a gate electrode, a source electrode and a drain electrode formed on or above the electron supply layer; a p-type semiconductor layer formed between the electron supply layer and the gate electrode; and a hole barrier layer formed between the electron supply layer and the p-type semiconductor layer, a band gap of the hole barrier layer being larger than that of the electron supply layer. | 2013-03-28 |
20130075752 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a first semiconductor layer formed on a substrate; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; a gate electrode formed on the third semiconductor layer; and a source electrode and a drain electrode formed in contact with the second semiconductor layer, wherein a semiconductor material of the third semiconductor layer is doped with a p-type impurity element; and the third semiconductor layer has a jutting out region that juts out beyond an edge of the gate electrode toward a side where the drain electrode is provided. | 2013-03-28 |
20130075753 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate comprised of gallium nitride; an active layer provided on the substrate; a first buffer layer that is provided between the substrate and the active layer and is comprised of indium aluminum nitride (In | 2013-03-28 |
20130075754 | SEMICONDUCTOR DEVICE, FABRICATION METHOD OF THE SEMICONDUCTOR DEVICES - In a semiconductor device, a YAG substrate is formed as a single-crystal substrate of any of surface orientations (100), (110), and (111). In the fabrication of the semiconductor device, a TMAl gas is first fed onto the YAG substrate so as to form a nucleation layer made of aluminum, which is a group-III element. Then, an NH | 2013-03-28 |
20130075755 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a light emitting device and a manufacturing method thereof. The light emitting device comprises a first conductive semiconductor layer with a lower surface being uneven in height, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer. | 2013-03-28 |
20130075756 | SEMICONDUCTOR DEVICE AND METHOD FOR REDUCED BIAS THRESHOLD INSTABILITY - According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate. | 2013-03-28 |
20130075757 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to the present embodiment includes a diamond substrate having a surface plane inclined from a (100) plane in a range of 10 degrees to 40 degrees in a direction of <011> ±10 degrees, and an n-type diamond semiconductor layer containing phosphorus (P) and formed above the surface plane described above. | 2013-03-28 |
20130075758 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A MOSFET includes a semiconductor substrate having a trench formed in a main surface, a gate oxide film, a gate electrode, and a source interconnection. A semiconductor substrate includes an n-type drift layer and a p-type body layer. The trench is formed to penetrate the body layer and to reach the drift layer. The trench includes an outer peripheral trench arranged to surround an active region when viewed two-dimensionally. On the main surface opposite to the active region when viewed from the outer peripheral trench, a potential fixing region where the body layer is exposed is formed. The source interconnection is arranged to lie over the active region when viewed two-dimensionally. The potential fixing region is electrically connected to the source interconnection. | 2013-03-28 |
20130075759 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A first layer has n type conductivity. A second layer is epitaxially formed on the first layer and having p type conductivity. A third layer is on the second layer and having n type conductivity. ND is defined to represent a concentration of a donor type impurity. NA is defined to represent a concentration of an acceptor type impurity. D | 2013-03-28 |
20130075760 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present application relates to technology for improving a withstand voltage of a semiconductor device. The semiconductor device includes a termination area that surrounds a cell area. The cell area is provided with a plurality of main trenches. The termination area is provided with one or more termination trenches surrounding the cell area. A termination trench is disposed at an innermost circumference of one or more termination trenches. A body region is disposed on a surface of a drift region. Each main trench reaches the drift region. A gate electrode is provided within each main trench. The termination trench reaches the drift region. Sidewalls and a bottom surface of the termination trench are covered with a insulating layer. A surface of the insulating layer covering the bottom surface of the termination trench is covered with a buried electrode. A gate potential is applied to the buried electrode. | 2013-03-28 |
20130075761 | PHOTOELECTRIC CONVERSION DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a photoelectric conversion device including a substrate having opaque interconnection layers, an insulating film formed on the substrate, and having a plurality of openings, light-emitting elements formed of the openings, each light-emitting element having an upper electrode layer, and light-receiving elements formed of the openings, each light-receiving element having an upper electrode layer, wherein a semiconductor material is different in the light-emitting element and the light-receiving element, the upper electrode layer both of the light-emitting element and the light-receiving element are formed as common electrodes, and each interconnection layer is formed on a region outside a region specified by the opening. | 2013-03-28 |
20130075762 | OPTICALLY TRANSMISSIVE METAL ELECTRODE, ELECTRONIC DEVICE, AND OPTICAL DEVICE - According to one embodiment, an optically transmissive metal electrode includes a plurality of first and second metal wires. The first metal wires are disposed along a first direction, and extend along a second direction intersecting the first direction. The second metal wires are disposed along a third direction parallel with a plane including the first and second directions and intersecting the first direction, contact the first metal wires, and extend along a fourth direction parallel with the plane and intersecting the third direction. A first pitch between centers of the first metal wires is not more than a shortest wavelength in a waveband including visible light. A second pitch between centers of the second metal wires exceeds a longest wavelength in the waveband. A thickness of the first and second metal wires along a direction vertical to the plane is not more than the shortest wavelength. | 2013-03-28 |
20130075763 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING TOUCH SUBSTRATE - A display apparatus includes a first substrate including a plurality of pixels, and a second substrate facing the first substrate, the second substrate comprising a sensor area and a peripheral area, the sensor area comprising a plurality of sensors. The second substrate includes an insulating layer, and a plurality of lines disposed on the insulating layer corresponding to the peripheral area and connected to the sensors. A void is formed in the insulating layer between two adjacent lines of the plurality of lines at a boundary of the sensor area and the peripheral area. | 2013-03-28 |
20130075764 | OPTICAL MODULE PACKAGE STRUCTURE - An optical module package structure includes a light-emitting chip and a light sensor chip respectively installed in a first cavity and a second cavity in a substrate, a reflective layer coated on the periphery of the first cavity, two packaging adhesive structures respectively molded in the first cavity and the second cavity to encapsulate the light-emitting chip and the light sensor chip respectively, and a lid integrally formed on the substrate to enhance the airtightness of the whole optical module package structure. | 2013-03-28 |
20130075765 | INFRARED LIGHT-EMITTING DIODE AND TOUCH SCREEN - This invention discloses an infrared light-emitting diode. The infrared light-emitting diode comprises: only one core for emitting infrared light; a packaging body which at least comprises a first surface that is convex and in front of the core and a second surface that is plane and on one side of the core; and leads connected to the core and extending to outside of the packaging body; wherein the infrared light emitted by the core forms at least two beams of infrared light in different directions after being emitted from the packaging body through the first surface and the second surface. With such infrared LED and the touch screen, touch system and interactive display based on the LED, at least two beams of infrared light in different directions can be emitted requiring only one core. | 2013-03-28 |
20130075766 | THIN FILM TRANSISTOR DEVICE AND PIXEL STRUCTURE AND DRIVING CIRCUIT OF A DISPLAY PANEL - A thin film transistor device, disposed on a substrate, includes a gate electrode, a semiconductor channel layer, a gate insulating layer disposed between the gate electrode and the semiconductor channel layer, a source electrode and a drain electrode disposed at two opposite sides of the semiconductor channel layer and partially overlapping the semiconductor channel layer, respectively, a capacitor electrode at least partially overlapping the gate electrode, and a capacitor dielectric layer disposed between the capacitor electrode and the gate electrode. The capacitor electrode, the gate electrode and the capacitor dielectric layer form a capacitor device. | 2013-03-28 |
20130075767 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD OF THE SAME - The light emitting device | 2013-03-28 |
20130075768 | Organic Light Emitting Diode Display Device and Method of Fabricating the Same - In an organic light emitting diode (OLED) display device and a method for fabricating the same, OLED pixels are patterned through a photolithography process, so a large area patterning can be performed and a fine pitch can be obtained, and an organic compound layer can be protected by forming a buffer layer of a metal oxide on an upper portion of the organic compound layer or patterning the organic compound layer by using a cathode as a mask, improving device efficiency. In addition, among red, green, and blue pixels, two pixels are patterned through a lift-off process and the other remaining one is deposited to be formed without patterning, the process can be simplified and efficiency can be increased. | 2013-03-28 |
20130075769 | SELECTION OF PHOSPHORS AND LEDS IN A MULTI-CHIP EMITTER FOR A SINGLE WHITE COLOR BIN - An emitter for an LED-based lighting device has multiple groups of LEDs that are independently addressable, allowing the emitter to be tuned to a desired color bin (e.g., a specific white color) by adjusting the relative current supplied to different groups. The LED dies for the groups and a phosphor chip for each LED die are individually selected such that each LED-die/phosphor-chip combination produces light in a desired source region associated with the group to which the LED belongs. Robotic pick-and-place systems can be used to automate assembly of the emitters by selecting LED dies from a bin based on based on spectral characteristics and phosphor chips from a number of distinct phosphor chip types. | 2013-03-28 |
20130075770 | Method and System for Epitaxy Processes on Miscut Bulk Substrates - A method for providing (Al,Ga,In)N thin films on Ga-face c-plane (Al,Ga,In)N substrates using c-plane surfaces with a miscut greater than at least 0.35 degrees toward the m-direction. Light emitting devices are formed on the smooth (Al,Ga,In)N thin films. Devices fabricated on the smooth surfaces exhibit improved performance. | 2013-03-28 |
20130075771 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes first and second electrode layers, a and second semiconductor layers, a light emitting layer and a first intermediate layer. The first electrode layer has a metal portion having through-holes. The second electrode layer is stacked with the first electrode layer along a stacked direction, and light-reflective. The first semiconductor layer is provided between the first and second electrode layers, and has a first conductivity type. The second semiconductor layer is provided between the first semiconductor layer and the second electrode layer, and has a second conductivity type. The light emitting layer is provided between the first and second semiconductor layers. The first intermediate layer is provided between the second semiconductor layer and the second electrode layer, transmissive to light emitted from the light emitting layer, and includes first contact portions and a first non-contact portion. | 2013-03-28 |
20130075772 | LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a light-emitting device including (a) a layer structure obtained by sequentially growing on a base substrate a first compound semiconductor layer of a first conductivity type, (b) an active layer formed of a compound semiconductor, and (c) a second compound semiconductor layer of a second conductivity type; a second electrode formed on the second compound semiconductor layer; and a first electrode electrically connected to the first compound semiconductor layer. The layer structure formed of at least a part of the second compound semiconductor layer in a thickness direction of the second compound semiconductor layer. The first compound semiconductor layer has a thickness greater than 0.6 μm. A high-refractive index layer formed of a compound semiconductor material having a refractive index higher than a refractive index of a compound semiconductor material of the first compound semiconductor layer is formed in the first compound semiconductor layer. | 2013-03-28 |
20130075773 | LIGHT EMITTING DEVICE - An object of the present invention is to provide a light emitting device which increases the emission efficiency of phosphor by reducing self-absorption of light by phosphor and by reducing absorption of fluorescent light by an encapsulating resin, and which increases the efficiency of light extraction from the phosphor layer by preventing light scattering caused by the phosphor. | 2013-03-28 |
20130075774 | Light Converting And Emitting Device With Minimal Edge Recombination - Light emitting system ( | 2013-03-28 |
20130075775 | Multicolored Light Converting LED With Minimal Absorption - Light emitting systems are disclosed. More particularly light emitting systems that utilize wavelength converting semiconductor layer stacks, and preferred amounts of potential well types in such stacks to achieve more optimal performance are disclosed | 2013-03-28 |
20130075776 | LIGHT DISTRIBUTION CONTROLLER, LIGHT-EMITTING DEVICE USING THE SAME, AND METHOD FOR FABRICATING LIGHT DISTRIBUTION CONTROLLER - A light distribution controller of a light-emitting device includes a first optical member formed of ZnO disposed over an LED interposing a transparent adhesive, and a second optical member which covers the first optical member. The first optical member includes a first concave portion having an opening in a regular hexagon shape whose area gradually increases. In the first concave portion, inner wall surfaces having inclined surfaces, each of whose bases is formed by one side of the hexagon of the opening shape, are formed. Outside of the first optical member, outer wall surfaces each having a trapezoidal shape are formed. The second optical member includes a second concave portion arranged so that light at an annular peak in the light distribution characteristic of the light traveled through the first optical member is totally reflected. | 2013-03-28 |
20130075777 | Opto-electric device and method for manufacturing the same - A thin-film optoelectric device is disclosed comprising
| 2013-03-28 |
20130075778 | LIGHT-TRANSMITTING METAL ELECTRODE, ELECTRONIC APPARATUS AND LIGHT EMITTING DEVICE - According to one embodiment, a light-transmitting metal electrode includes a metal layer. The metal layer is provided on a major surface of a member and includes a metal nanowire and a plurality of openings formed with the metal nanowire. The thin layer includes a plurality of first straight line parts along a first direction and a plurality of second straight line parts along a direction different from the first direction. A maximum length of the first line parts along the first direction and a maximum length of the second line parts along the direction different from the first direction are not more than a wave length of visible light. A ratio of an area of the metal layer viewed in a normal direction of the surface to an area of the metal layer viewed in the normal direction is more than 20% and not more than 80%. | 2013-03-28 |
20130075779 | LIGHT EMITTING DIODE WITH MULTIPLE TRANSPARENT CONDUCTIVE LAYERS AND METHOD FOR MANUFACTURING THE SAME - A light emitting diode includes a first-type semiconductor layer, an active layer, a second-type semiconductor layer and a transparent, electrically conductive layer formed in sequence. The transparent, electrically conductive layer includes a first transparent, electrically conductive layer on the second-type semiconductor layer and a second transparent, electrically conductive layer on the first transparent, electrically conductive layer. Both the first and second transparent, electrically conductive layers are made of indium tin oxide, while the first transparent, electrically conductive layer has a smaller thickness. During formation of the transparent, electrically conductive layer, a mass flow of introduced oxygen gas to the first transparent conductive layer is lower than that to the second transparent conductive layer. | 2013-03-28 |
20130075780 | RADIATION HEAT DISSIPATION LED STRUCTURE AND THE MANUFACTURING METHOD THEREOF - Disclosed are a radiation heat dissipation LED structure and a manufacturing method thereof. The radiation heat dissipation LED structure includes a sapphire substrate, an LED epitaxy layer, a base substrate, a radiation heat dissipation film, and a thermally conductive binding layer provided between the sapphire substrate and the radiation heat dissipation film to bind the sapphire substrate and the base substrate. The radiation heat dissipation film consists of a mixture of metal and nonmetal. The surface of the film has a microscopic structure with crystal, which has high efficiency of heat dissipation and can fast transfer the heat generated by the LED epitaxy layer outwards through the base substrate by thermal radiation. Therefore, the working temperature of the LED epitaxy layer is greatly reduced so as to improve the efficiency of light emitting and the lifetime. | 2013-03-28 |
20130075781 | LED WITH HONEYCOMB RADIATING HEAT DISSIPATION DEVICE - An LED with a honeycomb radiating heat dissipation device includes a sapphire substrate, an LED epitaxy layer on the sapphire substrate, a thermally conductive binding layer, an intermediate heat dissipation layer, a base substrate and a honeycomb-like heat dissipation device. The thermally conductive binding layer is provided to bind the sapphire substrate and the intermediate heat dissipation layer. The honeycomb-like heat dissipation device is in contact with the base substrate and includes a heat dissipation body and holes, each having a sidewall covered with a thermally radiative heat dissipation film. The intermediate heat dissipation layer and the thermally radiative heat dissipation film is made from a mixture of metal and nonmetal and has a microscopic surface structure with specific crystal, so as to provide high efficiency of heat dissipation by thermal radiation. | 2013-03-28 |
20130075782 | Light Emitting Element, Light Emitting Device, and Electronic Device - An object is to improve luminous efficiency of a light emitting element using triplet exciton energy effectively. Another object is to reduce power consumption of a light emitting element, a light emitting device, and an electronic device. Triplet exciton energy generated in a light emitting layer which exhibits short wavelength fluorescence can be effectively utilized by use of a structure in which the light emitting layers which exhibit short wavelength fluorescence are sandwiched between light emitting layers each including a phosphorescent compound. Further, the emission balance can be improved between the light emitting layer including a phosphorescent compound and the light emitting layer which exhibits fluorescence by the devising of the structure of the light emitting layer which exhibits fluorescence. | 2013-03-28 |
20130075783 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate, the semiconductor substrate comprising; an n type drift layer, a p type body layer on an upper surface side of the drift layer, and a high impurity n layer on a lower surface side of the drift layer. The high impurity n layer includes hydrogen ion donors as a dopant, and has a higher density of n type impurities than the drift layer. A lifetime control region including crystal defects as a lifetime killer is formed in the high impurity n layer and a part of the drift layer. A donor peak position is adjacent or identical to a defect peak position, at which a crystal defect density is highest in the lifetime control region in the depth direction of the semiconductor substrate. The crystal defect density in the defect peak position of the lifetime control region is 1×10 | 2013-03-28 |
20130075784 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a semiconductor substrate in which a diode region and an IGBT region are formed is provided. The diode region includes a first layer embedded in a diode trench reaching a diode drift layer from an upper surface side of the semiconductor substrate, and a second layer which is buried in the first layer and which has a lower end located deeper than a boundary between a diode body layer and the diode drift layer. The second layer pressures the first layer in a direction from inside to outside of the diode trench. A lifetime control region is formed in the diode drift layer at least at the depth of the lower end of the second layer, and a crystal defect density inside the lifetime control region is higher than a crystal defect density outside the lifetime control region. | 2013-03-28 |
20130075785 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - A semiconductor device includes a first semiconductor layer formed on a substrate, the first semiconductor containing an impurity element; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; and a gate electrode, a source electrode and a drain electrode that are formed on the third semiconductor layer. In the semiconductor device, the second semiconductor layer includes an impurity diffusion region in which an impurity element contained in the first semiconductor layer is diffused, the impurity diffusion region being located directly beneath the gate electrode and being in contact with the first semiconductor layer, and the impurity element causes the impurity diffusion region to be a p-type impurity diffusion region. | 2013-03-28 |
20130075786 | SEMICONDUCTOR DEVICE - A semiconductor device including a high resistance layer formed on a substrate, the high resistance layer being formed with a semiconductor material doped with an impurity element that makes the semiconductor material highly resistant; a multilayer intermediate layer formed on the high resistance layer; an electron transit layer formed with a semiconductor material on the multilayer intermediate layer; and an electron supply layer formed with a semiconductor material on the electron transit layer, wherein the multilayer intermediate layer is formed with a multilayer film in which a GaN layer and an AlN layer are alternately laminated. | 2013-03-28 |
20130075787 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An embodiment of a compound semiconductor device includes: a substrate; a compound semiconductor stacked structure formed over the substrate; and a gate electrode, a source electrode and a drain electrode formed on or above the compound semiconductor stacked structure. The compound semiconductor stacked structure includes: an electron channel layer; and a nitride semiconductor layer which includes an electron supply layer formed over the electron channel layer. An indium (In) fraction at a surface of the nitride semiconductor layer in each of a region between the gate electrode and the source electrode and a region between the gate electrode and the drain electrode is lower than an indium (In) fraction at a surface of the nitride semiconductor layer in a region below the gate electrode. | 2013-03-28 |
20130075788 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - A method for fabricating a semiconductor device is disclosed. The method includes sequentially forming a first semiconductor layer, a second semiconductor layer and a semiconductor cap layer containing a p-type impurity element on a substrate, forming a dielectric layer having an opening after the forming of the semiconductor cap layer, forming a third semiconductor layer containing a p-type impurity element on the semiconductor cap layer exposed from the opening of the dielectric layer, and forming a gate electrode on the third semiconductor layer. | 2013-03-28 |
20130075789 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device, comprising: a first semiconductor layer disposed on a substrate; a second semiconductor layer disposed on the first semiconductor layer; a lower insulating film disposed on the second semiconductor layer; a p-type electroconductive oxide film disposed on the lower insulating film; an upper insulating film disposed on the oxide film; and a gate electrode disposed on the upper insulating film, wherein the lower insulating film under the gate electrode has a depressed portion. | 2013-03-28 |
20130075790 | SEMICONDUCTOR INCLUDING LATERAL HEMT - A semiconductor including a lateral HEMT and to a method for production of a lateral HEMT is disclosed. In one embodiment, the lateral HEMT has a substrate and a first layer, wherein the first layer has a semiconductor material of a first conduction type and is arranged at least partially on the substrate. Furthermore, the lateral HEMT has a second layer, wherein the second layer has a semiconductor material and is arranged at least partially on the first layer. In addition, the lateral HEMT has a third layer, wherein the third layer has a semiconductor material of a second conduction type, which is complementary to the first conduction type, and is arranged at least partially in the first layer. | 2013-03-28 |
20130075791 | DEPLETED CHARGE-MULTIPLYING CCD IMAGE SENSOR - In various embodiments, a charge-coupled device includes channel stops laterally spaced away from the channel by fully depleted regions. | 2013-03-28 |
20130075792 | METAL-STRAPPED CCD IMAGE SENSORS - In various embodiments, image sensors include strapping grids of vertical and horizontal strapping lines conducting phase-control signals to underlying gate conductors that control transfer of charge within the image sensor. | 2013-03-28 |
20130075793 | FIELD EFFECT TRANSISTOR TYPE BIOSENSOR - Provided is a biosensor that makes it possible to detect the electrical properties of a bio-related material contained in an analyte fluid such as an aqueous solution placed on a sensitive membrane and to observe the bio-related material at a high magnification with an observation device such as a microscope. The biosensor comprises: a substrate | 2013-03-28 |
20130075794 | NANO-ELECTRONIC SENSORS FOR CHEMICAL AND BIOLOGICAL ANALYTES, INCLUDING CAPACITANCE AND BIO-MEMBRANE DEVICES - Embodiments of nanoelectronic sensors are described, including sensors for detecting analytes inorganic gases, organic vapors, biomolecules, viruses and the like. A number of embodiments of capacitive sensors having alternative architectures are described. Particular examples include integrated cell membranes and membrane-like structures in nanoelectronic sensors. | 2013-03-28 |
20130075795 | Aerogel dielectric layer - A circuit board assembly includes a circuit board, a chip attached to the circuit board and a dielectric layer. The chip has a circuit facing the circuit board and spaced from it. The dielectric layer includes an aerogel. In one embodiment, the aerogel has a dielectric constant of approximately 2.0 or less and a compression strength of at least approximately 100 psi. | 2013-03-28 |
20130075796 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method of fabricating a semiconductor device is disclosed. A dummy gate feature is formed between two active gate features over a substrate. An isolation structure is in the substrate and the dummy gate feature is over the isolation structure. In at least one embodiment, a non-conductive material is used for forming the dummy gate feature to replace a sacrificial gate electrode. | 2013-03-28 |
20130075797 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a semiconductor substrate, and a fin disposed on a surface of the semiconductor substrate and having a side surface of a (110) plane. The device further includes a gate insulator disposed on the side surface of the fin, and a gate electrode disposed on the side surface and an upper surface of the fin via the gate insulator. The device further includes a plurality of epitaxial layers disposed on the side surface of the fin in order along a height direction of the fin. | 2013-03-28 |
20130075798 | SEMICONDUCTOR DEVICE - A semiconductor device comprises: a MOS transistor connected between a power supply terminal and a ground terminal; a first diode connected between a drain and a gate of the MOS transistor; a second diode connected between the drain and the gate of the MOS transistor, in series with the first diode, and having a forward direction which is opposite to that of the first diode; and a capacitor connected between the drain and the gate of the MOS transistor, in series with the first diode and the second diode. | 2013-03-28 |
20130075799 | ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS - Disclosed is a pixel electrode which is electrically connected to a scanning line electrically connected to a gate electrode, a data line electrically connected to a data line side source and drain region, and a pixel electrode side source and drain region; and a capacitance element which has a first capacitance electrode which is electrically connected to a capacitance line, a second capacitance electrode which is provided to oppose the first capacitance electrode, and a dielectric layer which is interposed between the first capacitance electrode and the second capacitance electrode, where the first capacitance electrode is arranged to be covered with the dielectric layer and the second capacitance electrode between a layer where the transistor, the scanning line, and the data line are provided and a layer where the pixel electrode is provided. | 2013-03-28 |
20130075800 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - A semiconductor device manufacturing method includes loading a substrate to a processing chamber, a gate insulating film or a capacitor insulating film being formed on a surface of the substrate; forming an electrode, which includes a conductive oxide film and to which an additive that modulates a work function of the conductive oxide film is added, on the substrate; and unloading the substrate, on which the electrode is formed, from the processing chamber. | 2013-03-28 |
20130075801 | SELF-ADJUSTED CAPACITIVE STRUCTURE - A method for producing a capacitive structure in a semiconductor body includes forming a first trench in a first surface of the semiconductor body, forming a first dielectric layer on sidewalls and the bottom of the first trench, forming a first electrode layer on the first dielectric layer, forming at least one second trench by removing at least one part of the first dielectric layer to form a first gap in the first surface, and by widening the first gap, forming a second dielectric layer on sidewalls and the bottom of the at least one second trench, and forming a second electrode layer on the second dielectric layer. | 2013-03-28 |
20130075802 | CONTACT ARCHITECTURE FOR 3D MEMORY ARRAY - A vertical interconnect architecture for a three-dimensional (3D) memory device suitable for low cost, high yield manufacturing is described. Conductive lines (e.g. word lines) for the 3D memory array, and contact pads for vertical connectors used for couple the array to decoding circuitry and the like, are formed as parts of the same patterned level of material. The same material layer can be used to form the contact pads and the conductive access lines by an etch process using a single mask. By forming the contact pads concurrently with the conductive lines, the patterned material of the contact pads can protect underlying circuit elements which could otherwise be damaged during patterning of the conductive lines. | 2013-03-28 |
20130075803 | Flash-To-ROM Conversion - Flash-to-ROM conversion is performed by converting single transistor flash memory cells to single transistor ROM cells. An S-Flash memory cell is converted to a programmed ROM cell by introducing a threshold voltage implant into the channel region of the S-Flash memory cell. Alternately, an S-Flash memory cell is converted to a programmed ROM cell by introducing a threshold voltage implant into a substrate region in alignment with an edge of the gate electrode of the S-Flash memory cell. The width of the mask through which this threshold voltage implant is performed can be varied, such that the threshold voltage implant region can have different dopant concentrations, thereby allowing multiple bits to be represented by the programmed ROM cell. In another embodiment, a Y-flash memory cell is converted to a programmed ROM cell by adjusting the length of a floating gate extension region of the Y-Flash memory cell. | 2013-03-28 |
20130075804 | HIGH DENSITY SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided are a high density semiconductor memory device capable of precisely reading data by suppressing the occurrence of a leakage current due to the high-integration of the semiconductor memory device, and a method for manufacturing the semiconductor memory device. The high density semiconductor memory device includes: source and drain electrodes disposed over a substrate, and forming a Schottky junction with a channel region; and a floating gate disposed over the substrate of the channel region, and configured with a plurality of nanodots. The nanodots may be formed of a silicon compound or any material that can be charged. | 2013-03-28 |
20130075805 | METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a method for manufacturing a nonvolatile semiconductor storage device includes; forming a first and a second stacked bodies; forming a through hole penetrating through the first stacked body, a second portion communicating with the first portion and penetrating through a select gate, and a third portion communicating with the second portion and penetrating through a second insulating layer; forming a memory film, a gate insulating film, and a channel body; forming a third insulating layer inside the channel body; forming a first embedded portion above a boundary portion inside the third portion; exposing the channel body by removing part of the first embedded portion and part of the third insulating layer in the third portion; and embedding a second embedded portion including silicon having higher impurity concentration than the first embedded portion above the first embedded portion inside the third portion. | 2013-03-28 |
20130075806 | MULTI-GATE BANDGAP ENGINEERED MEMORY - Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation. | 2013-03-28 |
20130075807 | SEMICONDUCTOR MEMORY DEVICES HAVING SELECTION TRANSISTORS WITH NONUNIFORM THRESHOLD VOLTAGE CHARACTERISTICS - Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region. | 2013-03-28 |
20130075808 | Trench MOSFET with Integrated Schottky Barrier Diode - A Schottky diode includes a semiconductor layer formed on a semiconductor substrate; first and second trenches formed in the semiconductor layer where the first and second trenches are lined with a thin dielectric layer and being filled partially with a trench conductor layer and remaining portions of the first and second trenches are filled with a first dielectric layer; and a Schottky metal layer formed on a top surface of the semiconductor layer between the first trench and the second trench. The Schottky diode is formed with the Schottky metal layer as the anode and the semiconductor layer between the first and second trenches as the cathode. The trench conductor layer in each of the first and second trenches is electrically connected to the anode of the Schottky diode. In one embodiment, the Schottky diode is formed integrated with a trench field effect transistor on the same semiconductor substrate. | 2013-03-28 |
20130075809 | SEMICONDUCTOR POWER DEVICE WITH EMBEDDED DIODES AND RESISTORS USING REDUCED MASK PROCESSES - A trench semiconductor power device integrated with a Gate-Source and a Gate-Drain clamp diodes without using source mask is disclosed, wherein a plurality source regions of a first conductivity type of the trench semiconductor device and multiple doped regions of the first conductivity type of the clamp diodes are formed simultaneously through contact open areas defined by a contact mask. | 2013-03-28 |
20130075810 | SEMICONDUCTOR POWER DEVICES INTEGRATED WITH A TRENCHED CLAMP DIODE - A semiconductor power device having shielded gate structure integrated with a trenched clamp diode formed in a semiconductor silicon layer, wherein the shielded gate structure comprises a shielded electrode formed by a first poly-silicon layer and a gate electrode formed by a second poly-silicon layer. The trenched clamp diode is formed by the first poly-silicon layer. A shielded gate mask used to define the shielded gate is also used to define the trenched clamp diode. Therefore, one poly-silicon layer and a mask for the trenched clamp diode are saved. | 2013-03-28 |
20130075811 | DOUBLE GATE TRANSISTOR AND METHOD OF FABRICATING THE SAME - The present invention discloses a double gate transistor and a method of fabricating said transistor, said transistor comprising: a semiconductor layer on a substrate; a fin structure formed in said semiconductor layer, said fin structure having two end portions for forming source and drain regions and a middle portion between said two end portions for forming a channel region, said middle portion including two opposed side surfaces perpendicular to a substrate surface; a first gate dielectric layer and a first gate disposed on one side surface of said middle portion; and a second gate dielectric layer and a second gate disposed on the other side surface of said middle portion. | 2013-03-28 |
20130075812 | SINGLE-SIDED ACCESS DEVICE AND FABRICATION METHOD THEREOF - A single-sided access device includes an active fin structure comprising a source contact area and a drain contact area separated from each other by an isolation region therebetween; a trench isolation structure disposed at one side of the active fin structure, wherein the trench isolation structure intersects with the isolation region between the source contact area and the drain contact area; a sidewall gate disposed under the isolation region and on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by the trench isolation structure and the sidewall gate, wherein the sidewall gate has multi-fingers that engage with the active fin structure; and a gate dielectric layer between the sidewall gate and the active fin structure. | 2013-03-28 |
20130075813 | SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes the following processes. A first semiconductor structure is formed, which extends upwardly in a direction perpendicular to a main surface from a surface of a semiconductor substrate. A first insulating film is formed which extends on a surface of the first semiconductor structure. A gate electrode is formed which extends on the first insulating film. The gate electrode has a top surface which is lower than a top surface of the first semiconductor structure. A liner film is formed, which may include, but is not limited to, first and second liner portions. The first liner portion covers the gate electrode. The second liner portion extends upwardly from the top surface of the gate electrode. The liner film includes nitrogen and oxygen. | 2013-03-28 |
20130075814 | SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR VIA - A semiconductor device includes a semiconductor body having a first surface and a second surface, at least one electrode arranged in at least one trench extending from the first surface into the semiconductor body, and a semiconductor via extending in a vertical direction of the semiconductor body within the semiconductor body to the second surface. The semiconductor via is electrically insulated from the semiconductor body by a via insulation layer. The at least one electrode extends in a first lateral direction of the semiconductor body through the via insulation layer and is electrically connected to the semiconductor via. | 2013-03-28 |
20130075815 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a semiconductor substrate and a first semiconductor element provided on the semiconductor substrate. The first semiconductor element includes: a first semiconductor; a second semiconductor layer; a third semiconductor layer; a first insulating layer; a first base region; a first source region; a first gate electrode; a first drift layer; a first drain region; a first source; and a first drain electrode. A concentration of an impurity element of the first conductivity type included in the first drift layer is lower than a concentration of an impurity element of the first conductivity type included in the first semiconductor layer. The concentration of the impurity element of the first conductivity type included in the first drift layer is higher than a concentration of an impurity element of the first conductivity type included in the second semiconductor layer. | 2013-03-28 |
20130075816 | LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed are an LDMOS device and a method for manufacturing the same capable of decreasing the concentration of a drift region between a source finger tip and a drain, thereby increasing a breakdown voltage. An LDMOS device includes a gate which is formed on a substrate, a source and a drain which are separately arranged on both sides of the substrate with the gate interposed therebetween, a field oxide film which is formed to have a step between the gate and the drain, a drift region which is formed of first condition type impurity ions between the gate and the drain on the substrate, and at least one internal field ring which is formed inside the drift region and formed by selectively ion-implanting second conduction type impurity ions in accordance with the step of the field oxide film. | 2013-03-28 |
20130075817 | JUNCTIONLESS TRANSISTOR - A transistor includes a semiconductor layer, and a gate dielectric is formed on the semiconductor layer. A gate conductor is formed on the gate dielectric and an active area is located in the semiconductor layer underneath the gate dielectric. The active area includes a graded dopant region that has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer. This graded dopant region has a gradual decrease in the doping concentration. The transistor also includes source and drain regions that are adjacent to the active region. The source and drain regions and the active area have the same conductivity type. | 2013-03-28 |
20130075818 | 3D Semiconductor Device and Method of Manufacturing Same - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate and a 3D structure disposed over the substrate. The semiconductor device further includes a dielectric layer disposed over the 3D structure, a WFMG layer disposed over the dielectric layer, and a gate structure disposed over the WFMG layer. The gate structure traverses the 3D structure and separates a source region and a drain region of the 3D structure. The source and drain region define a channel region therebetween. The gate structure induces a stress in the channel region. | 2013-03-28 |
20130075819 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device includes an active section for a main current flow and a breakdown withstanding section for breakdown voltage. An external peripheral portion surrounds the active section on one major surface of an n-type semiconductor substrate. The breakdown withstanding section has a ring-shaped semiconductor protrusion, with a rectangular planar pattern including a curved section in each of four corners thereof, as a guard ring. The ring-shaped semiconductor protrusion has a p-type region therein, is sandwiched between a plurality of concavities deeper than the p-type region, and has an electrically conductive film across an insulator film on the surface thereof. Because of this, it is possible to manufacture at low cost a breakdown withstanding structure with which a high breakdown voltage is obtained in a narrow width, wherein there is little drop in breakdown voltage, even when there are variations in a patterning process of a field oxide film. | 2013-03-28 |
20130075820 | Superior Integrity of High-K Metal Gate Stacks by Forming STI Regions After Gate Metals - When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage, superior process robustness, reduced yield loss and an enhanced degree of flexibility in designing the overall process flow may be accomplished by forming and patterning the sensitive gate materials prior to forming isolation regions. | 2013-03-28 |
20130075821 | Semiconductor Device Comprising Replacement Gate Electrode Structures and Self-Aligned Contact Elements Formed by a Late Contact Fill - When forming self-aligned contact elements in sophisticated semiconductor devices in which high-k metal gate electrode structures are to be provided on the basis of a replacement gate approach, the self-aligned contact openings are filled with an appropriate fill material, such as polysilicon, while the gate electrode structures are provided on the basis of a placeholder material that can be removed with high selectivity with respect to the sacrificial fill material. In this manner, the high-k metal gate electrode structures may be completed prior to actually filling the contact openings with an appropriate contact material after the removal of the sacrificial fill material. In one illustrative embodiment, the placeholder material of the gate electrode structures is provided in the form of a silicon/germanium material. | 2013-03-28 |
20130075822 | STRUCTURES AND METHODS OF SELF-ALIGNED GATE FOR SB-BASED FETS - The advantage of narrow-bandgap Sb-based devices is the realization of high-frequency operation with much lower power consumption. However, some properties such as chemical stability are the key issues for developing Sb-based devices. The process temperature of the ion implant and thermal annealing in conventional silicon industry is over 1000° C. Sb-based materials are easily degraded at temperature greater 300° C. Thus, this invention provides three processes for self-aligned gate with lower process temperature (<300° C.) to reduce device access region resistance and maintain material quality. | 2013-03-28 |
20130075823 | RELIABLE CONTACTS - A method for forming a device is disclosed. The method includes providing a substrate prepared with first and second contact regions and a dielectric layer over the contact region. First and second vias are formed in the dielectric layer. The first via is in communication with the first contact region and the second via is in communication with the second contact region. A buried void provides a communication path between the first and second vias. The vias and buried void are at least partially filled with a dielectric filler. The partially filled buried void blocks the communication path between the first and second vias created by the buried void. The dielectric filler in the vias is removed, leaving remaining dielectric filler in the buried void to block the communication path between the first and second vias and contact plugs are formed in the vias. | 2013-03-28 |
20130075824 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device has first and second conductive type transistors on a substrate. First conductive type transistor includes: a first lower gate electrode portion on the substrate, including silicon including first impurity ions; a first intervening layer on the first lower gate electrode portion, including silicon including oxygen and/or nitrogen; and a first upper gate electrode portion on the first intervening layer, the first upper gate electrode portion including silicon including the first impurity ions. Second conductive type transistor includes: a second lower gate electrode portion on the substrate, the second lower gate electrode portion including silicon including second impurity ions; a second intervening layer on the second lower gate electrode portion, the second intervening layer including silicon including oxygen and/or nitrogen; and a second upper gate electrode portion on the second intervening layer, the second upper gate electrode portion including silicon including the second impurity ions. | 2013-03-28 |
20130075825 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME - To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells. | 2013-03-28 |
20130075826 | SEMICONDUCTOR DEVICE WITH STRAINED CHANNELS INDUCED BY HIGH-K CAPPING METAL LAYERS - A semiconductor device with a metal gate is disclosed. The device includes a semiconductor substrate including a plurality of source and drain features to form a p-channel and an n-channel. The device also includes a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a high-k (HK) dielectric layer formed over the semiconductor substrate. A tensile stress HK capping layer is formed on top of the HK dielectric layer in close proximity to the p-channel, and a compressive stress HK N-work function (N-WF) metal layer is formed on top of the HK dielectric layer in close proximity to the n-channel. A stack of metal gate layers is deposited over the capping layers. | 2013-03-28 |
20130075827 | REPLACEMENT GATE SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device including providing a semiconductor substrate having a first opening and second opening. A dielectric layer is formed on the substrate. An etch stop layer on the dielectric layer in the first opening. Thereafter, a work function layer is formed on the etch stop layer and fill metal is provided on the work function layer to fill the first opening. | 2013-03-28 |
20130075828 | SEMICONDUCTOR DEVICE - A semiconductor device according to the invention includes: a first region on a semiconductor substrate, in which a first transistor is formed, the first transistor including first gate insulating film | 2013-03-28 |
20130075829 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge (ESD) protection device includes a first transistor and a second transistor. The first transistor includes a first bulk electrode, a first electrode and a second electrode. The first bulk electrode and the first electrode form a first parasitic diode. The first bulk electrode and the second electrode form a second parasitic diode. The second transistor includes a second bulk electrode, a third electrode and a fourth electrode. The second bulk electrode and the third electrode form a third parasitic diode. The second bulk electrode and the fourth electrode form a fourth parasitic diode. The first bulk electrode is connected to the third electrode, and the second bulk electrode is connected to the first electrode. | 2013-03-28 |
20130075830 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a method, a gate dielectric film is formed on a semiconductor substrate. A gate electrode is formed on the gate dielectric film. Impurities of a first conduction-type are introduced into a drain-layer formation region. The impurities of the first conduction-type in the drain-layer formation region are activated by performing heat treatment. Single crystals of the semiconductor substrate in a source-layer formation region are amorphized by introducing inert impurities into the source-layer formation region. Impurities of a second conduction-type is introduced into the source-layer formation region. At least an amorphous semiconductor in the source-layer formation region is brought into a single crystal semiconductor and the impurities of the second conduction-type in the source-layer formation region is activated by irradiating the semiconductor substrate with microwaves. The impurities of the second conduction-type in the source-layer formation region is shallower than the impurities of the first conduction-type in the drain-layer formation region. | 2013-03-28 |
20130075831 | METAL GATE STACK HAVING TIALN BLOCKING/WETTING LAYER - A metal gate stack having a TiAlN blocking/wetting layer, and methods of manufacturing the same, are disclosed. In an example, an integrated circuit device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack includes a gate dielectric layer disposed over the semiconductor substrate; a work function layer disposed over the gate dielectric layer; a multi-function wetting/blocking layer disposed over the work function layer, wherein the multi-function wetting/blocking layer is a titanium aluminum nitride layer; and a conductive layer disposed over the multi-function wetting/blocking layer. | 2013-03-28 |
20130075832 | PROCESS FOR PRODUCING A CONDUCTING ELECTRODE - A process for producing a conducting electrode on a substrate, including: depositing a layer made of a dielectric; depositing a protective layer made of the nitride of a metal on the dielectric layer; depositing a functionalization layer made of a material including a chemical species, such that the free enthalpy of formation of the nitride of the species is less, in absolute value, than the free enthalpy of formation of the nitride of the metal of the protective layer over the temperature range between 0° C. and 1200° C.; and annealing the assembly including the protective layer and the funtionalization layer so that the species diffuse from the functionalization layer into the protective layer and the nitrogen atoms migrate from the protective layer into the functionalization layer. | 2013-03-28 |
20130075833 | MULTI-LAYER SCAVENGING METAL GATE STACK FOR ULTRA-THIN INTERFACIAL DIELCTRIC LAYER - A multi-layer scavenging metal gate stack, and methods of manufacturing the same, are disclosed. In an example, a gate stack disposed over a semiconductor substrate includes an interfacial dielectric layer disposed over the semiconductor substrate, a high-k dielectric layer disposed over the interfacial dielectric layer, a first conductive layer disposed over the high-k dielectric layer, and a second conductive layer disposed over the first conductive layer. The first conductive layer includes a first metal layer disposed over the high-k dielectric layer, a second metal layer disposed over the first metal layer, and a third metal layer disposed over the second metal layer. The first metal layer includes a material that scavenges oxygen impurities from the interfacial dielectric layer, and the second metal layer includes a material that adsorbs oxygen impurities from the third metal layer and prevents oxygen impurities from diffusing into the first metal layer. | 2013-03-28 |
20130075834 | Bulk Silicon Moving Member with Dimple - A method for forming a semiconductor device includes forming a substrate, forming a moveable member of bulk silicon and forming a first dimple structure on a first surface of the moveable member, where the first surface faces the substrate. | 2013-03-28 |
20130075835 | MICRO-ELECTRO-MECHANICAL MICROPHONE AND MICRO-ELECTRO-MECHANICAL MICROPHONE CHIP INTEGRATED WITH FILTER - A microelectromechanical microphone comprises a shell body, a microelectromechanical microphone chip and an integrated circuit. The shell body having a cavity and an opening, sound from outside enters into the cavity from the opening. The microelectromechanical microphone chip and the integrated circuit are disposed on a circuit layout inside the cavity. A filter is integrated with the microelectromechanical microphone chip at an appropriate location. Sound entered from the opening into the cavity is received by the microelectromechanical microphone chip, then the sound or audio signals are converted to electrical signals through the filter and the integrated circuit, to be transmitted to external electronic devices. | 2013-03-28 |
20130075836 | Vented MEMS Apparatus And Method Of Manufacture - A micro-electromechanical system (MEMS) device includes a housing and a base. The base includes a port opening extending therethrough and the port opening communicates with the external environment. The MEMS die is disposed on the base and over the opening. The MEMS die includes a diaphragm and a back plate and the MEMS die, the base, and the housing form a back volume. At least one vent extends through the MEMS die and not through the diaphragm. The at least one vent communicates with the back volume and the port opening and is configured to allow venting between the back volume and the external environment. | 2013-03-28 |
20130075837 | TECHNIQUE FOR SMOOTHING AN INTERFACE BETWEEN LAYERS OF A SEMICONDUCTOR DEVICE - The present disclosure provides a semiconductor memory device. The device includes a pinning layer having an anti-ferromagnetic material and disposed over a first electrode; a pinned layer disposed over the pinning layer; a composite layer disposed over the pinned layer, the composite layer having a magnetic material randomly distributed in a non-magnetic material; a barrier layer disposed on the composite layer; a free layer disposed over the barrier layer; and a second electrode disposed over the free layer. | 2013-03-28 |
20130075838 | METHOD AND STRUCTURE FOR A MRAM DEVICE WITH A BILAYER PASSIVATION - The present disclosure provides a magnetoresistive random access memory (MRAM) device. The MRAM device includes a magnetic tunnel junction (MTJ) stack on a substrate; and a dual-layer passivation layer disposed around the MTJ stack. The dual-layer passivation layer includes an oxygen-free film formed adjacent sidewalls of the MTJ stack; and a moisture-blocking film formed around the oxygen-free film. | 2013-03-28 |