13th week of 2013 patent applcation highlights part 22 |
Patent application number | Title | Published |
20130076340 | REED SWITCH CHAIN TO DETECT METER TAMPERING - Aspects of the invention provide for detecting tampering with an electronic utility meter. In one embodiment, aspects of the invention include an electronic utility meter, comprising a metering circuit enclosed within a cover; a switch chain including at least one reed switch operatively coupled to the metering circuit, and positioned around an inner circumference of the cover; and a sensor enclosed within the cover, coupled to the switch chain, the sensor sensing the at least one three reed switch closing in response to a user interaction with the electronic utility meter. | 2013-03-28 |
20130076341 | HIGH CURRENT SENSORS - Embodiments relate to high current sensors having generally flat conductors. In an embodiment, the conductor is formed of a non-magnetic material such as copper or aluminum and has a coarse slot, one that reduces the cross-sectional area for current flow by a factor of about two. The slot also functions as an aperture in which the sensor package can mounted, thereby protected from environmental influences. | 2013-03-28 |
20130076342 | ELECTRICAL METERING AND SWITCHING EQUIPMENT - An electrical service equipment provides electrical service to a building or other similar venue. The equipment includes a cabinet with two portions structured to hold a meter pan and a switch, respectively. The switch is preferably an HCP switch. The portion holding the meter pan includes a subassembly including two horizontal plates and a plurality of buses passing through the plate and adapted to provide connection to the current and voltage transformers of the meter pan. | 2013-03-28 |
20130076343 | NON-CONTACT CURRENT AND VOLTAGE SENSING CLAMP - A clamping current and voltage sensor provides an isolated and convenient technique for measuring current passing through a conductor such as an AC branch circuit wire, as well as providing an indication of an electrostatic potential on the wire, which can be used to indicate the phase of the voltage on the wire, and optionally a magnitude of the voltage. The device includes a body formed from two handle portions that contain the current and voltage sensors within an aperture at the distal end, which may be a ferrite cylinder with a hall effect sensor disposed in a gap along the circumference to measure current, or alternatively a winding provided through the cylinder along its axis and a capacitive plate or wire disposed adjacent to, or within, the ferrite cylinder to provide the indication of the voltage. When the handles are compressed the aperture is opened to permit insertion of a wire for measurement. | 2013-03-28 |
20130076344 | INDUCTION-BASED REFERENCE POINT LOCATOR - According to one aspect of the present disclosure, an induction-based reference point locator is provided. The locator includes transmitter locatable at a position on a first side of a structure, the transmitter configured to generate an alternating magnetic field at a desired frequency; and a receiver locatable on a second side of the structure opposite the first side, the receiver configured to detect the magnetic field and provide a directional indication to the position of the transmitter relative to the second side of the structure. | 2013-03-28 |
20130076345 | System and method of determining relative position - A system is configured to determine the displacement of a moveable member relative to a reference member. A set of sensors is fixed relative to one of the reference member and moveable member. An array of encoded words is provided. The encoded words define the positions of the moveable member along a first direction. Each encoded word includes a plurality of indicia and each indicia is a multi-level logic unit configured as one of at least three states. | 2013-03-28 |
20130076346 | System and method of determining relative position - A system is configured to determine the displacement of a moveable member relative to a reference member. A set of sensors is fixed relative to one of the reference member and moveable member. An array of encoded words is provided. The encoded words define each position of the moveable member along a first direction. Each encoded word includes a plurality of indicia and each indicia is a multi-level logic unit configured as one of at least two states. The position of the encoded words relative to the set of sensors defines a position of the movable member along a second direction. | 2013-03-28 |
20130076347 | CRACK DETERMINING DEVICE AND SEMICONDUCTOR DEVICE - There are provided a crack determining device capable of determining, in real time and with precision, the fact that a crack has occurred in a solder layer, and a semiconductor device comprising same. A crack determining device of the present invention is a crack determining device that determines whether or not a crack has occurred in a solder layer with respect to a semiconductor device in which at least a semiconductor element is connected to a connectee member via the solder layer, the crack determining device comprising a generation part that generates a magnetic field and that is fixed to a member forming the semiconductor device, and a detection part that detects a magnitude of a magnetic field and that is disposed within the solder layer, wherein the magnetic field generated at the generation part is detected at the detection part, and it is determined that a crack has occurred in the solder layer if this magnitude of the magnetic field varies from a magnitude of the magnetic field detected before the crack occurred. | 2013-03-28 |
20130076348 | EDDY CURRENT SENSOR AND EDDY CURRENT MEASUREMENT METHOD - An eddy current sensor that includes: a probe and a computing unit. The probe has an exciting portion and a detecting portion. The exciting portion includes a first excitation coil that is wound around a non-magnetic bobbin so that a center axis direction is oriented in an x-axis direction and a second excitation coil that is wound around the non-magnetic bobbin to intersect with the first excitation coil so that a center axis direction is oriented in a y-axis direction. The detecting portion includes a detection coil that is arranged at the lower one of two intersecting portions of the first excitation coil and the second excitation coil. An eddy current measurement method for determining the thickness of a hardened layer. | 2013-03-28 |
20130076349 | EDDY CURRENT PROBE - An eddy current probe | 2013-03-28 |
20130076350 | MAGNETIC SENSOR DEVICE - A magnetic sensor device for generating a logic output in accordance with a magnetic field intensity applied to a magnetoelectric conversion element includes: a comparator for inputting amplified output signals of the magnetoelectric conversion element, and outputting a comparison result; and a logic circuit for performing arithmetic processing on an output signal of the comparator. Only when the logic output is changed by a change in the magnetic field intensity, the logic circuit performs successive matching determination of logic outputs a plurality of times. Thus, the variation in determination for detection or canceling of a magnetic field intensity, which is caused by noise generated from respective constituent elements included in the magnetic sensor device and external noise, may be reduced while suppressing electric power consumption. | 2013-03-28 |
20130076351 | METERING DEVICE AND METERING METHOD - Provided is a metering device and a metering method. The metering device includes a Hall sensor configured to output a Hall voltage generated by a magnetic field generated from a power supply line, an analog-digital converter configured to receive a voltage signal between a minimum voltage value and a maximum voltage value to convert the voltage signal into a digital signal and output the digital signal, an output adjustment unit connected between the Hall sensor and the analog-digital converter, and configured to attenuate and output the Hall voltage when the Hall voltage output from the Hall sensor is larger than the maximum voltage value and output adjustment information that adjusted the Hall voltage, and a control unit connected to the analog-digital converter and the output adjustment unit, and calculate the digital signal output from the analog-digital converter and the adjustment information output from the output adjustment unit to calculate wattage. | 2013-03-28 |
20130076352 | METHOD TO SELECT AN UNDERSAMPLING SCHEME FOR MAGNETIC RESONANCE IMAGING, AND MAGNETIC RESONANCE IMAGING METHOD AND SYSTEM USING SUCH A SELECTED UNDERSAMPLING SCHEME - In a method to select an undersampling scheme of k-space and an associated set of reconstruction kernels to acquire reduced magnetic resonance (MR) data sets with multiple coils, a calibration data set is acquired for each of the respective coils, a noise covariance is determined from autocorrelations and correlations of the noise of the various coils. At least one set of reconstruction kernels is calculated for each of the multiple undersampling schemes from the calibration data sets of the various coils. For each set of reconstruction kernels, a characteristic value is calculated from the noise covariance and the respective reconstruction kernels of the coils, with the characteristic value being proportional to a spatial mean value of a signal noise of an MR image. A selected undersampling scheme and a selected set of reconstruction kernels are selected based on the calculated characteristic values. | 2013-03-28 |
20130076353 | RECORDING OF CALIBRATION DATA FOR A MAGNETIC RESONANCE SYSTEM - A local coil with a plurality of magnetic resonance antenna elements and a plurality of test signal coupling units assigned individually or in groups to the plurality of magnetic resonance antenna elements is provided. In order to transmit a test signal, each test signal coupling unit of the plurality of test signal coupling units is connected via a star connection unit to a joint test signal connector and/or to a transmission cable of a transmit and/or receive chain of an assigned magnetic resonance antenna element of the plurality of magnetic resonance antenna elements. | 2013-03-28 |
20130076354 | MAGNETIC RESONANCE SYSTEM AND METHOD FOR CARRYING OUT MAGNETIC RESONANCE MEASUREMENTS IN AN INTRAORAL REGION - The present embodiments relate to a magnetic resonance system for carrying out magnetic resonance measurements in an intraoral region. The magnetic resonance system includes a magnetic resonance coil element and an intraoral measuring device that measures the position of a number of measuring points situated in the intraoral region. | 2013-03-28 |
20130076355 | Fast, Low Energy Deposition and Homogeneous T2 Weighted Variable Amplitude PSIF (T2 VAPSIF) Imaging in the Presence of B0inhomogeneities - A method for acquiring medical images, including: applying, during a first period, a plurality of radio frequency (RF) pulses to an area of interest, wherein the RF pulses applied during the first period are Kaiser-Bessel pulses; applying, during a second period, a plurality of 180 degree RF preparation pulses to the area; applying, during a third period, a plurality of 180 degree RF pulses to the area to acquire a center of a k-space; applying, during a fourth period, a plurality of RF pulses to the area, wherein the RF pulses applied during the fourth period have an angle smaller than the 180 degree RF pulses applied during the third period; applying, during a fifth period, a plurality of constant RF pulses to the area to acquire outer lines of the k-space; and generating an image of the area by using a steady-state free precession echo readout. | 2013-03-28 |
20130076356 | MAGNETIC RESONANCE IMAGING METHOD AND APPARATUS TO CORRECT DISTORTIONS DUE TO INHOMOGENEITIES OF THE BASIC MAGNETIC FIELD - In a magnetic resonance method and system to correct spatial shifts in MR data, at least two measurement data sets are acquired, the additional measurement data set or sets being acquired while switching an additional gradient relative to acquisition of the first measurement data set. For respective corresponding measurement points of the measurement data sets, a phase difference is initially determined from the first measurement data set and at least one additional measurement data set acquired with the additional gradient, with a spatial shift of the measurement points of the first measurement data set being determined from the spatial shift. The magnitude values of the initially measured measurement points are distributed to their correct spatial position corresponding to the determined spatial shifts, so a corrected image data set is created. | 2013-03-28 |
20130076357 | METHOD AND MAGNETIC RESONANCE APPARATUS TO GENERATE A SERIES OF MR IMAGES TO MONITOR A POSITION OF AN INTERVENTIONAL DEVICE - In a magnetic resonance (MR) method and system to generate a series of MR images to monitor the position of an interventional device located in an examination region, radial scanning of k-space is combined with other scans, in particular for the k-space center. The measurement time until the entirety of k-space corresponding to the imaging region is scanned is thereby markedly shortened in total. The short echo times that are possible with this reduce susceptibility artifacts in the reconstructed image data and enable a depiction of tissue or substances with very short T2 values, for example plastics. Due to the rapidly repeated excitation and acquisition of measurement data and the reconstruction of image data, it is possible to monitor a position of the intervention device in the examination region. | 2013-03-28 |
20130076358 | ADJUSTABLE MRI HEAD COIL APPARATUS AND MRI SYSTEM - An adjustable MRI head coil apparatus and MRI system include a fixture and a plurality of plates attached to the fixture. Each of the plurality of plates includes a plurality of RF receive elements arranged in a fixed orientation. The adjustable MRI head coil apparatus and MRI system also include an actuator mechanism configured to adjust the relative position of each of the plurality of plates in order to fit a variety of different patient head sizes. | 2013-03-28 |
20130076359 | OUTPUT STAGE MODULE FOR A POWER AMPLIFIER DEVICE - An output stage module for a power amplifier device (e.g., for a power amplifier device of a transmit unit of a magnetic resonance device) includes a housing and a carrier that is arranged within the housing. The carrier is made of a non-electrically-conducting, thermally-conducting material with low electrical losses (e.g., a ceramic carrier). At least two transistor dies are arranged on the carrier. At least one transistor, in each case, is assigned to a phase of a symmetrical input signal. In and/or on the carrier, a first conductor structure connecting (e.g., inductively) a drain output of the at least two transistor dies to an output signal and to second conductor structures each conducting an input signal to at least one gate input of the at least two transistor dies are provided. At least one cooling channel routed adjacent to at least one transistor die of the at least two transistor dies is provided. | 2013-03-28 |
20130076360 | POWER MODULE AND MANUFACTURING PROCESS - A power module for a high frequency amplifier unit is provided. The power module includes a base support plate, on which at least one power electronic module is contacted via a number of contact pins. A shield plate is arranged on a side of the power electronic module facing away from the base support plate. The power electronic module is in contact with a cooling element at a side facing the shield plate. | 2013-03-28 |
20130076361 | RF RECEIVING COIL AND MAGNETIC RESONANCE IMAGING APPARATUS USING THE SAME - To order to provide an RF receiving coil having a structure that can be safely mounted on an object and an MRI apparatus including the RF receiving coil, the RF receiving coil includes a main body having one or more flexible closed conductor loops for receiving a nuclear magnetic resonance signal, a flexible outer cover section that covers the closed conductor loop, a preamplifier section that amplifies the nuclear magnetic resonance signal received by the closed conductor loop, and a housing section in which the preamplifier section is housed and which is more rigid than the outer cover section. The RF receiving coil is mounted on the object in a state where the main body is bent such that the end surfaces of both ends of the main body face each other, and the MRI apparatus performs imaging using such an RF receiving coil. | 2013-03-28 |
20130076362 | Ion Sensing Method for Capacitive Discharge Ignition - A method of ion sensing in a CD ignition system for an internal combustion engine comprises: a) closing the controllable switch in synchronism with the internal combustion engine for a period of time to transfer energy to the ignition coil primary to cause a spark breakdown across the spark plug; and b) observing the current in the secondary winding circuit indicative of ionization in the vicinity of the spark plug electrodes. | 2013-03-28 |
20130076363 | SYSTEM AND METHOD FOR DETERMINING DEGRADATION OF RECHARGEABLE LITHIUM ION BATTERY - An MPU performs a degradation diagnosis based on an open circuit voltage characteristic of a rechargeable lithium ion battery indicating how the battery varies in open circuit voltage as the battery varies in capacity to obtain a capacity ratio of a positive electrode, a capacity ratio of a negative electrode, and a deviated capacity of the battery. The MPU applies the capacity ratio of the positive electrode and the capacity ratio of the negative electrode to a predetermined map for degradation attributed to wear to estimate a deviated capacity resulting from degradation attributed to wear and separates the deviated capacity into the deviated capacity resulting from degradation attributed to wear and a deviated capacity resulting from deposition of lithium. The MPU uses at least the deviated capacity resulting from deposition of lithium to determine whether a rechargeable lithium ion battery subject to determination of degradation is reusable and/or recyclable. | 2013-03-28 |
20130076364 | BATTERY DETECTION METHOD - A battery detection method detecting if a voltage to be tested falls within a voltage range between a highest voltage of a rechargeable battery and a highest detection voltage. If the voltage to be tested is less than the highest detection voltage, further determine if the voltage to be tested reaches a target voltage within a test time period. If the voltage to be tested reaches the target voltage after the test time period expires, determine that the voltage to be tested is from a rechargeable battery. If the voltage to be tested reaches the target voltage within the test time period, determine that the voltage to be tested is from a non-rechargeable battery. Accordingly, the battery detection method can easily detect if a voltage to be tested is from a rechargeable battery. | 2013-03-28 |
20130076365 | BATTERY CELL CONTROL SYSTEM AND METHOD - In battery cell control system and method, a monitoring section connected to a battery cell included in an assembled battery, operated with the battery cell as a power source, and configured to monitor a state of the battery cell is provided and a first consumption of the battery cell which is consumed by the monitoring section in accordance with a voltage of the battery cell is estimated using the voltage of the battery cell. | 2013-03-28 |
20130076366 | BATTERY CAPACITY DISPLAY APPARATUS AND BATTERY CAPACITY DISPLAY METHOD - A battery capacity display method to display a full charge capacity of a battery and a residual capacity of the battery, respectively, as a full charge capacity display value and a residual capacity display value, the battery capacity display method includes: correcting the full charge capacity display value and/or the residual capacity display value so as to decrease a difference between the full charge capacity display value and the residual capacity display value when the battery is in the full charge state and the full charge capacity and the residual capacity in the full charge state are different from each other, and displaying a corrected full charge capacity display value and/or a corrected residual capacity display value. | 2013-03-28 |
20130076367 | SYSTEM AND METHOD FOR ESTIMATING THE SHORT CIRCUIT CURRENT OF A SOLAR DEVICE - Described herein is a method and system for determining a short-circuit current of a solar device before the solar device is tested in a solar simulator. A solar device includes a substrate layer, a front contact layer, a window/emitter layer, an absorber layer and a back contact. A thickness of the window/emitter layer and an absorption wavelength of the absorber layer are determined. The window/emitter layer thickness and absorber layer absorption wavelength are used with a fitting parameter that corresponds to transmission properties of the substrate and first contact layers in order to determine the solar device's short-circuit current. | 2013-03-28 |
20130076368 | Electric Vehicle Service Equipment Tester - A tester connects with the connector of electrical vehicle service equipment (EVSE). The tester simulates the battery supply of an electric vehicle to test whether the EVSE is properly operating without requiring that the electric vehicle be present. In one embodiment LEDs are employed to indicate whether the EVSE meets specifications. In a second embodiment various measurements of voltage levels and signals are provided to allow for a more detailed analysis of the performance characteristics of the EVSE. Ground fault, proximity sensor, and re-closure tests are also undertaken. | 2013-03-28 |
20130076369 | DETECTION CIRCUIT AND METHOD FOR OPERATING A DETECTION CIRCUIT - A detection circuit has a detection path and a control path. The detection path comprises a signal limiter ( | 2013-03-28 |
20130076370 | Diagnostic Circuit for Monitoring an Analog-Digital Converter Circuit - Described is monitoring of an analog-digital conversion of a measured value of at least one of a pressure gauge, a level gauge and a flowmeter. Different measured values can be provided for the analog-digital converter by means of a first microcontroller, wherein these measured values are subsequently transmitted from this first area into a second area by means of a unidirectional coupler. These values are acquired by a second microcontroller in the second area and compared with reference values that are stored in the second area or at another location. This diagnostic circuit may make it possible to detect drifts of resistances and of reference voltages, as well as a faulty analog-digital converter or a program execution error of the first microcontroller. | 2013-03-28 |
20130076371 | ADHESIVE WITH ANISOTROPIC ELECTRICAL CONDUCTIVITY AND METHODS OF PRODUCING AND USING SAME - The invention relates to an electrically conductive adhesive, comprising an adhesively acting, curable and electrically non-conductive matrix material and a phase of electrically conductive carbon nanotubes distributed in the matrix material. According to the invention, the carbon nanotubes are present in a plurality of individual macrostructures, and each macrostructure consists of a plurality of agglomerated carbon nanotubes forming and electrical contact among each other. Another aspect of the invention concerns a method of producing such an electrically conductive adhesive, and a method for electrically conductive bonding of two components and for checking the quality of an adhesive bond formed in such a manner. | 2013-03-28 |
20130076372 | CHARACTERIZATION AND CORRECTION OF VOLTAGE PROBE, CURRENT PROBE AND CABLE - Responses of voltage and current probes are characterized or corrected. A voltage probe method includes measuring output of the voltage probe and a first output of a through, in response to an input signal applied to the through, with the voltage probe connected, measuring a second output of the through with the voltage probe disconnected, and characterizing the response of the voltage probe using the output of the voltage probe and the first and/or second outputs. A current probe method includes measuring output current of the current probe and first output current of a through, in response to an input signal applied to the through with the current probe connected in series, measuring second output current of the through with the current probe disconnected, and characterizing the response of the current probe using the output current of the current probe and the first and/or second output currents of the through. | 2013-03-28 |
20130076373 | TARGET SENSOR - Target sensor comprising: sensor probe having a resonance frequency that changes as the separation of the sensor probe and a target changes. Oscillator arranged to apply a radio frequency (RF) signal to the sensor probe, the oscillator having: control circuitry configured to regulate the frequency of the RF signal applied to the sensor probe to below the resonance frequency of the sensor probe. Detector arranged to detect an electrical characteristic of the oscillator that varies with the impedance of the sensor probe indicating an interaction of the sensor probe with the target. | 2013-03-28 |
20130076374 | CHARGED BODY SENSING SYSTEM - A charged body sensing electrode is provided which includes a signal generator, a filter and a detector. The signal generator generates an excitation signal, and the filter is coupled to the signal generator and receives the excitation signal from the signal generator. The filter includes at least one charged body sensing unit. The detector is coupled to the filter and detects an output signal corresponding to the filter. Accordingly, when the charged body neared or touched the charged body sensing electrode, the output signal of the filter will be changed. The trajectory, the velocity or the location of the charged body, or the impedance variation of the charged body sensing unit can be obtained by the change of the output signal of the filter which is detected by the detector. | 2013-03-28 |
20130076375 | CAPACITANCE SENSING CIRCUITS, METHODS AND SYSTEMS HAVING CONDUCTIVE TOUCH SURFACE - A capacitance sense device can include a plurality of sense electrodes; a nonconductive structure comprising first regions formed over the sense electrodes and second regions formed between first regions that are less compressible than the first regions; a conductive touch surface formed over the nonconductive structure; and a capacitance sense circuit coupled to at least the sense electrodes. | 2013-03-28 |
20130076376 | CAPACITANCE MEASUREMENT CIRCUIT AND METHOD THEREFOR - A capacitance measurement circuit includes an operation amplifier; a reference capacitor having a first terminal coupled to a first input terminal of the operation amplifier and a second terminal selectively coupled to a first or second reference voltage; a sensor capacitor having a first terminal coupled to a second input terminal of the operation amplifier and a second terminal selectively coupled to the first or second reference voltage; an approximation unit having an output terminal and an input terminal coupled to an output terminal of the operation amplifier; a conversion unit having an output terminal and an input terminal coupled to the output terminal of the approximation unit; and a coupling capacitor having a first terminal coupled to the first or second input terminal of the operation amplifier and a second terminal coupled to the output terminal of the conversion unit. | 2013-03-28 |
20130076377 | CAPACITANCE MEASUREMENT CIRCUIT AND METHOD THEREFOR - A capacitance measurement circuit includes an operation amplifier; a reference capacitor having a first terminal coupled to a first input terminal of the operation amplifier and a second terminal selectively coupled to a first or second reference voltage; a sensor capacitor having a first terminal coupled to a second input terminal of the operation amplifier and a second terminal selectively coupled to the first or second reference voltage; an approximation unit having an output terminal and an input terminal coupled to an output terminal of the operation amplifier; a conversion unit having an output terminal and an input terminal coupled to the output terminal of the approximation unit; and a coupling capacitor having a first terminal coupled to the first or second input terminal of the operation amplifier and a second terminal coupled to the output terminal of the conversion unit. | 2013-03-28 |
20130076378 | Integrated capacitance bridge for high-resolution wide-temperature-range capacitance measurement - The present approach is based on the use of an integrated capacitance bridge circuit to measure the capacitance of a device under test. A significant feature of this approach is that the operating point is not the null point of the bridge circuit. Instead, the operating point of the bridge circuit is tuned to be away from the null point. By moving away from the null point, the output signal from the bridge circuit is increased. Preferably, this output signal is substantially larger than the input noise floor of an amplifier connected to the bridge circuit output, while being substantially less than Gν | 2013-03-28 |
20130076379 | SUSPENSION DEVICE FOR A MEMBRANE TEST SYSTEM - Embodiments of suspension clamps for use in testing membrane samples used in fuel cells are provided. One example of a suspension clamp comprises a frame, a clamp member, a plurality of electrodes, and a suspension component. The clamp member is hingedly attached to one end of the frame. Each of the plurality of electrodes extends along a membrane-facing surface of at least one of the clamp member and the frame. A suspension component is attached to at least one of the clamp member and the frame and is configured to suspend the suspension clamp during testing of a membrane sample. The suspension clamp can be used to measure one or more of resistance, impedance, conductance, proton permeability and through-thickness of the membrane sample. | 2013-03-28 |
20130076380 | METHOD AND APPARATUS FOR ELECTRICALLY ACCESSING PHOTOVOLTAIC MODULES - An apparatus and a method for testing and/or conditioning photovoltaic modules. The apparatus includes a set of contacts for contacting electrical conductors of the module and a testing and/or conditioning system for testing and/or conditioning of the module and measuring parameters associated therewith. | 2013-03-28 |
20130076381 | Threshold-Based Temperature-Dependent Power/Thermal Management with Temperature Sensor Calibration - A method and apparatus for temperature sensor calibration is disclosed. In one embodiment, an integrated circuit (IC) is tested at a first known temperature corresponding to a first temperature threshold. During the test, a first temperature reading is obtained from a temperature sensor. A first offset is calculated by determining the difference between the first known temperature and the first temperature reading. The first offset is recorded in a storage unit for later use during operation of the IC. During operation, the first offset may be added to temperature readings obtained from a temperature sensing unit to produce an adjusted temperature value. The adjusted temperature value may be compared to one or more temperature thresholds. Based on the comparisons, a power management unit may perform power control actions. | 2013-03-28 |
20130076382 | Apparatus and Method for Measurement of Radiation Intensity for Testing Reliability of Solar Cell, and Method for Testing Reliability of Solar Cell - An apparatus and method for measurement of radiation intensity for testing reliability of a solar cell, and a method for testing the reliability of the solar cell. The apparatus includes a first solar cell receiving a predetermined intensity of radiation or more to generate electricity, a second solar cell receiving a predetermined intensity of radiation or more to generate electricity; a temperature sensor sensing a temperature of the second solar cell; a cooler cooling the first solar cell; and a controller measuring the intensity of radiation applied to the first solar cell, and controlling the cooler to prevent the temperature of the first solar cell from increasing above a predetermined temperature depending on the temperature of the second solar cell sensed by the temperature sensor. | 2013-03-28 |
20130076383 | METHOD FOR TESTING AN INTEGRATED CIRCUIT - A method for testing an integrated circuit and an integrated circuit. The integrated circuit has an internal testing structure which may be accessed via an internal test access port and a control bus which is conducted to the outside via control ports, it being possible to switch over between a running mode and a test mode so that, in the test mode, the test access port is accessed via the control ports and the control bus, thus testing the integrated circuit. | 2013-03-28 |
20130076384 | METHOD FOR TESTING MULTI-CHIP STACKED PACKAGES - Disclosed is a method for testing multi-chip stacked packages. Initially, one or more substrate-less chip cubes are provided, each consisting of a plurality of chips such as chips stacked together having vertically connected with TSV's where there is a stacked gap between two adjacent chips. Next, the substrate-less chip cubes are adhered onto an adhesive tape where the adhesive tape is attached inside an opening of a tape carrier. Then, a filling encapsulant is formed on the adhesive tape to completely fill the chip stacked gaps. Next, the tape carrier is fixed on a wafer testing carrier in a manner to allow the substrate-less chip cubes to be loaded into a wafer tester without releasing from the adhesive tape. Accordingly, the probers of the wafer tester can be utilized to probe testing electrodes of the substrate-less chip cubes so that it is easy to integrate this testing method in TSV fabrication processes. | 2013-03-28 |
20130076385 | Semiconductor Test Structures - A resistive test structure that includes a semiconductor substrate with an active region, a gate stack formed over the active region, a first electrical contact in communication with the active region on opposing sides of the gate stack, the first electrical contact providing an electrical short across a first dimension of the gate stack, and a second electrical contact in communication with the active region on the opposing sides of the gate stack, the second electrical contact providing an electrical short across the first dimension of the gate stack, the first and second electrical contacts spaced along a second dimension of the gate stack perpendicular to the first dimension. | 2013-03-28 |
20130076386 | Virtual Load Board And Test System And Test Method for Liquid Crystal Display Control Board - A virtual load board includes a connection port, a conversion circuit, and an indication unit, wherein the connection port comprises at least one terminal. The terminal receives an output voltage from the liquid crystal display control board. The conversion circuit converts the output voltage into an operating voltage for the indication unit and supplies the operating voltage to the indication unit. A test system and a test method for liquid crystal display control board are also provided. With the above-discussed arrangement, the virtual load board replaces a liquid crystal display panel to carry out a reliability test of the liquid crystal display control board, and has the advantages of small volume and low cost and can be accommodated, together with the liquid crystal display control board, in reliability test equipment in order to carry out a reliability test of the liquid crystal display control board in a specific environment. | 2013-03-28 |
20130076387 | SEMICONDUCTOR CHIP, SEMICONDUCTOR DEVICE, AND METHOD OF MEASURING THE SAME - In a semiconductor device in which semiconductor chips having a number of signal TSVs are stacked, a huge amount of man-hours have been required to perform a continuity test for each of the signal TSVs. According to the present invention, no continuity test is performed directly on signal TSVs. Dummy bumps are arranged in addition to signal TSVs. The dummy bumps of the semiconductor chips are connected through a conduction path that can pass the dummy bumps between the semiconductor chips with one stroke when the semiconductor chips are stacked. A continuity test of the conduction path allows a bonding defect on bonded surfaces of two of the stacked semiconductor chips to be measured and detected. | 2013-03-28 |
20130076388 | TRANSISTOR ARRAY FOR TESTING - A transistor array for testing is provided. The transistor array includes a plurality of tested units. Each of the tested unit includes a tested transistor and a first to third switches. The tested transistor has a control terminal, a first and a second terminals and a bulk. The first switch is coupled between the first terminal and a leakage transporting line. The second switch is coupled between the second terminal and the leakage transporting line. The third switch is coupled between the control terminal and a bias providing line. The first to third switches are turned on or turned off according to a control signal. When the tested transistor is selected to be tested, the first to third switches are turned on according to the control signal. | 2013-03-28 |
20130076389 | CURRENT TRANSFORMER ASSEMBLY FOR USE WITH ELECTRICAL MONITORING SYSTEMS AND METHODS OF ASSEMBLING SAME - A current transformer assembly for use in an electrical monitoring system is described herein. The current transformer assembly includes a housing including a plurality of shielding members that at least partially define a cavity therein. The housing further includes an inner surface that defines an opening that extends therethough. A first current transformer is positioned within the housing. A second current transformer is positioned within the housing and is spaced a distance from the first current transformer to facilitate reducing electronic noise interference between the first and second current transformers. | 2013-03-28 |
20130076390 | Programmable Logic Sensing in Magnetic Random Access Memory - A Magnetic Random Access Memory (MRAM) logic circuit includes read sensing circuitry having a first level corresponding to a first category of logic circuitry and a second logic level corresponding to a second category of logic circuitry. The logic circuitry may be switchable between circuitry having the first logic level and circuitry having the second logic level according to the category of the logic circuit being implemented. | 2013-03-28 |
20130076391 | PROGRAMMABLE GATE ARRAY AS DRIVERS FOR DATA PORTS OF SPARE LATCHES - Aspects of the invention provide for improving a success rate of an engineering design change (ECO) for an integrated circuit. In one embodiment, aspects of the invention include a method for improving a success rate of an engineering design change (ECO) for an integrated circuit, including: identifying a plurality of spare latches within the integrated circuit; determining an input driver for each of the spare latches; and replacing each input driver with a programmable gate array, such that the programmable gate array is programmed to a functionality of the input driver. | 2013-03-28 |
20130076392 | NONVOLATILE PROGRAMMABLE LOGIC SWITCH - A nonvolatile programmable logic switch according to an embodiment includes first and second cells, each of the first and second cells including: a first memory having a first to third terminals, the third terminal being receiving a control signal; a first transistor connected at one of source/drain to the second terminal; and a second transistor connected at a gate to the other of the source/drain of the first transistor, the third terminal of the first memory in the first cell and the third terminal of the first memory in the second cell being connected in common. When conducting writing into the first memory in the first cell, the third terminal is connected to a write power supply generating a write voltage, the first terminals in the first and second cells are connected to a ground power supply and a write inhibit power supply generating a write inhibit voltage respectively. | 2013-03-28 |
20130076393 | SPLIT DECODE LATCH WITH SHARED FEEDBACK - An apparatus having a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to (i) an intermediate signal, and (ii) a clock signal. The second circuit may be configured to generate the intermediate signal and a digital complement of the output signal in response to (i) an input signal and (ii) the clock signal. The intermediate signal may form a feedback to ensure the output signal and the digital complement of the output signal are in complementary states during a power up. | 2013-03-28 |
20130076394 | Compact High-Speed Mixed-Signal Interface - An apparatus is disclosed for converting signals from one digital integrated circuit family to be compatible with another digital integrated circuit family. The apparatus includes a primary interface and a secondary interface to convert a differential output signal from one digital integrated circuit family for use as an input signal by another digital integrated circuit family. The primary and secondary interfaces include gain stages that are configurable to provide rail to rail voltage swings and are characterized as having single pole architectures. The secondary interface may be unterminated such that a substantially equal load is presented to both components of the differential output signal. | 2013-03-28 |
20130076395 | SEMICONDUCTOR DEVICE - A semiconductor device includes a code generator configured to generate a supplementary code with a value changing in response to a variation of an impedance code, a main driver configured to receive an output data and drive the received output data to a data output pad, wherein a driving force of the main driver is controlled according to the impedance code, and an auxiliary driver configured to receive the output data and drive the received output data to the data output pad, wherein a driving force of the auxiliary driver is controlled according to the supplementary code. | 2013-03-28 |
20130076396 | METHOD, SYSTEM AND DEVICE FOR REMOVING MEDIA ACCESS CONTROL ADDRESSES - Embodiments of the present invention disclose a method and device for selecting a sampling clock signal. The method includes: obtaining, by a logic chip, a data edge of a data signal and a clock edge of a clock signal, selecting a sampling edge according to the data edge and the clock edge, and sending a selecting signal corresponding to the sampling edge to a selector; and selecting, by the selector, a sampling clock signal according to the selecting signal. The technical solutions provided by the embodiments of the present invention can solve problems of poor system maintainability and high cost of operation and maintenance because a receiver device needs to select a sampling clock signal through manual configuration in the synchronous serial-port communication in the prior art. | 2013-03-28 |
20130076397 | METHOD AND CIRCUIT CONFIGURATION FOR DETERMINING POSITION MINUS TIME - A circuit configuration for a data processing system for predicting a coordinate for at least one operation to be carried out is provided, the prediction being connected to at least one input signal and being a function of a predefined first time value and at least one predefined first value which represents another physical variable. Upon each change of the at least one input signal, a second time value is calculated in each case from the first value, and to subtract the first time value from the second time value to form a third time value, and/or to calculate a second value from the first time value, and to subtract the first value from the second value to form a third value, in order to determine from the third time value and/or the third value a state in which the at least one operation is to be carried out. | 2013-03-28 |
20130076398 | INTEGRATED CIRCUIT DEVICE, ELECTRONIC DEVICE AND METHOD FOR DETECTING TIMING VIOLATIONS WITHIN A CLOCK - An integrated circuit device comprises at least one clock monitor. The at least one clock monitor comprises a timer arranged to receive a clock signal, generate a first timing signal arranged to toggle between states in response to a trigger edge of the clock signal, and generate a second timing signal arranged to toggle between states in response to a trigger edge of the clock signal such that a state transition of the second timing signal in response to a trigger edge of the clock signal is delayed by a period T with respect to the trigger edge of the clock signal in response to which that transition occurs. The at least one clock monitor further comprises a detector arranged to receive at a first input thereof the first timing signal, receive at a second input thereof the second timing signal, compare states of the first and second timing signals, and configure an indication of a timing discrepancy based at least partly on the comparison of the first and second timing signals. | 2013-03-28 |
20130076399 | COMPARISON CIRCUIT AND IMPEDANCE CALIBRATION CIRCUIT USING THE SAME - A comparison circuit includes: an offset removal unit configured to store offset information of a comparator in response to a reference voltage, and compare a pad voltage with the reference voltage based on the offset information to drive a first node; and a comparison signal output unit configured to buffer a signal of the first node and output a comparison signal. | 2013-03-28 |
20130076400 | COMPARATOR CIRCUIT - A comparator includes a first power source terminal, a second power source terminal, a first transistor of a first conductivity type coupled between the first power source terminal and a first node, and including a control terminal coupled to a first terminal, a second transistor of the first conductivity type coupled between the first power source terminal and a second node, and including a control terminal coupled to a second terminal, a third transistor of a second conductivity type coupled between the first node and a third terminal, and including a control terminal coupled to the first node, a fourth transistor of the second conductivity type coupled between the second node and the second power source terminal, and including a control terminal coupled to the first node, and a fourth terminal coupled to the second node. | 2013-03-28 |
20130076401 | INPUT BUFFER CIRCUIT OF SEMICONDUCTOR APPARATUS - The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal. | 2013-03-28 |
20130076402 | TECHNIQUES FOR REDUCING CORRELATED ERRORS IN MULTI-CHANNEL SAMPLING SYSTEMS - Techniques to reduce correlated errors in a multi-channel sampling system. A plurality of clock signals may be generated from a master clock signal, each with edges offset from each other. The offset clock signals may be distributed to a plurality of sampling devices. Each sampling device may capture a respective input signal according to its offset clock. In this manner, the sampling units may sample their inputs signals over a distributed window of time rather than sampling in response to a common clock edge. By distributing the switching operations performed by the sampling units, noise effects are likely to be reduced. | 2013-03-28 |
20130076403 | VOLTAGE-TO-CURRENT CONVERTER - A conversion circuit includes a super source follower circuit configured to lower an impedance of a first node. A digital control circuit is configured to adjust a current at the first node based on a current through the super source follower. An output transistor has a gate configured to receive a first signal. A drain of the output transistor is coupled to a first node, and a source of the output transistor is configured to output an output current based on a voltage of the first signal. | 2013-03-28 |
20130076404 | LOW VOLTAGE DIFFERENTIAL SIGNAL DRIVING CIRCUIT AND ELECTRONIC DEVICE COMPATIBLE WITH WIRED TRANSMISSION - A low voltage differential signal driving circuit including positive and negative differential output terminals, an automatic level selector, an output level detector and a transition accelerator. The positive and negative differential output terminals provide a transmission interface with a differential output signal for transmission of a data signal. The automatic level selector outputs a reference voltage corresponding to the transmission interface. The output level detector generates a low-high (or high-low) transition acceleration control signal based on the data signal, the reference voltage, and VTXP signal at the positive differential output terminal (or VTXN signal at the negative differential output terminal). In accordance with the low-high (or high-low) transition acceleration control signal, the transition accelerator couples the positive (or negative) differential output terminal to a high voltage source and couples the negative (or positive) differential output terminal to a low voltage source to accelerate transition of the differential output signal. | 2013-03-28 |
20130076405 | SYSTEMS AND METHODS FOR DISCHARGING BUS VOLTAGE USING SEMICONDUCTOR DEVICES - Systems, apparatus, and methods are provided for discharging a voltage bus using a transistor. An exemplary gate drive circuit associated with the transistor includes a pulse generation module having an input and an output and a switched capacitance arrangement coupled between the output and a reference voltage node. The pulse generation module is configured to generate a voltage pulse at its output in response to a control signal at the input. In one embodiment, the control signal results in the voltage pulse having a duty cycle that operates the transistor associated with the gate drive circuit in a linear mode when the switched capacitance arrangement is activated. | 2013-03-28 |
20130076406 | ISOLATED GATE DRIVER ADAPTED FOR PWM-BASED SWITCHING POWER SUPPLY - An isolated gate driver including a driving control circuit, an isolated transformer, an anti-circuit and a secondary processing circuit is provided. The driving control circuit is configured to generate a driving PWM signal for driving a power switch tube. The isolated transformer has a primary winding and a secondary winding. The anti-circuit is connected between the driving control circuit and the primary winding of the isolated transformer, and is configured to suppress a variation of an induced voltage in the secondary winding of the isolated transformer when a duty cycle of the driving PWM signal is sharply decreased. The secondary processing circuit is connected in parallel with the secondary winding of the isolated transformer, and is configured to perform a voltage clamping action on a gate-source voltage of the power switch tube when the duty cycle of the driving PWM signal is sharply decreased. | 2013-03-28 |
20130076407 | CIRCUIT SYSTEM HAVING AT LEAST TWO INVERTER MODULES CONNECTED IN PARALLEL, METHOD FOR CONNECTING AT LEAST TWO INVERTER MODULES IN PARALLEL AND CIRCUIT SUBSTRATE FOR A GATE DRIVER CIRCUIT OF AN INVERTER MODULE - A circuit system having at least two inverter modules connected in parallel, each of which includes an inverter circuit having power semiconductor circuit breakers and a gate driver circuit for controlling the power semiconductor circuit breakers; the gate driver circuit of a first inverter module includes a signal transmission circuit via which a control signal is transmittable from a low-voltage side to a high-voltage side, and a first driver output terminal which is electrically connected to the first driver input terminals of the gate driver circuits of the inverter modules connected in parallel, and via which the high-voltage side control signal or a control signal deduced therefrom is transmittable to the gate driver circuits of the inverter modules connected in parallel. The power semiconductor circuit breakers of the inverter circuits of the inverter modules, connected in parallel to the first inverter module, are controlled based on the transmitted control signal. | 2013-03-28 |
20130076408 | High Performance Divider Using Feed Forward, Clock Amplification and Series Peaking Inductors - A phase lock loop (PLL) is an important component in wireless systems. CMOS technology offers voltage controlled oscillator designs operating at 60 GHz. One of the difficulties is dividing the high frequency clock down to a manageable clock frequency using conventional CMOS. Although injection locked dividers can divide down this clock frequency, these dividers have limitations. A divide by 2 is presented that uses several techniques; feed forward, clock amplification and series peaked inductors to overcome these limitations. | 2013-03-28 |
20130076409 | Multiple Channel Distributed System and Method - A complex acquisition system and method for synchronizing components thereof. The complex acquisition system further including a master acquisition module. The master acquisition module further including an analog to digital acquisition signal generator for generating an analog to digital acquisition signal, a memory acquisition signal generator for generating a memory acquisition signal, a delay calibration signal for generating a delay calibration signal, a step source signal generator for generating a step source signal, and a synchronization module. The complex acquisition system further includes a plurality of slave acquisition modules, each also including a synchronization module. The complex acquisition system additionally includes a distribution system for distributing each of the analog to digital acquisition signal, memory acquisition signal, delay calibration signal and step source signal to each of the synchronization modules in the master and plurality of slave acquisition modules. | 2013-03-28 |
20130076410 | POWER ON RESET SIGNAL GENERATING APPARATUS AND METHOD - A power on reset signal generating apparatus is provided. The power on reset signal generating apparatus includes a trigger capacitor, a reference current supplying circuit, and a current regulator. One end of the trigger capacitor is coupled to a ground voltage, and the other end of the trigger capacitor generates a power on reset signal. The reference current supplying circuit is coupled to a signal generating end. The current regulator is coupled to the signal generating end, and the signal generating end draws a splitting current to adjust the value of the current received by the trigger capacitor. | 2013-03-28 |
20130076411 | CDR CIRCUIT - A CDR circuit includes a clock recovery circuit that generates, from an external clock, a first clock with which data of a received data signal is to be sampled and a second clock with which an edge of the received data signal is to be sampled and adjusts phases of the first clock and the second clock. The CDR circuit includes a phase detecting circuit that outputs a result of sampling of the received data signal with the first clock as a data sampling result and a result of sampling of the received data signal with the second clock as an edge sampling result. The CDR circuit includes a result comparing circuit that determines that a false lock condition has occurred and outputs a false lock condition detection signal if the edge sampling result matches with the data pattern. | 2013-03-28 |
20130076412 | CDR CIRCUIT - When the comparison result signal indicates that the amplitude of the received data signal in synchronization with the data sampling clock signal is larger than the reference voltage, the lock detecting circuit determines that a lock condition occurs in which the data sampling clock signal locks the phase of the data of the received data signal, and outputs a lock flag signal. | 2013-03-28 |
20130076413 | SEMICONDUCTOR DEVICE INCLUDING DLL CIRCUIT HAVING COARSE ADJUSTMENT UNIT AND FINE ADJUSTMENT UNIT - Disclosed herein is a device that includes a coarse adjusting circuit generating first and second clock signals having different phases from each other, and a fine adjusting circuit generating a third clock signal having a phase between a phase of the first clock signal and a phase of the second clock signal. The fine adjusting circuit includes a plurality of first transistors receiving the first clock signal and a plurality of second transistors receiving the second clock signal. The fine adjusting circuit controls the phase of the third clock signal by synthesizing the first clock signal output from selected zero or more of the first transistors based on adjustment codes and the second clock signal output from selected zero or more of the second transistors based on the adjustment codes. The adjustment codes are not a binary system. | 2013-03-28 |
20130076414 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING AN ON-CHIP PLL AND OPERATING METHOD THEREOF - An on-chip phase-locked loop circuit has reduced power consumption in a semiconductor integrated circuit. The phase locked loop circuit is equipped with a phase frequency comparator, a loop attenuator, a charge pump, a loop filter, a voltage controlled oscillator and a divider. The attenuator includes a sampling circuit and a counter. A sampling pulse and first and second output signals both outputted from the phase frequency comparator are supplied to the sampling circuit. The sampling circuit outputs a sampling output signal. When the counter completes a countup of a predetermined number of sampling pulses outputted from the sampling circuit, the counter outputs a countup completion output signal. The charge pump outputs a charging current or a discharging current to the loop filter in response to the countup completion output signal. | 2013-03-28 |
20130076415 | PLL USING INTERPOLATIVE DIVIDER AS DIGITALLY CONTROLLED OSCILLATOR - One or more PLLs are formed on an integrated circuit. Each PLL includes an interpolative divider configured as a digitally controlled oscillator, which receives a reference clock signal and supplies an output signal divided according to a divide ratio. A feedback divider is coupled to the output signal of the interpolative divider and supplies a divided output signal as a feedback signal. A phase detector receives the feedback signal and a clock signal to which the PLL locks. The phase detector supplies a phase error corresponding to a difference between the clock signal and the feedback signal and the divide ratio is adjusted according to the phase error. | 2013-03-28 |
20130076416 | SUB-MICRON CMOS VCO THAT USES DELAY-BASED CALIBRATION AND METHOD OF OPERATION - A system for calibrating a circuit comprising a delay to voltage converter for receiving an input signal and generating an output signal that represents a delay metric. A counter for receiving the output signal and generating a binary output as a function of the delay metric. | 2013-03-28 |
20130076417 | MAINTAINING PULSE WIDTH MODULATION DATA-SET COHERENCY - Multi-phase, frequency coherent pulse width modulation (PWM) signals are generated that maintain PWM data-set coherency regardless of user or system events. PWM data-set coherency is accomplished by adding data buffers to hold and transfer new PWM data during a data-set update from a processor. After the data-set transfer to the data buffers is complete and when the next PWM cycle is about to start, the data-set stored in the data buffers is transferred to the active PWM registers in time for the start of the next PWM cycle. | 2013-03-28 |
20130076418 | System and Method for Calibration of Timing Mismatch for Envelope Tracking Transmit Systems - One embodiment of the present invention relates to a system for calibrating of timing between an amplifier input signal and a modulated supply power. The system includes a supply modulation component, an error metric component, and a delay determiner. The supply modulation component provides the modulated supply power and the amplifier input signal according to an input signal and a set delay signal. The error metric component provides information from a transmitted amplitude signal and a received amplitude signal. The delay determiner generates timing adjustments in the form of the set delay signal from the error metric information. | 2013-03-28 |
20130076419 | Piecewise Linear Phase Interpolator - In one embodiment, a phase interpolator with a phase range of n degrees, where 0m; and for each of the k sections, select a relative gain of one or more weights assigned to the one or more reference signals, respectively, with respect to the control code provided by the control signal. | 2013-03-28 |
20130076420 | DIGITALLY CONTROLLED PULSE WIDTH MODULATOR UTILIZING REAL TIME CALIBRATION - A system and method for controlling pulse width for electronic devices in real time is disclosed. The system includes a Digital Pulse Width Modulator (DPWM), a real time calibration circuit and a delay line circuit. The real time calibration circuit is configured to ensure proper fractional delay is applied to yield correct duty cycle of the DPWM. The delay line circuit comprising a multiplexer delay line with built in decoders, modulates the pulse width for fractional clock cycle delay. | 2013-03-28 |
20130076421 | ELECTRONIC CIRCUIT AND METHOD FOR STATE RETENTION POWER GATING - A method and a electronic circuit, the method includes: sending to a switching circuit, to a state retention power gating (SRPG) circuit and to a first power source a control signal indicating that the SRPG circuit should operate in a functional mode; coupling, by the switching circuit, a third power grid to a first power grid; supplying power from the first power source to the SRPG circuit via the first power grid, the switching circuit and the third power grid; supplying power from a second power source to a second circuit via a second power grid; sending to the switching circuit, to the SRPG circuit and to the first power source a control signal indicating that the SRPG circuit should operate in a state retention mode; coupling, by the switching circuit, the third power grid to the second power grid; supplying power from the second power source to the SRPG circuit via the second power grid, the switching circuit and the third power grid; supplying power from the second power source to the second circuit via the second power grid; and storing, by the SRPG state information. | 2013-03-28 |
20130076422 | Reduced Frequency Clock Delivery with Local Recovery - Circuits and methods for full rate data reception and transmission using half-frequency clock signals are disclosed. In one embodiment, a flop circuit includes a data input, a data output, and a clock input. The clock signal has a first frequency, while the flop circuit is configured to output data at a rate corresponding to a second frequency. In one embodiment, the second frequency is twice the first frequency. The flop circuit is configured to transmit a first data bit responsive to a first edge (e.g., a rising edge) of the clock signal and a second data bit responsive to a second edge (e.g., a falling edge) of the clock signal that is the next edge following the first edge. Accordingly, the flop circuit may effectively operate at the second frequency utilizing the clock signal at the first lower frequency. | 2013-03-28 |
20130076423 | Integrated Circuit With Delay Circuitry - The delay circuit, such as a clock circuit, of an integrated circuit operates with tolerance of variation in temperature. For example, the delay circuit has a temperature dependent current generator that has an adjustable temperature coefficient, such that a range of temperature coefficients is selectable at a particular current output. Also, the clock circuit of an integrated circuit operates with multiple versions of a current that controls a discharging rate and/or a charging rate between reference signals of timing circuitry. | 2013-03-28 |
20130076424 | SYSTEM AND METHOD FOR REDUCING CROSS COUPLING EFFECTS - A device includes a plurality of driver circuits coupled to a plurality of bus lines. A first driver circuit of the plurality of driver circuits is coupled to a first bus line of the plurality of bus lines. The first driver circuit includes one of a skewed inverter, a level shifter, a latch, and a sense amplifier configured to produce an output signal that transitions after a first delay in response to a first digital value transition of an input signal from high to low and transitions after a second delay in response to a second digital value transition of the input signal from low to high. The first delay is different from the second delay by an amount sufficient to reduce power related to transmission of signals over the first bus line and over a second bus line in close physical proximity to the first bus line. | 2013-03-28 |
20130076425 | INTEGRATED CIRCUIT DEVICE TIMING CALIBRATION - Techniques for performing timing calibration for an integrated circuit (IC) device are described. During operation, a first integrated circuit device transmits a first calibration pattern having differently delayed rising edge transitions with respect to a timing reference. The first integrated circuit device additionally transmits a second calibration pattern having differently delayed falling edge transitions with respect to the timing reference. Next, the first integrated circuit generates a timing offset for transmitting data from the first integrated circuit device. This timing offset is derived from information received from a second integrated circuit device sampling the first calibration pattern and the second calibration pattern. | 2013-03-28 |
20130076426 | APPARATUS FOR SUPPLYING CLOCK AND METHOD THEREOF - An apparatus for providing clock and a method thereof are provided. The provided apparatus includes a frequency generation unit and a control unit. The frequency generation unit decides amplitude of a clock signal to be a first amplitude or a second amplitude in response to a mode signal. The frequency generation unit converts an external oscillation signal into the clock signal. The control unit receives the clock signal, and outputs the mode signal in response to a system status signal. The control unit outputs the clock signal to external when determining that the clock signal has a stable oscillation. When the system status signal is a power on signal, the first amplitude is used as the amplitude of the clock signal, and when the system status signal is a power off signal, the second amplitude smaller than the first amplitude is used as the amplitude of the clock signal. | 2013-03-28 |
20130076427 | APPARATUS AND METHOD FOR REMOVING DC OFFSET IN POWER METER - Disclosed herein are an apparatus and a method for removing a DC offset in a power meter. The apparatus for removing a DC offset in a power meter according to exemplary embodiment includes: an ADC; a HPF removing the DC offset from the signal output from the ADC; a selector receiving the signals passing through the HPF and bypassing the HPF and outputting any one thereof; a determination block receiving a signal output from the ADC or from the selector and determining whether the received signal is a sinusoidal signal; an offset calculation block calculating the DC offset to be compensated from the signal input to the determination block or output from the selector; and an offset compensation unit disposed on a path bypassing the HPF, compensating the calculated DC offset value in the signal output from the ADC and outputting the compensated result to the selector. | 2013-03-28 |
20130076428 | LEVEL CONVERTER AND PROCESSOR - A level converter includes a level conversion circuit, which is provided between a reference power supply line having a reference voltage level and a first power supply line coupled to a first power supply outputting a first voltage level, which inputs a first signal and outputs a second signal, the first signal having a first logic level and a second logic level, the second signal having a first logic level and a second logic level; a control signal generating circuit to output a control signal having the reference voltage level when a second power supply outputting the second voltage level is turned off and the first voltage level when the second power supply is turned on; and a coupling circuit to control an electrically connection between the first power supply line and an output node of the level conversion circuit based on the control signal. | 2013-03-28 |
20130076429 | RF Switch Circuit, RF Switch and Method for Switching RF Signals - An RF switch circuit for switching RF signals includes a first terminal and a second terminal and a series connection of a plurality of transistors between the first terminal of the RF switch circuit and the second terminal of the RF switch circuit. Furthermore, the RF switch circuit includes a control circuit configured to conductively couple, in a high impedance state of the RF switch circuit, the first terminal of the RF switch circuit to a control terminal of a first transistor in a series of the series connection of the plurality of transistors. The second terminal of the RF switch circuit is conductively coupled to a control terminal of a last transistor in the series of the series connection of the plurality of transistors. | 2013-03-28 |
20130076430 | Semiconductor Integrated Circuit and Data Processing System - An arrangement for detecting local light irradiation in an illegal attack attempt to intentionally induce a malfunction or faulty condition is formed on a small chip occupancy area so as to provide high detection sensitivity. In a region containing a logic circuit, a plurality of series-coupled detection inverters are distributively disposed as photodetector elements having a constant logical value of primary-stage input. When at least one of the series-coupled detection inverters is irradiated with light, an output thereof is inverted, thereby producing a final output through the series-coupled detection inverters. Based on the final output thus produced, local light irradiation can be detected. | 2013-03-28 |
20130076431 | SWITCH WITH MULTIPLE TRIGGER FUNCTION - The present invention relates to a switch with multiple trigger function, which comprises: a touch switch having a button thereon; a first sensor having a sensing zone; and a microcontroller coupled to the touch switch and the first sensor; when the button is pressed by an object, the touch switch is conducted, and the microcontroller executes actions corresponding to the touch switch, thereby driving a controlled device; or when the object enters the sensing zone, the first sensor senses the signal change, and the microcontroller enables the touch switch to be conducted according to the signal change, or generates a signal the same as the signal for conducting the touch switch for executing corresponding actions, thereby driving a controlled device. | 2013-03-28 |
20130076432 | HIGH VOLTAGE CHARGE PUMP REGULATION SYSTEM WITH FINE STEP ADJUSTMENT - A regulator system for a charge pump system divides the binary decoding into two branches. One controls a set of parallel connected resistors for fine output voltage steps. The other branch controls a serial resistor to provide the large step size. For example, a 9-bit digital input signal is split into 2 least significant for the fine adjustment and the other 7 bits for the larger adjustments. In the example of a 50 mV step size, in one current path 2 bits of the binary input then control two parallel resistors for 50 mV and 100 mV step size, and in the other current path 7 bits are used for one-hot-decode control serial resistors to provide a 200 mV step size. A unity gain operational amplifier and a high voltage device are added in between the two branches to decouple the parasitic capacitance of large parallel resistors from the other elements. | 2013-03-28 |
20130076433 | ADAPTIVE FILTER WITH COEFFICIENT DETERMINATION BASED ON OUTPUT OF REAL TIME CLOCK - An adaptive filter implemented in a communication system transmitter or receiver has a real time clock associated therewith, and one or more coefficients of the adaptive filter are determined based at least in part on an output of the real time clock. For example, the adaptive filter may comprise a coefficient update engine and a memory for storing a plurality of sets of adaptive filter coefficients in association with respective time indicators derived from the output of the real time clock, with the coefficient update engine being configured to determine a particular one of the sets of filter coefficients for use by the adaptive filter based at least in part on one or more of the time indicators. The time indicators may comprise respective time stamps generated based on the output of the real time clock at respective times at which the corresponding sets of coefficients are determined. | 2013-03-28 |
20130076434 | Differential Source Follower having 6dB Gain with Applications to WiGig Baseband Filters - A Sallen-Key filter requires an operational amplifier with a large input impedance and a small output impedance to meet the external filter characteristics. The operational amplifier requires an internal feedback path for stability that limits performance. This invention eliminates the need for internal feedback and increases the gain of a source follower which has characteristics matching the operational amplifier in the Sallen-Key filter. The source follower provides 6 dB of AC voltage gain and is substituted for the operational amplifier in the Sallen-Key filter. The Sallen-Key filter requires a differential configuration to generate all the required signals with their compliments and uses these signals in a feed forward path. Furthermore, since the source follower uses only two n-channel stacked devices, the headroom voltage is maximized to several hundred millivolts for a 1.2V voltage supply in a 40 nm CMOS technology. Thus, the required 880 MHz bandwidth of the Sallen-Key filter can be easily met using the innovative source follower. | 2013-03-28 |
20130076435 | AMPLIFYING SYSTEM - A system for amplifying an input signal can comprise a main amplifier to amplify a delayed version of the input signal. The system can also comprise a peak amplifier to amplify the input signal upon the input signal reaching a threshold level and disable amplification upon the input signal falling below the threshold level. The system can further comprise a voltage combiner to electromagnetically couple the output of the main amplifier and the peak amplifier, such that an output impedance at an output node of the voltage combiner is a high impedance if the input signal is below the threshold level. | 2013-03-28 |
20130076436 | LOAD DETECTING IMPEDANCE MATCHING BUFFER - A buffer amplifier has a power on state and a sleep state. During regular operation a coupling state of a load to an output node is detected using feedback voltage. In a sleep mode and in a power collapse mode a detection current is injected into the output node, to produce a voltage, and the coupling state of the load is detected from the voltage. Optionally, the detection current and detecting of the voltage on the output node is enables by a low duty cycle clock. Optionally, signals generated in detecting the coupling state are qualified through a debounce circuit. | 2013-03-28 |
20130076437 | COMBINED PREDISTORTER AND FEEDFORWARD CORRECTOR APPARATUS SUITABLE FOR USE IN A TRANSMITTER - In accordance with the present disclosure, there is provided a predistorter combined with a feedforward corrector that addresses power dissipation of the feedforward error path while maintaining a sufficiently simple digital predistortion model so as to further minimize power dissipation without sacrificing linearity. | 2013-03-28 |
20130076438 | Current Efficient Mixer Architecture - In one embodiment, the present invention includes a mixer having various stages, including a transconductance stage with a differential transistor pair, a bias circuit, and a feedback circuit. The transistor pair can include a first transistor having a first terminal to receive a first input radio frequency (RF) voltage and to output a first RF current via a second terminal of the first transistor, and a second transistor having a first terminal to receive a second input RF voltage and to output a second RF current via a second terminal of the second transistor. In turn, the bias circuit is coupled to the second terminals of the transistors to provide a bias current to these transistors. The feedback circuit is in turn coupled to the second terminals of the transistors to generate a feedback signal corresponding to a common mode voltage at the second terminals of the transistors. | 2013-03-28 |
20130076439 | Limiting Amplifier And Method Thereof - A limiting amplifier and method are provided. In one implementation an apparatus includes a plurality of amplifier stages including a first amplifier stage and a last amplifier stage configured in a cascade arrangement, and a transconductance amplifier, wherein the first amplifier stage is configured to receive an input signal; the last amplifier stage outputs an output signal; the transconductance amplifier is configured receive a voltage signal from the last amplifier stage via a first resistor; and the transconductance amplifier is configured to output a current signal to an output node of the first amplifier stage via a second resistor in a negative feedback manner. | 2013-03-28 |