13th week of 2016 patent applcation highlights part 36 |
Patent application number | Title | Published |
20160092292 | DETERMINING FAILURE LOCATION IN A STORAGE SYSTEM - Embodiments of the present disclosure provide a method, a computer program product and an apparatus for determining a failure location in a storage system by obtaining performance information of a disk; in response to the performance information indicating that at least one or more performance indices exceed a corresponding predetermined threshold, determining whether a health condition of the disk is normal based on at least one or more performance indices; and in response to determining that the health condition of the disk is normal, determining a failure location based on the health condition information of at least one or more elements in a communication path of the disk, and it may be diagnosed whether a failure occurs to the disk per se or in its communication path, and before a potential failure occurs to the disk, it may also predict the failure thereby preventing data loss. | 2016-03-31 |
20160092293 | SEMICONDUCTOR MEMORY DEVICE - The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array. | 2016-03-31 |
20160092294 | FAULT TRACKING IN A TELECOMMUNICATIONS SYSTEM - A method and apparatus can be configured to automatically trigger a notifying event when a failure occurs. The method can also store information specifically relating to the failure. The storing is performed upon the automatic triggering of the notifying event. The specific information is stored such that the specific information persists after a system restart. | 2016-03-31 |
20160092295 | ADAPTIVE APPLICATION LOGGER - Embodiments of the invention provide systems and methods for logging of messages in a development environment. More specifically, embodiments of the present invention provide dynamically adaptive logging of runtime messages generated by an application. These embodiments provide a way to handle the volume of information stored in the logs by dynamically changing the severity associated with generated messages based on previous code path execution. Embodiments can use a set of metrics to replace the usual static log level associated with the code by the developer. For example, such metrics can include but are not limited to a cost-based (storage volume on disk), an exception-based (weight increase in catch block), and/or a crowd-based (community can vote down noise). As a result, embodiments can provide more detailed information when the error is recurring for a particular user but without generating so much information as to make the log difficult to use. | 2016-03-31 |
20160092296 | RESOURCE MANAGER FAILURE HANDLING IN A MULTI-PROCESS TRANSACTION ENVIRONMENT - A processor receives a request to perform a transaction, wherein each activity of the transaction is respectively associated with an application server process. The processor creates an entry in a mapping file, which includes at least information regarding the transaction, one or more resource managers to perform activities of the transaction, and the resources managed by the one or more resource managers. In response to detection of a failure of a resource manager of the one or more resource managers, the processor receives a notification from a call-back function of an XA specification switch of the resource manager associated with the failure. The processor identifies an application server process associated with the failure of the resource manager, and sends an event to terminate the application server process associated with the failure of the resource manager. | 2016-03-31 |
20160092297 | API Gateway System and Method - An API gateway provides a failure policy for services that fail when presented with a request. An API definition includes a policy for controlling subsequent calls to a server once failures are detected. The policy provides a threshold number of failures before requests are failed-fast. After a timeout period, requests are again presented to the service in an attempt to reset the system. The first request is allowed to pass and subsequent calls are either allowed to pass, if the requests succeed, or fail fast if the requests fail. When the requests succeed, the system follows a procedure to ramp up the use of the service in order to allow the system time to recover, by looping through stages configured by the service and set out in the API definition. | 2016-03-31 |
20160092298 | TIME ALIGNED TRANSMISSION OF CONCURRENTLY CODED DATA STREAMS - A method includes receiving a plurality of streams of data from a plurality of data sources. During a first time interval of receiving the streams of data, the method further includes dividing each of the plurality of streams into a first time-aligned data segment to produce a set of first time-aligned data segments. The method further includes generating a first data matrix from data blocks of the set of first time-aligned data segments. The method further includes encoding the first data matrix using an encoding matrix to produce a first coded matrix. The method further includes slicing the first coded matrix into a first set of encoded data slices based on the first orientation. The method further includes outputting a first set of encoded data slices of the first coded matrix. | 2016-03-31 |
20160092299 | METHOD AND SYSTEM FOR USING NAND PAGE BUFFERS TO IMPROVE THE TRANSFER BUFFER UTILIZATION OF A SOLID STATE DRIVE - A page data (e.g., upper page data) received from a host is stored in a transfer buffer of a controller of a solid state drive. Another page data (e.g., lower page data) is read from a non-volatile memory (e.g., a NAND memory) to store in the transfer buffer as an error corrected page data. The error corrected page data and the page data are written to the non-volatile memory. In additional embodiments, a controller loads a page data (e.g., upper page data) received from the host in one or more NAND page buffers. The controller reads another page data (e.g., lower page data) from a NAND memory to store in a transfer buffer as an error corrected page data. The error corrected page data stored in the transfer buffer is loaded to the one or more NAND page buffers. | 2016-03-31 |
20160092300 | USING RELIABILITY INFORMATION FROM MULTIPLE STORAGE UNITS AND A PARITY STORAGE UNIT TO RECOVER DATA FOR A FAILED ONE OF THE STORAGE UNITS - Provided are a method, system, and apparatus using reliability information from multiple storage units and a parity storage unit to recover data for a failed one of the storage units. A decoding operation of the codeword is performed in each of the storage units comprising the data storage units other than the target data storage unit and the parity storage unit to produce reliability information. In response to the decoding operation failing for at least one additional failed storage unit comprising the data and/or parity storage units other than the target data storage unit that failed to decode, reliability information is obtained for the data portion of the at least one additional failed storage unit. The reliability information obtained from the storage units other than the target data storage unit is used to produce corrected data for the data unit in the target data storage unit. | 2016-03-31 |
20160092301 | CORRECTING SOFT RELIABILITY MEASURES OF STORAGE VALUES READ FROM MEMORY CELLS - A method for data storage includes reading storage values, which represent stored data, from a group of memory cells using read thresholds, and deriving respective soft reliability metrics for the storage values. The storage values are classified into two or more subgroups based on a predefined classification criterion. Independently within each subgroup, a subgroup-specific distribution of the storage values in the subgroup is estimated, and the soft reliability metrics of the storage values in the subgroup are corrected based on the subgroup-specific distribution. The stored data is decoded using the corrected soft reliability metrics. | 2016-03-31 |
20160092302 | INITIALIZATION SCHEME DURING DUAL PROGRAMMING OF A MEMORY SYSTEM - A memory system or flash memory device may include mechanism for handling power loss with a dual programming architecture. The state of primary and secondary blocks may be reconstructed to a state immediately preceding a power loss. The reconstruction may include comparing error correction code (ECC) headers of blocks to recreate a block exchange with fewer control updates. The comparison can be used to identify a primary and secondary block. The header may identify a particular stream, identify a free block, identify a release block, and other information. | 2016-03-31 |
20160092303 | METHOD AND APPARATUS FOR READING DATA STORED IN FLASH MEMORY BY REFERRING TO BINARY DIGIT DISTRIBUTION CHARACTERISTICS OF BIT SEQUENCES READ FROM FLASH MEMORY - A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences. | 2016-03-31 |
20160092304 | METHOD AND SYSTEM FOR IMPROVING FLASH STORAGE UTILIZATION BY PREDICTING BAD M-PAGES - A method for managing persistent storage. The method includes selecting a page for a proactive read request, where the page is located in the persistent storage. The method further includes issuing the proactive read request to the page, receiving, in response to the proactive read request, a bit error value (BEV) for data stored on the page, obtaining a BEV threshold (T) for the page, wherein T is determined using a program/erase cycle value associated with the page and a retention time of the data stored on the page, making a first determination that the BEV is greater than T, based on the first determination: identifying an m-page, where the m-page is a set of pages and the page is in the set of pages, and setting the m-page as non-allocatable for future operations. | 2016-03-31 |
20160092305 | ECC WORD CONFIGURATION FOR SYSTEM-LEVEL ECC COMPATIBILITY - In some examples, a memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction may be performed by the memory device on each of the ECC words associated with a page and a second level of error correction may be performed on the data output by each of the input/output pads during a particular period of time. Each of the one or more input/output pads of the memory device may be configured to provide only one bit of data per ECC word to an external source during an access from an external source. | 2016-03-31 |
20160092306 | PLATFORM ERROR CORRECTION - An example device in accordance with an aspect of the present disclosure includes a first error corrector to perform platform error correction based on a stride length. A memory includes a second error corrector that is to perform on-memory error correction that is to be disabled for platform error correction. | 2016-03-31 |
20160092307 | EXCHANGING ECC METADATA BETWEEN MEMORY AND HOST SYSTEM - Exposing internal error correction bits from a memory device for use as metadata bits by an external memory controller. In a first mode the memory device applies internal error correction bits for internal error correction at the memory device. In a second mode the memory device exposes the internal error correction bits to the memory controller to allow the memory controller to use the data. | 2016-03-31 |
20160092308 | DISASTER RECOVERY SYSTEM - Disclosed herein is a computer implemented method of performing recovery for a customer server system that has an associated backup of server system data of the customer server system, the method comprising the steps of: receiving a server recovery request at a portal for a rebuild of at least part of the customer server system; and, sending a request from the portal to a cloud-based data centre for on-demand provisioning of cloud-based server resources, wherein the request includes information on the location of at least part of the backup of the server system data to enable the deployment of a rebuild of at least part of the customer server system at the cloud-based data centre. Advantages include a user being able to easily manage disaster recovery testing as well as actual live recovery operations. The use of temporary servers in the cloud is an efficient, and inexpensive, use of resources as the servers can be rented and used only when required. | 2016-03-31 |
20160092309 | OPTIMIZATION OF REBUILDING IN SOLID STATE DRIVES - According to one embodiment, a method includes initiating a rebuild process in a storage system having at least one solid state drive, obtaining a bitmap indicating which blocks of data are in a garbage collection process, determining which blocks of data are in the garbage collection process using the bitmap, accessing the blocks of data that are not in the garbage collection process, not accessing the blocks of data that are in the garbage collection process, and performing the rebuild process using the blocks of data that are not in the garbage collection process. | 2016-03-31 |
20160092310 | SYSTEMS AND METHODS FOR MANAGING GLOBALLY DISTRIBUTED REMOTE STORAGE DEVICES - Methods and systems are described managing module for remotely managing hardware of at least one of a plurality of distributed remote storage devices. A computer implemented method includes locally monitoring a system (including, for example, a core operating system) of the hardware, locally detecting an abnormal or unresponsive state of the system, generating a notice when the abnormal or unresponsive state is detected, delivering the notice to a remotely located central service, and automatically rebooting the hardware when the abnormal or unresponsive state is detected. | 2016-03-31 |
20160092311 | UTILIZING AN INCREMENTAL BACKUP IN A DECREMENTAL BACKUP SYSTEM - Utilizing an incremental backup in a decremental backup system. In one example embodiment, a method for utilizing an incremental backup in a decremental backup system includes creating a base backup that includes all original allocated blocks in a source storage at a first point in time. Next, an incremental backup is created that includes allocated blocks in the source storage that were newly allocated or were changed between the first point in time and a second point in time. The changed allocated blocks in the incremental backup are identified. During a third time period, a decremental backup is created and the incremental backup is ingested into the base backup by copying, into the decremental backup, original allocated blocks from the base backup that correspond to the changed allocated blocks in the incremental backup. Lastly, the newly-allocated blocks and the changed allocated blocks from the incremental backup are added to the base backup. | 2016-03-31 |
20160092312 | DEDUPLICATED DATA DISTRIBUTION TECHNIQUES - In connection with a data distribution architecture, client-side “deduplication” techniques may be utilized for data transfers occurring among various file system nodes. In some examples, these deduplication techniques involve fingerprinting file system elements that are being shared and transferred, and dividing each file into separate units referred to as “blocks” or “chunks.” These separate units may be used for independently rebuilding a file from local and remote collections, storage locations, or sources. The deduplication techniques may be applied to data transfers to prevent unnecessary data transfers, and to reduce the amount of bandwidth, processing power, and memory used to synchronize and transfer data among the file system nodes. The described deduplication concepts may also be applied for purposes of efficient file replication, data transfers, and file system events occurring within and among networks and file system nodes. | 2016-03-31 |
20160092313 | Application Copy Counting Using Snapshot Backups For Licensing - Technologies are described herein to use snapshot backups for licensing. Some example technologies may access a snapshot backup that is taken during an execution of a virtual machine on a server. One or more snapshot backups may be examined to detect applications that executed on the server at a time the snapshot backup was taken. A determination may be made as to what applications that were identified are subject to a license. Licensing information may be provided that includes information associated with the one or more of the applications that are subject to the license. | 2016-03-31 |
20160092314 | HIGH AVAILABILITY PROTECTION FOR ASYNCHRONOUS DISASTER RECOVERY - A computer-implemented method, carried out by one or more processors, for a modified asynchronous replication session. In an embodiment, the method comprises the steps of acquiring a lock on a volume configuration, where the lock prevents changes to the volume configuration between a first volume and a second volume at a remote site. Internal control block information is updated, where the update includes at least a volume serial number of the first volume matching a volume serial number of the second volume. Responsive to updating internal control block information, the acquired lock is released to allow changes to the volume configuration. | 2016-03-31 |
20160092315 | FILE SYSTEM FOR ROLLING BACK DATA ON TAPE - Rolling back data on tape in a file system is provided. A management tape is prepared. The management tape has only index files recorded thereon. The index files contain information about start positions and lengths of corresponding data files recorded on normal tapes. The index files further contain identification information for the normal tapes. A first index file of the management tape is read. The first index file is related to a data file to be rolled back. The first index file is read out from the management tape mounted on a first tape drive. The data file to be rolled back is read out of a first normal tape. The first normal tape is identified based on information in the first index file. The first normal tape is mounted on a second tape drive. | 2016-03-31 |
20160092316 | STAGED RESTORE OF A DECREMENTAL BACKUP CHAIN - Staged restore of a decremental backup chain. In one example embodiment, a method includes, first, restoring a first backup of a source storage to a restore storage. Next, a second backup of the source storage in a decremental backup chain of the source storage is identified. Then, a third backup of the source storage in the decremental backup chain of the source storage is identified. Next, blocks in the decremental backup chain that were newly allocated in the source storage between the first point in time and the second point in time are identified. Then, the newly-allocated blocks are restored to the restore storage. Next, blocks in the decremental backup chain that were changed in the source storage between the first point in time and the second point in time are identified. Lastly, the changed blocks are restored to the restore storage. | 2016-03-31 |
20160092317 | STREAM-PROCESSING DATA - A method for stream-processing data including a missing part in real time and thereafter updating the result of the stream processing. A technique for processing data is included. The technique includes receiving data; detecting a probably missing part in the received data while stream-processing the received data in real time; and comparing master data corresponding to the received data and having no missing part with the probably missing part, and if the received data has the missing part, updating the result of the stream processing using the master data. | 2016-03-31 |
20160092318 | RESOURCE MANAGER FAILURE HANDLING IN A MULTI-PROCESS TRANSACTION ENVIRONMENT - A processor receives a request to perform a transaction, wherein each activity of the transaction is respectively associated with an application server process. The processor creates an entry in a mapping file, which includes at least information regarding the transaction, one or more resource managers to perform activities of the transaction, and the resources managed by the one or more resource managers. In response to detection of a failure of a resource manager of the one or more resource managers, the processor receives a notification from a call-back function of an XA specification switch of the resource manager associated with the failure. The processor identifies an application server process associated with the failure of the resource manager, and sends an event to terminate the application server process associated with the failure of the resource manager. | 2016-03-31 |
20160092319 | SYSTEM AND METHOD FOR TRANSACTION RECOVERY IN A MULTITENANT APPLICATION SERVER ENVIRONMENT - In accordance with an embodiment, described herein is a system and method for transaction recovery in a multitenant application server environment. At least one resource manager associated with a partition can be designated as a determiner resource for that partition only, in order to support eliminating transaction logs (TLOG) in processing a two-phase commit transaction. A transaction manager can prepare all other resource managers in the mid-tier transactional system before the determiner resource. Furthermore, the transaction manager can rely on the list of outstanding transactions to be committed that is provided by the determiner resource for recovering the transaction. The transaction manager can commit an in-doubt transaction returned from a resource manager that matches the list of in-doubt transactions returned from the determiner resource. Otherwise, the transaction manager can roll back the in-doubt transaction. | 2016-03-31 |
20160092320 | ELECTRONIC FAULT DETECTION UNIT - An electronic fault detection unit is provided that has a first register, a second register, a comparator circuit, and a timer circuit. The first and second register can be written from a first software portion, and a second software portion, respectively. The comparator circuit is arranged to detect that both the first and second register have been written, verify a relationship between first data written to the first register and second data written to the second register, and signal a fault upon said verification failing. The timer circuit is arranged to signal a fault if said verification of the comparator circuit does not occur within a time limit. | 2016-03-31 |
20160092321 | RECORDING MEDIUM STORING CONTROL PROGRAM, CONTROL DEVICE AND CONTROL METHOD - A non-transitory computer-readable recording medium stores therein a control program. The control program is executed by a control device that controls an access point conducting a communication by using a first identifier. The control device identifies an access point that becomes a target of disaster setting, in which a communication is conducted by using a second identifier different from the first identifier, on the basis of disaster information obtained from a providing source of information. The control device outputs, to a user interface, information for confirming whether or not the disaster setting is to be applied. Further, the control device sends an instruction to apply the disaster setting to the access point when a request to apply the disaster setting has been obtained. | 2016-03-31 |
20160092322 | SEMI-AUTOMATIC FAILOVER - Semi-automatic failover includes automatic failover by a service provider as well as self-serviced failover by a service consumer. A signal can be afforded by a service provider based on analysis of an incident that affects the service provider. Initiation of self-serviced failover by a service consumer can be predicated on the signal. In one instance, the signal provides information that aids a decision of whether or not to failover. In another instance, the signal can grant or deny permission to perform a self-serviced failover. | 2016-03-31 |
20160092323 | MULTI-PARTITION NETWORKING DEVICE AND METHOD THEREFOR - A multi-partition networking device comprising a primary partition running on a first set of hardware resources and a secondary partition running on a further set of hardware resources. The multi-partition networking device is arranged to operate in a first operating state, whereby the first set of hardware resources are in an active state and the primary partition is arranged to process network traffic, and the further set of hardware resources are in a standby state. The multi-partition networking device is further arranged to transition to a second operating state upon detection of a suspicious condition within the primary partition, whereby the further set of hardware resources are transitioned from a standby state to an active state, and to transition to a third operating state upon detection of a failure condition within the primary partition, whereby processing of network traffic is transferred to the secondary partition. | 2016-03-31 |
20160092324 | FAST SINGLE-MASTER FAILOVER - Techniques for switching mastership from one service in a first data center to a second (redundant) service in a second data center are provided. A service coordinator in the first data center is notified about the master switch. The service coordinator notifies each instance of the first service that the first service is not a master. Each instance responds with an acknowledgement. After it is confirmed that all instances of the first service have responded with an acknowledgement, a client coordinator in the first and/or second data center is updated to indicate that the second service is the master so that clients may send requests to the second service. Also, a service coordinator in the second data center is notified that the second service is the master. The service coordinator notifies each instance of the second service that the second service is the master. Each instance responds with an acknowledgement. | 2016-03-31 |
20160092325 | FAILURE LOGGING MECHANISM TO REDUCE GARBAGE COLLECTION TIME IN PARTIALLY REUSED BAD BLOCKS - A memory system logs failures to optimize garbage collection in partial bad blocks that are reused in non-volatile memory. A failure in a primary block may be logged in an inverse global address table. A garbage collection operation can reference the log in order to automatically avoid the failure in the primary block when the primary block is picked as the source block for garbage collection. Likewise, the garbage collection operation may scan only the logged wordlines in the secondary block when the secondary block is picked as the source block for garbage collection. | 2016-03-31 |
20160092326 | METHOD AND APPARATUS FOR ACCELERATING DATA RECONSTRUCTION FOR A DISK ARRAY - A method, system, and computer program product for accelerating data reconstruction for a disk array, the disk array comprising a plurality of physical disks, the method, system, and computer program product including virtualizing the plurality of physical disks as a plurality of virtual disks, applying a data protection algorithm to the plurality of virtual disks to obtain redundant information on data to be stored, providing a map from the plurality of virtual disks to the plurality of physical disks, storing, based on the map, the data and the redundant information in the plurality of physical disks according to a predetermined allocation policy, and in response to at least one of the plurality of physical disks failing, implementing a data reconstruction for a disk array based on the redundant information and the data in working disks from amongst the plurality of physical disks. | 2016-03-31 |
20160092327 | DEBUGGING SYSTEM AND DEBUGGING METHOD OF MULTI-CORE PROCESSOR - The invention relates to a debugging system and a debugging method of a multi-core processor. The debugging system includes a debugging host, a target processor, and a mapping and protocol conversion device. The debugging host includes a debugger, and the target processor includes a plurality of cores. The mapping and protocol conversion device is connected between the debugging host and the target processor, identifies a core architecture to which each of the cores belongs, and maps each of the cores respectively to at least one thread of at least one process according to the core architecture to which each of the cores belongs. Afterwards, the debugger executes a debugging procedure on the target processor according to the process and the thread corresponded to each of the cores. | 2016-03-31 |
20160092328 | MEMORY DEVICE TEST APPARATUS AND METHOD - Disclosed herein are a method and an apparatus for shortening a data comparison test time by using peer-to-peer transfers between peripheral component interconnect express (PCIe) endpoints when testing solid state drive (SSD) devices. A memory device test apparatus performing a data comparison test of a memory device mounted in a downstream port of a peripheral component interconnect express (PCIe) switch by performing a writing process and a reading-back process by a control of a host central processing unit (CPU) includes: a comparison test unit (FPGA) connected to the downstream port of the PCIe switch, performing peer-to-peer communication with the memory device to supply write data to the memory device and receive read-back data from the memory device, and performing the data comparison test. | 2016-03-31 |
20160092329 | Final Result Checking For System With Pre-Verified Cores - Provided are a system and method for generating final result checking for a test case. A test case is executed for a coherent memory system having a processor core. An event log is generated for the processor core. The event log is analyzed. The test case for the core is annotated with a checker for performing expected data checking for physical addresses modified by the processor core. | 2016-03-31 |
20160092330 | DEVICE, METHOD AND PROGRAM FOR PERFORMING SYSTEM TESTING - In an approach for testing the operations of a host system during a host system migration, a terminal agent exchanges messages already exchanged between the current host system and a terminal with the new host system. A manual operation replay unit replays messages generated by manual operations among the messages sent to the current host system by the terminal. An automatic response unit automatically generates a response message for messages received from the new host system. The automatic response unit also generates screen data for a screen displayed on the terminal on the basis of messages received from the new host system. A comparison unit compares and evaluates screen data generated by the automatic response unit and screen data from a screen generated by the terminal on the basis of messages received from the current host system. | 2016-03-31 |
20160092331 | REDUNDANT TRANSACTIONS FOR SYSTEM TEST - A method for detecting errors in hardware including running a transaction on a plurality of cores, wherein each of the cores runs a respective copy of the transaction, periodically synchronizing the transaction on the cores throughout execution of the transaction, comparing results of the transaction on the cores, and determining an error in one or more of the cores. | 2016-03-31 |
20160092332 | CONTROLLING A BYTE CODE TRANSFORMER ON DETECTION OF COMPLETION OF AN ASYNCHRONOUS COMMAND - Controlling a byte code transformer on detection of completion of an asynchronous command. An asynchronous command is received by an asynchronous manager from a test framework. The asynchronous command manager issues the asynchronous command to an application. A transformer is loaded for transforming byte code associated with the application in order to output one or more method names and associated timestamps of one or more method entry points and one or more method exit points. A check is made as to whether an expected result has been generated by the application. In response to determining that an expected result has been successfully generated, a time period associated with successful generation of the expected result is compared with the timestamps in order to determine matching timestamps and associated matching method names. The transformer is modified in accordance with the matching method names such that a subsequent transformation executes on byte code associated with the matching method names. | 2016-03-31 |
20160092333 | Telemetry for Data - Embodiments are directed to a unified and extensible telemetry method together with a data telemetry model aimed at the data activities of a system. Information collected using the telemetry data model is analyzed using telemetry analytics to derive insights on data activities, through the analysis of single events and subsequent linear relationships between these events, as well as the more generally networked multi-dimensional relationships among the data activities. Such analysis can provide insights for system owners to understand past data activities, optimize current data activities, and predict future data activity demands and requirements. | 2016-03-31 |
20160092334 | EVALUATING FAIRNESS IN DEVICES UNDER TEST - Pre-silicon fairness evaluation to detect fairness issues pre-silicon. Drivers drive a plurality of commands on one or more interfaces of a device under test to test the device under test. State associated with the device under test is checked. Based on the state, a determination is made as to whether the drivers are to continue driving commands against the device under test. Based on determining that the drivers are to continue driving the commands, a further determination is made as to whether a predefined limit has been reached. Based on determining the predefined limit has been reached, ending the test of the device under test in which the test fails. | 2016-03-31 |
20160092335 | LINK RETRAINING BASED ON RUNTIME PERFORMANCE CHARACTERISTICS - Systems and methods may provide for monitoring one or more runtime performance characteristics of a link and determining a state of the link based on at least one of the one or more runtime performance characteristics. Additionally, a retraining of the link may be automatically scheduled based on the state of the link. In one example, scheduling the retraining of the link further includes setting one or more retraining parameters. | 2016-03-31 |
20160092336 | CODE ANALYSIS FOR CLOUD-BASED INTEGRATED DEVELOPMENT ENVIRONMENTS - The disclosure generally describes computer-implemented methods, software, and systems, including methods for generating visualizations. On a client side, a user request is received for an inter-entity call visualization. Code analysis data is accessed. A visualization model is built. The visualization is shown. User inputs are received for interacting with the visualization. The visualization is updated based on the received user inputs. On a server side, a request is received for code analysis data. The requested data collected, including running analyzers for any available data. The requested data is sent. The code analysis data can be used for other purposes than visualizations. | 2016-03-31 |
20160092337 | EVALUATING FAIRNESS IN DEVICES UNDER TEST - Pre-silicon fairness evaluation to detect fairness issues pre-silicon. Drivers drive a plurality of commands on one or more interfaces of a device under test to test the device under test. State associated with the device under test is checked. Based on the state, a determination is made as to whether the drivers are to continue driving commands against the device under test. Based on determining that the drivers are to continue driving the commands, a further determination is made as to whether a predefined limit has been reached. Based on determining the predefined limit has been reached, ending the test of the device under test in which the test fails. | 2016-03-31 |
20160092338 | INSTALLATION HEALTH DASHBOARD - The disclosure generally describes computer-implemented methods, software, and systems for presenting error information. Logs are received from different locations, the logs associated with a plurality of builds at the different locations and associated with one or more systems. The logs are stored in a centralized location. Build information is generated for a given build, including identifying errors associated with the given build. Information for a current log associated with the given build is analyzed, including accessing information for previous logs associated with previous related builds related to the given build. Based on the analyzing, error diagnostic information that is to be presented is determined, including an analysis of errors that occurred in the given build and previous related builds. Instructions are provided, the instructions operable to present the error diagnostic information to a user, including providing log information, for presentation in a user interface. | 2016-03-31 |
20160092339 | EFFICIENT MEANS TO TEST SERVER GENERATED APPLICATIONS ON MOBILE DEVICE - Systems and methods are provided to test changes for a mobile app built by web-based tooling directly on a physical mobile device. A first application can be loaded on a mobile device. The first application can receive metadata of a second application. The first application can execute the second application using the metadata. Access to local resources can be intercepted and redirected to the server for processing. Additionally, changes made to the second application using the web-based tooling can be pushed to the first application using a persistent channel allowing the changes to be immediately tested. | 2016-03-31 |
20160092340 | METHOD AND SYSTEM FOR REVIEWING OF CLUSTERED-CODE ANALYSIS WARNINGS - A system and method for reviewing of warning generated during static analysis of a clustered software code by identifying, common point warnings and unique warnings from warnings associated with a software code, and further identifying, a top of must overlapped function for each of the common point warnings. Generating, one or more groups of the common point warnings based on the top of must overlapped function, and assigning, the top of must overlapped function as a constraint for corresponding group of common point warnings. Eliminating, warnings from each of the one or more groups using a review output wherein the review output is identified by reviewing a common point warning from the one or more group under the constraint such that the review of the common point warning under the constraint satisfy for review of all remaining for reviews of all remaining common point warnings of the group. | 2016-03-31 |
20160092341 | USING HARDWARE PERFORMANCE COUNTERS TO DETECT STALE MEMORY OBJECTS - Systems and methods may provide for conducting an object trace of an allocation status of one or more objects in a computing system and using one or more hardware performance counters to conduct a hardware based address profiling of the computing system. Additionally, one or more stale objects in the system may be automatically identified based on the object trace and the hardware based address profiling. In one example, the object trace is initiated prior to a start of a task on the computing system and the hardware based address profiling is initiated in response to an end of the task on the computing system. | 2016-03-31 |
20160092342 | SYSTEM AND METHOD FOR DYNAMIC DEBUGGING IN A MULTITENANT APPLICATION SERVER ENVIRONMENT - In accordance with an embodiment, described herein is a system and method for dynamic debugging in an application server environment. An exemplary method can provide, at one or more computers, including an application server environment executing thereon, a plurality of deployable resources which can be used within the application server environment, one or more running managed servers, the one or more managed servers being within a domain, and a debug framework, the debug framework comprising a debug patch directory, the debug patch directory containing one or more debug patches. The method can activate a selected debug patch within the domain, the selected debug patch comprising at least one class, the selected debug patch designed to gather information about the problem within the domain. The managed servers, upon activation of the selected debug patch, can remain running. The method can also deactivate the selected debug patch without requiring a restart. | 2016-03-31 |
20160092343 | DATACENTER MANAGEMENT COMPUTING SYSTEM - A system may include an active first point of deployment (POD) configured to provide a specified business functionality and may include a first server and a first instance of a platform to provide the specified business function. A dark second POD may be configured to include a second server and a second instance of the platform template, where the first platform template instance comprises a different version than the second platform template instance. A POD management computing device may test an operation of the second POD in parallel with the operation of the first POD. The POD management computing device may upgrade the business functionality by deactivating the first POD and activating the second POD to provide the specified business function using the second instance of the platform template. | 2016-03-31 |
20160092344 | END-TO-END, LIFECYCLE AWARE, API MANAGEMENT - An application programming interface (API) consumption development environment (CDE) is integrated with an API administration component and a determination is made whether an existing API conforms to application development requirements. A desired API is defined including test data, and the desired API and test data is forwarded to an API developer as a development request. The API CDE is integrated with the API administration component. A developed API is deployed to an API provider creating an integration testing deployment, and the API administration component is notified of the integration testing deployment. The developed API is deployed to an API provider productive for productive use. | 2016-03-31 |
20160092345 | PATH-SPECIFIC BREAK POINTS FOR STREAM COMPUTING - A plurality of processing elements having stream operators and operating on one or more computer processors receive a stream of tuples. A first stream operator adds a first attribute to a tuple received on a first port of the first stream operator. The first attribute indicates the first port and the first stream operator. A second stream operator adds a second attribute to a tuple received on a first port of the second stream operator. The second attribute indicates the first port of the second stream operator and the second stream operator. It is determined whether a debug tuple has been received by a third stream operator. A debug tuple is a tuple that includes the first and second attributes. An operation, such as halting execution or incrementing a count of debug tuples, is performed when it is determined that a debug tuple has been received. | 2016-03-31 |
20160092346 | COVERAGE GUIDED TECHNIQUE FOR BUG FINDING IN CONTROL SYSTEMS AND SOFTWARE - A computer-implemented method for automatically identifying a faulty behavior of a control system. The method includes receiving, at a test processor, a description of the faulty behavior. The method also includes selecting, using the test processor, a goal state based on a heuristic decision. The method also includes selecting, using the test processor, a selected system state. The method also includes selecting, using the test processor, a selected variable to the control system based on the goal state. The method also includes loading, from a memory, a control model of the control system. The method also includes performing, using the test processor, a simulation of the control model using the selected variable and the selected system state as parameters of the simulation. The method also includes determining, using the test processor, whether the faulty behavior was observed based on the simulation. | 2016-03-31 |
20160092347 | MEDICAL SYSTEM TEST SCRIPT BUILDER - Computerized systems and methods facilitate the generation of customized test scripts for testing customized healthcare information technology systems. A number of different test script templates may be provided that each corresponds with a different scenario of use of the healthcare information technology system. A user may select a test script template and modify the test script template to generate a customized test script to meet the unique design and/or patient scenarios for a given installation of a healthcare information technology system. The test script template modification process may include first presenting an outline of the test script template, which the user may choose to modify. A detailed view of the test script template may then be provided that allows the user to view and customize actions and expected results in order to generate the customized test script. | 2016-03-31 |
20160092348 | UPDATABLE NATIVE MOBILE APPLICATION FOR TESTING NEW FEATURES - For cloud development tools building native mobile applications, it is often useful to test out parts of an application on a physical device. Systems and methods are provide for providing an native application that allows portions of itself to uptake newly developed features allowing rapid testing of these features. | 2016-03-31 |
20160092349 | CORRELATING OUT-OF-BAND PROCESS DATA DURING MOBILE TEST AUTOMATION - Methods and arrangements for testing mobile applications. A mobile application for testing is input at a mobile device. The mobile application is automatically tested using a test script, wherein the testing requires data from an out-of-band channel. The testing includes: invoking a listener module based on the mobile application; using the listener module to automatically obtain data from an out-of-band channel; and communicating the automatically obtained data to the mobile application. Other variants and embodiments are broadly contemplated herein. | 2016-03-31 |
20160092350 | CALLPATH FINDER - Techniques and systems for creating a function call graph for a codebase are disclosed. Graph creation includes identifying functions in the codebase by a function signature and representing a function as a first node in the call graph. For that function, identifying call-to functions, call-from functions, and inheritance parents and children, and a base class from the function signature of that function; adding child nodes to the first node based on the identified call-to and call-from functions; for an interface call to a base class method in the function, adding child nodes to the first node based on implementations of an override of the base class method; for an added child node, removing that child node from the first node if a source file that includes an implementation of an override and a source code file that includes the function don't share at least one common binary file. | 2016-03-31 |
20160092351 | MEMORY MODULE HAVING DIFFERENT TYPES OF MEMORY MOUNTED TOGETHER THEREON, AND INFORMATION PROCESSING DEVICE HAVING MEMORY MODULE MOUNTED THEREIN - A memory module having different types of memory mounted together on a double-sided substrate has a first edge and opposite second edge and includes a plurality of memory controllers, a plurality of flash memories, and a plurality of second memories having a higher signal transmission rate than the flash memories. A socket terminal for connecting the double-sided substrate to a motherboard is formed on the front surface and the back surface of the double-sided substrate on the first edge side; the memory controllers are disposed on the second edge side; the second memories are disposed on the second edge side at positions opposite the positions at which the memory controllers are disposed; and the flash memories are disposed on at least the back surface thereof at positions that are closer to the first edge than are the positions at which the memory controllers and the second memories are disposed. | 2016-03-31 |
20160092352 | REDUCING WRITE AMPLIFICATION IN SOLID-STATE DRIVES BY SEPARATING ALLOCATION OF RELOCATE WRITES FROM USER WRITES - In one embodiment, a method includes maintaining a first open logical erase block for user writes, maintaining a second open logical erase block for relocate writes, wherein the first and second open logical erase blocks are different logical erase blocks, receiving a first data stream having the user writes, transferring the first data stream to the first open logical erase block, receiving a second data stream having the relocate writes, and transferring the second data stream to the second open logical erase block. Other systems, methods, and computer program products are described in additional embodiments. | 2016-03-31 |
20160092353 | ESTABLISHING COLD STORAGE POOLS FROM AGING MEMORY - Systems and methods may provide for detecting a pending write operation directed to a target memory region and determining whether the target memory region satisfies a degradation condition in response to the pending write operation. Additionally, the target memory region may be automatically reconfigured as a cold storage region if the target memory region satisfies the degradation condition. In one example, determining whether the target memory region satisfies the degradation condition includes updating the number of write operations directed to the target memory region based on the pending write operation and comparing the number of write operations to an offset value, wherein the degradation condition is satisfied if the number of write operations exceeds the offset value. | 2016-03-31 |
20160092354 | HARDWARE APPARATUSES AND METHODS TO CONTROL CACHE LINE COHERENCY - Methods and apparatuses to control cache line coherency are described. A processor may include a first core having a cache to store a cache line, a second core to send a request for the cache line from the first core, moving logic to cause a move of the cache line between the first core and a memory and to update a tag directory of the move, and cache line coherency logic to create a chain home in the tag directory from the request to cause the cache line to be sent from the tag directory to the second core. A method to control cache line coherency may include creating a chain home in a tag directory from a request for a cache line in a first processor core from a second processor core to cause the cache line to be sent from the tag directory to the second processor core. | 2016-03-31 |
20160092355 | SPLIT WRITE OPERATION FOR RESISTIVE MEMORY CACHE - A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes receiving a read command and executing the read command before executing a next write sub-command. | 2016-03-31 |
20160092356 | INTEGRATED PAGE-SHARING CACHE - In an embodiment, a method can include storing a plurality of volumes on persistent media. A set of the volumes can store at least one portion of a same copy of data. The method can further include caching the set of the volumes as a single group. In an embodiment, the plurality of volumes can include at least one of drives, snapshots, clones and replicas. | 2016-03-31 |
20160092357 | Apparatus and Method to Transfer Data Packets between Domains of a Processor - In an embodiment, a processor includes a first domain to operate according to a first clock. The first domain includes a write source, a payload bubble generator first in first out buffer (payload BGF) to store data packets, and write credit logic to maintain a count of write credits. The processor also includes a second domain to operate according to a second clock. When the write source has a data packet to be stored while the second clock is shut down, the write source is to write the data packet to the payload BGF responsive to the count of write credits being at least one, and after the second clock is restarted the second domain is to read the data packet from the payload BGF. Other embodiments are described and claimed. | 2016-03-31 |
20160092358 | CACHE COHERENCY VERIFICATION USING ORDERED LISTS - Embodiments relate to cache coherency verification using ordered lists. An aspect includes maintaining a plurality of ordered lists, each ordered list corresponding to a respective thread that is executed by a processor, wherein each ordered list comprises a plurality of atoms, each atom corresponding to a respective operation performed in a cache by the respective thread that corresponds to the ordered list in which the atom is located, wherein the plurality of atoms in an ordered list are ordered based on program order. Another aspect includes determining a state of an atom in an ordered list of the plurality of ordered lists. Another aspect includes comparing the state of the atom in an ordered list to a state of an operation corresponding to the atom in the cache. Yet another aspect includes, based on the comparing, determining that there is a coherency violation in the cache. | 2016-03-31 |
20160092359 | MULTI-GRANULAR CACHE MANAGEMENT IN MULTI-PROCESSOR COMPUTING ENVIRONMENTS - Cache lines in a multi-processor computing environment are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. Each cache is associated with a directory having a number of directory entries and with a side table having a smaller number of entries. The directory entry for a cache line associates the cache line with a tag and a set of full-line descriptive bits. Creating a side table entry for the cache line places the cache line in sub-line coherency mode. The side table entry associates each of the sub-cache line portions of the cache line with a set of sub-line descriptive bits. Removing the side table entry may return the cache line to full-line coherency mode. | 2016-03-31 |
20160092360 | HYBRID CACHE COMPRISING COHERENT AND NON-COHERENT LINES - An electronic system for multiple agents, both coherent and non-coherent, to communicate with a hybrid cache, the hybrid cache to provide functionality associated with a cache for coherent agents in an outer shareable domain, and to provide functionality associated with a cache for non-coherent agents in a system shareable domain, the functionality provided by tag fields in cache lines stored in the hybrid cache. The tag fields are configured to indicate if a cache line of the hybrid cache belongs to at least one of a logical coherent cache or a logical system cache. | 2016-03-31 |
20160092361 | CACHING TECHNOLOGIES EMPLOYING DATA COMPRESSION - Caching technologies that employ data compression are described. The technologies of the present disclosure include cache systems, methods, and computer readable media in which data in a cache line is compressed prior to being written to cache memory. In some embodiments the technologies enable a caching controller to understand the degree to which data in a cache line is compressed, prior to writing the compressed data to cache memory. Consequently the cache controller may determine where the compressed data is to be stored in cache memory based at least in part on the size of the compressed data, a compression ratio attributable to the compressed data (or its corresponding input data), or a combination thereof. | 2016-03-31 |
20160092362 | MEMORY NETWORK TO ROUTE MEMORY TRAFFIC AND I/O TRAFFIC - According to an example, memory traffic including memory access commands is routed between compute nodes and memory nodes in a memory network. Other traffic is also routed in the memory network. The other traffic may include input/output traffic between the compute nodes and peripherals connected to the memory network. | 2016-03-31 |
20160092363 | Cache-Aware Adaptive Thread Scheduling And Migration - In one embodiment, a processor includes: a plurality of cores each to independently execute instructions; a shared cache memory coupled to the plurality of cores and having a plurality of clusters each associated with one or more of the plurality of cores; a plurality of cache activity monitors each associated with one of the plurality of clusters, where each cache activity monitor is to monitor one or more performance metrics of the corresponding cluster and to output cache metric information; a plurality of thermal sensors each associated with one of the plurality of clusters and to output thermal information; and a logic coupled to the plurality of cores to receive the cache metric information from the plurality of cache activity monitors and the thermal information and to schedule one or more threads to a selected core based at least in part on the cache metric information and the thermal information for the cluster associated with the selected core. Other embodiments are described and claimed. | 2016-03-31 |
20160092364 | MANAGEMENT OF STORAGE SYSTEM - In an approach for managing a storage system, distribution of storage volumes among a plurality of storage controller groups may be adjusted dynamically or adaptively based on the current access hot degrees of respective storage volumes in the storage system. In this way, optimized distribution of storage volumes can be achieved without user interference. Such redistribution eliminates the degradation of performance of the storage system. | 2016-03-31 |
20160092365 | SYSTEM AND METHOD FOR COMPACTING PSEUDO LINEAR BYTE ARRAY - In accordance with an embodiment, described herein is a system and method for compacting a pseudo linear byte array, for use with supporting access to a database. A database driver (e.g., a Java Database Connectivity (JDBC) driver) provides access by software application clients to a database. When a result set (e.g., ResultSet) is returned for storage in a dynamic byte array (DBA), in response to a database query (e.g., a SELECT), the database driver determines if the DBA is underfilled and, if so, calculates the data size of the DBA, creates a static byte array (SBA) in a cache at the client, compacts the returned data into the SBA, and stores the data size as part of the metadata associated with the cache. In accordance with an embodiment, the DBA and the SBA can use a same interface for access by client applications. | 2016-03-31 |
20160092366 | METHOD AND APPARATUS FOR DISTRIBUTED SNOOP FILTERING - An apparatus and method are described for distributed snoop filtering. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions and process data; first snoop logic to track a first plurality of cache lines stored in a mid-level cache (“MLC”) accessible by one or more of the cores, the first snoop logic to allocate entries for cache lines stored in the MLC and to deallocate entries for cache lines evicted from the MLC, wherein at least some of the cache lines evicted from the MLC are retained in a level 1 (L1) cache; and second snoop logic to track a second plurality of cache lines stored in a non-inclusive last level cache (NI LLC), the second snoop logic to allocate entries in the NI LLC for cache lines evicted from the MLC and to deallocate entries for cache lines stored in the MLC, wherein the second snoop logic is to store and maintain a first set of core valid bits to identify cores containing copies of the cache lines stored in the NI LLC. | 2016-03-31 |
20160092367 | HARDWARE APPARATUSES AND METHODS TO CONTROL ACCESS TO A MULTIPLE BANK DATA CACHE - Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. In another embodiment, a method includes detecting multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle, and granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. | 2016-03-31 |
20160092368 | CACHE COHERENCY VERIFICATION USING ORDERED LISTS - Embodiments relate to cache coherency verification using ordered lists. An aspect includes maintaining a plurality of ordered lists, each ordered list corresponding to a respective thread that is executed by a processor, wherein each ordered list comprises a plurality of atoms, each atom corresponding to a respective operation performed in a cache by the respective thread that corresponds to the ordered list in which the atom is located, wherein the plurality of atoms in an ordered list are ordered based on program order. Another aspect includes determining a state of an atom in an ordered list of the plurality of ordered lists. Another aspect includes comparing the state of the atom in an ordered list to a state of an operation corresponding to the atom in the cache. Yet another aspect includes, based on the comparing, determining that there is a coherency violation in the cache. | 2016-03-31 |
20160092369 | Partner-Aware Virtual Microsectoring for Sectored Cache Architectures - Embodiments described include systems, apparatuses, and methods using sectored dynamic random access memory (DRAM) cache. An exemplary apparatus may include at least one hardware processor core and a sectored dynamic random access (DRAM) cache coupled to the at least one hardware processor core. | 2016-03-31 |
20160092370 | PASS-THROUGH TAPE ACCESS IN A DISK STORAGE ENVIRONMENT - A command to write data to a virtual location is received at a disk storage system. The virtual location is mapped to a tape storage system. A record is generated including the data, the virtual location, and a sequence value. The sequence value indicates relative sequence when compared to other sequence values. The record is written to a record location on a tape cartridge loaded in a tape drive. Record metadata on the disk storage system is modified to indicate that the first record location contains the first record. The data on the record can be read from the tape cartridge. | 2016-03-31 |
20160092371 | Method and Apparatus For Deterministic Translation Lookaside Buffer (TLB) Miss Handling - An apparatus and method are described for translation lookaside buffer (TLB) miss handling. For example, one embodiment of a processor comprises: a translation lookaside buffer (TLB) to store virtual-to-physical address translations; a page miss handler (PMH) to process TLB misses when a desired virtual-to-physical address translation is not present in the TLB; and a compressed page table to be managed by the PMH, the compressed page table to store specified portions of page tables, wherein in response to a TLB miss for a first address translation, the PMH is to check the compressed page table to determine if a page table entry corresponding to the first address translation is stored therein and, if so, to provide the first address translation from the compressed page table. | 2016-03-31 |
20160092372 | READ CACHE MANAGEMENT IN MULTI-LEVEL CELL (MLC) NON-VOLATILE MEMORY - A method includes reading memory pages from a non-volatile memory that holds at least first memory pages having a first bit significance and second memory pages having a second bit significance, different from the first bit significance. At least some of the read memory pages are cached in a cache memory. One or more of the cached memory pages are selected for eviction from the cache memory, in accordance with a selection criterion that gives eviction preference to the memory pages of the second bit significance over the memory pages of the first bit significance. The selected memory pages are evicted from the cache memory. | 2016-03-31 |
20160092373 | INSTRUCTION AND LOGIC FOR ADAPTIVE DATASET PRIORITIES IN PROCESSOR CACHES - A processor includes a front end, a cache, and a cache controller. The front end includes logic to receive an instruction defining a priority dataset. The priority dataset includes ranges of memory addresses each corresponding to a respective priority level. The cache controller includes logic to detect a miss in the cache for a requested cache value, determine a candidate cache victim from the cache, determine a priority of the requested cache value and the candidate cache victim according to the priority dataset, and evict the candidate cache victim based on a determination that the priority of the candidate cache victim is less or equal to the priority of the requested cache value. | 2016-03-31 |
20160092374 | CHUNK-LEVEL CLIENT SIDE ENCRYPTION IN HIERARCHICAL CONTENT ADDRESSABLE STORAGE SYSTEMS - Techniques for chunk-level client side encryption are provided. In a content-addressable storage system, a plurality of chunks is used to implement a hierarchical file system. The hierarchical file system supports both encrypted and non-encrypted volumes. A folders and files layer makes calls directly to a chunk system layer for operations involving non-encrypted volumes. The folders and files layer makes calls to a volume encryption layer for operations involving encrypted volumes. The volume encryption layer receives calls from the folders and files layer through an API that matches the API through which the chunk system layer receives calls from the folders and files layer. | 2016-03-31 |
20160092375 | DATA ACCESS PROTECTION FOR COMPUTER SYSTEMS - A protection circuit can be used with a computer system having a master device and at least one slave device that are connected by an inter-integrated circuit (I2C) bus. A first access request is received that includes an address that identifies a first slave device. In response to a permissible mode, the first access request is communicated to the first slave device using the I2C bus. A sticky protection bit can be set. In response to the sticky protection bit being set, the protection circuit can be placed in a protected mode. A second access request is received. The second access request can be determined to be a protected access to the first slave device. In response to the determining and the protected mode, the second access request to the first slave device can be denied. | 2016-03-31 |
20160092376 | PROCESSING SECURE DATA - An electronic device is provided. The electronic device includes a first control module including a normal module and a security module, and a second control module distinct from the first control module. The normal module sets a secure memory which the security module and the second control module access, and the security module determines validity of the set secure memory. | 2016-03-31 |
20160092377 | METHOD FOR FAST ACCESS TO A SHARED MEMORY - A system, a method, and an apparatus are disclosed. In an embodiment, a system includes a host processor with a communications unit, a memory coupled to the communications unit, and a coprocessor coupled to the communications unit. The memory may include at least a first area and a second area. The coprocessor may be configured to request access to the first area of the memory via the communications unit. The communications unit may be configured to verify an identity of the coprocessor, and grant access to the first area of the memory responsive to a positive identification of the coprocessor. | 2016-03-31 |
20160092378 | PROCESSING DATA - A method for executing a program code is suggested, the method comprising: checking a memory access policy resource based on a trigger; and comparing a current program counter with a program counter information provided by the memory access policy resource and, in case the comparison of the current program counter and the program counter information fulfills a predefined condition, conducting a memory access policy check to allow permitted operations. | 2016-03-31 |
20160092379 | PRIORITY FRAMEWORK FOR A COMPUTING DEVICE - Proving for a framework for propagating priorities to a memory subsystem in a computing system environment is disclosed herein. By way of example, a memory access handler is provided for managing memory access requests and determining associated priorities. The memory access handler includes logic configured for propagating memory requests and the associated priorities to lower levels of a computer hierarchy. A memory subsystem receives the memory access requests and the priorities. | 2016-03-31 |
20160092380 | LEVELING IO - A method, system, and computer program product for IO leveling comprising receiving an IO, determining if there is a delay for processing IO because of pending IO, based on a positive determination there is a delay for processing IO, determining a priority for the IO, and based on the priority of IO determining whether to process the IO. | 2016-03-31 |
20160092381 | IN-BAND CONFIGURATION MODE - A first state of an interconnect protocol is entered. A particular signal is sent according to the protocol to a device over a link. During the first state, it is detected that a response to the particular signal is received in the first state. It is determined that the device supports a configuration mode outside the protocol based on the received response. The configuration mode is entered based on the response. One or more in-band configuration messages are sent within the configuration mode. | 2016-03-31 |
20160092382 | AVOIDING PREMATURE ENABLING OF NONMASKABLE INTERRUPTS WHEN RETURNING FROM EXCEPTIONS - A processor of an aspect includes a decode unit to decode an exception handler return instruction. The processor also includes an exception handler return execution unit coupled with the decode unit. The exception handler return execution unit, responsive to the exception handler return instruction, is to not configure the processor to enable delivery of a subsequently received nonmaskable interrupt (NMI) to an NMI handler if an exception, which corresponds to the exception handler return instruction, was taken within the NMI handler. The exception handler return execution unit, responsive to the exception handler return instruction, is to configure the processor to enable the delivery of the subsequently received NMI to the NMI handler if the exception was not taken within the NMI handler. Other processors, methods, systems, and instructions are disclosed. | 2016-03-31 |
20160092383 | COMMON DIE IMPLEMENTATION FOR MEMORY DEVICES - A memory device and a memory controller can interface over a system data bus that has a narrower bandwidth than a data bus internal to the memory device. The memory device and memory controller transfer data over the system data bus on all transfer periods of a burst length, but send fewer bits than would be needed for the exchange to transfer all bits that can be read or written on the internal data bus of the memory device. The memory device can have different operating modes to allow for a common memory device to be used in different system configurations based on the ability to interface with the narrower bandwidth system data bus. | 2016-03-31 |
20160092384 | READ WRITEABLE RANDOMLY ACCESSIBLE NON-VOLATILE MEMORY MODULES - A read writeable random accessible non-volatile memory module includes a printed circuit board with an edge connector that can be plugged into a socket of a printed circuit board. The read writeable random accessible non-volatile memory modules further include a plurality of read writable non-volatile memory devices. | 2016-03-31 |
20160092385 | Single-Wire Communication with Adaptive Start-Bit Condition - The present disclosure pertains to a wired network which includes a master device and a plurality of slave devices coupled to the master device by a wired connection. The master device includes control logic to determine whether information is to be sent to a slave device. In addition, the master device includes a transmitter to drive a logic level for a predetermined amount of time to address the slave device in response to the control logic to determine whether information is to be sent to a slave device. | 2016-03-31 |
20160092386 | CONNECTION EQUIPMENT AND A FIELD DEVICE CONTROL SYSTEM - A connection equipment (IJB | 2016-03-31 |
20160092387 | DATA ACCESS PROTECTION FOR COMPUTER SYSTEMS - A protection circuit can be used with a computer system having a master device and at least one slave device that are connected by an inter-integrated circuit (I2C) bus. A first access request is received that includes an address that identifies a first slave device. In response to a permissible mode, the first access request is communicated to the first slave device using the I2C bus. A sticky protection bit can be set. In response to the sticky protection bit being set, the protection circuit can be placed in a protected mode. A second access request is received. The second access request can be determined to be a protected access to the first slave device. In response to the determining and the protected mode, the second access request to the first slave device can be denied. | 2016-03-31 |
20160092388 | MODULE AUTO ADDRESSING IN PLATFORM BUS - A system and approach for addressing modules on a platform bus that may incorporate a master module and one or more slave modules. The platform bus may run through sub-base connectors that interlock modules together on a rail. Addressing of the modules may occur automatically and dynamically in that the master module may have a first address by default, and a first slave module adjoining the master module may be assigned a second address. A second slave module adjoining the first slave module, if there is one, may be assigned a third address. Each of the other slave modules, adjoining a preceding slave module assigned an address, may be assigned a next address after an address assigned to a preceding slave module. Addresses may be assigned in a numerical order to each module based on a physical position of the respective module on a rail. | 2016-03-31 |
20160092389 | UNIFIED DEVICE INTERFACE FOR A MULTI-BUS SYSTEM - The present disclosure is directed to a unified device interface for a multi-bus system. In at least one embodiment, a system may comprise more than one data bus. Each data bus may be to convey data between an operating system (OS) and at least one device in the system, wherein a plurality of driver instances may facilitate interaction between the OS and a device via one or more of the data buses. In one embodiment, a main driver instance may be determined from the plurality of driver instances to present the device to the OS and coordinate operation of other driver instances. The other driver instances may map addresses in the memory of processing entities corresponding to each of the data buses and report these mappings to the main driver instance. Alternatively, a supervisory driver may be loaded to present the device and to control operation of the driver instances. | 2016-03-31 |
20160092390 | INSTRUMENTATION CHASSIS WITH HIGH SPEED BRIDGE BOARD - An instrumentation chassis includes a backplane, multiple peripheral slots located on the backplane and configured to receive insertable peripheral modules, respectively, and at least one protocol agnostic high speed connection mounted on, but not electrically connected to the backplane. The high speed connection is configured to interconnect at least two peripheral modules in corresponding peripheral slots of the multiple peripheral slots, bypassing the backplane. | 2016-03-31 |
20160092391 | INTERFACE APPARATUS, VEHICLE HAVING THE SAME, AND METHOD OF CONTROLLING THE SAME - An interface apparatus of communicating with a multimedia player includes a slot part into which a card type memory is inserted; a hub part connected to the slot part, and configured to switch a communication line of the card type memory to a USB communication line; a port part to which an external device allowing USB communications is connected; a first connector connected to the hub part, and configured to transmit data stored in the card type memory to the multimedia player; and a second connector connected to the port part, and configured to transmit data stored in the external device to the multimedia player. Since a slot part for card type memory, a USB port, and an AUX terminal are arranged together, it is possible to improve the commercial value and design of the multimedia player. | 2016-03-31 |