13th week of 2016 patent applcation highlights part 46 |
Patent application number | Title | Published |
20160093295 | STATISTICAL UNIT SELECTION LANGUAGE MODELS BASED ON ACOUSTIC FINGERPRINTING - Methods, systems, and apparatus, including computer programs encoded on computer storage media, for providing statistical unit selection language modeling based on acoustic fingerprinting. The methods, systems and apparatus include the actions of obtaining a unit database of acoustic units and, for each acoustic unit, linguistic data corresponding to the acoustic unit; obtaining stored data associating each acoustic unit with (i) a corresponding acoustic fingerprint and (ii) a probability of the linguistic data corresponding to the acoustic unit occurring in a text corpus; determining that the unit database of acoustic units has been updated to include one or more new acoustic units; for each new acoustic unit in the updated unit database: generating an acoustic fingerprint for the new acoustic unit; identifying an acoustic unit that (i) has an acoustic fingerprint that is indicated as similar to the fingerprint of the new acoustic unit, and (ii) has a stored associated probability. | 2016-03-31 |
20160093296 | SYSTEM AND METHOD FOR MACHINE-MEDIATED HUMAN-HUMAN CONVERSATION - Disclosed herein are systems, methods, and non-transitory computer-readable storage media for processing speech. A system configured to practice the method monitors user utterances to generate a conversation context. Then the system receives a current user utterance independent of non-natural language input intended to trigger speech processing. The system compares the current user utterance to the conversation context to generate a context similarity score, and if the context similarity score is above a threshold, incorporates the current user utterance into the conversation context. If the context similarity score is below the threshold, the system discards the current user utterance. The system can compare the current user utterance to the conversation context based on an n-gram distribution, a perplexity score, and a perplexity threshold. Alternately, the system can use a task model to compare the current user utterance to the conversation context. | 2016-03-31 |
20160093297 | METHOD AND APPARATUS FOR EFFICIENT, LOW POWER FINITE STATE TRANSDUCER DECODING - A system, apparatus and method for efficient, low power, finite state transducer decoding. For example, one embodiment of a system for performing speech recognition comprises: a processor to perform feature extraction on a plurality of digitally sampled speech frames and to responsively generate a feature vector; an acoustic model likelihood scoring unit communicatively coupled to the processor over a communication interconnect to compare the feature vector against a library of models of various known speech sounds and responsively generate a plurality of scores representing similarities between the feature vector and the models; and a weighted finite state transducer (WFST) decoder communicatively coupled to the processor and the acoustic model likelihood scoring unit over the communication interconnect to perform speech decoding by traversing a WFST graph using the plurality of scores provided by the acoustic model likelihood scoring unit. | 2016-03-31 |
20160093298 | CACHING APPARATUS FOR SERVING PHONETIC PRONUNCIATIONS - Systems and processes for generating a shared pronunciation lexicon and using the shared pronunciation lexicon to interpret spoken user inputs received by a virtual assistant are provided. In one example, the process can include receiving pronunciations for words or named entities from multiple users. The pronunciations can be tagged with context tags and stored in the shared pronunciation lexicon. The shared pronunciation lexicon can then be used to interpret a spoken user input received by a user device by determining a relevant subset of the shared pronunciation lexicon based on contextual information associated with the user device and performing speech-to-text conversion on the spoken user input using the determined subset of the shared pronunciation lexicon. | 2016-03-31 |
20160093299 | FILE CLASSIFYING SYSTEM AND METHOD - A file classifying system and a file classifying method are disclosed herein, where the system includes a storing device storing at least one recognizing audio signal, a receiving device, and a processor. The receiving device receives an audio file or a video file. The processor compares a related audio signal and the at least one recognizing audio signal so as to generate a result of process, where the related audio signal is correlated to the audio file or the video file, and then automatically classifies the audio file or video file into a category. | 2016-03-31 |
20160093300 | LIBRARY OF EXISTING SPOKEN DIALOG DATA FOR USE IN GENERATING NEW NATURAL LANGUAGE SPOKEN DIALOG SYSTEMS - A machine-readable medium may include a group of reusable components for building a spoken dialog system. The reusable components may include a group of previously collected audible utterances. A machine-implemented method to build a library of reusable components for use in building a natural language spoken dialog system may include storing a dataset in a database. The dataset may include a group of reusable components for building a spoken dialog system. The reusable components may further include a group of previously collected audible utterances. A second method may include storing at least one set of data. Each one of the at least one set of data may include ones of the reusable components associated with audible data collected during a different collection phase. | 2016-03-31 |
20160093301 | PARSIMONIOUS HANDLING OF WORD INFLECTION VIA CATEGORICAL STEM + SUFFIX N-GRAM LANGUAGE MODELS - Systems and processes are disclosed for predicting words using a categorical stem and suffix word n-gram language model. A word prediction includes determining a stem probability using a stem language model. The word prediction also includes determining a suffix probability using suffix language model decoupled from the stem model, in view of one or more stem categories. The word prediction also includes determine a probability of the stem belonging to the stem category. A joint probability is determined based on the foregoing, and one or more word predictions having sufficient likelihood. In this way, the categorical stem and suffix language model constraints predicted suffixes to those that would be grammatically valid with predicted stems, thereby producing word predictions with grammatically valid stem and suffix combinations. | 2016-03-31 |
20160093302 | SYSTEMS AND METHODS FOR CONVERTING TAXIWAY VOICE COMMANDS INTO TAXIWAY TEXTUAL COMMANDS - Systems and methods are provided for converting taxiway voice commands into taxiway textual commands. In various embodiments, the systems can comprise a radio receiver that is configured to receive the taxiway voice commands from an air traffic control center, a voice recognition processor coupled to the radio receiver that is configured to receive and convert the taxiway voice commands into the taxiway textual commands, and/or a taxiway clearance display coupled to the voice recognition processor that is configured to receive and display the taxiway textual commands. | 2016-03-31 |
20160093303 | SYSTEM AND METHOD FOR EFFICIENT UNIFIED MESSAGING SYSTEM SUPPORT FOR SPEECH-TO-TEXT SERVICE - Disclosed herein are systems, methods, and non-transitory computer-readable storage media for communicating information about transcription progress from a unified messaging (UM) server to a UM client. In one embodiment, the transcription progress describes speech to text transcription of speech messages such as voicemail. The UM server authenticates and establishes a session with a UM client, then receives a get message list request from a UM client as of a first time, responds to the get message list request with a view of a state of messages and available transcriptions for transcribable messages in a list of messages associated with the get message list call at the first time, and, at a second time subsequent to the first time, transmits to the UM client a notification that provides an indication of progress for at least one transcription not yet complete in the list of messages. The messages can include video. | 2016-03-31 |
20160093304 | SPEAKER IDENTIFICATION AND UNSUPERVISED SPEAKER ADAPTATION TECHNIQUES - Systems and processes for generating a speaker profile for use in performing speaker identification for a virtual assistant are provided. One example process can include receiving an audio input including user speech and determining whether a speaker of the user speech is a predetermined user based on a speaker profile for the predetermined user. In response to determining that the speaker of the user speech is the predetermined user, the user speech can be added to the speaker profile and operation of the virtual assistant can be triggered. In response to determining that the speaker of the user speech is not the predetermined user, the user speech can be added to an alternate speaker profile and operation of the virtual assistant may not be triggered. In some examples, contextual information can be used to verify results produced by the speaker identification process. | 2016-03-31 |
20160093305 | BIO-PHONETIC MULTI-PHRASE SPEAKER IDENTITY VERIFICATION - Systems and methods for bio-phonetic multi-phrase speaker identity verification are disclosed. Generally, a speaker identity verification engine generates a dynamic phrase including at least one dynamically-generated word. The speaker identity verification engine prompts a user to speak the dynamic phrase and receives a dynamic phrase utterance. The speaker identity verification engine extracts at least one voice characteristic from the dynamic phrase utterance and compares the at least one voice characteristic with a voice profile the generate a score. The speaker identity verification engine then determines whether to accept a speaker identity claim based on the score. | 2016-03-31 |
20160093306 | OPTIMIZING FREQUENT IN-BAND SIGNALING IN DUAL SIM DUAL ACTIVE DEVICES - A method includes: receiving a first speech frame; identifying a first codec mode based at least in part on a Codec Mode Command (CMC) comprising the first speech frame; identifying a second codec mode based at least in part on a downlink (DL) Codec Mode Indication (DCMI) comprising the first speech frame; determining, based at least in part on a current uplink (UL) codec mode, to apply one of the first codec mode, the second codec mode, and a third codec mode having a higher bit rate than the first codec mode; and applying one of the first codec mode, the second codec mode, and the third codec mode. | 2016-03-31 |
20160093307 | Latency Reduction - Provided are systems and methods for reducing end-to-end latency. An example method includes configuring an interface, between a codec and a baseband or application processor, to operate in a burst mode. Using the burst mode, a transfer of real-time data is performed between the codec and the baseband or application processor at a high rate. The high rate is defined as rate faster than a real-time rate. The exemplary method includes padding data in a time period remaining after the transfer, at the high rate, of a sample of the real-time data samples. The padded of the data may be configured such that data can be ignored by the receiving component. The interface can include a Serial Low-power Inter-chip Media Bus (SLIMBus). Power consumption may be reduced for the SLIMBus by utilizing the gear shifting or clock stopping SLIMbus features. | 2016-03-31 |
20160093308 | PREDICTIVE VECTOR QUANTIZATION TECHNIQUES IN A HIGHER ORDER AMBISONICS (HOA) FRAMEWORK - A device configured to decode a bitsream comprising a memory and one or more processors may be configured to perform the techniques herein. The memory may be configured to store a reconstructed plurality of weights used to approximate the multi-directional V-vector in the higher order ambisonics domain from a past time segment; and the one or more processors may be configured to extract, from the bitstream, a weight index, retrieve, from the memory, the reconstructed plurality of weights from the past time segment, vector dequantize the weight index to determine a plurality of residual weight error, and reconstruct a plurality of weights for a current time segment based on the plurality of residual weight errors and the reconstructed plurality of weights used to approximate the multi-directional V-vector in the higher order ambisonics domain from the past time segment. | 2016-03-31 |
20160093309 | DIGITAL WATERMARK EMBEDDING DEVICE, DIGITAL WATERMARK DETECTING DEVICE, DIGITAL WATERMARK EMBEDDING METHOD, DIGITAL WATERMARK DETECTING METHOD, COMPUTER-READABLE RECORDING MEDIUM CONTAINING DIGITAL WATERMARK EMBEDDING PROGRAM, AND COMPUTER-READABLE RECORDING MEDIUM CONTAINING DIGITAL WATERMARK DETECTING PROGRAM - A digital watermark embedding device includes a generating unit that makes use of a key random number which is input, and outputs a filter for determining a first band and a second band which represent at least a single pair of frequency bands in which a digital watermark bit is to be embedded; and an embedding unit that, when the digital watermark bit is to be embedded in a unit frame of a voice signal which is input, varies a sum of amplitude spectrum intensities of at least one of the first band and the second band in such a way that a first sum of amplitude spectrum intensities of the first band is greater than a second sum of amplitude spectrum intensities of the second band. | 2016-03-31 |
20160093310 | Spectral Translation/Folding in the Subband Domain - The present invention relates to a new method and apparatus for improvement of High Frequency Reconstruction (HFR) techniques using frequency translation or folding or a combination thereof. The proposed invention is applicable to audio source coding systems, and offers significantly reduced computational complexity. This is accomplished by means of frequency translation or folding in the subband domain, preferably integrated with spectral envelope adjustment in the same domain. The concept of dissonance guard-band filtering is further presented. The proposed invention offers a low-complexity, intermediate quality HFR method useful in speech and natural audio coding applications. | 2016-03-31 |
20160093311 | SWITCHING BETWEEN PREDICTIVE AND NON-PREDICTIVE QUANTIZATION TECHNIQUES IN A HIGHER ORDER AMBISONICS (HOA) FRAMEWORK - A device comprising a memory and one or more processors may be configured extract, from the bitstream, a type of quantization mode. The one or more processors may also be configured to switch, based on the type of quantization mode, between non-predictive vector dequantization to reconstruct a first set of one or more weights used to approximate the multi-directional V-Vector in the higher order ambisonics domain, and predictive vector dequantization to reconstruct a second set of one or more weights used to approximate the multi-directional V-Vector in the higher order ambisonics domain. The memory may be configured to store the reconstructed first set of one or more weights used to approximate the multi-directional V-Vector in the higher order ambisonics domain, and the reconstructed second set of one or more weights used to approximate the multi-directional V-Vector in the higher order ambisonics domain. | 2016-03-31 |
20160093312 | AUDIO ENCODER AND DECODER WITH MULTIPLE CODING MODES - In one embodiment, an audio decoder for decoding an audio bitstream is disclosed. The decoder includes a first decoding module adapted to operate in a first coding mode and a second decoding module adapted to operate in a second coding mode, the second coding mode being different from the first coding mode. The decoder further includes a pitch filter in either the first coding mode or the second coding mode, the pitch filter adapted to filter a preliminary audio signal generated by the first decoding module or the second decoding module to obtain a filtered signal. The pitch filter is selectively enabled or disabled based on a value of a first parameter encoded in the audio bitstream, the first parameter being distinct from a second parameter encoded in the audio bitstream, the second parameter specifying a current coding mode of the audio decoder. | 2016-03-31 |
20160093313 | NEURAL NETWORK VOICE ACTIVITY DETECTION EMPLOYING RUNNING RANGE NORMALIZATION - A “running range normalization” method includes computing running estimates of the range of values of features useful for voice activity detection (VAD) and normalizing the features by mapping them to a desired range. Running range normalization includes computation of running estimates of the minimum and maximum values of VAD features and normalizing the feature values by mapping the original range to a desired range. Smoothing coefficients are optionally selected to directionally bias a rate of change of at least one of the running estimates of the minimum and maximum values. The normalized VAD feature parameters are used to train a machine learning algorithm to detect voice activity and to use the trained machine learning algorithm to isolate or enhance the speech component of the audio data. | 2016-03-31 |
20160093314 | AUDIO COMMUNICATION SYSTEM, AUDIO COMMUNICATION METHOD, AUDIO COMMUNICATION PURPOSE PROGRAM, AUDIO TRANSMISSION TERMINAL, AND AUDIO TRANSMISSION TERMINAL PURPOSE PROGRAM - An audio communication system includes a generation unit that superimposes an addition sound having a volume level determined on the basis of a voice acquired by a voice acquisition unit on an input voice acquired by the voice acquisition unit of a transmission terminal and generates a synthesis sound and a transmission unit that transmits a signal of the synthesis sound generated by the generation unit to a reception terminal. | 2016-03-31 |
20160093315 | ELECTRONIC DEVICE, METHOD AND STORAGE MEDIUM - According to one embodiment, an electronic device includes circuitry configured to display, during recording, a first mark indicative of a sound waveform collected from a microphone and a second mark indicative of a section of voice collected from the microphone, after processing to detect the section of voice. | 2016-03-31 |
20160093316 | Management, Replacement and Removal of Explicit Lyrics during Audio Playback - Unwanted audio, such as explicit language, may be removed during audio playback. An audio player may identify and remove unwanted audio while playing an audio stream. Unwanted audio may be replaced with alternate audio, such as non-explicit lyrics, a “beep”, or silence. Metadata may be used to describe the location of unwanted audio within an audio stream to enable the removal or replacement of the unwanted audio with alternate audio. An audio player may switch between clean and explicit versions of a recording based on the locations described in the metadata. The metadata, as well as both the clean and explicit versions of the audio data, may be part of a single audio file, or the metadata may be separate from the audio data. Additionally, real-time recognition analysis may be used to identify unwanted audio during audio playback. | 2016-03-31 |
20160093317 | MAGNETIC TAPE REWIND OVERWRITE DATA PROTECTION - A computer-implemented method for preventing overwriting of data, e.g., on a magnetic medium, includes receiving a write command to write to a magnetic tape. The current location of the magnetic tape is determined. A determination is also made as to whether data corresponding to the write command is at least one of: a size and type specified for a block at the current location. Execution of the write command is disallowed in response to determining that the data corresponding to the write command is not of the specified size and/or type. | 2016-03-31 |
20160093318 | MAGNETIC HEAD, HEAD GIMBAL ASSEMBLY, AND MAGNETIC RECORDING AND REPRODUCING APPARATUS - A magnetic head has a magnetic head slider that includes a recording element that generates a recording signal magnetic field, a microwave magnetic field generating element that generates a microwave magnetic field, a terminal electrode, and a first transmission line that interconnects the terminal electrode and the microwave magnetic field generating element. A second transmission line is connected to the terminal electrode, the second transmission line being used to transmit a microwave signal from the outside of the magnetic head slider to the magnetic head slider. A capacitor connected to the first transmission line is provided between the terminal electrode and the microwave magnetic field generating element. Accordingly, in the magnetic head, a microwave signal is efficiently propagated. | 2016-03-31 |
20160093319 | MAGNETORESISTIVE SENSOR WITH SAF STRUCTURE HAVING AMORPHOUS ALLOY LAYER - A magnetoresistive (MR) sensor including a synthetic antiferromagnetic (SAF) structure that is magnetically coupled to a side shield element. The SAF structure includes at least one magnetic amorphous layer that is an alloy of a ferromagnetic material and a refractory material. The amorphous magnetic layer may be in contact with a non-magnetic layer and antiferromagnetically coupled to a layer in contact with an opposite surface of the non-magnetic layer. | 2016-03-31 |
20160093320 | DETECTING DAMAGE TO TUNNELING MAGNETORESISTANCE SENSORS - Embodiments of the present invention provide methods, systems, and computer program products for detecting damage to tunneling magnetoresistance (TMR) sensors. In one embodiment, resistances of a TMR sensor are measured upon application of one or both of negative polarity bias current and positive polarity bias current at a plurality of current magnitudes. Resistances of the TMR sensor can then be analyzed with respect to current, voltage, voltage squared, and/or power, including analyses of changes to slopes calculated with these values and hysteresis-induced fluctuations, all of which can be used to detect damage to the TMR sensor. The present invention also describes methods to utilize the measured values of neighbor TMR sensors to distinguish normal versus damaged parts for head elements containing multiple TMR read elements. | 2016-03-31 |
20160093321 | MAGNETIC RECORDING MEDIUM AND COATING COMPOSITION FOR MAGNETIC RECORDING MEDIUM - The magnetic recording medium comprises a magnetic layer comprising ferromagnetic powder and binder on a nonmagnetic support, and further comprises a compound denoted by Formula (1): | 2016-03-31 |
20160093322 | MAGNETIC TAPE - The magnetic tape comprises, on a nonmagnetic support, a nonmagnetic layer comprising nonmagnetic powder and binder, and on the nonmagnetic layer, a magnetic layer comprising ferromagnetic powder, nonmagnetic powder, and binder, wherein a total thickness of the magnetic tape is less than or equal to 4.80 μm, and a coefficient of friction as measured on a base portion of a surface of the magnetic layer is less than or equal to 0.35. | 2016-03-31 |
20160093323 | MAGNETIC TAPE AND METHOD OF MANUFACTURING THE SAME - The magnetic tape comprises a nonmagnetic layer comprising nonmagnetic powder and binder on a nonmagnetic support, and comprises a magnetic layer comprising ferromagnetic powder and binder on the nonmagnetic layer, wherein a fatty acid ester, a fatty acid amide, and a fatty acid are contained in either one or both of the magnetic layer and the nonmagnetic layer, with the magnetic layer and nonmagnetic layer each comprising at least one selected from the group consisting of a fatty acid ester, a fatty acid amide, and a fatty acid, a quantity of fatty acid ester per unit area of the magnetic layer in extraction components extracted from a surface of the magnetic layer with n-hexane falls within a range of 1.00 mg/m | 2016-03-31 |
20160093324 | ANTI-PIRACY FEATURE FOR OPTICAL DISCS - Disclosed are techniques and systems for manufacturing an optical disc having a stochastic (i.e., non-deterministic) anti-piracy feature in the form of a multi-spiral structure, and for verifying the feature on the optical disc to authenticate the disc for playback. The multi-spiral structure may be comprised of multiple partially interleaved, and partially overlapping, spiral data tracks formed in a designated area of the optical disc. A process of forming the multi-spiral structure may include forming, in the designated area, a first spiral data track with first track pitch and a second spiral data track with second track pitch that is different than the first track pitch. The multi-spiral structure may be analyzed to determine verification parameters for verifying the multi-spiral structure, and those verification parameters may be encrypted so that they may be subsequently decrypted and used to verify the multi-spiral structure on a disc reading device. | 2016-03-31 |
20160093325 | DYNAMIC GAIN CONTROL FOR USE WITH ADAPTIVE EQUALIZERS - According to one embodiment, a method for processing data includes directing first data through a first FIR gain module in response to a determination that the first data is being read from a magnetic tape medium in an asynchronous mode to control FIR gain of the first data. The method also includes directing second data through a second FIR gain module in response to a determination that the second data is being read from the magnetic tape medium in a synchronous mode to control FIR gain of the second data. Other systems and methods for processing data using dynamic gain control with adaptive equalizers are presented according to more embodiments. | 2016-03-31 |
20160093326 | DYNAMIC GAIN CONTROL FOR USE WITH ADAPTIVE EQUALIZERS - According to one embodiment, a magnetic tape drive includes a controller configured to direct first data through a first finite impulse response (FIR) gain module in response to a determination that the first data is being read from a magnetic tape medium in an asynchronous mode to control FIR gain of the first data. The controller is also configured to direct second data through a second FIR gain module in response to a determination that the second data is being read from the magnetic tape medium in a synchronous mode to control FIR gain of the second data. A FIR gain value of the second FIR gain module is automatically controlled. Other systems for dynamic gain control with adaptive equalizers are described according to more embodiments. | 2016-03-31 |
20160093327 | METHOD FOR RECORDING A PLURALITY OF AUDIO FILES - A method for recording a plurality of audio files, which can be played individually and, at least in pairs, synchronously and which can be modified individually with respect to playing parameters, said method being implemented by means of electronic processing hardware and software means, including: —at least two independent devices originating sound signals, comprising storage means or a microphone input or an in line input; —means for playing audio files, and—software means for playing one or more audio files individually or synchronously, wherein (step | 2016-03-31 |
20160093328 | RECORDING MEDIUM HAVING INDEPENDENT TRACK FOR VELOCITY, TIMING AND/OR LONGITUDINAL POSITION - A product according to one embodiment includes a magnetic recording tape having at least one first servo track, and a supplemental servo track positioned in a spare area located within a data band of the magnetic recording tape. An apparatus according to one embodiment includes a magnetic head and at least one module having an array of transducers. The apparatus is configured to read and/or write to magnetic recording media having at least one first servo track, and a supplemental servo track positioned in a spare area located within a data band of the magnetic recording tape. | 2016-03-31 |
20160093329 | System and Method for Time Delayed Playback - A system and method that time delays a playback from a first feed at a first time to a second feed at a second time. The method includes recording the first feed that is received at the first time to be used at least partially as a playback of the second feed at the second time. The second time has a predetermined delay relative to the first time. The method includes determining whether the first feed has a discrepancy in the actual playback from a desired playback. The discrepancy is at a known time and lasting a known time amount. The method includes transmitting the playback to the second feed after the predetermined delay. A fix is aired instead of the playback for the known time amount corresponding to the discrepancy. | 2016-03-31 |
20160093330 | System and Method for Time Delayed Playback - A system that includes at least two time delayed playback (TDP) devices for recording and playback. Each of the two TDP devices may perform a method that includes recording a first feed to be used at least partially as a playback of a second feed, determining whether a failure results in a missed feed portion from the recording of the first feed, the missed feed portion being at a known time and lasting a known time amount. When there is a failure, the method includes providing a backup recording corresponding to the missed feed portion from the other TDP device that is recording the first feed in parallel with the first TDP device and transmitting the playback of the second feed including the backup recording at the known time and lasting the known time amount. | 2016-03-31 |
20160093331 | VIDEO EDITING - A method to edit digital videos includes dividing a first digital video into digital video segments, presenting a graphical user interface to select the digital video segments, receiving one or more selections of one or more of the digital video segments through the graphical user interface, and saving a second digital video with the selected digital video segments. | 2016-03-31 |
20160093332 | AUTOMATED CREATION OF PHOTOBOOKS INCLUDING STATIC PICTORIAL DISPLAYS SERVING AS LINKS TO ASSOCIATED VIDEO CONTENT - An image processing system (IPS) is provided for creating a video-linked photobook. The method includes: receiving a video file including video content; processing the video file to identify a series of still image frames extracted from the video content; formatting the series of still image frames into a pictorial compilation; storing in a memory the pictorial compilation, and an association between the pictorial compilation and the video file; and transmitting from the image processing system computer-readable instructions for printing the pictorial compilation. Accordingly, images excerpted from a video file can be used to create a printed pictorial compilation. Imaging of the pictorial compilation with a smartphone/tablet PC can responsively result in display of the associated video file on the smartphone/tablet PC. | 2016-03-31 |
20160093333 | RECORDING MEDIUM RECORDED WITH MULTI-TRACK MEDIA FILE, METHOD FOR EDITING MULTI-TRACK MEDIA FILE, AND APPARATUS FOR EDITING MULTI-TRACK MEDIA FILE - A recording medium recorded with a multi-track media file, a method for editing a multi-track media file and an apparatus for editing a multi-track media file. The apparatus for editing a media file stores a multi-track media file including an audio track and an video track corresponding to the audio track, receives an output adjustment command for adjusting an output of an audio or video track, generates a volume adjustment value according to the output adjustment command, and records the generated volume adjustment value in the multi-track media file, thereby realizing the present invention. According to the present invention, users may produce his/her own unique multimedia file by editing according to his/her taste, for example, by inserting his/her voice, in place of an existing audio, into a multimedia file such as a music video file, or inserting a video taken on his/her own, in place of an existing video, thereinto. | 2016-03-31 |
20160093334 | GENERATING STORY GRAPHS WITH LARGE COLLECTIONS OF ONLINE IMAGES - Embodiments presented herein describe techniques for generating a story graph using a collection of digital media, such as images and video. The story graph presents a structure for activities, events, and locales commonly occurring in sets of photographs taken by different individuals across a given location (e.g., a theme park, tourist attraction, convention, etc.). To build a story graph, streams from sets of digital media are generated. Each stream corresponds to media (e.g., images or video) taken in sequence at the location by an individual (or related group of individuals) over a period of time. For each stream, features from each media are extracted relative to the stream. Clusters of media are generated and are connected by directed edges. The connections indicate a path observed to have occurred in the streams from one cluster to another cluster. | 2016-03-31 |
20160093335 | Time-Lapse Video Capture With Temporal Points Of Interest - Traditionally, time-lapse videos are constructed from images captured at given time intervals called “temporal points of interests” or “temporal POIs.” Disclosed herein are intelligent systems and methods of capturing and selecting better images around temporal points of interest for the construction of improved time-lapse videos. According to some embodiments, a small “burst” of images may be captured, centered around the aforementioned temporal points of interest. Then, each burst sequence of images may be analyzed, e.g., by performing a similarity comparison between each image in the burst sequence and the image selected at the previous temporal point of interest. Selecting the image from a given burst that is most similar to the previous selected image allows the intelligent systems and methods described herein to improve the quality of the resultant time-lapse video by discarding “outlier” or other undesirable images captured in the burst sequence around a particular temporal point of interest. | 2016-03-31 |
20160093336 | Method and System for Non-Causal Zone Search in Video Monitoring - A computing system processes a video recording to identify a plurality of motion events, each corresponding to a respective video segment along a timeline of the video recording. The computing system identifies at least one object in motion within a scene depicted in the video recording and stores a respective event mask for each event. The computing system receives a definition of a zone of interest within the scene. In response to receiving the definition, the computing system determines, for each motion event, whether the respective event mask of the motion event overlaps with the zone of interest by at least a predetermined overlap factor, and identifies one or more events of interest from the plurality of motion events, wherein the respective event mask of each identified event of interest is determined to overlap with the zone of interest by at least the predetermined overlap factor. | 2016-03-31 |
20160093337 | METHOD AND DEVICE FOR TRANSMITTING AUDIO AND VIDEO FOR PLAYBACK - A system that incorporates teachings of the subject disclosure may include, for example, detecting a first action at a first time during a first presentation of video content of a multimedia stream. The first action is coincident with a visual aspect of an event observable in the video content. A second action is detected at a second time during a second presentation of audio content of an audio stream, wherein the second action is coincident with an audible aspect of the event observable in a the second presentation of the audio content. A time difference is determined between the first time and the second time, wherein the first presentation of the video content and the second presentation of the audio content are synchronized based on the time difference. Other embodiments are disclosed. | 2016-03-31 |
20160093338 | Method and System for Categorizing Detected Motion Events - A computing system device with processor(s) and memory displays a video monitoring user interface on the display, the video monitoring user interface including a video feed from a camera located remotely from the client device in a first region of the video monitoring user interface and an event timeline in a second region of the video monitoring user interface, and the event timeline includes indicators corresponding to motion events previously detected by the camera. The computing system obtains an indication of a detected motion event and associates the detected motion event with a respective category. The computing system displays an indicator for the detected motion event on the event timeline with a display characteristic corresponding to the respective category. | 2016-03-31 |
20160093339 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS - A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane. | 2016-03-31 |
20160093340 | COMPACT MICROELECTRONIC ASSEMBLY HAVING REDUCED SPACING BETWEEN CONTROLLER AND MEMORY PACKAGES - A microelectronic package has terminals at a surface of a substrate having first and second half areas, each half area extending from a diagonal that bisects the first surface and a respective opposite corner of the first surface. Terminals for carrying data and address information in the first half area provide first memory channel access to a first memory storage array, and terminals for carrying data and address information in the second half area provide second memory channel access to a second memory storage array. The package may include first and second microelectronic elements overlying a same surface of the substrate which may be stacked in transverse orientations. | 2016-03-31 |
20160093341 | MEMORY DEVICE WITH SHARED AMPLIFIER CIRCUITRY - In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portions of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portion of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry. | 2016-03-31 |
20160093342 | PORTABLE STORAGE DEVICE THAT CAN CHECK MEMORY FREE SPACE - A portable storage device is provided with a memory part, a free space detecting part, a vibration detecting part, a reporting part, and a controller. The memory part stores data. The free space detecting part detects a free space of the memory part. The vibration detecting part detects vibration. The reporting part reports the free space. The controller performs writing and reading of data for the memory part. If vibration is detected by the vibration detecting part, the controller causes the reporting part to report corresponding to the detection result of the free space of the memory part by the free space detecting part. | 2016-03-31 |
20160093343 | LOW POWER COMPUTATION ARCHITECTURE - An embodiment includes a system, comprising a first memory; a plurality of first circuits, wherein each first circuit is coupled to the memory; and includes a second circuit configured to generate a first output value in response to an input value received from the first memory; and an accumulator configured to receive the first output value and generate a second output value; and a controller coupled to the memory and the first circuits, and configured to determine the input values to be transmitted from the memory to the first circuits. | 2016-03-31 |
20160093344 | METHOD, APPARATUS AND SYSTEM TO MANAGE IMPLICIT PRE-CHARGE COMMAND SIGNALING - Techniques and mechanisms for exchanging information between a memory controller and a memory device. In an embodiment, a memory controller receives information indicating for a memory device a threshold number of pending consolidated activation commands to access that memory device. The threshold number indicated by the information is less than a theoretical maximum number of pending consolidated activation commands, the theoretical maximum number defined based on timing parameters of the memory device. In another embodiment, the memory controller limits communication of consolidated activation commands to the memory device based on the information indicating the threshold number. | 2016-03-31 |
20160093345 | DYNAMIC RANDOM ACCESS MEMORY TIMING ADJUSTMENTS - A method includes detecting, at a controller, a rate-of-change between first data traffic to be sent to a dynamic random access memory (DRAM) at a first time and second data traffic to be sent to the DRAM at a second time. The method also includes adjusting a data rate of the second data traffic in response to a determination that the rate-of-change satisfies a threshold. | 2016-03-31 |
20160093346 | VOLTAGE LEVEL SHIFTED SELF-CLOCKED WRITE ASSISTANCE - Systems and methods for generating voltage level shifted self-clocked write assistance include a circuit with self-clocked true and complement data input signals in a first voltage domain. First and second full voltage level shifters are configured to generate voltage level shifted self-clocked intermediate true and complement signals in a second voltage domain, based on the self-clocked true and complement data input signals in the first voltage domain. Tristating logic including first and second complementary metal oxide semiconductor (CMOS) circuits are configured to generate voltage level shifted self-clocked tristated true and complement output signals used for providing write assistance for a memory array in the second voltage domain, based on the voltage level shifted self-clocked intermediate true and complements signals. | 2016-03-31 |
20160093347 | REFERENCE VALUES FOR MEMORY CELLS - It is proposed to determine a reference value on the basis of a plurality of half reference values stored in memory cells, wherein the plurality of half reference values are read from the memory cells, wherein a subset of half reference values is determined from the plurality of half reference values, and wherein the reference value is determined on the basis of the subset of half reference values. | 2016-03-31 |
20160093348 | DEVICES, METHODS, AND SYSTEMS SUPPORTING ON UNIT TERMINATION - The present disclosure includes devices, methods, and systems supporting on unit termination. A number of embodiments include a number of memory units, wherein a memory unit includes termination circuitry, and a memory unit does not include termination circuitry. | 2016-03-31 |
20160093349 | WRITE VERIFY PROGRAMMING OF A MEMORY DEVICE - A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state. | 2016-03-31 |
20160093350 | LATCH OFFSET CANCELATION SENSE AMPLIFIER - Systems and methods relate to operations on a magnetoresistive random access memory (MRAM) bit cell using a circuit configured in multiple phases. In a sensing circuit phase, the circuit configured to determine a first differential voltage between a data voltage across the bit cell and a reference voltage. In a pre-amplifying phase, the circuit is configured to pre-amplify the first differential voltage to generate a pre-amplified differential voltage, which does not have offset voltages that may arise due to process variations. In a sense amplifier phase, the circuit is configured to amplify the pre-amplified differential voltage in a latch. Generation of the pre-amplified differential voltage cancels offset voltages which may arise in the latch. In a write phase, the circuit is further configured to write a write data value to the MRAM bit cell. | 2016-03-31 |
20160093351 | CONSTANT SENSING CURRENT FOR READING RESISTIVE MEMORY - Systems and methods relate to providing a constant sensing current for reading a resistive memory element. A load voltage generator provides a load voltage based on a current mirror configured to supply a constant current that is invariant with process-voltage-temperature variations. A data voltage is generated based on the generated load voltage, by passing a sensing current mirrored from the constant current, through the resistive memory element. A reference voltage is generated, also based on the generated load voltage and by passing reference current mirrored from the constant current, through reference cells. A logical value stored in the resistive memory element is determined based on a comparison of the data voltage and the reference voltage, where the determination is free from effects of process-voltage-temperature variations. | 2016-03-31 |
20160093352 | REFERENCE VOLTAGE GENERATION FOR SENSING RESISTIVE MEMORY - Systems and methods relate to providing a correct reference voltage for reading a resistive memory element such as a magnetoresistive random access memory (MRAM) bit cell. Two or more reference voltages are provided for each MRAM bit cell and a correct reference voltage is selected from the two or more reference voltages for reading the MRAM bit cell. The correct reference voltage meets sensing margin requirements for reading the MRAM bit cell and overcomes non-idealities and offset voltages in read circuitry for reading the MRAM bit cell. An indication of the correct reference voltage is stored in a non-volatile latch or other non-volatile programmable memory and provided to the read circuitry. | 2016-03-31 |
20160093353 | DUAL STAGE SENSING CURRENT WITH REDUCED PULSE WIDTH FOR READING RESISTIVE MEMORY - Systems and methods for reducing a probability of read disturbance during a read operation on a resistive memory bit cell include a dual stage sensing scheme, which is used to reduce pulse widths of sensing currents for reading the resistive memory bit cell. During a first stage of the read operation on the resistive memory bit cell, a first sensing current is passed in a first direction through the resistive memory bit cell, and during a second stage of the read operation, a second sensing current is passed in an opposite, second direction through the resistive memory bit cell. Durations of the first and second stages are each equal to half of the duration of the read operation, which reduces pulse width of the first and second sensing currents. Probability of read disturbance occurring is limited to at most one of the first or second stages. | 2016-03-31 |
20160093354 | SHORT DETECTION AND INVERSION - In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell. | 2016-03-31 |
20160093355 | MAGNETIC FIELD-ASSISTED MEMORY OPERATION - In one embodiment, a magnetoresistance random access memory (MRAM) such as a spin transfer torque (STT) random access memory (RAM), for example, has a subarray of bitcells and an electro-magnet positioned adjacent the subarray. A magnetic field is directed through a ferromagnetic device of bitcells of the first subarray to assist in the changing of states of bitcells of the subarray from a first state to a second state in which the ferromagnetic device of the bitcell is changed from one of parallel and anti-parallel polarization to the other of parallel and anti-parallel polarization. Accordingly, the content of the subarray may be readily preset or erased to one of the parallel or anti-parallel state with assistance from an electro-magnet. | 2016-03-31 |
20160093356 | Methods of Reading and Writing Data in a Thyristor Random Access Memory - A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array. | 2016-03-31 |
20160093357 | Methods of Retaining and Refreshing Data in a Thyristor Random Access Memory - A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read, write, retain and refresh data stored therein. | 2016-03-31 |
20160093358 | Power Reduction in Thyristor Random Access Memory - A volatile memory array using vertical thyristors is disclosed together with methods of reducing power consumption in such arrays. | 2016-03-31 |
20160093359 | OVERVOLTAGE PROTECTION FOR A FINE GRAINED NEGATIVE WORDLINE SCHEME - A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage. | 2016-03-31 |
20160093360 | OVERVOLTAGE PROTECTION FOR A FINE GRAINED NEGATIVE WORDLINE SCHEME - A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage. | 2016-03-31 |
20160093361 | OVERVOLTAGE PROTECTION FOR A FINE GRAINED NEGATIVE WORDLINE SCHEME - A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage. | 2016-03-31 |
20160093362 | Two-Transistor SRAM Circuit and Methods of Fabrication - A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. | 2016-03-31 |
20160093363 | MULTI-PORT MEMORY CIRCUITS - A multi-port hybrid full-swing/low-swing memory circuit in a static random access memory (SRAM) device comprises a first wordline driver that comprises a read wordline driver, a second wordline driver that comprises either a read wordline driver or a read/write wordline driver, a memory cell coupled to the first and second wordline drivers, a sense amplifier coupled to the memory cell, and a latch coupled to the memory cell. The memory circuit is capable of achieving high-speed low-swing or low-speed full-swing operations while avoiding the need for a large circuit area on an integrated circuit. | 2016-03-31 |
20160093364 | SELECTIVE CURRENT BOOSTING IN A STATIC RANDOM-ACCESS MEMORY - Systems and methods include a static random-access memory (SRAM) bit cell circuit having an access transistor configured to pass a read current to a storage node, the access transistor including an access transistor back gate. The access transistor back gate is biased to enable selective current boosting of the read current during a read operation. | 2016-03-31 |
20160093365 | SEVEN-TRANSISTOR STATIC RANDOM-ACCESS MEMORY BITCELL WITH REDUCED READ DISTURBANCE - Systems and methods relate to a seven transistor static random-access memory (7T SRAM) bit cell which includes a first inverter having a first pull-up transistor, a first pull-down transistor, and a first storage node, and a second inverter having a second pull-up transistor, a second pull-down transistor, and a second storage node. The second storage node is coupled to gates of the first pull-up transistor and the first pull-down transistor. A transmission gate is configured to selectively couple the first storage node to gates of the second pull-up transistor and the second pull-down transistor during a write operation, a standby mode, and a hold mode, and selectively decouple the first storage node from gates of the first pull-up transistor and a first pull-down transistor during a read operation. The 7T SRAM bit cell can be read or written through an access transistor coupled to the first storage node. | 2016-03-31 |
20160093366 | MEMORY DEVICE - An electronic device is disclosed that includes n memory cells, a replica memory array, and a sensing unit. Each of the n memory cells stores bit data, in which n is a positive integer. The replica memory array includes a first reference memory cell having a high logic state, a second reference memory cell having a low logic state, n−1 first pseudo reference memory cells having the low logic state, and n−1 second pseudo reference memory cells having the high logic state. The first reference memory cell and the n−1 first pseudo reference memory cells generate a first signal, and the second reference memory cell and the n−1 second pseudo reference memory cells generate a second signal. The sensing unit determines a logic state of the bit data of one of the n memory cells according to the first signal and the second signal. | 2016-03-31 |
20160093367 | Cross-Coupled Thyristor SRAM Circuits and Methods of Operation - A memory cell based upon thyristors for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. Special circuitry provides lowered power consumption during standby. | 2016-03-31 |
20160093368 | Six-Transistor SRAM Circuits and Methods of Operation - A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. | 2016-03-31 |
20160093369 | Write Assist SRAM Circuits and Methods of Operation - A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. | 2016-03-31 |
20160093370 | STATIC RAM AND SEMICONDUCTOR DEVICE INCLUDING STATIC RAM - A static RAM includes: a plurality of word lines; a plurality of bit line pairs; a plurality of memory cells provided at intersections of the plurality of bit line pairs and the plurality of word lines; a write driver connected between a high potential power source line, of which potential is higher than a reference potential, and a drive line; a column switch having transistor pairs which connect one of the plurality of bit line pairs, which is selected, to the write driver; and a boost circuit which boosts the drive line of the write driver to a negative potential, which is a potential lower than the reference potential, at a time of writing of the memory cell, wherein a well of the transistor pairs of the column switch is connected to the drive line. | 2016-03-31 |
20160093371 | METHOD FOR PERFORMING MEMORY ACCESS MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing memory access includes: performing a plurality of sensing operations respectively corresponding to a plurality of different sensing voltages to generate a first digital value of a Flash cell of a Flash memory and a second digital value of the Flash cell of the Flash memory; using the first digital value and the second digital value to obtain soft information of a bit stored in the Flash cell; and using the soft information to perform soft decoding. | 2016-03-31 |
20160093372 | READING RESISTIVE RANDOM ACCESS MEMORY BASED ON LEAKAGE CURRENT - A data storage device includes a resistive random access memory (ReRAM). The data storage device includes read circuitry coupled to a storage element of the ReRAM. The read circuitry is configured to read a data value from the storage element, during a read operation, based on a read current sensed during a first phase of the reading operation and a leakage current sensed during a second phase of the reading operation. The data storage device also includes a controller coupled to the read circuitry. The controller is configured to provide an input value to an error correction coding (ECC) decoder, where the input value includes a hard bit value and a soft bit value. The hard bit value corresponds to the data value, and the soft bit value is at least partially based on the leakage current. | 2016-03-31 |
20160093373 | APPARATUS AND METHODS FOR SENSING HARD BIT AND SOFT BITS - A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times. | 2016-03-31 |
20160093374 | METHODS AND APPARATUS FOR VERTICAL CROSS POINT RE-RAM ARRAY BIAS CALIBRATION - Methods for operating a non-volatile storage system are described. The non-volatile storage system includes a plurality of bit lines, a plurality of word line combs each comprising a plurality of word lines, and a plurality of resistance-switching memory elements. Each resistance-switching memory element is coupled between one of the bit lines and one of the word lines. The method includes calibrating a plurality of bias voltages for the word lines and bit lines based on estimates of data values stored in the resistance-switching memory elements. | 2016-03-31 |
20160093375 | REFERENCE ARCHITECTURE IN A CROSS-POINT MEMORY - The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes word line (WL) switch circuitry configured to select a global WL (GWL) and a local WL (LWL) associated with the target memory cell; bit line (BL) switch circuitry configured to select a global BL (GBL) and a local BL (LBL) associated with the target memory cell; and sense circuitry including a first sense circuitry capacitance and a second sense circuitry capacitance, the sense circuitry configured to precharge the selected GWL, the LWL and the first sense circuitry capacitance to a WL bias voltage WLVDM, produce a reference voltage (V | 2016-03-31 |
20160093376 | RESISTIVE MEMORY DEVICE AND METHOD OF OPERATING THE SAME TO REDUCE LEAKAGE CURRENT - A method of operating a memory device includes determining a value of an operating current flowing through a selected first signal line, to which a selection voltage is applied, from among a plurality of first signal lines; dividing an array of memory cells into n blocks, n being an integer greater than 1, based on the value of the operating current; and applying inhibit voltages having different voltage levels corresponding to the n blocks to unselected ones of second signal lines included in the n blocks. Each of the unselected second signal lines is a pathway through which leakage current may potentially flow due to the operating current flowing through the selected first signal line and a memory cell addressed by the unselected second signal line and the selected first signal line. | 2016-03-31 |
20160093377 | NONVOLATILE MEMORY MODULE - Memory modules, controllers, and electronic devices comprising memory modules are described. In one embodiment, a memory module comprises a nonvolatile memory and an interface to a volatile memory bus, at least one input power rail to receive power from a host platform, and a controller comprising logic, at least partially including hardware logic, to convert the power from the input power rail from an input voltage to at least one output voltage, different from the input voltage. Other embodiments are also disclosed and claimed. | 2016-03-31 |
20160093378 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device may include a plurality of memory chips stacked upon one another, and electrically coupled to one another through a plurality of first TSVs. The semiconductor memory device may include a plurality of second memory chips stacked separately from the first memory chips, and the plurality of second memory chips electrically coupled to one another through a plurality of second TSVs. The semiconductor memory device may include a plurality of external connection electrodes coupled to both to the first memory chips and the second memory chips. Wherein one of the first and second memory chips may be accessed in response to chip select signals inputted through the external connection electrodes. | 2016-03-31 |
20160093379 | NAND MEMORY ADDRESSING - Technology for performing addressing in a NAND memory is described. A defined number of address cycles supported at either a memory controller or a NAND memory to address individual memory units in the NAND memory can be identified. The defined number of address cycles in which to operate can be selected in order to address the individual memory units in the NAND memory. Either the memory controller or the NAND memory can be configured to operate at the selected number of address cycles where the individual memory units in the NAND memory are uniquely addressable using a multi die select (MDS). | 2016-03-31 |
20160093380 | MODIFYING PROGRAM PULSES BASED ON INTER-PULSE PERIOD TO REDUCE PROGRAM NOISE - Techniques are provided for more accurately programming memory cells by reducing program noise caused by charge loss in a programming pass in which the number of verify tests varies in different program loops. In an nth program loop, at least one programming characteristic is modified based on the number (N) of data states which were subject to verify tests in the n−1 | 2016-03-31 |
20160093381 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device. The method includes forming memory cells which share a data storage layer; performing a first strong program operation on first memory cells, arranged in a checker board pattern among the memory cells; performing a first annealing process after the first strong program operation; performing a second strong program operation on second memory cells arranged in a reverse checker board pattern among the memory cells, and performing a slight program operation on the first memory cells; and performing a second annealing process after the second strong program operation and the slight program operation. | 2016-03-31 |
20160093382 | MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - According to an embodiment, an operation method for a memory device which has a first memory element and a second memory element respectively provided on both sides of a semiconductor member includes applying a first potential on the second word line to write a second data to the second memory and applying a second potential on the first word line to write the first data to the first memory. The first potential increases by a first step voltage and the second potential increases by a second step voltage. | 2016-03-31 |
20160093383 | METHOD AND APPARATUS FOR RELOCATING DATA IN NON-VOLATILE MEMORY - Apparatus and methods implemented therein, in response to receiving an indication to program data to both a primary and secondary memory page determine whether a folding operation is in progress. In response to determining that the folding operation is in progress, programming of the data is delayed until completion of the folding operation. In response to determining the completion of the folding operation, data is programmed to the primary memory page and secondary memory page. | 2016-03-31 |
20160093384 | SELF-TIMED SLC NAND PIPELINE AND CONCURRENT PROGRAM WITHOUT VERIFICATION - A hierarchical-GBL/LBL NAND array with a plurality of LG and MG groups in either orthogonal BL/CSL scheme or parallel BL/SL scheme including a plurality of block-decoders with a shared self-timed delay control circuit and a plurality of fully-shielding dynamic CACHE registers made of 2 local broken metal lines within the array and DRAM-like SA is provided. Each DCR capacitor is flexibly expandable by connecting multiple C | 2016-03-31 |
20160093385 | FLASH MEMORY ARRANGEMENT - A flash memory arrangement includes first memory cells for non-volatile memory of information and a read-write circuit. The read-write circuit includes a write latch, read amplifier, bit circuit pre-charge circuit, and databus interface, with the first memory cell being connected to a first bit circuit, word circuit, VSE circuit, and a select circuit, and the read-write circuit being connected to a column decoder, databus, and a read control signal circuit. A first memory column is arranged such that in a first partial matrix the first memory cell is arranged, in which a first select transistor, a memory transistor, and a second select transistor are arranged between the first bit circuit and a discharge hub. The second select transistor can be controlled by a global, non address-decoded read-write select circuit. At every bit circuit, a reference memory cell is arranged. A second partial matrix is provided equivalent to the first partial matrix. | 2016-03-31 |
20160093386 | MITIGATING RELIABILITY DEGRADATION OF ANALOG MEMORY CELLS DURING LONG STATIC AND ERASED STATE RETENTION - A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells. | 2016-03-31 |
20160093387 | METHOD OF OPERATING A MEMORY SYSTEM HAVING AN ERASE CONTROL UNIT - A method of operating a memory system including a nonvolatile memory including a memory block, and a memory controller including an erase control unit, includes performing pre-reading a plurality of memory cells connected to a selected word line of the memory block, generating an off cell count based on the pre-reading result, by operation of the erase control unit, comparing the off cell count with a reference value to generate a comparison result, and changing an erase operation condition based on the comparison result, by operation of the nonvolatile memory, and erasing the memory block according to the changed erase operation condition. | 2016-03-31 |
20160093388 | NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF - An operating method of a nonvolatile memory device is provided. The nonvolatile memory device includes first and second page buffers, and first and second bit lines connected thereto, respectively. First and second latch nodes of the first page buffer are charged to have a voltage having a first level according to data stored in a first latch of the first page buffer. After the charging of the first latch node is started, a sensing node of the second page buffer is pre-charged. The sensing node is connected to the second bit line. Data stored in the first latch is dumped into a second latch of the first page buffer during the pre-charging of the sensing node of the second page buffer. | 2016-03-31 |
20160093389 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory can reduce variations in an amount of current during data writing operation. This allows for the writing of data to memory cells with high precision. The nonvolatile semiconductor memory includes a plurality of memory cells, word lines connected to the memory cells, and bit lines connected to each of the memory cells. At least two of the bit lines are selected, and a current is simultaneously supplied from a power supply line to those memory cells which are connected to the selected bit lines in order to write data thereto. The nonvolatile semiconductor memory also includes charge amount measurement units for measuring respective amounts of charge stored in the memory cells. The nonvolatile semiconductor memory also includes current path switching circuits connected to the respective bit lines. Those current path switching circuits which are connected to the selected bit lines supply a current from the power supply line to the memory cells or a predetermined terminal depending on a measured value of the amount of charge measured by the charge amount measurement section. | 2016-03-31 |
20160093390 | Read With Look-Back Combined With Programming With Asymmetric Boosting In Memory - A read operation compensates for program disturb when distinguishing between an erased-state and a lowest programmed data state, where the program disturb is a function of the data state of an adjacent, previously-programmed memory cell on a common charge-trapping layer. The read operation occurs in connection with a programming operation which avoids program disturb of the programmed data states by using asymmetric pass voltages. Before reading the memory cells on a selected word line (WLn), the memory cells on the adjacent, previously-programmed word line (WLn−1) are read. The read operation for WLn uses multiple read voltages—one for each data state on WLn−1, and one of the read results is selected based on the data state of the adjacent memory cell. Other read operations distinguish between each pair of adjacent programmed data states using a read voltage which is independent of the data state of the adjacent memory cell. | 2016-03-31 |
20160093391 | SEMICONDUCTOR DEVICE - A semiconductor device may include a memory string coupled between a bit line and a common source line and configured to include a drain select transistor, memory cells, and a source select transistor. The drain select transistor may be configured to operate based on a voltage applied to a drain select line. The memory cells may be configured to operate based on a voltage applied to word lines. The source select transistor may be configured to operate based on a voltage applied to a source select line. The semiconductor device may include an operation circuit configured to perform a read operation or a verify operation of the memory cells. The operation circuit may be configured to apply a negative voltage to the common source line during the read operation or the verify operation. | 2016-03-31 |
20160093392 | MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - According to an embodiment, an operation method for a memory device which has a first memory element and a second memory element respectively provided on both sides of a semiconductor member includes applying a first voltage to a second word line, the first voltage being negative for a voltage of a cell source line, and applying a second voltage to a first word line, the second voltage being positive for the voltage of the cell source line when reading out a data from the first memory element. | 2016-03-31 |
20160093393 | FLASH MEMORY APPARATUS FOR PHYSICAL UNCLONABLE FUNCTION AND EMBODYING METHOD OF THE SAME - A flash memory apparatus having a physical unclonable function (PUF) and an embodying method of the same are provided. To elaborate, the flash memory apparatus includes a flash memory unit that comprises a main memory area and a peripheral memory area; a challenge input unit that receives input of a challenge value; a read voltage setting unit that sets a read voltage based on the input challenge value; a data reading unit that reads data by applying the read voltage to a memory cell included in a pre-set memory area in the peripheral memory area each time the challenge value is input; and a response output unit that outputs the read data as a response value corresponding to the challenge value, wherein the pre-set memory area consists of a plurality of memory cells comprising two or more memory cells having different threshold voltage values. | 2016-03-31 |
20160093394 | STORAGE DEVICE AND OPERATING METHOD OF STORAGE DEVICE - An operating method is provided which includes receiving a read command and a read address, performing a read operation about memory cells selected according to the read address, and performing a reliability verification read operation about unselected memory cells adjacent to the selected memory cells. A number of memory cells each corresponding to at least one state of an erase state and program states of the unselected memory cells is counted as a count value based on the result of the reliability verification read operation. Data read through the read operation is output to an external device and data read through the reliability verification read operation is not output to the external device. | 2016-03-31 |