13th week of 2016 patent applcation highlights part 48 |
Patent application number | Title | Published |
20160093495 | METHOD FOR PERFORMING ACTIVATION OF DOPANTS IN A GAN-BASE SEMICONDUCTOR LAYER BY SUCCESSIVE IMPLANTATIONS AND HEAT TREATMENTS - The method for performing activation of n-type or p-type dopants in a GaN-base semiconductor includes the following steps: providing a substrate including a GaN-base semiconductor material layer, performing the following successive steps at least twice: implanting electric dopant impurities in the semiconductor material layer, performing heat treatment so as to activate the electric dopant impurities in the semiconductor material layer, a cap layer covering the semiconductor material layer when the heat treatment is performed, two implantation steps of electric dopant impurities being separated by a heat treatment step. | 2016-03-31 |
20160093496 | METHOD FOR FABRICATING AN IMPROVED GAN-BASED SEMICONDUCTOR LAYER - The invention relates to a post-activation method of dopants in a doped and activated GaN-base semiconductor layer, including the following successive steps: providing said doped and activated substrate, eliminating a part of the semiconductor material layer. | 2016-03-31 |
20160093497 | SALICIDE FORMATION USING A CAP LAYER - A method of forming a semiconductor device includes forming a gate stack over a first portion of a source and a first portion of a drain. The method includes depositing a first cap layer comprising silicon over a second portion of the source and depositing a second cap layer comprising silicon over a second portion of the drain. The method includes depositing a metal layer over the gate stack, the first cap layer and the second cap layer. The method includes annealing the semiconductor device until all of the silicon in the first and second cap layers reacts with metal from the metal layer, wherein the annealing causes metal from the metal layer to react with silicon in the first cap layer, the second cap layer, the source, and the drain. Annealing the semiconductor device includes forming a salicide layer having a germanium concentration less than 3% by weight. | 2016-03-31 |
20160093498 | METHOD FOR FORMING CONTROL GATE SALICIDE - A method for forming a semiconductor device includes forming a conductive structure of a silicon material on a substrate and forming a planarized dielectric layer adjacent the conductive structure. The method also includes removing a portion of the dielectric layer to expose a top portion of the conductive structure and removing an outer portion of the exposed top portion of the conductive structure such that the top portion of the gate structure has a narrower width than the unexposed portion. The method further includes forming a metal layer over the exposed portion of the gate structure and a top surface of the dielectric layer, and forming a silicide layer over the top portion of the conductive structure. The width of the silicided top portion of the conductive structure is substantially the same as the width of the bottom portion of the conductive structure. | 2016-03-31 |
20160093499 | Method of Manufacturing Semiconductor Device - To provide a semiconductor device having improved performance while improving the throughput in the manufacturing steps of the semiconductor device. An insulating film portion comprised of first, second, third, fourth, and fifth insulating films is formed on a semiconductor substrate. The second insulating film is a first charge storage film and the fourth insulating film is a second charge storage film. The first charge storage film contains silicon and nitrogen; the third insulating film contains silicon and oxygen; and the second charge storage film contains silicon and nitrogen. The thickness of the third insulating film is smaller than that of the first charge storage film and the thickness of the second charge storage film is greater than that of the first charge storage film. The third insulating film is formed by treating the upper surface of the first charge storage film with a water-containing treatment liquid. | 2016-03-31 |
20160093500 | METHOD FOR PROCESSING A CARRIER, A METHOD FOR OPERATING A PLASMA PROCESSING CHAMBER, AND A METHOD FOR PROCESSING A SEMICONDUCTOR WAFER - According to various embodiments, a method for processing a carrier may include: performing a dry etch process in a processing chamber to remove a first material from the carrier by an etchant, the processing chamber including an exposed inner surface including aluminum and the etchant including a halogen; and, subsequently, performing a hydrogen plasma process in the processing chamber to remove a second material from at least one of the carrier or the inner surface of the processing chamber. | 2016-03-31 |
20160093501 | METHOD FOR CONTROLLING ETCHING IN PITCH DOUBLING - Embodiments of the invention describe a method for controlling etching in pitch doubling. According to one embodiment, the method includes receiving a substrate having a pattern thereon defined by spacers formed on sidewalls of a plurality mandrels, and transferring the pattern defined by the spacers into the substrate using a plasma etch process that etches the mandrels and the substrate, the transferring forming first recessed features in the substrate below the mandrels and second recessed features in the substrate between the mandrels, where the plasma etch process utilizes an etching gas containing O | 2016-03-31 |
20160093502 | FIN CUT FOR TIGHT FIN PITCH BY TWO DIFFERENT SIT HARD MASK MATERIALS ON FIN - Methods that enable fin cut at very tight pitch are provided. After forming a first set of paired sidewall image transfer (SIT) spacers and a second set of paired SIT spacers composed of different materials, portions of the first set of the paired SIT spacers can be selectively removed without adversely affecting the second set of the paired SIT spacers, even portions of both sets of the paired SIT spacers are exposed by the cut mask due to the different etching characteristics of the different materials. | 2016-03-31 |
20160093503 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - In a substrate processing apparatus, chemical-solution processing is performed by supplying a chemical solution to the upper surface of a substrate in a state where a top plate is located at a first relative position. Also, cleaning processing is performed by supplying a cleaning liquid to the upper surface of the substrate in a state where the top plate is located at a second relative position closer to the substrate than the first relative position is. Moreover, dry processing is performed on the substrate by rotating the substrate in a state where the top plate is located at a third relative position closer to the substrate than the second relative position is. This allows a chemical atmosphere above the substrate to be efficiently removed during the cleaning processing. Consequently, the occurrence of particles due to the chemical atmosphere above the substrate can be suppressed during the dry processing. | 2016-03-31 |
20160093504 | METHOD FOR PRODUCING A MULTILEVEL MICROELECTRONIC STRUCTURE - The invention relates to a method for producing a multilevel microelectronic structure, comprising at least:
| 2016-03-31 |
20160093505 | OXIDE ETCH SELECTIVITY ENHANCEMENT - A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using plasma effluents formed in a remote plasma. The remote plasma excites a fluorine-containing precursor in combination with an oxygen-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor or an alcohol. The combination react with the patterned heterogeneous structures to remove an exposed silicon oxide portion faster than an exposed silicon nitride portion. The inclusion of the oxygen-containing precursor may suppress the silicon nitride etch rate and result in unprecedented silicon oxide etch selectivity. | 2016-03-31 |
20160093506 | SILICON OXIDE SELECTIVE REMOVAL - A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using plasma effluents formed in a remote plasma. The remote plasma excites a fluorine-containing precursor in combination with an oxygen-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor or an alcohol. The combination react with the patterned heterogeneous structures to remove an exposed silicon oxide portion faster than a second exposed portion. The inclusion of the oxygen-containing precursor may suppress the second exposed portion etch rate and result in unprecedented silicon oxide etch selectivity. | 2016-03-31 |
20160093507 | METHOD OF LOCALIZED ANNEALING OF SEMI-CONDUCTING ELEMENTS USING A REFLECTIVE AREA - A method of making crystal semi-conducting material-based elements, including providing a support having amorphous semi-conducting material-based semi-conducting elements, the support being further provided with one or more components and with a reflective protective area configured so as to reflect a light radiation in a given wavelength range, exposing the element(s) to a laser radiation emitting in the given wavelength range so as to recrystallize the elements, the reflective protective area being arranged on the support relative to the elements and to the components so as to reflect the laser radiation and protect the components from this radiation. | 2016-03-31 |
20160093508 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM - The present invention provides a technology that includes: forming an intermediate film on a substrate having an insulating film formed thereon; and forming a metal film on the intermediate film. The intermediate film is more susceptible to oxidation than the metal film and has a smaller thickness than the metal film. | 2016-03-31 |
20160093509 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device in which a gettering layer is formed in a semiconductor substrate, and a method for forming the same are disclosed, resulting in increased reliability of the semiconductor substrate including the gettering layer. The semiconductor device includes a semiconductor substrate; a gettering layer formed of a first-type impurity and a second-type impurity in the semiconductor substrate so as to perform gettering of metal ion; and a deep-well region formed over the gettering layer in the semiconductor substrate. | 2016-03-31 |
20160093510 | METHOD FOR PERFORMING ACTIVATION OF DOPANTS IN A GAN-BASE SEMICONDUCTOR LAYER - The method for performing activation of p-type dopants in a GaN-base semiconductor comprises a first step consisting in providing a substrate comprising (i) a GaN-base semiconductor material layer comprising p-type electric dopant impurities, (ii) a cap block devoid of any silicon-base compound, in contact with the semiconductor material layer, and (iii) a silicon-base covering layer covering the cap block. The method comprises a second heat treatment step at a temperature of more than 900° C. so as to activate the p-type electric dopant impurities in the semiconductor material layer. | 2016-03-31 |
20160093511 | MULTIGATE TRANSISTOR DEVICE AND METHOD OF ISOLATING ADJACENT TRANSISTORS IN MULTIGATE TRANSISTOR DEVICE USING SELF-ALIGNED DIFFUSION BREAK (SADB) - A multigate transistor device such as a fin-shaped field effect transistor (FinFET) is fabricated by applying a self-aligned diffusion break (SADB) mask having an opening positioned to expose an area of at least one portion of at least one gate stripe designated as at least one tie-off gate in the multigate transistor device and removing the tie-off gate through the opening of the SADB mask to isolate transistors adjacent to the tie-off gate. | 2016-03-31 |
20160093512 | Substrate Processing Apparatus, Method of Manufacturing Semiconductor Device and Non-Transitory Computer-Readable Recording Medium - Provided is a configuration capable of suppressing a variation in characteristics of transistor. The configuration includes: a process chamber; a gas supply unit configured to supply a hard mask forming gas into the process chamber; a substrate support table configured to support a substrate W | 2016-03-31 |
20160093513 | SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHODS - A method for forming a semiconductor device includes providing a semiconductor structure which has a substrate and N sub-stack structures numbered from 1 to N, where N is an integer. Each sub-stack structure includes two sub-stacks, and a mask layer overlying the N sub-stack structures. The method also includes repeatedly removing a portion of the mask layer and removing exposed portions of the sub-stack structures to form a first stepped structure, and forming first spacers on sidewalls of the mask layer and the sub-stack structures in the stepped structure, each spacer covering a portion of the exposure portions of the sub-stack structures. The method further includes using the mask layer and the first spacers as masks to remove exposed portions of an upper sub-stack in the first stepped structure, and removing the mask layer and the spacers to form a second stepped structure. | 2016-03-31 |
20160093514 | MANUFACTURING PROCESS FOR SUBSTRATE STRUCTURE HAVING COMPONENT-DISPOSING AREA - A process for a substrate having a component-disposing area is provided, and includes the following steps. A core layer including a first surface, a metallic layer and a component-disposing area is provided. The metallic layer is disposed on the first surface and patterned to form a patterned metallic layer including pads located in the component-disposing area. A first dielectric layer is formed on the first surface and covers the patterned metallic layer. A laser-resistant metallic pattern is formed on the first dielectric layer and surrounds a projection area of the first dielectric layer. A release film is disposed on the projection area and covers a portion of the laser-resistant metallic pattern within the projection area. A second dielectric layer is formed on the first dielectric layer and covers the release film and the laser-resistant metallic pattern. A first open hole and a plurality of second open holes are formed. | 2016-03-31 |
20160093515 | SUBSTRATE PROCESSING APPARATUS - A processing liquid is supplied from a supply tank to a processing liquid nozzle of a processing unit, and the processing liquid is supplied from the processing liquid nozzle to a substrate. The processing liquid used in the processing unit is collected and selectively supplied to first and second replenishment tanks. In a period in which the used processing liquid is supplied to the first replenishment tank, the supply tank is replenished with the processing liquid in the second replenishment tank, and the processing liquid in the first replenishment tank circulates while being heated by a heater. In a period in which the used processing liquid is supplied to the second replenishment tank, the supply tank is replenished with the processing liquid in the first replenishment tank and the processing liquid in the second replenishment tank circulates while being heated by the heater. | 2016-03-31 |
20160093516 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - The method includes holding a substrate horizontally with a holding and rotating mechanism; introducing processing liquid from a fluid introduction portion of, in a processing liquid pipe in which a processing liquid nozzle having a discharge port at a tip end is provided at one end, the other end of the processing liquid pipe into the processing liquid pipe so as to discharge the processing liquid from the discharge port toward the substrate; introducing, after stopping the processing liquid discharge step, a gas from the fluid introduction portion into the processing liquid pipe so as to extrude the processing liquid within the processing liquid pipe and within the processing liquid nozzle outwardly; and stopping, after starting the introduction of the gas, the introduction of the gas into the processing liquid pipe with the processing liquid being left within the processing liquid pipe and/or the processing liquid nozzle. | 2016-03-31 |
20160093517 | SUBSTRATE LIQUID PROCESSING METHOD, SUBSTRATE LIQUID PROCESSING APPARATUS, AND RECORDING MEDIUM - Disclosed is a substrate liquid processing method. The method includes: supplying a first processing liquid to a central portion of a substrate at a first flow rate by a first nozzle while rotating the substrate using a substrate holding unit; supplying a second processing liquid to a location between the central portion and an outer circumferential end of the substrate by a second nozzle while supplying the first processing liquid to the central portion of the substrate at the first flow rate; and changing the flow rate of the first processing liquid supplied from the first nozzle to a second flow rate lower than the first flow rate, so as to continue forming of the liquid film on the overall surface of the substrate while supplying the second processing liquid by the second nozzle to the substrate that is formed with a liquid film on the overall surface thereof. | 2016-03-31 |
20160093518 | INITIATOR AND METHOD FOR DEBONDING WAFER SUPPORTING SYSTEM - Provided are an initiator and a method for debonding a wafer supporting system. The initiator for debonding a wafer supporting system includes a rotation chuck having an upper surface on which a wafer supporting system (WSS), which includes a carrier wafer, a device wafer, and a glue layer for bonding the carrier wafer and the device wafer to each other, is seated to rotate the wafer supporting system, a detecting module detecting a height and a thickness of the glue layer and a laser module generating a fracture portion on the glue layer through irradiating a side surface of the glue layer with a laser on the basis of the height and the thickness of the glue layer. | 2016-03-31 |
20160093519 | SUBSTRATE HEAT TREATMENT APPARATUS, SUBSTRATE HEAT TREATMENT METHOD, STORAGE MEDIUM AND HEAT-TREATMENT-CONDITION DETECTING APPARATUS - A substrate heat treatment apparatus includes: a placement unit on which a substrate is placed; a heat treatment unit for heating or cooling the substrate on the placement unit; a plurality of temperature sensors positioned correspondingly to a plurality of locations of the substrate on the placement unit; and a control unit. The control unit is configured to control the heat treatment unit based on temperatures detected by the temperature sensors, to calculate a position of a thermal center of gravity of the substrate based on the temperatures detected by the temperature sensors, and to detect heat treatment condition of the substrate based on the position of the thermal center of gravity. | 2016-03-31 |
20160093520 | PROCESSING APPARATUS AND PROCESSING METHOD - Disclosed is a processing apparatus. The processing apparatus includes: a load port in which a conveyance container accommodating a plurality of semiconductor wafers is placed; a dummy wafer storage area in which a conveyance container accommodating a plurality of dummy wafers is placed; a normal-pressure conveyance room in which a first conveyance arm is installed; an equipment that processes the plurality of semiconductor wafers in a state where the semiconductor wafers and the dummy wafers which are conveyed are placed in slots, respectively; and a controller that controls each component of the processing apparatus. The controller classifies the dummy wafers accommodated in the conveyance container into a plurality of groups, and controls the first conveyance arm to preferentially convey the dummy wafers within one of the classified groups to the equipment and, in replacing the dummy wafers, to perform replacement of the dummy wafers group to group as classified. | 2016-03-31 |
20160093521 | DUAL TEMPERATURE HEATER - A method and apparatus for heating a substrate in a chamber are provided. an apparatus for positioning a substrate in a processing chamber. In one embodiment, the apparatus comprises a substrate support assembly having a support surface adapted to receive the substrate and a plurality of centering members for supporting the substrate at a distance parallel to the support surface and for centering the substrate relative to a reference axis substantially perpendicular to the support surface. The plurality of the centering members are movably disposed along a periphery of the support surface, and each of the plurality of centering members comprises a first end portion for either contacting or supporting a peripheral edge of the substrate. | 2016-03-31 |
20160093522 | WAFER PROCESSING LAMINATE, TEMPORARY ADHESIVE MATERIAL FOR WAFER PROCESSING, AND METHOD FOR MANUFACTURING THIN WAFER - A wafer processing laminate including a support, a temporary adhesive material layer formed on the support, and a wafer laminated on the temporary adhesive material layer, the wafer having a circuit-forming front surface and back surface to be processed, wherein the temporary adhesive material layer includes a complex temporary adhesive material layer having two-layered structure including a first temporary adhesive layer composed of a thermoplastic organopolysiloxane polymer layer (A) having a film thickness of less than 100 nm and a second temporary adhesive layer composed of a thermosetting siloxane-modified polymer layer (B), the first temporary adhesive layer being releasably laminated to the front surface of the wafer, the second temporary adhesive layer being releasably laminated to the first temporary adhesive layer and the support. A temporary adhesive material for a wafer processing which withstand a thermal process at high temperature exceeding 300° C., facilitating temporary adhesion and delamination. | 2016-03-31 |
20160093523 | SEMICONDUCTOR STRUCTURE WITH AIRGAP - A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap. | 2016-03-31 |
20160093524 | MULTIHEIGHT ELECTRICALLY CONDUCTIVE VIA CONTACTS FOR A MULTILEVEL INTERCONNECT STRUCTURE - A method of making multi-level contacts includes providing an in-process multilevel device having a device region and a contact region including a stack of alternating sacrificial layers and insulating layers located over a major surface of a substrate. A contact mask having contact mask openings is provided over the stack, and a first over mask having first over mask openings is provided over the contact mask. A subset of the contact mask openings is substantially aligned with the first over mask openings. Contact openings are formed through the stack, wherein each of the contact openings extends substantially perpendicular to the major surface of the substrate to a respective one of the sacrificial layers. A plurality of electrically conductive via contacts is formed in the plurality of the contact openings. | 2016-03-31 |
20160093525 | PRINTED INTERCONNECTS FOR SEMICONDUCTOR PACKAGES - A method forming a packaged semiconductor device includes providing a first semiconductor die (first die) having bond pads thereon mounted face-up on a package substrate or on a die pad of a lead frame (substrate), wherein the substrate includes terminals or contact pads (substrate pads). A first dielectric layer is formed including printing a first dielectric precursor layer including a first ink having a first liquid carrier solvent extending from the substrate pads to the bond pads. A first interconnect precursor layer is printed including a second ink having a second liquid carrier over the first dielectric layer extending from the substrate pads to the bond pads. Sintering or curing the first interconnect precursor layer removes at least the second liquid carrier to form an electrically conductive interconnect including an ink residue which connects respective substrate pads to respective bond pads. | 2016-03-31 |
20160093526 | DIFFUSION BARRIER LAYER FORMATION - A method of forming a titanium nitride (TiN) diffusion barrier includes exposing a deposition surface to a first pulse of a titanium-containing precursor and to a first pulse of a nitrogen-rich plasma to form a first TiN layer with a first nitrogen concentration making a lower portion of the TiN diffusion barrier, the first nitrogen concentration of the first TiN layer is increased by the first pulse of the nitrogen-rich plasma reducing a reactivity of the lower portion of the TiN diffusion barrier to prevent fluorine diffusion. The first TiN layer is exposed to second pulses of the titanium-containing precursor and the nitrogen-rich plasma to form a second TiN layer with a second nitrogen concentration above the first TiN layer making an upper portion of the TiN diffusion barrier, the first pulse of the nitrogen-rich plasma has a substantially longer duration than the second pulse of the nitrogen-rich plasma. | 2016-03-31 |
20160093527 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE INCLUDING SILICON-CONTAINING LAYER AND METAL-CONTAINING LAYER, AND CONDUCTIVE STRUCTURE OF THE SAME - A method for fabricating a semiconductor device includes forming a silicon-containing layer; forming a metal-containing layer over the silicon-containing layer; forming an undercut prevention layer between the silicon containing layer and the metal containing layer; etching the metal-containing layer; and forming a conductive structure by etching the undercut prevention layer and the silicon-containing layer. | 2016-03-31 |
20160093528 | FEATURE FILL WITH NUCLEATION INHIBITION - Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias. | 2016-03-31 |
20160093529 | Method of Manufacturing a Semiconductor Device Having a Cell Field Portion and a Contact Area - A semiconductor device is manufactured at least partially in a semiconductor substrate. The substrate has first and second opposing main surfaces. The method includes forming a cell field portion and a contact area, the contact area being electrically coupled to the cell field portion, and forming the cell field portion by at least forming a transistor. The method further includes insulating a part of the semiconductor substrate from other substrate portions to form a connection substrate portion, forming an electrode adjacent to the second main surface so as to be in contact with the connection substrate portion, forming an insulating layer over the first main surface, forming a metal layer over the insulating layer, forming a trench in the first main surface, and filling the trench with a conductive material, and electrically coupling the connection substrate portion to the metal layer via the trench. | 2016-03-31 |
20160093530 | METHOD FOR FORMING THROUGH SUBSTRATE VIAS - A method for forming through silicon vias (TSVs) in a silicon substrate is disclosed. The method involves forming a silicon post as an annulus in a first side of a silicon substrate, removing material from an opposite side to the level of the annulus, removing the silicon post and replacing it with a metal material to form a metal via extending through the thickness of the substrate. | 2016-03-31 |
20160093531 | METHOD FOR FORMING THROUGH SUBSTRATE VIAS WITH TETHERS - A method for forming through silicon vias (TSVs) in a silicon substrate is disclosed. The method involves forming a silicon post as an substantially continuous annulus in a first side of a silicon substrate, removing material from an opposite side to the level of the substantially continuous annulus, removing the silicon post and replacing it with a metal material to form a metal via extending through the thickness of the substrate. The substantially continuous annulus may be interrupted by at least one tether which connects the silicon post to the silicon substrate. The tether may be formed of a thing isthmus of silicon, or some suitable insulating material. | 2016-03-31 |
20160093532 | METHOD OF MANUFACTURING THROUGH SILICON VIA STACKED STRUCTURE - A method of manufacturing through silicon via stacked structures. A plurality of substrates is provided. At least one tapered hole is formed on one surface of each substrate. Each tapered hole is filled up with a tapered through silicon via. A recessed portion is formed on the wider end of each tapered through silicon via. A part of the substrate is removed until the narrower end of each tapered through silicon via protrudes from the other surface of the substrate. The substrates is stacked one after another by fitting and jointing the narrower end of each tapered through silicon via on one substrate into a corresponding recessed portion of the tapered through silicon via of another substrate. | 2016-03-31 |
20160093533 | SUBSTRATE FOR ALTERNATIVE SEMICONDUCTOR DIE CONFIGURATIONS - A method of assembling semiconductor devices with semiconductor dies of alternative different configurations uses the same substrate panel. The dies of the selected configuration are placed in an array, mounted, and connected to internal electrical contact pads on a first face of the panel using main fiducial markings and an array of subsidiary fiducial markings corresponding universally to arrays of semiconductor dies of the different alternative configurations. The pitch of the subsidiary fiducial markings is equal to the spacing between adjacent rows of the internal electrical contact pads on the panel and is a sub-multiple of the pitch of the array of dies. | 2016-03-31 |
20160093534 | Method for Separating Chips from a Wafer - The invention relates to a method for producing chips ( | 2016-03-31 |
20160093535 | METHOD AND APPARATUS OF MULTI THRESHOLD VOLTAGE CMOS - A first and a second instance of a common structured stack are formed, respectively, on a first fin and a second fin. The common structured stack includes a work-function metal layer, and a barrier layer. The barrier layer of the first instance of the common structured stack is etched through, and the work-function metal layer of the first instance of the common structure is partially etched. The partial etch forms a thinner work-function metal layer, having an oxide of the work-function metal as a new barrier layer. A gate element is formed on the new barrier layer. | 2016-03-31 |
20160093536 | INTEGRATED CIRCUIT HAVING PLURAL TRANSISTORS WITH WORK FUNCTION METAL GATE STRUCTURES - The present invention provides an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer. | 2016-03-31 |
20160093537 | APPARATUS AND METHOD OF MANUFACTURING FIN-FET DEVICES - A method of manufacturing a Fin-FET device includes forming a plurality of fins in a substrate, which the substrate includes a center region and a periphery region surrounding the center region. A gate material layer is deposited over the fins, and the gate material layer is etched with an etching gas to form gates, which the etching gas is supplied at a ratio of a flow rate at the center region to a flow rate at the periphery region in a range from 0.33 to 3. | 2016-03-31 |
20160093538 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first metal containing a first conductivity-type impurity above a substrate provided with a first conductivity-type impurity region containing a first conductivity-type impurity and a second conductivity-type impurity region containing a second conductivity-type impurity; and forming a metal silicide containing the first metal by selectively causing, by thermal treatment, a reaction between the first metal and silicon contained in the substrate in the first conductivity-type impurity region. | 2016-03-31 |
20160093539 | MODIFICATION PROCESSING DEVICE, MODIFICATION MONITORING DEVICE AND MODIFICATION PROCESSING METHOD - There is provided a technique for easily inspecting the modification state of a film in a semiconductor substrate. A modification processing device modifies a film by irradiating a semiconductor substrate with pulsed light emitted from a light irradiation part. The modification processing device includes an electromagnetic wave detection part for detecting an electromagnetic wave pulse including a millimeter wave or a terahertz wave radiated from the semiconductor substrate in response to the irradiation with the pulsed light. The modification processing device further includes a modification determination part for determining the modification state, based on the intensity of the electromagnetic wave pulse. | 2016-03-31 |
20160093540 | INLINE MEASUREMENT OF MOLDING MATERIAL THICKNESS USING TERAHERTZ REFLECTANCE - A method including emitting a terahertz beam from a light source at a layer of molding material; detecting a reflectance of the beam; and determining a thickness of the layer of molding material. A system including a panel supporter operable to support a panel including a plurality of substrates arranged in a planar array; a light source operable to emit a terahertz beam at a panel on the panel supporter; a detector operable to detect a reflection of a terahertz beam emitted at a panel; and a processor operable to determine a thickness of a material on the panel based on a time delay for an emitted terahertz beam to be detected by the detector. | 2016-03-31 |
20160093541 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor package includes providing a semiconductor chip including a circuit pattern, a connection pad, a first test pad and a second test pad, each of the connection pad, the first test pad and the second test pad respectively electrically connected to the circuit pattern, evaluating electrical characteristics of the semiconductor chip by applying a first test voltage to the first test pad and a second test voltage to the second test pad, the second test voltage being higher than the first test voltage, and electrically disconnecting the second test pad from the circuit pattern. | 2016-03-31 |
20160093542 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING APPARATUS - A method of manufacturing a semiconductor device includes forming a film along a surface of a semiconductor substrate in a first state having a first surface area by supplying a reaction gas at a first flow rate. The method further includes detecting a transition from the first state to a second state having a second surface area different from the first surface area. The method still further includes forming a film by changing the flow rate of the reaction gas from the first flow rate to a second flow rate different form the first flow rate after detecting the transition from the first state to the second state. | 2016-03-31 |
20160093543 | ARRAY SUBSTRATE, METHOD FOR FABRICATING AND TESTING ARRAY SUBSTRATE, AND DISPLAY DEVICE - The present invention provides an array substrate, which includes a plurality of pixel units, each pixel unit includes a thin film transistor, a pixel electrode, a common electrode and a passivation layer, the thin film transistor includes an active layer, a gate electrode, a source electrode and a drain electrode, the drain electrode and the pixel electrode are connected, the passivation layer is disposed on the active layer, the source electrode, the drain electrode and the pixel electrode, the common electrode is disposed above the pixel electrode with the passivation layer therebetween, a test electrode is disposed on the active layer and under the passivation layer, the test electrode is electrically insulated from the gate electrode, the source electrode and the drain electrode. Correspondingly, a method for fabricating and a method for testing the array substrate, and a display device including the array substrate are provided. | 2016-03-31 |
20160093544 | Packaging of Semiconductor Devices - A packaged semiconductor device comprising a stack including a die comprising a functional circuit, and a cap which is wafer bonded to the die for protecting the functional circuit as well as a mold component for packaging the stack. At least the cap and/or the die comprises at least one groove at least partially in contact with the mold component, for increasing adhesion of the mold component to the stack. A corresponding method for manufacturing such a packaged device also is described. | 2016-03-31 |
20160093545 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes: a package substrate; a semiconductor chip mounted on the package substrate and electrically connected to the package substrate; a first protective layer covering the semiconductor chip and having flexibility controlled by at least one of a material type, a thickness, a material composition ratio and viscosity of the first protective layer; and a second protective layer arranged on the first protective layer and having flexibility controlled by at least one of a material type and a thickness of the second protective layer, wherein the first protective layer comprises a first binder resin, a first hardener, and a first hardening catalyst. According to the semiconductor package of the inventive concept, protective layers protecting the semiconductor chip have flexibility, and thus, the semiconductor package may be bent. | 2016-03-31 |
20160093546 | PACKAGE STUCTURE AND METHOD OF FABRICATING THE SAME - A method of fabricating a package structure is provided. The method includes providing a carrier having two opposing surfaces, forming dielectric bodies on the two surfaces of the carrier, respectively, each of the dielectric bodies having a wiring layer embedded therein and a conductive layer formed on the wiring layer, and removing the carrier. Therefore, the wiring layers, the conductive layers and the dielectric bodies are formed on the two surfaces of the carrier, respectively, and the production yield is thus increased. The present invention further provides the package structure thus fabricated. | 2016-03-31 |
20160093547 | EPOXY RESIN COMPOSITION FOR ENCAPSULATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE ENCAPSULATED USING THE SAME - An epoxy resin composition for encapsulating a semiconductor device and a semiconductor package, the composition including an epoxy resin; a polyorganosiloxane resin represented by Formula 3, below; a curing agent; a curing accelerator; and an inorganic filler: | 2016-03-31 |
20160093548 | SEMICONDUCTOR PACKAGE WITH PRINTED SENSOR - A method forming packaged semiconductor devices includes providing a completed semiconductor package having a die with bond pads coupled to package pins. Sensor precursors including an ink and a liquid carrier are additively printed directly on the die or package to provide precursors for electrodes and a sensing material between the sensor electrodes. Sintering or curing removes the liquid carrier such that an ink residue remains to provide the sensor electrodes and sensing material. The sensor electrodes electrically coupled to the pins or bond pads or the die includes a wireless coupling structure coupled to the bond pads and the method includes additively printing an ink then sintering or curing to form a complementary wireless coupling structure on the completed semiconductor package coupled to the sensor electrodes so that sensing signals sensed by the sensor are wirelessly transmitted to the bond pads after being received by the wireless coupling structure. | 2016-03-31 |
20160093549 | INTEGRATED CIRCUIT HEATER FOR REDUCING STRESS IN THE INTEGRATED CIRCUIT MATERIAL AND CHIP LEADS OF THE INTEGRATED CIRCIT, AND FOR OPTIMIZING PERFORMANCE OF DEVICES OF THE INTEGRATED CIRCUIT - A device comprising a first detector, comprising an output, disposed at a first location of an integrated circuit chip and configured to determine a first temperature information, a chip heater, comprising an input to receive a control signal, disposed at a second location of the integrated circuit and configured to heat an area of the integrated circuit device that includes the first location and the second location, based upon the control signal, and a heater controller comprising a first input coupled to the output of the first detector to receive the first temperature information, and an output coupled to the input of the chip heater, the heater controller configured to generate the control signal based upon the first temperature information. | 2016-03-31 |
20160093550 | ELECTRONIC DEVICE HAVING A HEAT RADIATING UNIT - An electronic device includes a first electronic unit, a second electronic unit disposed adjacent to the first electronic unit, and a heat radiating unit. The second electronic unit has a first portion and a second portion that is closer to the first electronic unit than the first portion. The heat radiating unit is disposed such that heat generated in the second portion of the second electronic unit is directed towards the first portion of the second electronic unit and from the first portion towards an outside of the electronic device. | 2016-03-31 |
20160093551 | INTEGRATION OF HEAT SPREADER FOR BEOL THERMAL MANAGEMENT - A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader layer is disposed above a top surface of a substrate of the semiconductor device. The heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters. | 2016-03-31 |
20160093552 | INTEGRATION OF BACKSIDE HEAT SPREADER FOR THERMAL MANAGEMENT - A microelectronic device includes semiconductor device with a component at a front surface of the semiconductor device and a backside heat spreader layer on a back surface of the semiconductor device. The backside heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters. | 2016-03-31 |
20160093553 | ON DEMAND COOLING OF AN NVM USING A PELTIER DEVICE - Some examples relate to an electronic system that includes a substrate and a non-volatile memory (NVM) mounted on the substrate. The electronic system further includes a Peltier device mounted to a portion of the NVM to provide on demand short term cooling to the NVM during operation of the NVM. Other examples relate to a method that includes operating a plurality non-volatile memories (NVMs) that is part of an electronic system, and using a plurality of Peltier devices to provide on demand short term cooling to a portion of each NVM. | 2016-03-31 |
20160093554 | METHOD AND APPARATUS FOR COOLING A SEMICONDUCTOR DEVICE - A method and an apparatus for cooling a semiconductor device. The method comprises the steps of contacting a surface of the semiconductor device with respective end portions of an array of contact elements thermally coupled to a cooling fluid, and disposing a flexible, heat conductive sheet between the respective end portions of the contact elements and the surface of the semiconductor device for transferring heat generated in the semiconductor device to the cooling fluid via the sheet and the contact elements. | 2016-03-31 |
20160093555 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member. | 2016-03-31 |
20160093556 | QUAD-FLAT NON-LEAD PACKAGE STRUCTURE AND METHOD OF PACKAGING THE SAME - A quad-flat non-lead package structure includes a film layer, a conducting layer, a die, an encapsulant, and a plurality of metal bumps. The film layer has a plurality of through holes. A pad of the conducting layer and conducting wirings are disposed at the film layer but are not connected to each other. The conducting wirings are disposed at the through holes, respectively. The die is fixedly disposed at the pad and electrically connected to the conducting wirings. The encapsulant covers the conducting layer and the die. The metal bumps are disposed in the through holes, respectively, each have one end electrically connected to a corresponding one of the conducting wirings, and each have the other end protruding from a corresponding one of the through holes. Accordingly, the quad-flat non-lead package structure features reduced likelihood of pin disconnection and enhanced adhesiveness required for surface-mount technology. | 2016-03-31 |
20160093557 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second semiconductor chips, a plurality of leads, a plurality of wires, and a sealing body sealing those components. A first pad electrode, a second pad electrode, and an internal wiring electrically connected to the first and second electrode pads are formed on a main surface of the first semiconductor chip. A third pad electrode of the second semiconductor chip is electrically connected to the first electrode pad of the first semiconductor chip via a first wire, and the second electrode pad of the first semiconductor chip is electrically connected to a first lead via a second wire. A distance between the first lead and the first semiconductor chip is smaller than a distance between the first lead and the second semiconductor chip. The first electrode pad, the second electrode pad and the internal wiring are not connected to any circuit formed in the first semiconductor chip. | 2016-03-31 |
20160093558 | PACKAGED DEVICE WITH ADDITIVE SUBSTRATE SURFACE MODIFICATION - A method of lead frame surface modification includes providing at least one pre-fabricated metal lead frame or package substrate (substrate) unit including a base metal having a die pad and a plurality of contact regions surrounding the die pad. An ink including a material that is a solid or a precursor for a solid that forms a solid upon a curing step or a sintering step that removes a liquid carrier is additively deposited including onto at least one of (i) a region of the die pad and (ii) at one region of at least a first of the contact regions (first contact region). The ink is sintered or cured to remove the liquid carrier so that a substantially solid ink residue remains. | 2016-03-31 |
20160093559 | SEMICONDUCTOR PACKAGE WITH SMALL GATE CLIP AND ASSEMBLY METHOD - A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source electrode and a gate electrode at a top surface, are attached on two adjacent lead frame units of a lead frame such that the lead frame unit with the first chip formed thereon is rotated 180 degrees in relation to the other lead frame unit with the second semiconductor chip formed thereon. A first and second clip sets are mounted on the first and second semiconductor chips, wherein the first clip set is connected to the gate electrode of the first chip, the source electrode of the second chip, and their corresponding leads and the second clip set is connected to the gate electrode of the second chip, the source electrode of the first chip and their corresponding leads. | 2016-03-31 |
20160093560 | POWER SEMICONDUCTOR DEVICE AND THE PREPARATION METHOD - An ultrathin power semiconductor package with high thermal dissipation performance and its preparation method are disclosed. The package includes a lead frame unit with a staggered structure including an upper section and a lower section. A thin layer is attached on the surface of the lead frame unit having a plurality of contact holes on the upper section and at least one opening on the lower section. A semiconductor chip is attached on the opening on the lower section of the lead frame unit and then a plurality of metal bumps are deposited, where one metal bump is formed on each contact hole on the upper section and on each of the electrodes on the top surface of the semiconductor chip. | 2016-03-31 |
20160093561 | SEMICONDUCTOR DEVICE - To reduce a mounting area while securing a mounting strength of a semiconductor device, a power transistor includes a chip mounting portion, a semiconductor chip, a plurality of leads, and a sealing body. An outer lead portion in each of the plurality of leads includes a first portion protruding from a second side surface of the sealing body in a first direction, a second portion extending in a second direction intersecting with the first direction, and a third portion extending in a third direction intersecting with the second direction. Furthermore, a length of the third portion in the third direction of the outer lead portion is shorter than a length of the first portion in the first direction. | 2016-03-31 |
20160093562 | NON-INSULATED POWER SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME - A non-insulated power semiconductor module may include a housing, at least a pair of lead frames fixedly seated in the housing and having a plurality of power semiconductor chips mounted on surfaces thereof, and an insulation member disposed between the housing and the pair of lead frames. | 2016-03-31 |
20160093563 | BGA BALLOUT PARTITION TECHNIQUES FOR SIMPLIFIED LAYOUT IN MOTHERBOARD WITH MULTIPLE POWER SUPPLY RAIL - A microelectronic package can include a substrate and a microelectronic element. The substrate can include terminals comprising at least first power terminals and other terminals in an area array at a surface of the substrate. The substrate can also include a power plane element electrically coupled to the first power terminals. The area array can have a peripheral edge and a continuous gap between the terminals extending inwardly from the peripheral edge in a direction parallel to the surface. The terminals on opposite sides of the gap can be spaced from one another by at least 1.5 times a minimum pitch of the terminals. The power plane element can extend within the gap from at least the peripheral edge at least to the first power terminals. Each first power terminal can be separated from the peripheral edge by two or more of the other terminals. | 2016-03-31 |
20160093564 | APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE - An apparatus for a manufacturing semiconductor device including a plate member and a joint member. The apparatus includes a plate-type tool having the plate member mounted thereon, a first fixing tool and a second fixing tool having an inclined surface for abutting an upper edge of an end part in a width direction of plate member. The second fixing tool is fixed onto the plate-type tool adjacent to the end part. An ultrasonic horn applies ultrasonic vibration in the width direction of plate member while pressing the joint member toward the plate member. | 2016-03-31 |
20160093565 | PRINTING MINIMUM WIDTH FEATURES AT NON-MINIMUM PITCH AND RESULTING DEVICE - Methods for forming a semiconductor layer, such as a metal 1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a minimum pitch, determining an intervening shape between the first shape and the second shape, and designating a dummy shape within the intervening shape, wherein the dummy shape is at the minimum pitch from the first shape. | 2016-03-31 |
20160093566 | Air Gap Structure and Method - A device comprises a first protection layer over sidewalls and a bottom of a first trench in a first dielectric layer, a first barrier layer over the first protection layer, a first metal line in the first trench, a second protection layer over sidewalls and a bottom of a second trench in the first dielectric layer, a second barrier layer over the second protection layer, a second metal line in the first trench, an air gap between the first trench and the second trench and a third protection layer over sidewalls of a third trench in the first dielectric layer, wherein the first protection layer, the second protection layer and the third protection are formed of a same material. | 2016-03-31 |
20160093567 | SYSTEM, APPARATUS, AND METHOD OF INTERCONNECTION IN A SUBSTRATE - A semiconductor substrate according to some examples of the disclosure may include a substrate with a cavity in a top surface of the substrate, a plurality of cavity interconnections embedded below a bottom surface of the cavity and extending to a bottom surface of the substrate, and a plurality of side interconnections to either side of the cavity extending from the top surface of the substrate to the bottom surface of the substrate. Each of the plurality of side interconnections may include an electrically conductive stop etch layer in the same horizontal plane as the bottom of the cavity. | 2016-03-31 |
20160093568 | Semiconductor Device and Process - A metal first, via first process for forming interconnects within a metallization layer of a semiconductor device is provided. In an embodiment a conductive material is deposited and the conductive material is patterned into a conductive line and a via. A dielectric material is deposited over the conductive line and the via, and the dielectric material and the via are planarized. | 2016-03-31 |
20160093569 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a base body, an insulating layer, first contacts and a first wiring. The insulating layer is disposed above the base body. The first contacts are disposed in the insulating layer. The first contacts are in contact with the base body. The first wiring is disposed around the first contacts. The first wiring has a lower height than the first contacts have. The first wiring includes convex portions in a part of a bottom portion thereof. | 2016-03-31 |
20160093570 | SEMICONDUCTOR DEVICE - Dielectric breakdown is prevented between opposing two semiconductor chips, to improve the reliability of a semiconductor device. A first semiconductor chip has a wiring structure including a plurality of wiring layers, a first coil formed in the wiring structure, and an insulation film formed over the wiring structure. A second semiconductor chip has a wiring structure including a plurality of wiring layers, a second coil formed over the wiring structure, and an insulation film formed over the wiring structure. The first semiconductor chip and the second semiconductor chip are stacked via an insulation sheet with the insulation film of the first semiconductor chip and the insulation film of the second semiconductor chip facing each other. The first coil and the second coil are magnetically coupled with each other. Then, in each of the first and second semiconductor chips, wires and dummy wires are formed at the uppermost-layer wiring layer. | 2016-03-31 |
20160093571 | SEMICONDUCTOR PACKAGE INTERCONNECTIONS AND METHOD OF MAKING THE SAME - A semiconductor package according to some examples of the disclosure may include a base with a first redistribution layer on one side, first and second side by side die attached to the base on an opposite side from the first redistribution layer, an interposer attached to active sides of the first and second die to provide an interconnection between the first and second die, a plurality of die vias extending from the first and second die to a second redistribution layer on a surface of the package opposite the first redistribution layer, and a plurality of package vias extending through the package between the first and second redistribution layers. | 2016-03-31 |
20160093572 | INTEGRATED FAN-OUT PACKAGE WITH DUMMY VIAS - Disclosed herein is a device comprising a first redistribution layer (RDL) having first lands disposed on a bottom surface of the first RDL and active contact pads disposed on a top surface of the first RDL. The first RDL electrically connects the first lands to the active contact pads. A molding compound layer is disposed on the top surface of the first RDL. Active vias extend through the molding compound layer and are in electrical contact with the active contact pads. Dummy vias extending through the molding compound layer. Top surfaces of the active vias and top surfaces of the dummy vias are substantially planar with a top surface of the molding compound layer, and the dummy vias are electrically insulated from the active vias and the first lands. | 2016-03-31 |
20160093573 | OVERLAY MARK AND METHOD FOR FORMING THE SAME - An overlay mark applied to a LELE-type double patterning lithography (DPL) process including a first lithography step, a first etching step, a second lithography step and a second etching step in sequence is described. The overlay mark includes a first x-directional pattern and a first y-directional pattern of a previous layer, second x-directional and y-directional patterns of a current layer defined by the first lithography step, and third x-directional and y-directional patterns of the current layer defined by the second lithography step. The second x-directional patterns and the third x-directional patterns are arranged alternately beside the first x-directional pattern. The second y-directional patterns and the third y-directional patterns are arranged alternately beside the first y-directional pattern. | 2016-03-31 |
20160093574 | PHOTOLITHOGRAPHY ALIGNMENT MARK STRUCTURES, SEMICONDUCTOR STRUCTURES, AND FABRICATION METHOD THEREOF - A method is provided for fabricating a photolithography alignment mark structure. The method includes providing a substrate; thrilling a first grating, a second grating, a third grating and a fourth grating in the substrate; forming a photoresist layer on a surface of the substrate; obtaining a first alignment center along a first direction and a second alignment center along a second direction based on the first grating and the fourth grating, respectively; providing a mask plate having a fifth grating pattern and a sixth grating pattern; aligning the mask plate with the substrate by using the first alignment center as an alignment center along the first direction and the second alignment center as an alignment center along the second direction; reproducing the fifth grating pattern and the sixth grating pattern in the photoresist layer: and forming a fifth grating and a sixth grating on the substrate by removing a portion of photoresist layer. | 2016-03-31 |
20160093575 | OPTOELECTRONIC PACKAGES HAVING MAGNETIC FIELD CANCELATION - A stacked optoelectronic packaged device includes a bottom die having a top surface including bottom electrical traces and a light source die coupled to ≧1 bottom electrical traces. A first cavity die is on the bottom die. An optics die is on the first cavity die and a second cavity die on the optics die. A mounting substrate is on the second cavity die including top electrical traces. A photodetector die is optically coupled to receive light from the light source. The bottom and top electrical traces are both positioned substantially symmetrically on sides of a mirror plane so that when conducting equal and opposite currents a first magnetic field emanating from the first side and a second magnetic field emanating from the second side cancel one another to provide a reduction in magnetic flux density by more than 50% at one or more die locations on the optics die. | 2016-03-31 |
20160093576 | SEMICONDUCTOR PACKAGE AND RELATED METHOD - A semiconductor package is provided, including: a substrate having opposing first and second surfaces; a plurality of semiconductor components disposed on and electrically connected to the first surface; an encapsulant encapsulating the first surface and the semiconductor components and having at least one first groove that partitions the substrate into a plurality of package units, each of which has at least one of the semiconductor components; and a metal layer formed on the substrate and the encapsulant and encapsulating a periphery of the package units, with the second surface exposed from the metal layer, wherein the metal layer is formed along a wall surface of the first groove, to form a second groove corresponding in position to the first groove and having a metal surface. Therefore, the package units are isolated and form a multilayer isolated structure, including metal layers and air layers, and are electromagnetically shielded from one another. | 2016-03-31 |
20160093577 | SHIELDED RADIO-FREQUENCY MODULE HAVING REDUCED AREA - Shielded radio-frequency (RF) module having reduced area. In some embodiments, an RF module can include a packaging substrate configured to receive a plurality of components, and a plurality of shielding wirebonds implemented on the packaging substrate and configured to provide RF shielding functionality for one or more regions on the packaging substrate. The packaging substrate can include a first area associated with implementation of each shielding wirebond. The RF module can further include one or more devices mounted on the packaging substrate. The packaging substrate can further include a second area associated with mounting of each of the one or more devices. Each device can be mounted with respect to a corresponding shielding wirebond such that the second area associated with the device overlaps at least partially with the first area associated with the corresponding shielding wirebond. | 2016-03-31 |
20160093578 | NETWORK WITH INTEGRATED PASSIVE DEVICE AND CONDUCTIVE TRACE IN PACKAGING SUBSTRATE AND RELATED MODULES AND DEVICES - In an embodiment, an apparatus includes a packaging substrate and a die on the packaging substrate. The die includes an integrated passive device and a contact providing an electrical connection to the integrated passive device. A conductive trace of the packaging substrate is in an electrical path between the contact of the die and a ground potential. Such an integrated passive device and conductive trace can be included in a matching network configured to receive an amplified radio frequency signal from a power amplifier, for example. The packaging substrate can be, for example, a laminate substrate. | 2016-03-31 |
20160093579 | INPUT/OUTPUT TERMINATION FOR RIPPLE PREVENTION - Aspects of this disclosure relate to a termination circuit configured to mitigate crosstalk from a radio frequency (RF) input/output (I/O) path to a second I/O path, such as a digital I/O path. Such crosstalk can be due to coupling between adjacent bond wires, for example. The termination circuit can include a low impedance loss path, such as a series RC shunt circuit. According to certain embodiments, an electrostatic discharge (ESD) protection circuit can be in parallel with the termination circuit. | 2016-03-31 |
20160093580 | SEMICONDUCTOR DEVICE AND METHOD COMPRISING REDISTRIBUTION LAYERS - A method of making a semiconductor package can include forming a plurality of redistribution layer (RDL) traces disposed over active surfaces of a plurality of semiconductor die and electrically connected to contact pads on the plurality of semiconductor die. The method can include disposing an encapsulant material over the active surfaces, contacting at least four side surfaces of each of the plurality of semiconductor die, and disposed over the plurality of RDL traces. The method can also include forming a via through the encapsulant material to expose at least one of the plurality of RDL traces, forming an electrical interconnect disposed within the via and coupled to the at least one RDL trace, and singulating the plurality of semiconductor packages through the encapsulant material to leave an offset of 30-140 μm of the encapsulant material disposed around a periphery of each of the plurality of semiconductor die. | 2016-03-31 |
20160093581 | SEMICONDUCTOR DEVICE WITH A THROUGH ELECTRODE - A semiconductor device includes a through electrode penetrating a substrate such that a first end portion of the through electrode protrudes from a first surface of the substrate, a passivation layer covering the first surface of the substrate and a sidewall of the first end portion of the through electrode, a bump having a lower portion penetrating the passivation layer and coupled to the first end portion of the through electrode, and a lower metal layer disposed between the bump and the first end portion of the through electrode. The lower metal layer extends onto a sidewall of the bump and has a concave shape. | 2016-03-31 |
20160093582 | Fan Out Package Structure and Methods of Forming - An embodiment is a structure comprising a die having a pad on a surface and an encapsulant at least laterally encapsulating the die. The pad is exposed through the encapsulant. The structure further includes a first dielectric layer over the encapsulant and the die, a first conductive pattern over the first dielectric layer, and a second dielectric layer over the first conductive pattern and the first dielectric layer. The first dielectric layer and the second dielectric layer have a first opening to the pad of the die. The structure further includes a second conductive pattern over the second dielectric layer and in the first opening. The second conductive pattern adjoins a sidewall of the first dielectric layer in the first opening and a sidewall of the second dielectric layer in the first opening. | 2016-03-31 |
20160093583 | BOND PAD WITH MICRO-PROTRUSIONS FOR DIRECT METALLIC BONDING - A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (TSV) extending through the semiconductor substrate, and a copper pad electrically connected to the TSV and having a coupling side. The semiconductor device further includes a copper element that projects away from the coupling side of the copper pad. In another embodiment, a bonded semiconductor assembly comprises a first semiconductor substrate with a first TSV and a first copper pad electrically coupled to the first TSV, wherein the first copper pad has a first coupling side. The bonded semiconductor assembly further comprises a second semiconductor substrate, opposite to the first semiconductor substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side. A plurality of copper connecting elements extend between the first and second coupling sides of the first and second copper pads. | 2016-03-31 |
20160093584 | ADHESIVE COMPOSITION, ELECTRONIC-COMPONENT-MOUNTED SUBSTRATE AND - There are provided are an adhesive composition that keeps storage stability and further gives a cured product wherein metallic bonds are formed in the state that the cured product wets its components and is satisfactorily spread between the components (or parts), thereby turning excellent in adhesive property, electroconductivity, and reliability for mounting such as TCT resistance or high-temperature standing resistance; an electronic-component-mounted substrate using the same; and a semiconductor device. The adhesive composition comprises electroconductive particles (A) and a binder component (B), wherein the electroconductive particles (A) include a metal (a1) having a melting point equal to or higher than the reflow temperature and containing no lead, and a metal (a2) having a melting point lower than the reflow temperature and containing no lead, and the binder component (B) includes a thermosetting resin composition (b1) and an aliphatic dihydroxycarboxylic acid (b2). | 2016-03-31 |
20160093585 | THERMOCOMPRESSION FOR SEMICONDUCTOR CHIP ASSEMBLY - An assembly of a semiconductor chip having pads to a substrate having pads aligned to receive the semiconductor chip is provided, whereby at least one of the semiconductor chip pads and substrate pads include solder bumps. The solder bumps are deformed against the substrate pads and the semiconductor chip pads, whereby an underfill material is applied to fill the gap between the semiconductor chip and substrate. The underfill material does not penetrate between the deformed solder bumps, the semiconductor chip pads, and the substrate pads. At least one of the solder bumps have not been melted or reflowed to make a metallurgical bond between the semiconductor chip pads and the substrate pads, and at least another one of the solder bumps have been melted or reflowed to make a metallurgical bond between the semiconductor chip pads and the substrate pads. | 2016-03-31 |
20160093586 | SILVER-GOLD ALLOY BONDING WIRE - The silver-gold alloy bonding wire of the present invention includes an alloy composed of not lower than 10% and not higher than 30% of gold (Au) and not lower than 30 ppm and not higher than 90 ppm of calcium (Ca) with the remainder of silver (Ag) at purity relative to a metallic element except for elements Au and Ca of 99.99% or higher, in mass percentage; a layer enriched with oxygen (O) and calcium (Ca) formed as a surface layer on the surface of the alloy; and a gold-enriched layer formed immediately below the surface layer. | 2016-03-31 |
20160093587 | FLEXIBLE CIRCUIT LEADS IN PACKAGING FOR RADIO FREQUENCY DEVICES AND METHODS THEREOF - A packaged RF device is provided that can provide improved performance and flexibility though the use of flexible circuit leads. The RF device includes at least one integrated circuit (IC) die configured to implement the RF device. The IC die is contained inside a package. In accordance with the embodiments described herein, a flexible circuit is implemented as a lead. Specifically, the flexible circuit lead is coupled to the at least one IC die inside the package and extends to outside the package, the flexible circuit lead thus providing an electrical connection to the at least one IC die inside the package. | 2016-03-31 |
20160093588 | POWER SUPPLY ARRANGEMENT FOR SEMICONDUCTOR DEVICE - A semiconductor device includes a device die, a first power supply die, and a second power supply die different from the first power supply die. The device die includes a first circuit and a second circuit. The first power supply die is electrically coupled to the first circuit and configured to supply power for the first circuit. The second power supply die is electrically coupled to the second circuit and configured to supply power for the second circuit. The first and second power supply dies are attached to the device die, and overlap the device die in a thickness direction of the device die. | 2016-03-31 |
20160093589 | SEMICONDUCTOR DEVICE - Reduction in reliability of a semiconductor device is suppressed. A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a plurality of semiconductor chips mounted on the plurality of metal patterns. Also, the plurality of metal patterns include metal patterns MPH and MPU which face each other. In addition, a region which is provided between these metal patterns MPH and MPU and which is exposed from the plurality of metal patterns extends so as to zigzag along an extending direction of the metal pattern MPH. | 2016-03-31 |
20160093590 | Package-on-Package Structure and Method - A device comprises a top package mounted on a bottom package through a joint structure, wherein the joint structure comprises a solder ball of the top package coupled to a metal structure embedded in the bottom package and an epoxy protection layer having a first edge in direct contact with a top surface of the bottom package and a second edge surrounding a lower portion of the solder ball. | 2016-03-31 |
20160093591 | MICROELECTROMECHANICAL SYSTEM (MEMS) BOND RELEASE STRUCTURE AND METHOD OF WAFER TRANSFER FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT (3D IC) INTEGRATION - A microelectromechanical system (MEMS) bond release structure is provided for manufacturing of three-dimensional integrated circuit (3D IC) devices with two or more tiers. The MEMS bond release structure includes a MEMS sacrificial release layer which may have a pillar or post structure, or alternatively, a continuous sacrificial layer for bonding and release. | 2016-03-31 |
20160093592 | WAFER LEVEL INTEGRATION OF PASSIVE DEVICES - A semiconductor device is described that includes an integrated circuit coupled to a first semiconductor substrate with a first set of passive devices (e.g., inductors) on the first substrate. A second semiconductor substrate with a second set of passive devices (e.g., capacitors) may be coupled to the first substrate. Interconnects in the substrates may allow interconnection between the substrates and the integrated circuit. The passive devices may be used to provide voltage regulation for the integrated circuit. The substrates and integrated circuit may be coupled using metallization. | 2016-03-31 |
20160093593 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A semiconductor device includes a plurality of conductors for connecting another semiconductor device. Each conductor connects to a chip select pad within the semiconductor device through an upper vertical connection formed through an insulation layer formed on a substrate or connected to a straight vertical connection formed through the substrate and the insulation layer. The semiconductor device further includes a plurality of lower vertical connections formed through the substrate and correspondingly connecting to the chip select pads and a chip select terminal. The chip select terminal electrically connects to the die circuit of the semiconductor device while the chip select pads are electrically isolated from the die circuit. The lower vertical connections and the straight vertical connection can be arranged in two dimensions. | 2016-03-31 |
20160093594 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns. | 2016-03-31 |