13th week of 2022 patent applcation highlights part 64 |
Patent application number | Title | Published |
20220101834 | NATURAL LANGUAGE UNDERSTANDING MODEL WITH CONTEXT RESOLVER - A system and method for training a virtual assistant to recognize and learn new context for known terms is presented. The method includes receiving a natural language input, corresponding to at least one of a desired intent and a desired entity, at a natural language processor. The method involves scoring known intents based on the natural language input to generate an intent confidence score for each known intent, and scoring known entities based on the natural language input to generate an entity confidence score for each known entity. The method involves comparing the intent confidence scores and entity confidence scores to a threshold value, and determining that the natural language input does not correspond to at least one of the known intents and the known entities based on the comparing. Finally, at least one of a new intent and a new entity are determined based on the natural language input. | 2022-03-31 |
20220101835 | SPEECH RECOGNITION TRANSCRIPTIONS - An approach to correcting transcriptions of speech recognition models may be provided. A list of similar sounding phonemes from associated with the phonemes of high frequency terms may be generated for a particular node associated with a virtual assistant. An utterance may be transcribed and receive a confidence score regarding the correctness of the transcription based on audio metrics and other factors. The phonemes of the utterance can be compared to the phonemes of the high frequency terms from the list and a sounds similar score for the matching phonemes and similar sounding phonemes can be determined. If it is determined the sounds similar score for a term from the high frequency term list is above a threshold, the transcription can be replaced with the term, providing a corrected transcription. | 2022-03-31 |
20220101836 | Contextual Biasing for Speech Recognition - A method of biasing speech recognition includes receiving audio data encoding an utterance and obtaining a set of one or more biasing phrases corresponding to a context of the utterance. Each biasing phrase in the set of one or more biasing phrases includes one or more words. The method also includes processing, using a speech recognition model, acoustic features derived from the audio data and grapheme and phoneme data derived from the set of one or more biasing phrases to generate an output of the speech recognition model. The method also includes determining a transcription for the utterance based on the output of the speech recognition model. | 2022-03-31 |
20220101837 | Machine Learning System for Customer Utterance Intent Prediction - A method of operating a customer utterance analysis system includes obtaining a subset of utterances from among a first set of utterances. The method includes encoding, by a sentence encoder, the subset of utterances into multi-dimensional vectors. The method includes generating reduced-dimensionality vectors by reducing a dimensionality of the multi-dimensional vectors. Each vector of the reduced-dimensionality vectors corresponds to an utterance from among the subset of utterances. The method includes performing clustering on the reduced-dimensionality vectors. The method includes, based on the clustering performed on the reduced-dimensionality vectors, arranging the subset of utterances into clusters. The method includes obtaining labels for a least two clusters from among the clusters. The method includes generating training data based on the obtained labels. The method includes training a neural network model to predict an intent of an utterance based on the training data. | 2022-03-31 |
20220101838 | SYSTEMS AND METHODS RELATING TO BOT AUTHORING BY MINING INTENTS FROM NATURAL LANGUAGE CONVERSATIONS - A method for intent mining that includes: receiving conversation data; using an intent mining algorithm to automatically mine intents from the conversation data; and uploading the mined intents into the conversational bot. The intent mining algorithm may include: analyzing utterances of the conversation data to identify intent-bearing utterances; analyzing the identified intent-bearing utterances to identify candidate intents; selecting salient intents from the candidate intents; grouping the selected salient intents into salient intent groups in accordance with a degree of semantic similarity; for each of the salient intent groups, selecting one of the salient intents as the intent label and designating the others as the intent alternatives; and associating the intent-bearing utterances with the salient intent groups via determining a degree of semantic similarity between the candidate intents present in the intent-bearing utterance and the intent alternatives within each group. | 2022-03-31 |
20220101839 | SYSTEMS AND METHODS RELATING TO BOT AUTHORING BY MINING INTENTS FROM CONVERSATION DATA VIA INTENT SEEDING - A method for authoring a conversational bot including: receiving conversation data; receiving seed intent data that comprises seed intents having a seed intent label and sample intent-bearing utterances; using an intent mining algorithm to mine the conversation data to determine new utterances to associate with the seed intent; augmenting the seed intent data to include the mined new utterances associated with the seed intents; and uploading the augmented seed intent data into the conversation bot. The intent mining algorithm may include: identifying intent-bearing utterances; identifying candidate intents; for each of the seed intents, identifying seed intent alternatives from the sample intent-bearing utterances; associating the intent-bearing utterances from the conversation data with the seed intents via determining a degree of semantic similarity between the candidate intents of the intent-bearing utterances and the seed intent alternatives. | 2022-03-31 |
20220101840 | ASSESSMENT OF THE QUALITY OF A COMMUNICATION SESSION OVER A TELECOMMUNICATION NETWORK - Apparatus ( | 2022-03-31 |
20220101841 | SPEECH RECOGNITION - A speech recognition system comprises: an input, for receiving an input signal from at least one microphone; a first buffer, for storing the input signal; a noise reduction block, for receiving the input signal and generating a noise reduced input signal; a speech recognition engine, for receiving either the input signal output from the first buffer or the noise reduced input signal from the noise reduction block; and a selection circuit for directing either the input signal output from the first buffer or the noise reduced input signal from the noise reduction block to the speech recognition engine. | 2022-03-31 |
20220101842 | SYSTEMS, METHODS, AND APPARATUSES FOR IMPROVING PERFORMANCE OF EXECUTING A WORKFLOW OPERATION - A voice controlled apparatus for performing a workflow operation is described. The voice controlled apparatus can include a microphone, a speaker, and a processor. In some examples, the voice controlled apparatus can generate, via the speaker, a voice prompt associated with a task of a workflow and identify, via the microphone, a voice response received from a worker. In this regard, the voice prompt and the voice response can be a part of a voice dialogue. Further, the processor of the voice controlled apparatus can identify a performance status associated with the execution of the task, before providing a next voice prompt subsequent to the voice prompt. In this aspect, the performance status can be identified based on analyzing the voice dialogue using a machine learning model. Furthermore, the voice controlled apparatus can generate a message including a suggestion to improve the performance status of the task. | 2022-03-31 |
20220101843 | MESSAGE FILTERING BASED ON DYNAMIC VOICE-ACTIVATED RULES - Embodiments include methods, devices, systems, and non-transitory process-readable storage media for voice-activated message filtering rule generation. Some embodiments may include receiving a spoken command from a communication device, parsing the spoken command to identify an element of the spoken command, generating a message rule based on the identified element of the spoken command, determining whether the generated message rule has been met, and sending a message to the communication device in response to determining that the message rule has been met. | 2022-03-31 |
20220101844 | CONFIGURABLE CONVERSATION ENGINE FOR EXECUTING CUSTOMIZABLE CHATBOTS - A conversation engine performs conversations with users using chatbots customized for performing a set of tasks that can be performed using an online system. The conversation engine loads a chatbot configuration that specifies the behavior of a chatbot including the tasks that can be performed by the chatbot, the types of entities relevant to each task, and so on. The conversation may be voice based and use natural language. The conversation engine may load different chatbot configurations to implement different chatbots. The conversation engine receives a conversation engine configuration that specifies the behavior of the conversation engine across chatbots. The system may be a multi-tenant system that allows customization of the chatbots for each tenant. | 2022-03-31 |
20220101845 | VOICE COMMAND EXECUTION - Embodiments of the present invention provide a computer system a computer program product, and a method that comprises analyzing a received voice command by identifying a plurality of contextual factors associated with at least one user in a plurality of users using a natural language processing algorithm; dynamically identifying the at least one user in the plurality of users based on an analysis of the identified contextual factors associated with the received voice command; transmitting the received voice command to another computing device within a plurality of computing devices associated with another user in the plurality of users; and generating a line of communication between the plurality of computing devices based on a correlation between a summation of a plurality of security factors and a predetermined threshold of risk associated with authenticating an identity of each user within the plurality of users. | 2022-03-31 |
20220101846 | ELECTRONIC DEVICE FOR IDENTIFYING COMMAND INCLUDED IN VOICE AND METHOD OF OPEARATING THE SAME - An electronic device includes a communication module, a plurality of microphones, and a processor. The processor is configured to identify a position of a sound source based on a voice received through the plurality of microphones, identify whether the position of the sound source is included in a first zone between the electronic device and an access point that transmits and receives a communication signal with the electronic device, identify whether the voice has been uttered by a user based on a comparison between the communication signal and a preset communication signal, when the position of the sound source is included in the first zone, and determine whether to execute a command included in the voice based on the identification of whether the voice has been uttered by the user. | 2022-03-31 |
20220101847 | VOICE CONTROL IN A HEALTHCARE FACILITY - Systems for voice control of medical devices in a healthcare facility are disclosed herein. The systems employ continuous speech processing software, voice recognition software, natural language processing software, and other software to permit voice control of the medical devices. Systems are also provided for distinguishing which medical device from among multiple medical devices in a patient room is the particular medical device to be controlled by voice input from a caregiver or a patient. | 2022-03-31 |
20220101848 | MISSED UTTERANCE RESOLUTIONS - An example computing device can include a processing resource and a memory resource storing instructions thereon, the instructions executable by the processing resource to: log commands directed to the computing device, identify missed utterances from the logged commands, extract features from the missed utterances, wherein the features include an entity and a key phrase associated with the missed utterances, generate a list of the missed utterances based on a priority associated with the features associated with each of the missed utterances, and provide a portion of the missed utterances to a service for resolution, wherein the portion of the missed utterances are above a threshold priority within the list of the missed utterances. | 2022-03-31 |
20220101849 | VOICE CHAT APPARATUS, VOICE CHAT METHOD, AND PROGRAM - Provided are a voice chat apparatus, a voice chat method, and a program that achieve appropriate control on whether or not to provide text obtained as a result of voice recognition on voice in voice chat. A voice receiving unit receives voice in voice chat. A text acquiring unit acquires text obtained as a result of voice recognition on the voice received by the voice receiving unit. A transmission control unit controls, on a basis of whether or not display of a voice recognition result is performed in a voice chat system that is a communication destination, whether or not to transmit text data including the text acquired by the text acquiring unit to the communication destination. | 2022-03-31 |
20220101850 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM - The present technology relates to an information processing device, an information processing method, and a program that enable intuitive voice operation. | 2022-03-31 |
20220101851 | LOCALLY DISTRIBUTED KEYWORD DETECTION - In one aspect, a playback device includes at least one microphone configured to detect a voice input and generate sound input data. The playback device detects a first command keyword in the detected sound and, in response, makes a first determination, via a first local natural language unit (NLU), whether the input sound data includes at least one keyword within a first predetermined library of keywords. The playback device receives an indication of a second determination made by a second NLU that the input sound data includes at least one keyword from a second predetermined library of keywords. The playback device compares the results of the first determination and the second determination and, based on the comparison, foregoes further processing of the input sound data. | 2022-03-31 |
20220101852 | CONVERSATION SUPPORT DEVICE, CONVERSATION SUPPORT SYSTEM, CONVERSATION SUPPORT METHOD, AND STORAGE MEDIUM - A speech recognition portion generates utterance text representing utterance content by performing a speech recognition process on speech data. A topic analysis portion identifies a word or a phrase of a prescribed topic and a numerical value having a prescribed positional relationship with the word or the phrase from the utterance text. A display processing portion causes a display portion to display display information in which the numerical value or a numerical value derived from the numerical value is shown as a display value in association with the utterance text. | 2022-03-31 |
20220101853 | ELECTRONIC APPARATUS AND METHOD OF CONTROLLING THE SAME - An electronic apparatus and a controlling method thereof are provided. The electronic apparatus includes a communication interface and a processor configured to: receive one or more speech recognition requests from at least one of a plurality of external apparatuses, each of the one or more speech recognition requests including a start command recognized by the at least one of the plurality of external apparatuses; identify whether a number of the one or more speech recognition requests within a time section exceeds a predetermined threshold; control speech recognition to be performed based on the number of the one or more speech recognition requests not exceeding the predetermined threshold; and transmit a result of the speech recognition to the at least one of the plurality of external apparatuses. | 2022-03-31 |
20220101854 | DYNAMICALLY ASSIGNING MULTI-MODALITY CIRCUMSTANTIAL DATA TO ASSISTANT ACTION REQUESTS FOR CORRELATING WITH SUBSEQUENT REQUESTS - Implementations set forth herein relate to an automated assistant that uses circumstantial condition data, generated based on circumstantial conditions of an input, to determine whether the input should affect an action been initialized by a particular user. The automated assistant can allow each user to manipulate their respective ongoing action without necessitating interruptions for soliciting explicit user authentication. For example, when an individual in a group of persons interacts with the automated assistant to initialize or affect a particular ongoing action, the automated assistant can generate data that correlates that individual to the particular ongoing action. The data can be generated using a variety of different input modalities, which can be dynamically selected based on changing circumstances of the individual. Therefore, different sets of input modalities can be processed each time a user provides an input for modifying an ongoing action and/or initializing another action. | 2022-03-31 |
20220101855 | SPEECH AND AUDIO DEVICES - An example computing device includes a display, and a parametric speaker array operatively connected to the display. The parametric speaker array is to focus audio output to a localized area adjacent to the display. A camera is operatively connected to the display. The camera is set to capture lip movements of a user in the localized area. A processor is operatively connected to the display. The processor is to convert the lip movements into text and speech. | 2022-03-31 |
20220101856 | SYSTEM AND METHOD FOR DISAMBIGUATING A SOURCE OF SOUND BASED ON DETECTED LIP MOVEMENT - The present teaching relates to method, system, medium, and implementations for detecting a source of speech sound in a dialogue. A visual signal acquired from a dialogue scene is first received, where the visual signal captures a person present in the dialogue scene. A human lip associated with the person is detected from the visual signal and tracked to detect whether lip movement is observed. If lip movement is detected, a first candidate source of sound is generated corresponding to an area in the dialogue scene where the lip movement occurred. | 2022-03-31 |
20220101857 | PERSONAL ELECTRONIC CAPTIONING BASED ON A PARTICIPANT USER'S DIFFICULTY IN UNDERSTANDING A SPEAKER - Providing, using a computer, personalized captioning in response to a user having difficulty in understanding another participant speaking. Detecting, at a computer, the user having difficulty in understanding another participant speaking, or alternatively, receiving, at the computer, a communication from a user indicating that the user requests assistance to understand speech of a particular participant in an electronic group meeting. The speech of the particular participant is identified, and a speech input is captured from the particular participant in the electronic group meeting. The captured speech of the particular participant is transcribed, and an audio assistance output is generated for communication to the user. The audio assistance output is communicated to a device of the user. | 2022-03-31 |
20220101858 | SYSTEM AND METHOD FOR THE CREATION AND PLAYBACK OF SOUNDTRACK-ENHANCED AUDIOBOOKS - A synchronised soundtrack for an audiobook. The soundtrack has a soundtrack timeline having one or more audio regions that are configured for synchronised playback with corresponding narration regions in the audiobook playback timeline. Each audio region having a position along the soundtrack timeline that is dynamically adjustable to maintain synchronization of the audio regions of the soundtrack with their respective narration regions in the audiobook based on a narration speed variable indicative of the playback narration speed of the audiobook. | 2022-03-31 |
20220101859 | SPEAKER RECOGNITION BASED ON SIGNAL SEGMENTS WEIGHTED BY QUALITY - This speech processing device is provided with: a contribution degree estimation means which calculates a contribution degree representing a quality of a segment of the speech signal; and a speaker feature calculation means which calculates a feature from the speech signal, for recognizing attribute information of the speech signal, using the contribution degree as a weight of the segment of the speech signal. | 2022-03-31 |
20220101860 | AUTOMATED SPEECH GENERATION BASED ON DEVICE FEED - Computer-generated speech based on a device feed includes generating a corpus for robotic use by receiving first information representative of a user's speech in different environments at different times and second information representative of environmental conditions of different locations at the different times. The first and second information of corresponding different environments and different locations for each of the different times is combined with third information received from external data sources. A plurality of annotated combined datasets including the first information, the second information, and the third information is generated for each of the different times in a repository. The plurality of annotated combined datasets is correlated to create training data that is subsequently processed using a predetermined machine learning model. A correlation among spoken tone associated with a contextual situation based on skills of the user is identified in the training data and used to update the corpus. | 2022-03-31 |
20220101861 | SELECTIVE REQUESTS FOR AUTHENTICATION FOR VOICE-BASED LAUNCHING OF APPLICATIONS - Systems, methods, and computer-readable media are disclosed for systems and methods for selective requests for authentication for voice-based launching of applications. Example methods may include receiving first audio data representing an utterance, determining that the device is in a first operating mode when the audio data was received, determining that the device is in a locked state when the audio data is received, and receiving, from a remote system, a command to display information based at least on part on the audio data. Certain methods may include receiving an indication that the utterance was spoken by a user authorized to access the information while in the first operating mode and the locked state, and causing presentation of the information by the device. | 2022-03-31 |
20220101862 | ENCODING AND DECODING METHOD, DECODING METHOD, APPARATUSES THEREFOR AND PROGRAM - A technique is provided that can reduce degradation of the sound quality due to a tandem connection of paired coding and decoding, and can reduce the operation processing amount and the required memory amount of a multipoint control unit. At a terminal of a communication network having a larger communication capacity in multipoint connection between terminals in a plurality of communication networks (e.g., a fixed phone line and a mobile phone line) having different communication capacities, a multichannel coding including a monaural coding scheme of the communication network having the smaller communication capacity is performed on the coding side, whereas decoding of a multichannel-coded code of one point, decoding of a monaural-coded code of one point, or decoding of a monaural-coded code of a plurality of points is performed on the decoding side in accordance with the input code. | 2022-03-31 |
20220101863 | ANALOG-TO-DIGITAL CONVERTER AND METHOD - An analogue-to-digital converter (ADC), comprising: an adaptive whitening filter configured to filter an analogue input signal and output a whitened analogue input signal; a first converter configured to receive said whitened analogue input signal and output a whitened digital signal; a controller configured to adapt the whitening filter based on the received analogue input signal. | 2022-03-31 |
20220101864 | TRAINING GENERATIVE ADVERSARIAL NETWORKS TO UPSAMPLE AUDIO - Introduced here are approaches to training and then employing computer-implemented models designed to upsample discrete audio signals to higher sampling rates. Assume, for example, that a media production platform obtains a first discrete signal at a relatively low sampling rate. The relatively low sampling frequency may make the first discrete audio signal unsuitable for inclusion in media compilations, so the media production platform may attempt to improve its quality through upsampling. To accomplish this, the media production platform can apply a transform to the first discrete signal to produce a first magnitude spectrogram. Then, the media production platform can apply a computer-implemented model to the first magnitude spectrogram to produce a second magnitude spectrogram. Thereafter, the media production platform can apply an inverse transform to the second magnitude spectrogram to create a second discrete signal that has a higher sampling rate than the first discrete audio signal. | 2022-03-31 |
20220101865 | AUDIO ENCODER AND DECODER FOR INTERLEAVED WAVEFORM CODING - There is provided methods and apparatuses for decoding and encoding of audio signals. In particular, a method for decoding includes receiving a waveform-coded signal having a spectral content corresponding to a subset of the frequency range above a cross-over frequency. The waveform-coded signal is interleaved with a parametric high frequency reconstruction of the audio signal above the cross-over frequency. In this way an improved reconstruction of the high frequency bands of the audio signal is achieved. | 2022-03-31 |
20220101866 | AUDIO ENCODER WITH A SIGNAL-DEPENDENT NUMBER AND PRECISION CONTROL, AUDIO DECODER, AND RELATED METHODS AND COMPUTER PROGRAMS - An audio encoder for encoding audio input data has: a preprocessor for preprocessing the audio input data to obtain audio data to be coded; a coder processor for coding the audio data to be coded; and a controller for controlling the coder processor so that, depending on a first signal characteristic of a first frame of the audio data to be coded, a number of audio data items of the audio data to be coded by the coder processor for the first frame is reduced compared to a second signal characteristic of a second frame, and a first number of information units used for coding the reduced number of audio data items for the first frame is stronger enhanced compared to a second number of information units for the second frame. | 2022-03-31 |
20220101867 | CONCEPT FOR AUDIO ENCODING AND DECODING FOR AUDIO CHANNELS AND AUDIO OBJECTS - Audio encoder for encoding audio input data to obtain audio output data includes an input interface for receiving a plurality of audio channels, a plurality of audio objects and metadata related to one or more of the plurality of audio objects; a mixer for mixing the plurality of objects and the plurality of channels to obtain a plurality of pre-mixed channels, each pre-mixed channel including audio data of a channel and audio data of at least one object; a core encoder for core encoding core encoder input data; and a metadata compressor for compressing the metadata related to the one or more of the plurality of audio objects, wherein the audio encoder is configured to operate in at least one mode of the group of two modes. | 2022-03-31 |
20220101868 | AUDIO ENCODER WITH A SIGNAL-DEPENDENT NUMBER AND PRECISION CONTROL, AUDIO DECODER, AND RELATED METHODS AND COMPUTER PROGRAMS - An audio encoder for encoding audio input data has: a preprocessor for preprocessing the audio input data to obtain audio data to be coded; a coder processor for coding the audio data to be coded; and a controller for controlling the coder processor so that, depending on a first signal characteristic of a first frame of the audio data to be coded, a number of audio data items of the audio data to be coded by the coder processor for the first frame is reduced compared to a second signal characteristic of a second frame, and a first number of information units used for coding the reduced number of audio data items for the first frame is stronger enhanced compared to a second number of information units for the second frame. | 2022-03-31 |
20220101869 | System and Method for Hierarchical Audio Source Separation - The audio processing system includes a memory to store a neural network trained to process an audio mixture to output estimation of at least a subset of a set of audio sources present in the audio mixture. The audio sources are subject to hierarchical constraints enforcing a parent-children hierarchy on the set of audio sources, such that a parent audio source in includes a mixture of its one or multiple children audio sources. The subset includes a parent audio source and at least one of its children audio sources. The system further comprises a processor to process a received input audio mixture using the neural network to estimate the subset of audio sources and their mutual relationships according to the parent-children hierarchy. The system further includes an output interface configured to render the extracted audio sources and their mutual relationships. | 2022-03-31 |
20220101870 | NOISE FILTERING AND VOICE ISOLATION DEVICE AND METHOD - A method of isolating voice signal from a user, the method including capturing a first audio signal by a first microphone; capturing a second audio signal by a second microphone, the second microphone located at a distance from the first microphone; transmitting the first audio signal from the first microphone and the second audio signal from the second microphone to a processor; comparing, by the processor, the first audio signal and the second audio signal with a time delay corresponding to the distance between the first microphone and the second microphone; and finding a commonality between the first audio signal and the second audio signal if the first audio signal and the second audio signal are substantially different. | 2022-03-31 |
20220101871 | LIVE STREAMING CONTROL METHOD AND APPARATUS, LIVE STREAMING DEVICE, AND STORAGE MEDIUM - Embodiments of the present application relate to the technical field of Internet, and provide a live streaming control method and apparatus, a live streaming device, and a storage medium. Voice information of a live streamer is obtained, and the voice information is analyzed and processed, so that according to the processing result, a virtual image in a live streaming screen is controlled to execute an action matching the voice information, so as to improve the precision of controlling the virtual image and enable the virtual image in the live streaming screen and the live streaming content of the live streamer to have a high matching degree. | 2022-03-31 |
20220101872 | UPSAMPLING OF AUDIO USING GENERATIVE ADVERSARIAL NETWORKS - Introduced here are approaches to training and then employing computer-implemented models designed to upsample discrete audio signals to higher sampling rates. Assume, for example, that a media production platform obtains a first discrete signal at a relatively low sampling rate. The relatively low sampling frequency may make the first discrete audio signal unsuitable for inclusion in media compilations, so the media production platform may attempt to improve its quality through upsampling. To accomplish this, the media production platform can apply a transform to the first discrete signal to produce a first magnitude spectrogram. Then, the media production platform can apply a computer-implemented model to the first magnitude spectrogram to produce a second magnitude spectrogram. Thereafter, the media production platform can apply an inverse transform to the second magnitude spectrogram to create a second discrete signal that has a higher sampling rate than the first discrete audio signal. | 2022-03-31 |
20220101873 | TECHNIQUES FOR PROVIDING FEEDBACK ON THE VERACITY OF SPOKEN STATEMENTS - Embodiments of the present disclosure set forth a computer-implemented method comprising detecting a speech portion included in a first auditory signal generated by a speaker, determining that the speech portion comprises a factual statement, comparing the factual statement with a first fact included in a first data source, determining, based on comparing the factual statement with the first fact, a fact truthfulness value, and providing a response signal that indicates the fact truthfulness value. | 2022-03-31 |
20220101874 | READ HEAD STRESS REDUCTION - Systems and methods are disclosed for dynamically adjusting parameters used during a read operation to reduce stress on a read head. In certain embodiments, an apparatus may comprise a read head configured to read data stored to a data storage medium, and a control circuit that controls a parameter of the read head influencing the read head's ability to accurately read data. The control circuit may be configured to extend the working lifespan of the read head by monitoring a read performance of the read head, and adjusting the parameter to reduce the read performance when the read performance is greater than a first threshold. | 2022-03-31 |
20220101875 | READ HEAD STRESS REDUCTION - Systems and methods are disclosed for dynamically adjusting parameters used during a read operation to reduce stress on a read head. In certain embodiments, an apparatus may comprise a read head configured to read data stored to a data storage medium, and a control circuit that controls a parameter of the read head influencing the read head's ability to accurately read data. The control circuit may be configured to extend the working lifespan of the read head by monitoring a read performance of the read head, and adjusting the parameter to reduce the read performance when the read performance is greater than a first threshold. | 2022-03-31 |
20220101876 | MANUFACTURING METHOD OF DISK-DRIVE SUSPENSION AND MANUFACTURING APPARATUS OF DISK-DRIVE SUSPENSION - An adhesive reactive to ultraviolet rays is applied to an actuator mounting portion of a suspension. An electrical conducting material is applied to a conductor and the like of the actuator mounting portion. When the adhesive is irradiated with ultraviolet rays, the viscosity of the adhesive is increased. A piezoelectric element is placed on the adhesive the viscosity of which is increased. Thereafter, the adhesive and the electrical conducting material are heated, whereby the adhesive and the electrical conducting material are cured. | 2022-03-31 |
20220101877 | MAGNETIC-DISK GLASS SUBSTRATE, MAGNETIC-DISK GLASS SUBSTRATE INTERMEDIATE, AND METHOD FOR MANUFACTURING MAGNETIC-DISK GLASS SUBSTRATE - A magnetic-disk glass substrate contains an alkaline earth metal component as a glass composition and includes a pair of main surfaces, and an outer circumferential side edge surface that is a mirror surface. The outer circumferential side edge surface includes a surface having a roughness percentage of 40% or more and 68% or less when a bearing ratio of a roughness cross-sectional area is 50% in a bearing ratio curve of roughness cross-sectional areas obtained when a surface roughness of the outer circumferential side edge surface obtained after the outer circumferential side edge surface is etched by 2.5 μm is measured. A glass transition point of the glass composition that constitutes the magnetic-disk glass substrate is 700° C. or more. The glass composition that constitutes the magnetic-disk glass substrate is alkali-free glass. | 2022-03-31 |
20220101878 | HOLOGRAM RECORDING COMPOSITION, HOLOGRAM RECORDING MEDIUM, HOLOGRAM, AND OPTICAL DEVICE AND OPTICAL COMPONENT USING SAME - To provide a hologram recording composition capable of further improving diffraction characteristics. | 2022-03-31 |
20220101879 | Laser Feedback Suppressor for Heat-Assisted Magnetic Recording - A recording head includes a channel waveguide that delivers light to a media-facing surface. A near-field transducer (NFT) is at an end of the channel waveguide and proximate to the media-facing surface. A laser including an active region has a longitudinal axis corresponding to a propagation direction of the channel waveguide. The active region includes a back facet and a front facet proximate the NFT. The front facet has a surface shape configured to suppress back reflection of the light. | 2022-03-31 |
20220101880 | WRITE-A-MOVIE: UNIFYING WRITING AND SHOOTING - A method and device for implementing Write-A-Movie technology. The method includes: obtaining a screenplay of a movie; generating, according to the screenplay, an action list by performing natural language processing (NLP) on the screenplay, the action list comprising a plurality of actions with attributes, the attributes of each action including a subject, a predicate, and a location of the action; rendering, according to the action list, three-dimensional (3D) data in 3D scenes of the movie, the 3D data reflecting, for each action, the subject performing the action at the location in a corresponding 3D scene; determining camera sequence of cameras for shooting two-dimensional (2D) frames in the 3D scenes by performing an auto-cinematography optimization process; and generating a 2D video of the movie by combining the 2D frames shot by the cameras based on the determined camera sequence. | 2022-03-31 |
20220101881 | EXPERIENCE ACQUISITION SUPPORT APPARATUS - An experience acquisition support apparatus that supports acquisition of an experience through a vehicle includes circuitry that sets a destination and a travel route of the vehicle to be suggested to a first user. While the vehicle is operating in a trip mode in which the destination and the travel route are set, the circuitry notifies a first mobile terminal of the first user of a second user and sends information on the second user to the first mobile terminal such that the first user can interact with the second user having a second mobile terminal that is in the trip mode within a specified range around the first mobile terminal. The circuitry generates a video file, which can be browsed by the second user and the like, from videos captured by cameras of the vehicle. | 2022-03-31 |
20220101882 | VIDEO FRAMING BASED ON DEVICE ORIENTATION - A video may include visual content having a progress length. A user may interact with a mobile device to set framings of the visual content at moments within the progress length. The framings of the visual content may be provided to a video editing application. The video editing application may utilize the framings set via the mobile device to provide preliminary framings of the visual content at the moments within the progress length. | 2022-03-31 |
20220101883 | MASKING IN VIDEO STREAM - Methods and devices for combining a mask with a selectively progressing video stream may include receiving a selection of at least one mask with a mask zone that obscures at least a portion of the video stream. The methods and devices may include receiving a selection to emplace the at least one mask at a first location within the video stream. The methods and devices may include receiving a selection to enable a tracking icon to move the at least one mask to a second location within the video stream while the video stream progresses. The methods and devices may include generating a combined output of the video stream and the selective emplacement and movement of the at least one mask during the video stream progression. | 2022-03-31 |
20220101884 | VIDEO EDITING EQUIPMENT - Video editing equipment acquires videos captured by an in-vehicle camera and an outside camera during movement of a vehicle, acquires driving state information by a driver and emotional state-related information of the driver or a passenger during the movement of the vehicle, determines the first degree of action indicative of the influence of the element other than the interaction with the person on an experience of the driver or the passenger and the second degree of action indicative of the influence of the interaction with the person on the experience of the driver or the passenger based on the driving state information and the emotional state-related information, identifies plural highlight portions in the videos based on the first degree of action and the second degree of action, and edits the videos on the basis of the plural highlight portions. | 2022-03-31 |
20220101885 | METHODS, DEVICES, AND SYSTEMS FOR VIDEO SEGMENTATION AND ANNOTATION - Methods, devices, and systems for segmenting and annotating videos for analysis are disclosed. A user identifies specific moments of the video that provide a teachable moment. A pre-context and a post-context portion of the video surrounding the identified moment are used to create a tile video. One or more tile videos are compiled in a user-defined order to generate a weave video with a specific focus or theme. The generated weave video is shared with one or more users and can be annotated to facilitate teaching and/or discussion. | 2022-03-31 |
20220101886 | STRUCTURE FOR FACILITATING HARD DISK MAINTENANCE AND METHOD FOR HARD DISK MAINTENANCE - A structure for facilitating hard disk maintenance comprises a housing, a hard disk bracket, a hard disk backplane, a hard disk, and a hard disk mounting assembly. The hard disk bracket is provided at a front end and a rear end of the housing. The hard disk backplane connects to a bottom of the housing and the hard disk mounting assembly. The hard disk mounting assembly connects to the hard disk bracket. The hard disk backplane is further provided with a hard disk interface, and the hard disk is also connected to the hard disk interface. | 2022-03-31 |
20220101887 | MEMORY INTERCONNECTION ARCHITECTURE SYSTEMS AND METHODS - The systems and methods are configured to efficiently and effectively include processing capabilities in memory. In one embodiment, a processing in memory (PIM) chip a memory array, logic components, and an interconnection network. The memory array is configured to store information. In one exemplary implementation the memory array includes storage cells and array periphery components. The logic components can be configured to process information stored in the memory array. The interconnection network is configured to communicatively couple the logic components. The interconnection network can include interconnect wires, and a portion of the interconnect wires are located in a metal layer area that is located above the memory array. | 2022-03-31 |
20220101888 | SEMICONDUCTOR MEMORY DEVICE, PROCESSING SYSTEM INCLUDING THE SAME AND POWER CONTROL CIRCUIT FOR THE SAME - A semiconductor memory device may include a plurality of memory cells wherein identifiers may be provided to the memory cells, The semiconductor memory device may include a first circuit, a second circuit and a power control circuit. The first circuit may include a first power terminal and a second power terminal. The second circuit may include a third terminal and a fourth terminal, The power control circuit may be configured to apply a first power voltage or a ground voltage to the first power terminal and to apply the ground voltage to the second power terminal based on the identifiers. | 2022-03-31 |
20220101889 | METHOD OF RESETTING STORAGE DEVICE, STORAGE DEVICE PERFORMING THE SAME AND DATA CENTER INCLUDING THE SAME - In a method of resetting a storage device, an internal power supply voltage is generated based on an external power supply voltage. A first reset control signal that is activated when a level of the internal power supply voltage is higher than a reference level. A second reset control signal that is activated after a power-on of the storage device is completed or deactivated after a predetermined delay time from when the external power supply voltage is turned off. A final reset control signal is generated based on the first reset control signal and the second reset control signal. The final reset control signal is activated when at least one of the first and second reset control signals is activated. After the external power supply voltage is turned off, a reset operation is performed when the final reset control signal is activated. | 2022-03-31 |
20220101890 | MEMORY DEVICE, SENSE AMPLIFIER AND METHOD FOR MISMATCH COMPENSATION - A memory device that includes a first memory cell, a second memory cell and a sense amplifier. The sense amplifier includes a first branch and a second branch and are configured to output a first voltage and a second voltage to the first memory and the second memory, respectively in a trimming operation. A first clamp device of the sense amplifier includes a first clamp transistor and a plurality of first trimming transistors that are coupled to the first clamp transistor in parallel. The gate terminals of the first clamp transistor and the plurality of first trimming transistors are biased by a fixed clamp voltage. Each of the plurality of first trimming transistors is selectively conducted to compensate a mismatch between the first voltage and the second voltage. | 2022-03-31 |
20220101891 | BIASING ELECTRONIC COMPONENTS USING ADJUSTABLE CIRCUITRY - Embodiments relate to improving the biasing of active electronic components such as, for example, sense amplifiers. Embodiments include an adjustable bias signal generator that receives a reference signal as an input and generates a corresponding bias signal as an output. The adjustable bias signal generator may comprise a voltage driver and capacitor divider circuitry. In some embodiments, the capacitor divider circuitry is configurable by selecting specific capacitor dividers using a digital code. In other embodiments, the voltage driver is adjustable by applying different trim settings to tune the output of the voltage driver. The voltage driver may be temperature compensated by multiplexing different trim settings that correspond to different temperatures. | 2022-03-31 |
20220101892 | Amplifier Offset Cancelation - An amplifier system includes a differential amplifier and a calibration circuit. In response to a calibration operation, the calibration circuit generates a calibration value based on a test output signal generated by the differential amplifier circuit using a test input signal. The calibration value may be used to adjust loading of internal nodes of the differential amplifier circuit to compensate for imbalance in the differential amplifier circuit resulting from variation in manufacturing. By compensating for the imbalance, the offset of the differential amplifier may be reduced, allowing resolution of smaller differential voltages, thereby improving the performance of circuits employing the differential amplifier circuit. | 2022-03-31 |
20220101893 | MEMORY CHIP, MEMORY CONTROLLER AND OPERATING METHOD OF THE MEMORY CHIP - A memory chip, a memory controller, and an operating method of the memory chip are provided. The memory chip includes a plurality of pins; and an interface circuit configured to receive a swap command set from a memory controller through the plurality of pins, obtain a swap command and a swap address from the swap command set, generate a swap enable signal based on the swap command and the swap address, and swap and output a data signal according to the swap enable signal. | 2022-03-31 |
20220101894 | MEMORY DEVICE INCLUDING MULTIPLE MEMORY CHIPS AND DATA SIGNAL LINES AND A METHOD OF OPERATING THE MEMORY DEVICE - An operating method of a memory device includes selecting a receiver from a plurality of receivers of each memory chip of a plurality of memory chips included in the memory device as a first receiver. The plurality of memory chips share a plurality of data signal lines, each memory chip includes a plurality of on-die termination (ODT) resistors, and the plurality of ODT resistors are respectively connected to the plurality of receivers of each memory chip. The method further includes setting each ODT resistor which is connected to a first receiver to a first resistance value, setting ODT resistors which are connected to receivers which are not first receivers to a second resistance value, and setting an amplification strength of an equalizer circuit of each first receiver by performing training operations. Each data signal line of the plurality of data signal lines is respectively connected to a first receiver. | 2022-03-31 |
20220101895 | MEMORY DEVICE SUPPORTING DBI INTERFACE AND OPERATING METHOD OF MEMORY DEVICE - A memory device includes a memory cell array, a page buffer, a control logic circuit, a plurality of input/output pins, a data bus inversion (DBI) pin, and an interface circuit. The page buffer is connected to the memory cell array. The control logic circuit is configured to control an operation of the memory cell array. The plurality of input/output pins receive a plurality of data signals from the controller. The DBI pin receives a DBI signal from the controller. The interface circuit count a first number of bits having a logic value of 1 and a second number of bits having a logic value of 0 from the data signals and the DBI signal and provide the data signals to the page buffer or the control logic circuit based on the first number and the second number. | 2022-03-31 |
20220101896 | DATA STRUCTURES WITH MULTIPLE READ PORTS - A memory structure having 2 | 2022-03-31 |
20220101897 | PROGRAMMABLE LOGIC CIRCUIT, INFORMATION PROCESSING APPARATUS, AND NON-TRANSITORY COMPUTER READABLE MEDIUM - A programmable logic circuit includes multiple logic blocks that are connected communicatively, wherein multiple modules are reconfigured in any of the logic blocks, and wherein the modules include a first module that is being executed and a second module that is not being executed, and start of execution of the second module is delayed from a start time point of execution of the first module so as to obtain a state in which a first time at which the first module accesses a memory does not overlap a second time at which the second module accesses the memory. | 2022-03-31 |
20220101898 | SYSTEMS AND METHODS INVOLVING WRITE TRAINING TO IMPROVE DATA VALID WINDOWS - Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system. | 2022-03-31 |
20220101899 | DECODE CIRCUITRY COUPLED TO A MEMORY ARRAY - In an example, an apparatus includes a memory array in a first region and decode circuitry in a second region separate from a semiconductor. The decode circuitry is coupled to an access line in the memory array. | 2022-03-31 |
20220101900 | NON-VOLATILE MEMORY DEVICE, CONTROLLER AND MEMORY SYSTEM - A non-volatile memory device is provided. The non-volatile memory device includes a clock pin, a clock signal being received from a controller through the clock pin; a first input/output pin; a second input/output pin, data being received from the controller in synchronization with the clock signal through the second input/output pin; a command/address buffer configured to operate at a first operating speed and buffer a command and an address received through the first input/output pin in synchronization with the clock signal; a memory cell array including a plurality of memory cells; and a control logic configured to control operations with respect to the plurality of memory cells, based on the command and the address buffered in the command/address buffer. | 2022-03-31 |
20220101901 | MEMORY SYSTEM - According to one embodiment, a shift register memory includes blocks and a control circuit. The blocks each includes data storing shift strings. Each of the data storing shift strings includes layers. The control circuit performs storing and reading data by shifting one layer of the layers, in a direction along each of the data storing shift strings. The reading includes reading data from a first layer of the layers. The storing includes storing data to a second layer of the layers. The control circuit reads first data stored in one or more third layers of the layers, the one or more third layers being successive from the first layer, determines a shift parameter in accordance with the reading of the first data, and performs the reading using the determined shift parameter. | 2022-03-31 |
20220101902 | NON-VOLATILE MEMORY HAVING VIRTUAL GROUND CIRCUITRY - A memory includes virtual ground circuitry configured to generate a virtual ground voltage (greater than zero volts) at a virtual ground node, a memory array of resistive memory cells in which each resistive memory cell includes a select transistor and a resistive storage element and is coupled to a first column line of a plurality of first column lines, and a first decoder configured to select a set of first column lines for a memory read operation from a selected set of the resistive memory cells. The memory includes read circuitry, and a first column line multiplexer configured to couple each selected first column line of the set of first column lines to the read circuitry during the memory read operation, and configured to couple each unselected first column line of the plurality of first column lines to the virtual ground node during the memory read operation. | 2022-03-31 |
20220101903 | NON-VOLATILE MEMORY WITH VIRTUAL GROUND VOLTAGE PROVIDED TO UNSELECTED COLUMN LINES DURING MEMORY WRITE OPERATION - A non-volatile memory includes virtual ground circuitry configured to generate a virtual ground voltage at a virtual ground node, a memory array of memory cells in which each memory cell includes a select transistor and a storage element and is coupled to a first column line of a plurality of first column lines; and a first decoder configured to select a set of first column lines for a memory write operation to a selected set of the memory cells. The non-volatile memory also includes write circuitry configured to receive a write value for storage into the selected set of memory cells, and a first column line multiplexer configured to, during the memory write operation, couple each selected first column line of the set of first column lines to the write circuitry, and couple each unselected first column line of the plurality of first column lines to the virtual ground node. | 2022-03-31 |
20220101904 | Local Reference Voltage Generator for Non-Volatile Memory - A memory device including a reference voltage (V | 2022-03-31 |
20220101905 | DIFFERENTIAL SENSING FOR A MEMORY DEVICE - Methods, systems, and devices for differential sensing for a memory device are described. A memory device in accordance with examples as disclosed herein may include a sense component having a signal development component for generating a sense signal, a reference component for generating a reference signal, and a tail component coupled with the signal development component and the reference component. The tail component may be configured for canceling common aspects of the sense signal and the reference signal. Additionally or alternatively, a memory device in accordance with examples as disclosed herein may include a sense component having a sense amplifier configured to operate in multiple power domains, with one power domain associated with sense signal and reference signal generation and comparison, and another power domain associated with logical signal or information transfer. | 2022-03-31 |
20220101906 | NOVEL CAPACITOR STRUCTURE AND METHOD OF FORMING THE SAME - A capacitor is provided. The capacitor includes a substrate, at least two conductive plates formed in the substrate and extending into the substrate, at least one insulating structure formed between two adjacent conductive plates of the at least two conductive plates and extending into the substrate, and a plurality of contacts, each extending into respective one of the at least two conductive plates. | 2022-03-31 |
20220101907 | POWER CONTROL CIRCUIT, SEMICONDUCTOR APPARATUS INCLUDING THE SAME AND POWER CONTROL METHOD OF SEMICONDUCTOR APPARATUS - A power control circuit includes a power control signal generation circuit configured to generate a voltage control signal according to a deep sleep command for operating a semiconductor apparatus in a deep sleep mode; a voltage divider circuit having a division ratio that is changed according to the voltage control signal, and configured to generate a divided voltage by dividing an internal voltage at the changed division ratio; a comparator configured to generate a detection signal by comparing a reference voltage to the divided voltage; an oscillator configured to generate an oscillation signal according to the detection signal; and a pump configured to generate the internal voltage according to the oscillation signal. | 2022-03-31 |
20220101908 | MEMORY CONTROLLER WITH CLOCK-TO-STROBE SKEW COMPENSATION - An integrated circuit device outputs a sequence of differently delayed calibration data timing signals to a DRAM component via a data-signal timing line as part of a timing calibration operation and then stores a delay value, based on at least one of the calibration data timing signals, that compensates for a difference in signal propagation times over the data-signal timing line and a command/address-signal timing line. After the timing calibration operation, the integrated circuit device outputs write data to the DRAM component and outputs a write data timing signal, delayed according to the delay value, to via the data-signal timing line to time reception of the first write data within the DRAM. | 2022-03-31 |
20220101909 | MULTI-DECK NON-VOLATILE MEMORY ARCHITECTURE WITH IMPROVED WORDLINE BUS AND BITLINE BUS CONFIGURATION - Systems, apparatuses and methods may provide for a multi-deck non-volatile memory architecture with an improved wordline bus and bitline bus configuration. For example, wordline busses and bitline busses may be positioned so as to be located over the junctions between two tiles, e.g., between a memory tile and a termination tile and between two memory tiles. Additionally, multi-deck non-volatile memory architectures may utilize data shifting to select which one of a plurality of wordline drivers and a plurality of bitline drivers are in communication with a data circuit of each memory tile. In a configuration where wordline busses and bitline busses have been positioned so as to be located over the junctions between two tiles, such data shifting directions may be able to be implemented with a limited number of shifting direction. | 2022-03-31 |
20220101910 | APPARATUSES AND METHODS OF POWER SUPPLY CONTROL FOR THRESHOLD VOLTAGE COMPENSATED SENSE AMPLIFIERS - Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes circuits, such as a first transistor having a first conductivity type coupled to a first node and a second node; a second transistor having a second conductivity type coupled to the first node and at third node; a plurality of transistors coupled to the second node and further configured to receive a power supply voltage; and a control circuit configured to provide a plurality of control signals to the plurality of transistors. The control circuit provides the plurality of control signals indicative of a first drive strength in a first memory operation and further provides the plurality of signals indicative of a second drive strength in a second memory operation. | 2022-03-31 |
20220101911 | NONVOLATILE MEMORY DEVICE, SYSTEM INCLUDING THE SAME AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a first lower interlayer insulation layer and a second lower interlayer insulation layer that are sequentially stacked in a first direction; a lower metal layer disposed in the first lower interlayer insulation layer; and a plurality of lower bonding metals disposed in the first lower interlayer insulation layer and the second lower interlayer insulation layer and spaced apart from each other in a second direction that intersects the first direction. An uppermost surface in the first direction of the lower metal layer is lower than an uppermost surface in the first direction of the plurality of lower bonding metals, and the lower metal layer is placed between the plurality of lower bonding metals. | 2022-03-31 |
20220101912 | VARIABLE WIDTH MEMORY MODULE SUPPORTING ENHANCED ERROR DETECTION AND CORRECTION - Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC. | 2022-03-31 |
20220101913 | MEMORY WITH PER DIE TEMPERATURE-COMPENSATED REFRESH CONTROL - Memory devices, systems, and associated methods with per die temperature-compensated refresh control, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory cells and a sensor configured to measure a temperature of the memory device. The memory device determines a frequency at which it is receiving refresh commands. The memory device is further configured to skip refresh operations of the memory cells based, at least in part, on the determination and on the temperature of the memory device. | 2022-03-31 |
20220101914 | Memory Bit Cell for In-Memory Computation - A compute-memory circuit included in a computer system may include multiple compute data storage cells coupled to a compute bit line via respective capacitors. The compute data storage cells may store respective bits of a weight value. During a multiply operation, an operand may be used to generate a voltage level on a compute word line that is used to store respective amounts of charge on the capacitors, which are coupled to the compute bit line. The voltage on the compute bit line may be converted into multiple bits whose value is indicative of a product of the operand and the weight value. | 2022-03-31 |
20220101915 | NONVOLATILE MEMORY MULTILEVEL CELL PROGRAMMING - A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit. | 2022-03-31 |
20220101916 | MEMORY DEVICE - A memory device includes: a cell array that includes a first region including first memory cells and a second region including second memory cells; first word lines connected to each of the first memory cells; second word lines connected to each of the second memory cells; a first bit line commonly connected to the first memory cells and the second memory cells; a row decoder that selects one of the first word lines and one of the second word lines in parallel during a data read operation; and a sense amplifier between the first region and the second region and electrically connected to the first bit line during the data read operation. | 2022-03-31 |
20220101917 | TECHNIQUES FOR READ OPERATIONS - Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch. | 2022-03-31 |
20220101918 | PASSIVE COMPENSATION FOR ELECTRICAL DISTANCE - An architecture of the memory device may leverage a transmission path resistance compensation scheme for memory cells to reduce the effect of parasitic loads in accessing a memory cell. A memory cell of such a memory device may experience a total resistance including a transmission path resistance associated with the respective access lines of the memory cell and an added compensatory resistance. The foregoing memory device may leverage a spike mitigation scheme to mitigate the harmful effect of a voltage and/or rush current to the near memory cells of the memory device. In addition, spike mitigation circuitry may include coupling a resistor on access lines near the respective decoders. Further, spike mitigation circuitry may include coupling a resistor between the decoders. | 2022-03-31 |
20220101919 | SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME - Provided herein may be a method of operating a semiconductor device including memory cells each storing multi-bit data. The method includes receiving data that is to be programmed in a memory cell selected from the memory cells; and applying a program pulse to the selected memory cell, the program pulse being determined depending on a logic state of the data and being selected from a group including a first program pulse having a positive polarity, a second program pulse having the positive polarity and having at least one of a peak level, a peak period, and a falling slew rate different from those of the first program pulse, a third program pulse having a negative polarity, and a fourth program pulse having the negative polarity and having at least one of a peak level, a peak period, and a rising slew rate different from those of the third program pulse. | 2022-03-31 |
20220101920 | SPLIT-GATE, 2-BIT NON-VOLATILE MEMORY CELL WITH ERASE GATE DISPOSED OVER WORD LINE GATE, AND METHOD OF MAKING SAME - A memory device includes a semiconductor substrate, first and second regions in the substrate having a conductivity type different than that of the substrate, with a channel region in the substrate extending between the first and second regions. The channel region is continuous between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region. A second floating gate is disposed over and insulated from a second portion of the channel region. A first coupling gate is disposed over and insulated from the first floating gate. A second coupling gate is disposed over and insulated from the second floating gate. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. An erase gate is disposed over and insulated from the word line gate. | 2022-03-31 |
20220101921 | SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICE - A method of operating a semiconductor device includes applying a first voltage to a first source select line coupled to first source select transistors of memory strings included in an unselected memory block, among memory blocks, floating the first source select line after the first voltage is applied thereto, applying a second voltage having a lower voltage level than the first voltage to a second source select line coupled to second source select transistors of the memory strings included in the unselected memory block, applying a precharge voltage to a common source line, and applying a program voltage to a word line coupled to selected memory cells of memory strings included in a selected memory block, among the memory blocks. | 2022-03-31 |
20220101922 | CONTROL METHOD AND CONTROLLER OF 3D NAND FLASH - A memory device includes a memory array including a cell, and a controller coupled to the memory array. The controller is configured to control sequentially applying programming voltage pulses to the cell. A pulse width of each of the programming voltage pulses decreases as a pulse count of the programming voltage pulses increases. | 2022-03-31 |
20220101923 | MEMORY DEVICE AND METHOD OF OPERATING THE SAME - Provided is a memory device. The memory device may include a voltage code controller configured to generate a voltage code that generates a program voltage and pass voltages based on a number of times a program loop is performed, and a voltage generator configured to generate the program voltage and the pass voltages in response to the voltage code, transmit the program voltage to a selected word line, and transmit the pass voltages to unselected word lines, wherein the voltage generator is configured to sequentially increase the pass voltage that is applied to the unselected word lines in order of proximity to the selected word line as the number of times a program loop is performed increases. | 2022-03-31 |
20220101924 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The device is configured to execute a first operation, a second operation, and a third operation to write data into the first memory cell. In the first operation, a first voltage is applied to the second word line. In the second operation, after the first operation, a second voltage higher than the first voltage is applied to the second word line. In the third operation, after the second operation, a third voltage higher than the second voltage is applied to the first word line, and a fourth voltage lower than both the second voltage and the third voltage is applied to the second word line. | 2022-03-31 |
20220101925 | METHOD FOR PROGRAMMING 3D NAND FLASH MEMORY - The present disclosure relates to a method for programming a 3D NAND flash memory, which includes: S | 2022-03-31 |
20220101926 | NON-VOLATILE MEMORY WITH SWITCHABLE ERASE METHODS - To improve the erase process, multiple methods of erasing are utilized. A first method of erasing is relied on at the beginning of life of the memory system. A second method is increasingly relied on as the memory system is used and undergoes many program/erase cycles. In one example, the first method of erase includes applying an erase enable voltage separately to different subsets of the word lines while word lines not receiving the erase enable voltage receive an erase inhibit voltage. In one example, the second method of erase includes applying an erase enable voltage concurrently to all subsets of the word lines. | 2022-03-31 |
20220101927 | PROGRESSIVE PROGRAM SUSPEND RESUME - Systems, apparatuses and methods may provide for technology that resumes a program operation with respect to NAND memory during a first tier in response to a suspension counter reaching a first threshold and resumes the program operation with respect to the NAND memory during a second tier in response to the suspension counter reaching a second threshold. The technology may also resume the program operation with respect to the NAND memory during a third tier in response to the suspension counter reaching a third threshold. Additionally, the technology may service one or more read operations with respect to the NAND memory until the suspension counter reaches the first threshold during the first tier, until the suspension counter reaches the second threshold during the second tier, and until the suspension counter reaches the third threshold during the third tier. | 2022-03-31 |
20220101928 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device, and a method of operating the same, includes a memory cell array and a peripheral circuit. The memory cell array includes memory cells, each storing N bits of data. The peripheral circuit performs a program operation on a physical page including selected memory cells. The peripheral circuit is configured to receive pieces of data of N logical pages and program the pieces of data of the N logical pages to the physical page based on a logic code. The logic code is determined to equalize numbers of sensing operations required to read the pieces of data of the N logical pages. Weak read levels are assigned, using the logic code, to read data of a logical page for which the number of sensing operations is smallest. | 2022-03-31 |
20220101929 | MEMORY APPARATUS - The invention provides a memory apparatus including a memory cell array and a voltage generation circuit. The voltage generation circuit is electrically connected to the memory cell array and includes an active voltage circuit and a sensing circuit. The active voltage circuit is configured to output an operating voltage to the memory cell array when the memory apparatus is in an active mode. The sensing circuit is configured to sense the operating voltage when the memory apparatus is in a standby mode and briefly activate the active voltage circuit to pull up the operating voltage after the operating voltage drops below a threshold. | 2022-03-31 |
20220101930 | NONVOLATILE MEMORY DEVICE AND OPERATION METHOD THEREOF - A nonvolatile memory device includes a memory cell array having cell strings that each includes memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder is connected with the memory cells through word lines. The row decoder applies a setting voltage to at least one word line of the word lines and floats the at least one word line during a floating time. A page buffer circuit is connected with the cell strings through bit lines. The page buffer senses voltage changes of the bit lines after the at least one word line is floated during the floating time and outputs a page buffer signal as a sensing result. A counter counts a number of off-cells in response to the page buffer signal. A detecting circuit outputs a detection signal associated with a defect cell based on the number of off-cells. | 2022-03-31 |
20220101931 | MEMORY DEVICE INCLUDING MASSBIT COUNTER AND METHOD OF OPERATING THE SAME - A method of operating a memory device that includes a plurality of stages each having a plurality of page buffers. The method including performing a verify operation of a first program loop from among a plurality of program loops, the verify operation of the first program loop including, performing a first off-cell counting operation on a first stage of the plurality of stages based on a first sampling rate to generate a first off-cell counting result; selectively changing the first sampling rate based on the first off-cell counting result to generate a changed first sampling rate; and performing a second off-cell counting operation on a second stage of the plurality of stages based on one of the first sampling rate and the changed first sampling rate to generate a second off-cell counting result. | 2022-03-31 |
20220101932 | STRING CURRENT REDUCTION DURING MULTISTROBE SENSING TO REDUCE READ DISTURB - A memory device comprising a memory array; and controller circuitry to apply a first pass voltage to a first plurality of unselected wordlines of the memory array during a string current sensing phase; and reduce the first pass voltage applied to the first plurality of unselected wordlines during a multistrobe sensing phase that follows the string current sensing phase. | 2022-03-31 |
20220101933 | MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A memory device and a method of operating the same are provided. The memory device may include a peripheral circuit configured to perform a plurality of program loops and program a page selected from among the plurality of pages, wherein the peripheral circuit may count a number of memory cells whose threshold voltages have increased up to a first target voltage, among a part of memory cells included in the selected page, and may perform a current sensing check operation of determining whether a verify operation performed in a previous program loop has passed or failed, and a control logic circuit configured to control the peripheral circuit so that the current sensing check operation is performed when the number of memory cells whose threshold voltages have increased up to the first target voltage, is equal to or greater than a reference number of memory cells. | 2022-03-31 |