14th week of 2012 patent applcation highlights part 12 |
Patent application number | Title | Published |
20120080740 | CHARGE TRAPPING DIELECTRIC STRUCTURES - A dielectric structure may be arranged having a thin nitrided surface of an insulator with a charge blocking insulator over the nitrided surface. The insulator may be formed of a number of different insulating materials such as a metal oxide, a metal oxycarbide, a semiconductor oxide, or oxycarbide. In an embodiment, the dielectric structure may be formed by nitridation of a surface of an insulator using ammonia and deposition of a blocking insulator having a larger band gap than the insulator. The dielectric structure may form part of a memory device, as well as other devices and systems. | 2012-04-05 |
20120080741 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a device isolation insulating film which is buried in a semiconductor substrate, a gate insulation film which is provided on the semiconductor substrate, a gate electrode which is provided on the gate insulation film, a source region and a drain region which are provided in the semiconductor substrate and spaced apart from each other in a manner to sandwich the gate electrode, both end portions of each of the source region and the drain region being offset from the device isolation insulating film in a channel width direction by a predetermined distance, and first and second gate electrode extension portions which are provided in a manner to cover both end portions of each of the source region and the drain region in a channel length direction. | 2012-04-05 |
20120080742 | Semiconductor device having vertical type transistor - A semiconductor device includes: a first vertical type transistor having a first lower diffusion layer, a first upper diffusion layer, and a gate electrode; a second vertical type transistor having a second lower diffusion layer, a second upper diffusion layer, and a second gate electrode; a gate wiring connected to the first and second gate electrodes; a first wiring connected to the first lower diffusion layer and second upper diffusion layer; and a second wiring connected to the first upper diffusion layer and second lower diffusion layer. | 2012-04-05 |
20120080743 | SEMICONDUCTOR DEVICE WITH INCREASED CHANNEL LENGTH AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a trench formed in a predetermined portion of a substrate and a first recess region beneath the trench. A field oxide layer is buried into both the trench and the first recess region. An active region is defined by the field oxide layer, having first active region and a second active region. The latter has a second recess region formed in lower portion of the active region than the former. A step gate pattern is formed on border region between the first active region and the second active region. The gate pattern has step structure whose one side extends to a surface of the first active region and the other side extends to a surface of the second active region. Other embodiments are also described. | 2012-04-05 |
20120080744 | SEMICONDUCTOR DEVICE - A semiconductor device has a semiconductor substrate having an upper main surface and a lower main surface. The semiconductor substrate includes a drain layer, a main base region, an underpad base region and a source region. The semiconductor device includes a first main electrode connected to the main base regions and the source region and not connected to the underpad base region, a gate electrode opposed to a channel region in the main base region interposed between the drain layer and the source region with a gate insulating film provided therebetween, a conductive gate pad opposed to an exposed surface of the underpad base region in the upper main surface with an insulating layer interposed therebetween and the conductive gate pad is connected to the gate electrode, and a second main electrode connected to the lower main surface. | 2012-04-05 |
20120080745 | VERTICAL TRANSISTOR AND METHOD FOR FORMING THE SAME - A vertical transistor includes a semiconductor substrate provided with a pillar type active pattern over the surface thereof. A first tensile layer is formed over the semiconductor substrate and around the lower end portion of the pillar type active pattern, and a second tensile layer is formed over the upper end portion of the pillar type active pattern so that a tensile stress is applied in a vertical direction to the pillar type active pattern. A first junction region is formed within the surface of the semiconductor substrate below the first tensile layer and the pillar type active pattern. A gate is formed so as to surround at least a portion of the pillar type active pattern. A second junction region is formed within the upper end portion of the pillar type active pattern. | 2012-04-05 |
20120080746 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - Disclosed herein is a fabrication method of a semiconductor device to order to increase an operation liability of the semiconductor device. A method for fabricating a semiconductor device comprises forming a recess in a semiconductor substrate, forming a word line in a lower part of the recess, oxidizing a top portion of the word line, and depositing an insulating material in a remained part of the recess. | 2012-04-05 |
20120080747 | Semiconductor Device - A vertical transistor of a semiconductor device has a channel area formed in a vertical direction to a semiconductor substrate. After semiconductor poles corresponding to the length of semiconductor channels and gate electrodes surrounding sidewalls of the semiconductor poles are formed, subsequent processes of forming silicon patterns corresponding to junction areas, etc. are performed. The gate electrodes support the semiconductor poles during these subsequent processes. The height of the semiconductor poles corresponding to the length of the channel is increased, yet the semiconductor poles do not collapse or incline since the gate electrodes support the semiconductor poles. | 2012-04-05 |
20120080748 | TRENCH MOSFET WITH SUPER PINCH-OFF REGIONS - A trench MOSFET with short channel length and super pinch-off regions is disclosed, wherein the super pinch-off regions are implemented by forming at least two type pinch-off regions for punch-through prevention: a first type pinch-off region with a wide mesa width generated between lower portion of two adjacent trenched gates and below an anti-punch through region surrounding bottom of a trenched source-body contact filled with metal plug; a second type pinch-off region with a narrow mesa width generated below a body region and between upper portion of one trenched gate and the anti-punch-through region along sidewall of the trenched source-body contact. | 2012-04-05 |
20120080749 | UMOS SEMICONDUCTOR DEVICES FORMED BY LOW TEMPERATURE PROCESSING - UMOS (U-shaped trench MOSFET) semiconductor devices that have been formed using low temperature processes are described. The source region of the UMOS structure can be formed before the etch processes that are used to create the trench, allowing low-temperature materials to be incorporated into the semiconductor device from the creation of the gate oxide layer oxidation forward. Thus, the source drive-in and activation processing that are typically performed after the trench etch can be eliminated. The resulting UMOS structures contain a trench structure with both a gate insulting layer comprising a low temperature dielectric material and a gate conductor comprising a low temperature conductive material. Forming the source region before the trench etch can reduce the problems resulting from high temperature processes, and can reduce auto doping, improve threshold voltage control, reduce void creation, and enable incorporation of materials such as silicides that cannot survive high temperature processing. Other embodiments are described. | 2012-04-05 |
20120080750 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a semiconductor substrate comprising a word line decoder region and a memory cell region; a basic word line formed in the memory cell region in a buried gate type; and an additional word line formed to extend from the word line decoder region across the memory cell region, wherein the additional word line is formed over the basic word line in parallel to the basic word line and is coupled to the basic word line through two or more vias. | 2012-04-05 |
20120080751 | MOS DEVICE WITH VARYING CONTACT TRENCH LENGTHS - A semiconductor device is formed on a semiconductor substrate. The device comprises a drain; an epitaxial layer overlaying the drain; a body disposed in the epitaxial layer, having a body top surface and a body bottom surface; a source embedded in the body, extending from the body top surface into the body; a first gate trench extending into the epitaxial layer; a first gate disposed in the first gate trench; an active region contact trench extending through the source and at least part of the body into the drain; an active region contact electrode disposed within the active region contact trench; a second gate trench extending into the epitaxial layer; a second gate disposed in the gate trench; a gate contact trench formed within the second gate; and a gate contact electrode disposed within the gate contact trench. | 2012-04-05 |
20120080752 | HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR WITH STABLE THRESHOLD VOLTAGE AND RELATED MANUFACTURING METHOD - A high voltage metal-oxide-semiconductor (HVMOS) transistor includes a gate poly, wherein a channel is formed in an area projected from the gate poly in a thickness direction when the HVMOS is activated; two carrier drain drift regions, adjacent to the area projected from the gate poly, wherein at least one of the carrier drain drift regions has a gradient doping concentration; and two carrier plus regions, respectively locate within the two carrier drain drift regions, wherein the two carrier plus regions and the two carrier drain drift regions are communicating with each other through the channel when the HVMOS is activated. | 2012-04-05 |
20120080753 | GALLIUM ARSENIDE BASED MATERIALS USED IN THIN FILM TRANSISTOR APPLICATIONS - Embodiments of the invention provide a method of forming a group III-V material utilized in thin film transistor devices. In one embodiment, a gallium arsenide based (GaAs) layer with or without dopants formed from a solution based precursor may be utilized in thin film transistor devices. The gallium arsenide based (GaAs) layer formed from the solution based precursor may be incorporated in thin film transistor devices to improve device performance and device speed. In one embodiment, a thin film transistor structure includes a gate insulator layer disposed on a substrate, a GaAs based layer disposed over the gate insulator layer, and a source-drain metal electrode layer disposed adjacent to the GaAs based layer. | 2012-04-05 |
20120080754 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The semiconductor device includes a first transistor including a first impurity layer containing boron or phosphorus, a first epitaxial layer formed above the first impurity layer, a first gate electrode formed above the first epitaxial layer with a first gate insulating film formed therebetween and first source/drain regions, and a second transistor including a second impurity layer containing boron and carbon, or arsenic or antimony, a second epitaxial layer formed above the second impurity layer, a second gate electrode formed above the second epitaxial layer with a second gate insulating film thinner than the first gate insulating film formed therebetween, and second source/drain regions. | 2012-04-05 |
20120080755 | Methods for Forming Gates in Gate-Last Processes and Gate Areas formed by the Same - Methods are provided for forming gates in gate-last processes. The methods may include performing chemical mechanical polishing (CMP) on an interlayer dielectric (ILD) that is on a plurality of dummy gates, each of the plurality of dummy gates including a gate mask in an upper portion thereof, and the CMP exposing the gate mask. The methods may also include removing the gate mask by etching the gate mask. The methods may further include performing CMP on the ILD. | 2012-04-05 |
20120080756 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a high dielectric gate insulating film formed on a substrate, and a metal gate electrode formed on the high dielectric gate insulating film. The metal gate electrode includes a crystalline portion and an amorphous portion. A halogen element is eccentrically located in the amorphous portion. | 2012-04-05 |
20120080757 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - First protective films are formed to cover side surfaces of gate electrode portions. In an nMOS region, an extention implantation region is formed by causing a portion of the first protective film located on the side surface of the gate electrode portion to function as an offset spacer and using the offset spacer as a mask, and then, cleaning is done. Since silicon nitride films are formed on surfaces of the first protective films, the resistance to chemical solutions is improved. Furthermore, second protective films are formed on the first protective films, respectively. In a pMOS region, an extention implantation region is formed by causing a portion of the first protective film and a portion of the second protective film located on the side surface of the gate electrode portion to function as an offset spacer and using the offset spacer as the mask, and then, cleaning is done. | 2012-04-05 |
20120080758 | METHOD FOR FABRICATING AT LEAST THREE METAL-OXIDE SEMICONDUCTOR TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES - At least three metal-oxide semiconductor transistors with different threshold voltages are formed in and above corresponding first, second and third parts of a semiconductor substrate. The second transistor has a lower threshold voltage than the second transistor, and the third transistor has a lower threshold voltage than the second transistor. The gate oxide layers for the three transistors are formed as follows: a first oxide layer having a first thickness is formed above the first, second and third parts. The first oxide layer above the second part is etched and a second oxide layer having a second thickness smaller than the first thickness is formed. The first oxide layer above the third part is etched and a third oxide layer having a third thickness smaller than the second thickness is formed. The second and the third oxide layers are then nitrided to form first and second oxy-nitride layers. | 2012-04-05 |
20120080759 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A first transistor includes a first impurity layer of a first conduction type formed in a first region of a semiconductor substrate, a first epitaxial semiconductor layer formed above the first impurity layer, a first gate insulating film formed above the first epitaxial semiconductor layer, a first gate electrode formed above the first gate insulating film, and first source/drain regions of a second conduction type formed in the first epitaxial semiconductor layer and in the semiconductor substrate in the first region. A second transistor includes a second impurity layer of the first conduction type formed in a second region of the semiconductor substrate, a second epitaxial semiconductor layer formed above the second impurity layer and being thinner than the first epitaxial semiconductor layer, a second gate insulating film formed above the second epitaxial semiconductor layer, a second gate electrode formed above the second gate insulating film, and second source/drain regions of the second conduction type formed in the second epitaxial semiconductor layer and in the semiconductor substrate in the second region. | 2012-04-05 |
20120080760 | Dielectric structure, transistor and manufacturing method thereof - The present invention discloses a dielectric structure, a transistor and a manufacturing method thereof with praseodymium oxide. The transistor with praseodymium oxide comprises at least a III-V substrate, a gate dielectric layer and a gate. The gate dielectric layer is disposed on the III-V substrate, and the gate is disposed on the gate dielectric layer, and the gate dielectric layer is praseodymium oxide (Pr | 2012-04-05 |
20120080761 | SEMICONDUCTOR HAVING A HIGH ASPECT RATIO VIA - A semiconductor device includes a substrate wafer, a dielectric layer overlying the substrate wafer, a patterned conductor layer in the dielectric layer, and a first barrier layer overlying the conductor layer. A silicon top wafer is bonded to the dielectric layer. A via is formed through the top wafer and a portion of the dielectric layer to the first barrier layer. A sidewall dielectric layer is formed along inner walls of the via, adjacent the top wafer to a distance below an upper surface of the top wafer, forming a sidewall dielectric layer shoulder. A sidewall barrier layer is formed inward of the sidewall dielectric layer, lining the via from the first barrier layer to the upper surface of the top wafer. A conductive layer fills the via and a top barrier layer is formed on the conductive layer, the sidewall barrier layer, and the top wafer. | 2012-04-05 |
20120080762 | Plating process and apparatus for through wafer features - A method for forming through features in a substrate uses a seed layer deposited over a first substrate, and a second substrate bonded to the seed layer. The features may be formed in the first substrate, by plating a conductive filler material onto the seed layer. The first substrate and the second substrate may then be bonded to a third substrate, and the second substrate is removed, leaving through features and first substrate adhered to the third substrate. The through features may provide at least one of electrical access and motion to a plurality of devices formed on the third substrate, or may impart movement to a moveable feature on the first substrate, wherein the third substrate supports the first substrate after removal of the second substrate. | 2012-04-05 |
20120080763 | ELECTRONIC COMPONENT, ELECTRONIC DEVICE, AND METHOD OF MANUFACTURING THE ELECTRONIC COMPONENT - An electronic component includes: a semiconductor element including a circuit; a vibration element; a first electrode arranged on a first surface of the semiconductor element and connected to the circuit and the vibration element arranged on the first surface side; a second electrode arranged on the first surface; a first wiring board including a first wire connected to the second electrode; and a second wiring board including a second wire to which the first wire is connected At least a part of an inner side region of an outer contour of the vibration element is arranged to overlap the second electrode in plan view facing the first surface. | 2012-04-05 |
20120080764 | APPARATUS AND METHOD FOR MICROELECTROMECHANICAL SYSTEMS DEVICE PACKAGING - A MEMS package includes a substrate having an L-shaped cross-section. The substrate includes a vertical portion having a front surface and a back surface, and a horizontal portion protruding from a lower part of the front surface of the vertical portion, wherein the front surface of the vertical portion includes a mounting region. A MEMS die is mounted on the mounting region such that the MEMS die is oriented substantially parallel to the front surface; a lid attached to the front surface of the substrate while covering the MEMS die; and a plurality of leads formed on a bottom surface of the substrate. The leads can extend substantially parallel to one another, and substantially perpendicular to the front surface. The MEMS die can be oriented substantially perpendicular to a PCB substrate on which the package is mounted. | 2012-04-05 |
20120080765 | METHOD OF DAMAGE-FREE IMPURITY DOPING FOR CMOS IMAGE SENSORS - A method of fabricating a backside-illuminated pixel. The method includes forming frontside components of the pixel on or in a front side of a substrate, the frontside components including a photosensitive region of a first polarity. The method further includes forming a pure dopant region of a second polarity on a back side of the substrate, applying a laser pulse to the backside of the substrate to melt the pure dopant region, and recrystallizing the pure dopant region to form a backside doped layer. Corresponding apparatus embodiments are disclosed and claimed. | 2012-04-05 |
20120080766 | Image Sensing Device and Fabrication Thereof - An image sensing device is disclosed, including an epitaxy layer having the a conductivity type, including a first pixel area corresponding to a first incident light, a second pixel area corresponding to a second incident light, and a third pixel area corresponding to a third incident light, wherein the wavelength of the first incident light is longer than that of the second incident light and the wavelength of the second incident light is longer than that of the third incident light. A photodiode is disposed in an upper portion of the epitaxy layer, and a first deep well for reducing pixel-to-pixel talk of the image sensing device is disposed in a lower portion of the epitaxy layer in the second pixel area and the third pixel area, wherein at least a portion of the epitaxy layer in first pixel area does not include the first deep well. | 2012-04-05 |
20120080767 | Solid-state imaging device, method for manufacturing the same, and electronic apparatus - A method for manufacturing a solid-state imaging device includes: forming pixels that receive incident light in a pixel array area of a substrate; forming pad electrodes in a peripheral area located around the pixel array area of the substrate; forming a carbon-based inorganic film on an upper surface of each of the pad electrodes including a connection surface electrically connected to an external component; forming a coated film that covers upper surfaces of the carbon-based inorganic films; and forming an opening above the connection surface of each of the pad electrodes to expose the connection surface. | 2012-04-05 |
20120080768 | SHEET-MOLDED CHIP-SCALE PACKAGE - Embodiments include but are not limited to apparatuses and systems including a microelectronic device including a die having a first surface and a second surface opposite the first surface, a conductive pillar formed on the first surface of the die, and an encapsulant material encasing the die, including covering the first surface, the second surface, and at least a portion of a side surface of the conductive pillar. Methods for making the same also are described. | 2012-04-05 |
20120080769 | ESD DEVICE AND METHOD - A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes a transient voltage suppression structure that includes at least two diodes and a Zener diode. In accordance with embodiments, a semiconductor material is provided that includes an epitaxial layer. The at least two diodes and the Zener diode are created at the surface of the epitaxial layer, where the at least two diodes may be adjacent to the Zener diode. | 2012-04-05 |
20120080770 | Transformer Arrangement - A transformer arrangement and a method for producing a transformer arrangement is disclosed. | 2012-04-05 |
20120080771 | 3D VIA CAPACITOR WITH A FLOATING CONDUCTIVE PLATE FOR IMPROVED RELIABILITY - The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided. | 2012-04-05 |
20120080772 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, a first single conductor, a single insulator, and a second single conductor. The substrate includes first and second regions located adjacent to each other. The first region has blind holes, each of which has an opening on a front surface of the substrate. The second region has a through hole penetrating the substrate. A width of each blind hole is less than a width of the through hole. The first single conductor is formed on the front surface of the substrate in such a manner that an inner surface of each blind hole and an inner surface of the through hole are covered with the first single conductor. The single insulator is formed on the first single conductor. The second single conductor is formed on the single insulator and electrically insulated form the first single conductor. | 2012-04-05 |
20120080773 | SWITCHABLE MEMORY DIODES BASED ON FERROELECTRIC/CONJUGATED POLYMER HETEROSTRUCTURES AND/OR THEIR COMPOSITES - An embodiment of the present memory cell a first layer of a chosen conductivity type, and a second layer which includes ferroelectric semiconductor material of the opposite conductivity type, the layers forming a pn junction. The first layer may be a conjugated semiconductor polymer, or may also be of ferroelectric semiconductor material. The layers are provided between first and electrodes. In another embodiment, a single layer of a composite of conjugated semiconductor polymer and ferroelectric semiconductor material is provided between first and second electrodes. The various embodiments may be part of a memory array. | 2012-04-05 |
20120080774 | SEMICONDUCTOR, N-TYPE SEMICONDUCTOR, P-TYPE SEMICONDUCTOR, SEMICONDUCTOR JUNCTION DEVICE, PN JUNCTION DEVICE AND PHOTOELECTRIC CONVERTER - The semiconductor of the present invention has iron sulfide and a forbidden band control element contained in the iron sulfide. The forbidden band control element has a property capable of controlling the forbidden band of iron sulfide on the basis of the number density of the forbidden band control element in the iron sulfide. An n-type semiconductor is manufactured by incorporating a group 13 element of the IUPAC system into iron sulfide. Moreover, a p-type semiconductor is manufactured by incorporating a group Ia element into iron sulfide. A semiconductor junction device or a photoelectric converter is manufactured by using the n-type semiconductor and the p-type semiconductor. | 2012-04-05 |
20120080775 | METHOD OF POLISHING SILICON WAFER AS WELL AS SILICON WAFER - This invention is to provide a method of polishing a silicon wafer wherein a high flatness can be attained likewise the conventional polishing method and further the occurrence of defects due to the remaining of substances included in the polishing solution on the surface of the wafer can be suppressed as well as a polished silicon wafer. | 2012-04-05 |
20120080776 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: element formation regions each including a cell region where a semiconductor element is formed, a termination trench region; and a dicing line region including a groove separating the element formation regions. The termination trench region includes four trenches surrounding four sides of the cell region. Two of the trenches extend longitudinally in parallel to an X direction and the other two trenches extend longitudinally in parallel to a Y direction perpendicular to the X direction. The termination trench region is perpendicularly in contact with longitudinal sides of the dicing line region while the trenches extending longitudinally in parallel to the X direction intersect the trenches extending longitudinally in parallel to the Y direction at four corners of the element formation region, while vertical sections of the termination trench region in a cross direction are opened in four side surfaces of the element formation region. | 2012-04-05 |
20120080777 | TRIPLE OXIDATION ON DSB SUBSTRATE - According to certain embodiments, a semiconductor structure is formed having a gate oxide formed over a semiconductor substrate. The gate oxide is formed as to have three different regions characterized by a different average thickness of gate oxide in each region. A first oxidation process is performed on a semiconductor substrate having both a Si (110) orientation region and a Si (100) orientation region on a surface thereof. Gate oxide is formed at a faster rate on the Si (110) orientation region of the semiconductor substrate relative to the Si (100) orientation region. A portion of the gate oxide is selectively removed and a second oxidation process is performed to form additional gate oxide. A triple oxide semiconductor substrate is recovered with the gate oxide having three different thickness formed thereon. The triple oxide semiconductor substrate is formed using a decreased number of processing acts. | 2012-04-05 |
20120080778 | ELECTRONIC DEVICE - A device is prepared using a chemical vapor deposition method and has a patterned thin film on a substrate that is applied using a deposition inhibitor material. The deposition inhibitor material is a hydrophilic polymer that is a neutralized acid having a pKa of 5 or less, wherein at least 90% of the acid groups are neutralized. The deposition inhibitor material can be patterned simultaneously or subsequently to its application to the substrate, to provide selected areas of the substrate effectively not having the deposition inhibitor material. A thin film is substantially deposited only in the selected areas of the substrate not having the deposition inhibitor material. | 2012-04-05 |
20120080779 | ULTRA HIGH SELECTIVITY DOPED AMORPHOUS CARBON STRIPPABLE HARDMASK DEVELOPMENT AND INTEGRATION - Embodiments of the present invention generally relate to the fabrication of integrated circuits and particularly to the deposition of a boron containing amorphous carbon layer on a semiconductor substrate. In one embodiment, a method of processing a substrate in a processing chamber is provided. The method comprises providing a substrate in a processing volume, flowing a hydrocarbon containing gas mixture into the processing volume, generating a plasma of the hydrocarbon containing gas mixture by applying power from an RF source, flowing a boron containing gas mixture into the processing volume, and depositing a boron containing amorphous carbon film on the substrate in the presence of the plasma, wherein the boron containing amorphous carbon film contains from about 30 to about 60 atomic percentage of boron. | 2012-04-05 |
20120080780 | SEM ICONDUCTOR DEVICE HAVING PADS AND WHICH MINIMIZES DEFECTS DUE TO BONDING AND PROBING PROCESSES - A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes. | 2012-04-05 |
20120080781 | DELAMINATION RESISTANT DEVICE PACKAGE HAVING RAISED BOND SURFACE AND MOLD LOCKING APERTURE - A semiconductor package configured to attain a thin profile and low moisture sensitivity. Packages of this invention can include a semiconductor die mounted on a die attachment site of a leadframe and further connected with a plurality of elongate I/O leads arranged about the die attach pad and extending in said first direction. The leadframe having an “up-set” bonding pad arranged with a bonding support for supporting a plurality of wire bonds and a large mold flow aperture in the up-set bonding pad. The package encapsulated in a mold material that surrounds the bonding support and flows through the large mold flow aperture to establish well supported wire bonds such that the package has low moisture sensitivity. | 2012-04-05 |
20120080782 | METHOD OF MANUFACTURING LAYERED CHIP PACKAGE - A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and second layer portions; and a plurality of first and second terminals that are disposed on the top and bottom surfaces of the main part, respectively, and are electrically connected to the plurality of wires. The first and second terminals are formed by using electrodes of the first and second layer portions. The layered chip package is manufactured by fabricating a layered substructure by stacking two substructures each of which includes an array of a plurality of preliminary layer portions, and then cutting the layered substructure. The layered substructure includes a plurality of preliminary wires that are disposed between two adjacent pre-separation main bodies and are to become the plurality of wires. | 2012-04-05 |
20120080783 | THIN FLIP CHIP PACKAGE STRUCTURE - A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, the substrate comprises an insulating layer and a trace layer. The insulating layer comprises a top surface, a bottom surface and a plurality of apertures formed at the bottom surface, wherein the bottom surface of the insulating layer comprises a disposing area and a non-disposing area. Each of the apertures is located at the disposing area and comprises a lateral wall and a base surface. A first thickness is formed between the base surface and the insulating layer, a second thickness is formed between the top surface and the bottom surface, and the second thickness is larger than the first thickness. The chip disposed on the top surface comprises a chip surface and a plurality of bumps. The heat dissipation paste at least fills the apertures and contacts the base surface. | 2012-04-05 |
20120080784 | MULTICHIP ELECTRONIC PACKAGES AND METHODS OF MANUFACTURE - A multi-chip electronic package and methods of manufacture are provided. The multi-chip package includes a plurality of chips mounted on a chip carrier. The multi-chip package further includes a lid mounted on the chip carrier using a bonding material or compression seal, and at least one single piston extending from the lid. Each piston covers an entirety of multiple chips of the plurality of chips. | 2012-04-05 |
20120080785 | SEMICONDUCTOR COOLING APPARATUS - In some embodiments, a semiconductor cooling apparatus includes a monolithic array of cooling elements. Each cooling element of the monolithic array of cooling elements is configured to thermally couple to a respective semiconductor element of an array of semiconductor elements. At least two of the semiconductor elements have a different height and each cooling element independently flexes to conform to the height of the respective semiconductor element. | 2012-04-05 |
20120080786 | ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING THE SAME - An electronic component including a wiring board having interlayer insulation layers and conductive patterns, the wiring board having a first surface and a second surface on the opposite side of the first surface, multiple first bumps formed on a first conductive pattern positioned on the first surface of the wiring board among the conductive patterns of the wiring board, a semiconductor element mounted on the first surface of the wiring board through the first bumps, an encapsulating resin encapsulating the semiconductor element and at least a portion of a side surface of the wiring board, the side surface of the wiring board extending between the first surface and second surface of the wiring board, and multiple of second bumps formed on the second surface of the wiring board and connected to a second conductive pattern of the conductive patterns in the wiring board. | 2012-04-05 |
20120080787 | Electronic Package and Method of Making an Electronic Package - An electrical package and a method of forming the electrical package, where the electrical package has a substrate with a frontside, an intergrated circuit coupled to the frontside of the substrate, and at least one non-collapsible metal connector created on the frontside of the first substrate. | 2012-04-05 |
20120080788 | SEMICONDUCTOR DEVICE HAVING MULTILAYER WIRING STRUCTURE AND MANUFACTURING METHOD OF THE SAME - Disclosed is a semiconductor device | 2012-04-05 |
20120080789 | SEMICONDUCTOR CHIP AND MOUNTING STRUCTURE OF THE SAME (as amended) - Provided is a semiconductor chip having a narrowed pitch between terminals, the chip being capable of suppressing occurrence of poor connection between the chip and a substrate on which the chip is mounted. In an LSI chip including an input bump group, which is composed of a plurality of input bumps aligned in a line along one long side of its bottom surface, and an output bump group, which is composed of a plurality of output bumps arranged in a staggered manner along the other long side of the bottom surface, a dummy bump group is provided in an area between an area where the input bump group is provided and an area where the output bump group is provided, the dummy bump group including a plurality of rectangular dummy bumps which have long side extending along a direction perpendicular to the long sides of the bottom surface. | 2012-04-05 |
20120080790 | APPARATUS AND METHOD FOR UNIFORM METAL PLATING - Apparatus and methods for uniform metal plating onto a semiconductor wafer, such as GaAs wafer, are disclosed. One such apparatus can include an anode and a showerhead body. The anode can include an anode post and a showerhead anode plate. The showerhead anode plate can include holes sized to dispense a particular plating solution, such as plating solution that includes gold, onto a wafer. The showerhead body can be coupled to the anode post and the showerhead anode plate. The showerhead body can be configured to create a seal sufficient to substantially prevent a reduction of pressure in the plating solution flowing from the anode post to holes of the showerhead anode plate. | 2012-04-05 |
20120080791 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME - One or more embodiments relate to a method of forming an electronic device, comprising: providing a workpiece; forming a first barrier layer over the workpiece; forming an intermediate conductive layer over the first barrier layer; forming a second barrier layer over the intermediate conductive layer; forming a seed layer over the second barrier layer; removing a portion of the seed layer to leave a remaining portion of the seed layer and to expose a portion of the second barrier layer; and electroplating a fill layer on the remaining portion of the seed layer. | 2012-04-05 |
20120080792 | Metal Interconnection Structure and Method For Forming Metal Interlayer Via and Metal Interconnection Line - There is provided a method for forming a metal interlayer via, comprising: forming a seed layer on a first dielectric layer and a first metal layer embedded in the first dielectric layer; forming a mask pattern on the seed layer to expose a portion of the seed layer covering some of the first metal layer; growing a second metal layer on the exposed portion of the seed layer; removing the mask pattern and a portion of the seed layer carrying the mask pattern to expose side walls of the second metal layer, a portion of the first metal layer and the first dielectric layer; forming an insulating barrier layer on the side walls, the portion of the first metal layer and the first dielectric layer. There is also provided a method for forming a metal interconnection line. Both of them can suppress the occurrence of voids. There is further provided a metal interconnection structure comprising a contact plug, a via and a metal interconnection line, wherein the via is formed on the metal interconnection line, the metal gate and/or the contact plug. | 2012-04-05 |
20120080793 | SUBTRACTIVE PATTERNING TO DEFINE CIRCUIT COMPONENTS - Certain embodiments pertain to local interconnects formed by subtractive patterning of blanket layer of tungsten or other conductive material. The grain sizes of tungsten or other deposited metal can be grown to relatively large dimensions, which results in increased electrical conductivity due to, e.g., reduced electron scattering at grain boundaries as electrons travel from one grain to the next during conduction. | 2012-04-05 |
20120080794 | METHOD FOR PRODUCING A METALLIZATION HAVING TWO MULTIPLE ALTERNATING METALLIZATION LAYERS FOR AT LEAST ONE CONTACT PAD AND SEMICONDUCTOR WAFER HAVING SAID METALLIZATION FOR AT LEAST ONE CONTACT PAD - The invention relates to a method for producing a metallization for at least one contact pad and a semiconductor wafer having metallization for at least one contact pad. The invention relates to a metallization (and a semiconductor wafer having corresponding metallization) and to a method for the production thereof that first of all can be produced by means of physical gas phase separation (dry separation) and secondly ensures sufficient adhesion of a lot bump. The method for producing a metallization ( | 2012-04-05 |
20120080795 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME - One or more embodiments relate to a method for forming a semiconductor structure, comprising: providing a workpiece; forming a dielectric barrier layer over the workpiece; forming an opening through the dielectric barrier layer; forming a seed layer over the dielectric barrier layer and within the dielectric barrier layer opening; and electroplating a first fill layer on the seed layer. | 2012-04-05 |
20120080796 | DEVICE - According to one embodiment, a device includes an insulating layer with a first trench, a first interconnect layer in the first trench, the first interconnect layer including copper and includes a concave portion, and a first graphene sheet on an inner surface of the concave portion. | 2012-04-05 |
20120080797 | METAL WIRING STRUCTURES FOR UNIFORM CURRENT DENSITY IN C4 BALLS - In one embodiment, a sub-pad assembly of metal structures is located directly underneath a metal pad. The sub-pad assembly includes an upper level metal line structure abutting the metal pad, a lower level metal line structure located underneath the upper level metal line structure, and a set of metal vias that provide electrical connection between the lower level metal line structure located underneath the upper level metal line structure. In another embodiment, the reliability of a C4 ball is enhanced by employing a metal pad structure having a set of integrated metal vias that are segmented and distributed to facilitate uniform current density distribution within the C4 ball. The areal density of the cross-sectional area in the plurality of metal vias is higher at the center portion of the metal pad than at the peripheral portion of the planar portion of the metal pad. | 2012-04-05 |
20120080798 | MEMORY DEVICES HAVING CONTACT FEATURES - Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as carbon or titanium nitride is used to form the contact. In an alternative embodiment, a memory material itself is used to form the contact. These contact structures may be made by various processes, including chemical mechanical planarization and facet etching. | 2012-04-05 |
20120080799 | Semiconductor Module Comprising an Insert and Method for Producing a Semiconductor Module Comprising an Insert - A power semiconductor module is fabricated by providing a base with a metal surface and an insulating substrate comprising an insulation carrier having a bottom side provided with a bottom metallization layer. An insert exhibiting a wavy structure is provided. The insert is positioned between the insulation carrier and metal surface, after which the metal surface is soldered to the bottom side metallization layer and insert by means of a solder packing all interstices between the metal surface and bottom side metallization layer with the solder. | 2012-04-05 |
20120080800 | POWER MODULE AND METHOD FOR MANUFACTURING THE SAME - Provided is a power module that prevents a deterioration of reliability of bonded portions of aluminum wires, and enables a high-temperature operation of a Si or SiC device. A power module according to the present invention includes: insulating substrates arranged in a case; power elements bonded on the insulating substrates; wiring members as first wiring members which are rectangular tube-like metal, and have first side surfaces bonded to surface electrodes of the power elements; aluminum wires as wires connected to second side surfaces of the wiring members, which are opposite to the first side surfaces, and a sealing material filled into the case while covering the insulating substrates, the power elements, the wiring members and the aluminum wires. | 2012-04-05 |
20120080801 | SEMICONDUCTOR DEVICE AND ELECTRONIC COMPONENT MODULE USING THE SAME - A semiconductor device includes a circuit board having an element mounting area, connecting pads positioned in the same surface side as the element mounting area and external connectors to be connected with the connecting pads, respectively; and a semiconductor element mounted on the element mounting area of the circuit board and having electrode pads to be electrically connected with the connecting pads, respectively. The external connectors are detachably configured through a combination of convex portions and concave portions which are mechanically and electrically connected with one another. | 2012-04-05 |
20120080802 | THROUGH SILICON VIA IN N+ EPITAXY WAFERS WITH REDUCED PARASITIC CAPACITANCE - A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance. | 2012-04-05 |
20120080803 | METHOD OF MANUFACTURING A SEMICONDUCTOR COMPONENT AND STRUCTURE - A semiconductor component and methods for manufacturing the semiconductor component that includes a three dimensional helically shaped common mode choke. In accordance with embodiments, a transient voltage suppression device may be coupled to the monolithically integrated common mode choke. | 2012-04-05 |
20120080804 | ELECTRONIC DEVICE INCLUDING INTERCONNECTS WITH A CAVITY THEREBETWEEN AND A PROCESS OF FORMING THE SAME - A process of forming an electronic device can include providing a first interconnect over a substrate having a primary surface, depositing a first insulating layer over the first interconnect, and patterning the first insulating layer to define an opening extending towards the first interconnect. The process can also include depositing a second insulating layer over the first insulating layer to seal the opening and form a cavity within the first opening, and forming a second interconnect over the first and second insulating layers. The cavity can be disposed between the first interconnect and the second interconnect. In another aspect, an electronic device can include a first interconnect, a first insulating layer defining a cavity, and a second interconnect. The cavity can be disposed between the first interconnect and the second interconnect, and a via may not be exposed within the cavity. | 2012-04-05 |
20120080805 | Semiconductor device and method of manufacturing the same - A semiconductor device according to the invention includes a first Cu interconnect and a first barrier insulating film. a The first barrier insulating film is provided on the first Cu interconnect, and prevents Cu from being diffused from the first Cu interconnect. In addition, the semiconductor device includes a second Cu interconnect and a second barrier insulating film on the first barrier insulating film. The second barrier insulating film is provided on a first Cu interconnect, and prevents Cu from being diffused from the second Cu interconnect. The first and second barrier insulating films are made of a silicon-based insulating film having a branched alkyl group and a carbon-carbon double bond. | 2012-04-05 |
20120080806 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first package including a first substrate and at least one first semiconductor chip mounted on the first substrate, a redistribution wiring layer provided on the first package and including a connection pad, a bonding pad electrically connected to the connection pad and a dummy bonding pad electrically connected to the bonding pad, a second package stacked on the first package via the redistribution wiring layer and electrically connected to the connection pad of the redistribution wiring layer by a first connection member, a bonding wire electrically connecting the bonding pad to the first substrate, and a dummy bonding wire electrically connecting the dummy bonding pad to the first substrate. | 2012-04-05 |
20120080807 | OFF-CHIP VIAS IN STACKED CHIPS - A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements. | 2012-04-05 |
20120080808 | ADHESIVE COMPOSITION, PROCESS FOR PRODUCING THE SAME, ADHESIVE FILM USING THE SAME, SUBSTRATE FOR MOUNTING SEMICONDUCTOR AND SEMICONDUCTOR DEVICE - Disclosed is an adhesive composition which includes (a) an epoxy resin, (b) a curing agent and (c) a polymer compound incompatible with said epoxy resin, and further optionally includes (d) a filler and/or (e) a curing accelerator. Also disclosed are a process for producing an adhesive composition, including mixing (a) the epoxy resin and (b) the curing agent with (d) the filler, followed by mixing the resultant mixture with (c) the polymer compound incompatible with the epoxy resin; an adhesive film including the above-mentioned adhesive composition formed into a film; a substrate for mounting a semiconductor including a wiring board and the above-mentioned adhesive film disposed thereon on its side where chips are to be mounted; and a semiconductor device which includes the above-mentioned adhesive film or the substrate for mounting a semiconductor. | 2012-04-05 |
20120080809 | RESIN COMPOSITION FOR ENCAPSULATING SEMICONDUCTOR AND SEMICONDUCTOR DEVICE - Disclosed is a resin composition for encapsulating a semiconductor containing a curing agent, an epoxy resin (B) and an inorganic filler (C), wherein the curing agent is a phenol resin (A) having a predetermined structure. Also disclosed is a semiconductor device obtained by encapsulating a semiconductor element with a cured product of the resin composition for encapsulating a semiconductor. | 2012-04-05 |
20120080810 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The present invention provides a thin and bendable semiconductor device utilizing an advantage of a flexible substrate used in the semiconductor device, and a method of manufacturing the semiconductor device. The semiconductor device has at least one surface covered by an insulating layer which serves as a substrate for protection. In the semiconductor device, the insulating layer is formed over a conductive layer serving as an antenna such that the value in the thickness ratio of the insulating layer in a portion not covering the conductive layer to the conductive layer is at least 1.2, and the value in the thickness ratio of the insulating layer formed over the conductive layer to the conductive layer is at least 0.2. Further, not the conductive layer but the insulating layer is exposed in the side face of the semiconductor device, and the insulating layer covers a TFT and the conductive layer. | 2012-04-05 |
20120080811 | METHODS FOR FORMATION OF AN OPHTHALMIC LENS PRECURSOR AND LENS - This invention discloses methods for generating one or both of an ophthalmic lens precursor with at least a portion of one surface free-formed from a Reactive Mixture. In some embodiments, an ophthalmic lens precursor is formed on a substrate with an arcuate optical quality surface via a source of actinic radiation controllable to cure a definable portion of a volume of Reactive Mixture. | 2012-04-05 |
20120080812 | SYSTEMS FOR PURGING POLYETHYLENE TEREPHTHALATE FROM AN EXTRUSION BLOW MOLDING APPARATUS - A system for purging molten thermoplastic material from a molding apparatus. The purge system includes a blow mold apparatus, a purge diverter valve operably connected to the blow mold apparatus and including a channel, a closing member, a spacer having a conduit in communication with the channel, and a melt pipe. The system can be used to purge molten thermoplastic materials out from an upward extruding blow mold apparatus. | 2012-04-05 |
20120080813 | METHOD FOR THE MEASUREMENT OF THE TEMPERATURE OF A PLASTIFIED PLASTIC MATERIAL AT THE EXIT OF AN EXTRUDER - A method for the measurement of the temperature of a plastified plastic material at the exit of an extruder, characterized in that the function of the sound velocity in dependence of the temperature is measured and memorised for at least one plastified plastic material, the sound velocity is measured during the extrusion of the plastic material, and the respective temperature is determined from the velocity measurement values and the function. | 2012-04-05 |
20120080814 | Integratable Assisted Cooling System for Precision Extrusion Deposition in the Fabrication of 3D Scaffolds - The present invention relates to an integrated Assisting Cooling (AC) device, system and method for use with PED devices, allowing use of biopolymers having higher melting points in the fabrication of 3D scaffolds. The AC device cools the filament as it is extruding from the nozzle via low flow convective cooling. The AC device allows for cooling in the +/− direction of motion on an XY plane. The AC device elevates with the material delivery chamber. The AC device allows for scaffold fabrication at applied temperatures as high as about 250° C. | 2012-04-05 |
20120080815 | WIRE COOLING WATER TROUGH - The present invention generally relates to a cooling process and system that can be utilized in the manufacture of flexible elongate extruded materials, such as tubing or jacketed electrical wire and cable. More particularly, the present invention relates to a cooling trough for cooling flexible elongate extruded materials after extrusion. Cooling trough embodiments have a base, a wet cooling chamber above the base, and an air dry chamber above the wet cooling chamber. The base contains a reservoir for collecting and storing a cooling liquid. An extruded material, such as a cable, enters the wet cooling chamber, where the cooling liquid from the reservoir is sprayed onto the material, the material is then passed to the air dry chamber where it is dried. | 2012-04-05 |
20120080816 | APPARATUS AND METHOD FOR HEATING PLASTIC PREFORMS - An apparatus for heating containers, and in particular plastic preforms, comprises at least one microwave generating unit that generates an electromagnetic alternating field in the form of microwaves, a microwave transfer unit that transfers the microwaves generated by the microwave generating unit to a resonator unit, and a transport means that transports the plastic preforms relative to the resonator unit). The resonator unit includes a resonator housing forming a receiving chamber for heating the plastic preforms. The resonator unit is arranged such that the electric field lines (E) of an electric field that heats the container are arranged obliquely in relation to a longitudinal direction of the container. | 2012-04-05 |
20120080817 | APPARATUS AND METHOD OF PRODUCING OVAL PLASTICS MATERIAL CONTAINERS - An apparatus for tempering plastics material pre-forms with a tempering mould for tempering an outer wall of the plastics material pre-forms, wherein the tempering mould has at least one first mould part which is movable and wherein the first mould part contacts a first wall portion of the plastics material pre-form at least for a time, in order to temper this wall portion. The apparatus has a supply unit in order to supply the plastics material pre-forms to the tempering mould, and this supply unit has a holding device for holding the plastics material pre-forms as well as a movement device which, in order to supply the plastics material pre-forms into the tempering mould, produces a relative movement between the plastics material pre-form and at least one portion of at least one mould part in a longitudinal direction (L) of the plastics material pre-form. | 2012-04-05 |
20120080818 | MOLD FRAMES AND CAVITIES FOR MAKING DIMPLED GOLF BALLS - Universal mold frames for producing multi-piece golf balls are provided. The mold frames include lower and upper frame plates having locator pins that are inserted into corresponding locator slots in the mold cavities. The eccentric pin layout of the frame plates and corresponding slots in the cavities means the cavities can be fitted easily and aligned in the frame plates. The interior surfaces of the mold cavities define a specific dimple pattern such as icosahedron or tetrahedron-based patterns. The mold frames can accommodate cavities having different dimple patterns. A castable liquid polymer, for example, polyurethane is dispensed into the mold cavities, which are then pressed together to form the spherical cover for the ball. | 2012-04-05 |
20120080819 | PATTERNING MOLD AND MANUFACTURING METHOD THEREOF - Disclosed herein is a patterning mold to form a micropattern on a substrate or glass. The disclosed patterning mold includes a body having a patterning part formed at one end of the body. The patterning part may be configured to contact a surface of the substrate, to form a channel. In example embodiments, an ink supply passage communicating with the channel may be formed in the patterning mold, to supply an ink to the channel. In example embodiments, a fixing member is coupled to an exterior of the transfer body, to prevent or reduce deformation of the exterior of the transfer body. | 2012-04-05 |
20120080820 | IMPRINTING METHOD - Provided is an imprinting method for transferring a pattern formed on a mold to a substrate, the imprinting method including applying a resin to a predetermined shot area on the substrate; moving the shot area from an application position to an imprinting position; supplying gas to the shot area; and imprinting the mold into the shot area, wherein, in the gas supply step, gas is supplied only from a gas supplying unit located above a moving path extending from the application position to the imprinting position, and the supply of the gas is started before the shot area passes beneath the gas supplying unit to thereby supply the gas to the shot area while moving it. | 2012-04-05 |
20120080821 | MOLD RELEASE SHEET - A system for molding is provides and includes a first mold portion and a second mold portion. The first and second mold portions facilitate formation of a molded panel. A first sheet is inserted between the first mold portion and the second mold portion, such that the first sheet facilitates removal of the molded panel from the first mold portion. | 2012-04-05 |
20120080822 | Compatibilized Polypropylene and Polylactic Acid Blends and Methods of Making and Using Same - A composition comprising a blend of a polyolefin, polylactic acid, and a reactive modifier. A method of producing an oriented film comprising reactive extrusion compounding a mixture comprising polypropylene, polylactic acid, a reactive modifier to form a compatibilized polymeric blend, casting the compatibilized polymeric blend into a film, and orienting the film. A method of preparing a reactive modifier comprising contacting a polyolefin, a multifunctional acrylate comonomer, and an initiator under conditions suitable for the formation of an epoxy-functionalized polyolefin wherein the epoxy-functionalized polyolefin has a grafting yield of from 0.2 wt. % to 15 wt. %. | 2012-04-05 |
20120080823 | ENGINEERED WOOD FIBER PRODUCT SUBSTRATES AND THEIR FORMATION BY LASER PROCESSING - A laser is used to a form information indicative of a pattern on a surface of a support piece formed from a compressed wood fiber product substrate. The pattern can be a wood grain. The field of the laser is increased, to allow lazing more of the material at once. According to an embodiment, the field is increased in a way that does not reduce the resolution of the lasing. | 2012-04-05 |
20120080824 | CAST POLYURETHANE AND POLYUREA COVERS FOR GOLF BALLS - Compositions for golf balls that include thermoset polyurethane and/or thermoset polyurea In particular, the compositions of the invention, which are based on a polyurethane and/or polyurea, have improved crosslink density and hardness from crosslinking after the curative step. | 2012-04-05 |
20120080825 | IMPRINTING LITHOGRAPHY APPARATUS AND IMPRINTING LITHOGRAPHY METHOD - According to one embodiment, an imprint lithography apparatus includes an arithmetic unit calculating a mixing ratio of a demolding agent and a resist to be contained in a pattern forming agent on a basis of a pattern size formed on a template, a mixer mixing the resist and the demolding agent, a nozzle dropping the pattern forming agent on a substrate from the mixer, and an irradiation apparatus irradiating the pattern forming agent dropped on the substrate with light after pressing the template onto the pattern forming agent. | 2012-04-05 |
20120080826 | RESIN COMPOSITION FOR NANOIMPRINT, AND METHOD FOR FORMING STRUCTURE - A resin composition for nanoimprint includes a cationically polymerizable compound that has crystalline characteristics and is solid at ordinary temperature, and a photo cationic polymerization initiator. | 2012-04-05 |
20120080827 | Device for Forming Plastics Material Preforms into Plastics Material Containers with a Variable Output Rate - A device for forming plastics material preforms into plastics material containers includes a plurality of blowing stations, each comprising blow moulds, inside which preforms can be formed into containers. The device includes an admission arrangement to expose the preforms, for the forming thereof, to a free-flowing medium, and stretching rods to extend the preforms in the longitudinal direction thereof. The device includes a transport arrangement which transports the blowing stations with the preforms along a first predefined transport path, and a control arrangement which controls movement of the stretching rods and exposure of the preforms to the freeflowing medium so that predefined sub-steps of the forming process are carried out during transport of the preforms along the first path. Sub-steps of the forming process can be carried out irrespective of geometric position of the preforms along the first path, and an output rate of the device can thus be changed. | 2012-04-05 |
20120080828 | METHOD OF MANUFACTURING HONEYCOMB STRUCTURE - A method of manufacturing a honeycomb structure including a honeycomb unit includes causing inorganic particles to contain water. The inorganic particles have a specific surface area of approximately 50 m | 2012-04-05 |
20120080829 | VIBRATION ABSORPTION DEVICE - A floor portion ( | 2012-04-05 |
20120080830 | USER-SELECTABLE FORCE CONVERSION APPARATUS AND METHOD - A user-selectable force conversion apparatus includes a first and a second connecting member that are pivotally connected to each other between a sliding member and a fixed member. The apparatus also includes a leaf spring holder for removably retaining one or more leaf springs and loading the second connecting member with a substantially linear force response of the leaf springs. A user may change the combination of leaf springs and/or vary a length ratio for the first and second connecting members and thereby change the force response of the apparatus. Movement of the sliding member by the mechanical input may convert the substantially linear force response of the leaf springs to a user-selected force response for the mechanical input. A corresponding method is also disclosed. | 2012-04-05 |
20120080831 | DEVICE FOR RETAINING A TREAD BAND DURING TIRE RETREADING - An improvement in tire retreading is provided, and more specifically, a new device is provided for constraining a tread band onto the tire casing during retreading operations without requiring enclosure of the tread area. One or more membranes engage features on the tread band so as to apply a tensioning force to the tread band and thereby maintain the position of the tread band against the casing of the tire. The tensioning force is applied without enveloping the entire tread region of the tread band within the membrane(s). | 2012-04-05 |
20120080832 | DEVICES FOR METHODOLOGIES RELATED TO WAFER CARRIERS - Disclosed are systems, devices and methodologies for handling wafers in wafer processing operations through use of wafer carriers. In an example situation, a wafer carrier can be configured as a plate to allow bonding of a wafer thereto to provide support for the wafer during some processing operations. Upon completion of such operations, the processed wafer can be separated from the support plate so as to allow further processing. Various devices and methodologies related to such wafer carriers for efficient handling of wafers are disclosed. | 2012-04-05 |
20120080833 | IMAGE RECORDING DEVICE - An image recording device includes a housing, a tray unit mounted in the housing and configured to hold thereon sheets, a feeder configured to feed a sheet from the tray unit, a recording unit configured to record an image on the sheet fed by the feeder, and a discharging unit configured to discharge the sheet after the recording unit records the image on the sheet. The tray unit includes a first tray including a first holding surface for holding thereon a first sheet, a second tray includes a second holding surface for holding thereon a second sheet and configured to move above the first holding surface between a first position and a second position, and a third tray supported by the first tray and disposed above the second tray in the second position, and configured to receive the sheet discharged by the discharging unit. | 2012-04-05 |
20120080834 | SHEET FEED DEVICE AND IMAGE RECORDING APPARATUS HAVING SUCH SHEET FEED DEVICE - An image recording apparatus including a first tray having a first holding portion for holding sheets, a second tray disposed above the first tray and including a second holding portion for holding sheets, a sheet feeder that selectively feeds a sheet from one of the first tray and the second tray in a sheet feed direction, a recording unit that records an image on the sheet fed by the sheet feeder, and a discharge roller that discharges the sheet on which the image is recorded by the recording unit. The second holding portion of the second tray moves above the first holding portion of the first tray. The second tray further includes a discharged sheet receiving portion for receiving the sheet discharged by the discharge roller. The second tray including the discharged sheet receiving portion pivots relative to the first tray. | 2012-04-05 |
20120080835 | SERVO EDGE PRESSING PAPER FEEDING DEVICE - A paper feeding mechanism includes a vacuum absorption variable-speed paper feeding mechanism and a vacuum absorption constant-speed paper feeding mechanism, two edge pressing wheels are installed on a edge pressing paper feeding shaft arranged above a constant-speed paper feeding wheel in the middle, the gaps between the edge pressing wheels and the constant-speed paper feeding wheel in the middle are smaller than the thickness of a paper board, and the distance between the two edge pressing wheels is adjusted by moving on the edge pressing paper feeding wheel shaft. | 2012-04-05 |
20120080836 | Sheet feeder and image forming apparatus including the same - A sheet feeder includes: a friction pad held by a pad holder; and a separation roller that is in contact with the friction pad while in rotation. A separation nip formed between the friction pad and the separation roller separates a recording medium from a plurality of recording media fed into the separation nip, and the pad holder includes a convex portion that is provided downstream of the friction pad in a sheet feeding direction and at a middle portion in a first width direction perpendicular to the sheet feeding direction and that is capable of coming into contact with the recording medium. | 2012-04-05 |
20120080837 | SYSTEM AND METHOD FOR ROTATING SHEETS - This invention provides a system and method for rotating sheets, receiving cut sheets and providing them to a utilization device. The rotator continually engages sheets with a drive or rotation component throughout the transport and rotation process. The rotator includes a transport mechanism having nip roller pairs. The nip rollers can be engaged with, and disengaged from, the driven rollers. This allows for feed velocity differentials when entering and exiting the rotator feed table, and for clearance during sheet rotation. A rotator disk assembly is centered on the table, and comprises a driven rotator disk and an overriding, pressure disk. When sheets enter or pass through the rotator section, the pressure disk is raised to provide a clearance. Sheets are rotated by lowering the pressure disk and raising surrounding nips to provide clearance for the disk to turn. Nips can then be lowered to drive the rotated sheet downstream. | 2012-04-05 |
20120080838 | SHEET CONVEYING APPARATUS AND IMAGE FORMING APPARATUS - A sheet conveying apparatus including: a conveying roller pair conveying a sheet by a nip portion; a shutter portion which is rotatably supported on a rotary shaft of the first conveying roller; a same radius portion, provided in the shutter portion, which is formed to have substantially the same radius as a radius of the first conveying roller; an abutment portion, provided in the shutter portion, and against which the leading edge of the sheet is abutted; and a boundary portion, provided in a boundary of the abutment portion and the same radius portion, which guides the leading edge of the sheet to the nip portion when the shutter portion is rotated by abutting the leading edge of the sheet against the boundary portion. | 2012-04-05 |
20120080839 | DOCUMENT HOLDING DEVICE FOR AN IMAGE PROCESSING SYSTEM - A first rack of a pair of document guides slides in pressing contact against a pinion due to contact with a protrusion. As a result, the first rack is subjected to a larger sliding resistance than when the protrusion is not provided. When one of the document guides is operated, the operating force transmits directly to the first rack. Therefore, if a large force corresponding to the sliding resistance increased by the protrusion is applied, the first rack can be slid. When the other document guide is operated, the operating force transmits to the first rack through the pinion. Therefore, the sliding resistance increased by the protrusion increases due to the gear efficiency of the pinion. | 2012-04-05 |