14th week of 2011 patent applcation highlights part 5 |
Patent application number | Title | Published |
20110079789 | DISPLAY PANEL - A display panel includes a plurality of pads, a plurality of first contacts connected to the pads, a plurality of second contacts provided so as to be opposed to the plurality of first contacts, a polysilicon layer configured to form a plurality of polysilicon films to connect the plurality of first contacts and second contacts, and a gate metal layer. The gate metal layer forms at least one gate metal. The gate metal layer traverses the plurality of polysilicon films so as to form a plurality of transistors. The plurality of transistors are arranged in a zigzag pattern for each transistor set. A width of a portion of each of the polysilicon films, the portion forming a corresponding one of the transistors, is larger than a width of another portion of the polysilicon films. The other portion is connected to a corresponding one of the first contacts and second contacts. | 2011-04-07 |
20110079790 | GROUP III NITRIDE SEMICONDUCTOR ELEMENT AND EPITAXIAL WAFER - A primary surface | 2011-04-07 |
20110079791 | BETAVOLTAIC CELL - High aspect ratio micromachined structures in semiconductors are used to improve power density in Betavoltaic cells by providing large surface areas in a small volume. A radioactive beta-emitting material may be placed within gaps between the structures to provide fuel for a cell. The pillars may be formed of SiC. In one embodiment, SiC pillars are formed of n-type SiC. P type dopant, such as boron is obtained by annealing a borosilicate glass boron source formed on the SiC. The glass is then removed. In further embodiments, a dopant may be implanted, coated by glass, and then annealed. The doping results in shallow planar junctions in SiC. | 2011-04-07 |
20110079792 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE - Provided are a semiconductor device and a method of fabricating the semiconductor device, the semiconductor device including: a source trace, a drain trace, and a gate trace placed on a substrate; a transistor which is placed on the drain trace and includes a source pad and a gate pad; insulating films placed between the drain and source traces and between the drain and gate traces on the substrate so as to cover sidewall surfaces of the transistor; a source spray electrode which is placed on the insulating film between the source and drain traces and connects the source pad of the transistor and the source trace; and a gate spray electrode placed on the insulating film between the gate and drain traces and connects the gate pad of the transistor and the gate trace. | 2011-04-07 |
20110079793 | SEMICONDUCTOR SUBSTRATE AND ITS MANUFACTURING METHOD - A semiconductor substrate includes: a substrate having a single crystal silicon on at least one surface thereof; a buffer layer that is provided on the single crystal silicon and has at least one cobalt silicide layer primarily containing cobalt silicide; and a silicon carbide single crystal film provided on the buffer layer. | 2011-04-07 |
20110079794 | METHOD FOR MANUFACTURING ELECTRONIC DEVICES INTEGRATED IN A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICES - A method manufactures a vertical power MOS transistor on a semiconductor substrate comprising a first superficial semiconductor layer of a first conductivity type, comprising: forming trench regions in the first semiconductor layer, filling in said trench regions with a second semiconductor layer of a second conductivity type, to form semiconductor portions of the second conductivity type contained in the first semiconductor layer, carrying out an ion implantation of a first dopant type in the semiconductor portions for forming respective implanted body regions of said second conductivity type, carrying out an ion implantation of a second dopant type in one of the implanted body regions for forming an implanted source region of the first conductivity type inside one of the body regions, carrying out an activation thermal process of the first and second dopant types with low thermal budget suitable to complete said formation of the body and source regions. | 2011-04-07 |
20110079795 | SEMICONDUCTOR LIGHT EMITTING DEVICE, ILLUMINATION MODULE, ILLUMINATION APPARATUS, METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light emitting device ( | 2011-04-07 |
20110079796 | NANO STRUCTURED LEDS - An embodiment relates to a nanowire-containing LED device with optical feedback comprising a substrate, a nanowire protruding from a first side the substrate, an active region to produce light, a optical sensor and a electronic circuit, wherein the optical sensor is configured to detect at least a first portion of the light produced in the active region, and the electronic circuit is configured to control an electrical parameter that controls a light output of the active region. Yet, another embodiment relates to an image display having the nanowire-containing LED device with optical feedback. | 2011-04-07 |
20110079797 | DISPLAY DEVICE - A display device includes an array of pixels including a plurality of organic EL elements each having a pair of electrodes and an organic compound layer including a light-emitting layer and disposed between the pair of electrodes and includes a protective layer disposed on the plurality of the organic EL elements. The protective layer has a first protective layer made of an inorganic material, a second protective layer made of a resin material and disposed on the first protective layer, and a third protective layer made of an inorganic material and disposed on the second protective layer. The second protective layer includes lenses for diverging at least part of light emitted from the light-emitting layer. The lenses have an elongated concave shape. | 2011-04-07 |
20110079798 | Light emitting apparatus - A light emitting apparatus includes a plurality of single crystal semiconductor thin films that emit light. The single crystal semiconductor thin films are secured in intimate contact to the surface of a substrate or a bonding layer formed on the substrate. A first conductive electrode is formed on the single crystal semiconductor thin film and is connected to a first conductive side metal layer. The first conductive side metal layer is closer to the surface of the substrate than a top surface of the single crystal semiconductor thin film. A second conductive electrode is formed on the single crystal semiconductor thin film. A second conductive side metal layer is connected to the second conductive electrode. The second conductive side metal layer is closer to the surface of the substrate than the top surface of the single crystal semiconductor thin film. | 2011-04-07 |
20110079799 | ANISOTROPIC CONDUCTIVE FILM AND DISPLAY DEVICE HAVING THE SAME - An anisotropic conductive film (ACF) is disclosed. The ACF includes a film, an adhesive layer positioned on the film, and one or more conductive balls within the adhesive layer. The conductive balls include a first core part having a first hardness, a second core part covering the first core part and having a second hardness that is greater than the first hardness, and a conductive part covering the second core part, respectively. | 2011-04-07 |
20110079800 | LIGHT EMITTING ELEMENT - A light emitting element according to an embodiment of the invention includes a semiconductor substrate, a light emitting part having a first conductivity type first cladding layer; a second conductivity type second cladding layer different from the first cladding layer in the conductivity type and an active layer sandwiched between the first cladding layer and the second cladding layer, a reflecting part for reflecting a light emitted from the active layer, disposed between the semiconductor substrate and the light emitting part so as to have a thickness of 1.7 μm to 8.0 μm and an electric current dispersing layer disposed on a side of the light emitting part opposite to the reflecting part, having a uneven part on the surface thereof, wherein the reflecting part is formed so as to have at least three pair layers formed of a first semiconductor layer and a second semiconductor layer different from the first semiconductor layer, the first semiconductor layer has a thickness T | 2011-04-07 |
20110079801 | OPTOELECTRONIC DEVICES WITH LAMINATE LEADLESS CARRIER PACKAGING IN SIDE-LOOKER OR TOP-LOOKER DEVICE ORIENTATION - A laminate leadless carrier package comprising an optoelectronic chip, a substrate supporting the chip, the substrate comprising a plurality of conductive and dielectric layers; a wire bond coupled to the optoelectronic chip and a wire bond pad positioned on the top surface of the substrate; an encapsulation covering the optoelectronic chip, the wire bond, and at least a portion of the top surface of the substrate, wherein the encapsulation is a molding compound; and wherein the package is arranged to be mounted as a side-looker. A process for manufacturing laminate leadless carrier packages, comprising preparing a substrate; applying epoxy adhesive to a die attach pad; mounting an optoelectronic chip on the die attach pad; wire-bonding the optoelectronic chip; molding a molding compound to form an encapsulation covering the optoelectronic chip, a wire bond, and the top surface of the substrate; and dicing the substrate into individual packages. | 2011-04-07 |
20110079802 | LIGHT EMITTER - Embodiments of light sources are disclosed herein. An embodiment of the light source comprises a lead frame having a first side and a second side. A hole extends through the lead frame between the first side and the second side. An adhesive is located in the hole and extends beyond the hole, wherein the adhesive extends beyond the diameter of the hole on the first side and the second side of the first lead frame. A light emitter adhered to the adhesive proximate the first side of the first lead frame. | 2011-04-07 |
20110079803 | Carrying Structure of Semiconductor - A carrying structure of semiconductor includes a carrier made of a plastic material with a heat conduction region, each surface of the carrier has an interface layer formed on, and an electrically insulation circuit and a metal layer are defined on the interface layer. The insulation circuit is located on the surface of the heat conduction region and on an encircling annular region extended from two surfaces of the heat conduction region, and at the same time exposing parts of the carrier surface thereby splitting the metal layer on the interface layer into at least two electrodes. A thermal conductor formed in the heat conduction region has a LED chip adhered on it which has at least a contact point connected with the corresponding metal layer with a metal wiring so as to dissipate the heat generated by the chip rapidly with the thermal conductor. | 2011-04-07 |
20110079804 | POLARIZED LIGHT EMITTING DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a polarized light emitting diode (LED) device and the method for manufacturing the same, in which the LED device comprises: a base, a light emitting diode (LED) chip, a polarizing waveguide and a packaging material. In an exemplary embodiment, the LED chip is disposed on the base and is configured with a first light-emitting surface for outputting light therefrom; and the waveguide, being comprised of a polarization layer, a reflection layer, a conversion layer and a light transmitting layer, is disposed at the optical path of the light emitted from the LED chip; and the packaging material is used for packaging the waveguide, the LED chip and the base into a package. | 2011-04-07 |
20110079805 | LIGHT-EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - A light-emitting diode and a method for manufacturing the same are described. The light-emitting diode includes a bonding substrate, a first conductivity type electrode, a bonding layer, an epitaxial structure, a second conductivity type electrode, a growth substrate and an encapsulant layer. The first conductivity type electrode and the bonding layer are respectively disposed on two surfaces of the bonding substrate. The epitaxial structure includes a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer. A trench is set around the epitaxial structure and extends from the second conductivity type semiconductor layer to the first conductivity type semiconductor layer. The second conductivity type electrode is electrically connected to the second conductivity type semiconductor layer. The growth substrate is disposed on the epitaxial structure and includes a cavity exposing the epitaxial structure and the trench. The encapsulant layer is filled in the cavity. | 2011-04-07 |
20110079806 | LIGHT-EMITTING DIODE STRUCTURE - A light-emitting diode structure is provided. The light-emitting diode structure includes a light-emitting diode chip, a lead frame for electrically connecting and supporting the light-emitting diode chip, and a lens covering the light-emitting diode chip and to partially cover the lead frame. A recess disposed on the upper portion of the lens has a ladder-like inner wall formed of an upper inclined wall portion, a lower inclined wall portion, and a connecting wall portion connected to the upper and lower inclined wall portions. The slope of the upper inclined wall portion is greater than that of the lower inclined wall portion, and the slope of the connecting wall portion is greater than the upper and lower inclined wall portions. | 2011-04-07 |
20110079807 | LIGHT-EMITTING DIODE STRUCTURE - A light-emitting diode structure includes a base with a recessed portion, a light-emitting chip and a light-transmissive block. The light-emitting chip disposed in the recessed portion of the base and emits a light beam. The light-transmissive block disposed on the base covers the recessed portion and the light-emitting chip, so that the light beam emitted from the light-emitting chip is radiated outwardly via the light-transmissive block. The light-transmissive block is a flat-top multilateral cone including a bottom surface, a top surface, and several side surfaces connected to and located between the bottom surface and the top surface. A slot with a bottom portion is formed on the top surface of the light-transmissive block. | 2011-04-07 |
20110079808 | LIGHT EMITTING DIODE - A light emitting diode is provided, including an LED chip, a reflector, a lens, a circuit plate, a circuit substrate and an electrical conductivity device. The LED chip is disposed in the reflector and the lens is disposed on the reflector, covering the reflector and the LED chip. The LED chip is electrically connected to the circuit plate. The circuit plate further includes a first through hole therein and the circuit substrate further includes a second through hole therein. The electrical conductivity device passes through the first through hole and the second through hole so that the circuit plate is electrically connect to the circuit substrate. The reflector is installed between the circuit plate and the circuit substrate. The first through hole and the second through hole are not connected to the reflector. | 2011-04-07 |
20110079809 | OPTICAL MODULE INSTALLING OPTICAL DEVICE WITH IDENTIFYING MARK VISUALLY INSPECTED AFTER ASSEMBLY THEREOF - An optical module is described, where the optical module installs an optical device whose identification mark is able to be distinguished even after the optical device is installed in the optical module. The identifying mark of the optical device is formed in a position able to be inspected from the direction of the normal line of the light-emitting facet of the optical device. Accordingly, the identifying mark becomes able to be identified through the lens after the optical device is installed in the package of the optical module. | 2011-04-07 |
20110079810 | Optoelectronic Semiconductor Chip Comprising a Reflective Layer - An optoelectronic semiconductor chip is specified, comprising a first contact location ( | 2011-04-07 |
20110079811 | SEMICONDUCTOR CHIP ASSEMBLY WITH BUMP/BASE HEAT SPREADER AND DUAL-ANGLE CAVITY IN BUMP - A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a bump that includes first, second and third bent corners that shape a cavity. The conductive trace includes a pad and a terminal. The semiconductor device is located within the cavity, is electrically connected to the conductive trace and is thermally connected to the bump. The bump extends into an opening in the adhesive and provides a recessed die paddle and a reflector for the semiconductor device. The conductive trace provides signal routing between the pad and the terminal. | 2011-04-07 |
20110079812 | LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed are a light emitting device and a method for manufacturing the same. The light emitting device includes a substrate having a lead frame, a light emitting diode mounted on the substrate, a mold member formed on the substrate and the light emitting diode, and a reflecting member having an opening portion at one side thereof and being inclined at an outer portion of the mold member. | 2011-04-07 |
20110079813 | VERTICAL GALLIUM NITRIDE-BASED LIGHT EMITTING DIODE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a vertical GaN-based LED comprises forming a light emission structure in which an n-type GaN-based semiconductor layer, an active layer, and a p-type GaN-based semiconductor layer are sequentially laminated on a substrate; etching the light emission structure such that the light emission structure is divided into units of LED; forming a p-electrode on each of the divided light emission structures; filling a non-conductive material between the divided light emission structures; forming a metal seed layer on the resulting structure; forming a first plated layer on the metal seed layer excluding a region between the light emission structures; forming a second plated layer on the metal seed layer between the first plated layers; separating the substrate from the light emission structures; removing the non-conductive material between the light emission structures exposed by separating the substrate; forming an n-electrode on the n-type GaN-based semiconductor layer; and removing portions of the metal seed layer and the second plated layer between the light emission structures. | 2011-04-07 |
20110079814 | LIGHT EMITTED DIODE SUBSTRATE AND METHOD FOR PRODUCING THE SAME - A method for producing the LED substrate has steps of: p providing a conductive metallic board, forming multiple grooves in a top of the conductive metallic board; protecting the conductive metallic board from corrosion, forming an etched substrate with circuits and wires for plating on the conductive metallic board, electroless plating the etched substrate to form an electroless plated substrate, plating metal on the electroless plated substrate, and coating solder mask to obtain the LED substrate. Because LED chips are mounted on the surfaces of the metal layer without insulating adhesive below, heat from LED chips can be dissipated efficiently. The LED substrate of the present invention can be soldered directly onto a dissipation module to further enhance dissipation efficiency. | 2011-04-07 |
20110079815 | ORGANIC ELECTROLUMINESCENCE DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, an organic EL device includes an insulating substrate, a pixel electrode disposed above the insulating substrate, an organic layer disposed on the pixel electrode, a counter-electrode disposed on the organic layer, at least one of a first recess portion in which the organic layer and the counter-electrode are missing on the pixel electrode, and a second recess portion in which the counter-electrode is missing on the organic layer, and a protection film covering the counter-electrode and the at least one of the first recess portion and the second recess portion. | 2011-04-07 |
20110079816 | OPTICAL-SEMICONDUCTOR ENCAPSULATING MATERIAL - The present invention relates to a sheet-shaped optical-semiconductor encapsulating material including: a first resin layer containing inorganic particles; and a second resin layer containing a phosphor and being superposed directly or indirectly on the first resin layer, and relates to a kit for optical-semiconductor encapsulation including: a sheet-shaped molded body including a first resin layer containing inorganic particles; and a sheet-shaped molded body including a second resin layer containing a phosphor. | 2011-04-07 |
20110079817 | LIGHT-EMITTING ELEMENT AND LIGHT-EMITTING DEVICE - An object is to provide a highly functional and reliable light-emitting element and light-emitting device with lower power consumption and high emission efficiency. The light-emitting element has an EL layer that has a stacked structure including a light-emitting element containing an organic compound and a functional layer having separate functions between a pair of electrode layers. In the light-emitting element including the functional layer and the light-emitting element containing an organic compound, a mixed-valence compound is contained in the functional layers. When an element in a compound has a plurality of valences, this element is in a state that is referred to as a mixed-valence state and this compound is referred to as a mixed-valence compound. | 2011-04-07 |
20110079818 | Semiconductor circuit including electrostatic discharge circuit having protection element and trigger transistor - A semiconductor circuit includes a first pad for a first power source, a second pad for a second power source, a third pad for an input/output signal, a protection element arranged between the first pad and the third pad, and a transistor functioning as a trigger element for use in passing a trigger current through the protection element. The transistor includes source connected to the third pad, a gate and a backgate commonly connected to the second pad. | 2011-04-07 |
20110079819 | IGBT WITH FAST REVERSE RECOVERY TIME RECTIFIER AND MANUFACTURING METHOD THEREOF - An IGBT with a fast reverse recovery time rectifier includes an N-type drift epitaxial layer, a gate, a gate insulating layer, a P-type doped base region, an N-type doped source region, a P-type doped contact region, and a P-type lightly doped region. The P-type doped base region is disposed in the N-type drift epitaxial layer, and the P-type doped contact region is disposed in the N-type drift epitaxial layer. The P-type lightly doped region is disposed between the P-type contact doped region and the N-type drift epitaxial layer, and is in contact with the N-type drift epitaxial layer. | 2011-04-07 |
20110079820 | DEVICE WITH SELF ALIGNED STRESSOR AND METHOD OF MAKING SAME - A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material. | 2011-04-07 |
20110079821 | Integrated Devices on a Common Compound Semiconductor III-V Wafer - A method of fabricating an integrated circuit on a compound semiconductor III-V wafer including at least two different types of active devices by providing a substrate; growing a first epitaxial structure on the substrate; growing a second epitaxial structure on the first epitaxial structure; and processing the epitaxial structures to form different types of active devices, such as HBTs and FETs. | 2011-04-07 |
20110079822 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A compound semiconductor device includes an electron transit layer; an electron supply layer formed over the electron transit layer; a first recessed portion and a second recessed portion formed in the electron supply layer; a chemical compound semiconductor layer including impurities that buries the first recessed portion and the second recessed portion and covers over the electron supply layer; a source electrode formed over the chemical compound semiconductor layer which buries the first recessed portion; a drain electrode formed over the chemical compound semiconductor layer which buries the second recessed portion; and a gate electrode formed over the electron supply layer between the source electrode and the drain electrode, wherein, in the chemical compound semiconductor layer, a concentration of impurities included below the source electrode and the drain electrode is higher than a concentration of impurities included near the gate electrode. | 2011-04-07 |
20110079823 | VERTICAL TRANSISTOR AND ARRAY OF VERTICAL TRANSISTOR - A vertical transistor includes a substrate, a gate, a source region, a drain region, a channel region and a gate dielectric layer. A trench is formed in the substrate, and the gate is disposed in the trench. The source region is disposed in the substrate beneath the gate. The drain region is disposed above the gate. The channel region is disposed at two sides of the gate and located between the source region and the drain region. The gate dielectric layer is located between the gate and the channel region. | 2011-04-07 |
20110079824 | ALTERNATE 4-TERMINAL JFET GEOMETRY TO REDUCE GATE TO SOURCE CAPACITANCE - A 4-Terminal JFET includes a substrate having a first conduction type and an upper layer having a second, opposite, conduction type over the substrate. A gate and a source are embedded in the upper layer. A gate pad is electrically connected to the gate. A region, which has a first conduction type, is formed in the upper layer and separates the upper layer into two sections. This region reduces the overall capacitance between the gate pad and the source. Reduced overall gate to source capacitance can result in reduced noise amplification in the JFET. | 2011-04-07 |
20110079825 | Cascoded high voltage junction field effect transistor - A cascoded junction field transistor (JFET) device comprises a first stage high voltage JFET cascoded to a second stage low voltage JFET wherein one of the first and second stages JFET is connected to a drain electrode of another JFET stage. | 2011-04-07 |
20110079826 | SEMICONDUCTOR DEVICE, METHOD FOR FABRICATING THE SAME AND APPARATUS FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a gate electrode on a surface of a substrate via a gate insulating film, forming an insulating film on a side surface of the gate electrode, and exposing an oxygen plasma onto the surface of the substrate. An electron temperature of the oxygen plasma in a vicinity of the surface of the substrate is equal to or less than about 1.5 eV. | 2011-04-07 |
20110079827 | STRUCTURE AND METHOD TO CREATE A DAMASCENE LOCAL INTERCONNECT DURING METAL GATE DEPOSITION - A method and structure to create damascene local interconnect during metal gate deposition. A method includes: forming a gate dielectric on an upper surface of a substrate; forming a mandrel on the gate dielectric; forming an interlevel dielectric (ILD) layer on a same level as the mandrel; forming a trench in the ILD layer; removing the mandrel; and forming a metal layer on the gate dielectric and in the trench. | 2011-04-07 |
20110079828 | METAL GATE FET HAVING REDUCED THRESHOLD VOLTAGE ROLL-OFF - A structure and method to create a metal gate having reduced threshold voltage roll-off. A method includes: forming a gate dielectric material on a substrate; forming a gate electrode material on the gate dielectric material; and altering a first portion of the gate electrode material. The altering causes the first portion of the gate electrode material to have a first work function that is different than a second work function associated with a second portion of the gate electrode material. | 2011-04-07 |
20110079829 | FINFETS AND METHODS FOR FORMING THE SAME - A Fin field effect transistor (FinFET) includes a fin-channel body over a substrate. A gate electrode is disposed over the fin-channel body. At least one source/drain (S/D) region is disposed adjacent to the fin-channel body. The at least one S/D region is substantially free from including any fin structure. | 2011-04-07 |
20110079830 | METAL GATE STRUCTURE AND METHOD OF MANUFACTURING SAME - A method of manufacturing a metal gate structure includes providing a substrate ( | 2011-04-07 |
20110079831 | Metal Oxide Semiconductor Field Effect Transistors (MOSFETS) Including Recessed Channel Regions - Unit cells of metal oxide semiconductor (MOS) transistors are provided having an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is between the source region and the drain region. A channel region is provided between the source and drain regions. The channel region has a recessed region that is lower than bottom surfaces of the source and drain regions. Related methods of fabricating transistors are also provided. | 2011-04-07 |
20110079832 | SOLID-STATE IMAGE PICKUP DEVICE, IMAGE PICKUP APPARATUS INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A solid-state image pickup device includes: a semiconductor substrate; and a plurality of pixel circuits formed on the semiconductor substrate; each of the plurality of pixel circuits formed on the semiconductor substrate including a photoelectric conversion element, a first buried gate electrode formed adjacent to the photoelectric conversion element, a second buried gate electrode formed away from each of the photoelectric conversion element and the first buried gate electrode, a first diffusion layer formed between the first buried gate electrode and the second buried gate electrode, and a second diffusion layer formed between the first buried gate electrode and the second buried gate electrode away from the first diffusion layer so as to overlap the first diffusion layer; wherein electric charges accumulated in the photodiode conversion element are transferred to the second diffusion layer through the first diffusion layer. | 2011-04-07 |
20110079833 | Semiconductor device and method for manufacturing same - A hard mask material film is formed on a semiconductor substrate and a recess is formed immediately below an opening in an upper surface of the semiconductor substrate. Next, a p-type region is formed immediately below the recess by implanting impurities into an imaging region using the hard mask material film as a mask. Moreover, a trench is formed by further processing the recess in a processing region. A half-buried dielectric film and a STI are formed by burying a dielectric material in the recess and the trench to remove the hard mask material film. Next, two electrodes are formed so as to overlap the half-buried dielectric film and the STI, respectively, and impurities are implanted into the imaging region using one electrode and the half-buried dielectric film as a mask, and hence a n-type region constituting a photodiode is formed in a region being in contact with the p-type region in the semiconductor substrate. | 2011-04-07 |
20110079834 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device has: a MISFET having source/drain diffusion layers; first plugs respectively connected to the source/drain diffusion layers; a first interconnection connected to one of the source/drain diffusion layers through the first plug; a second plug electrically connected to the other Of the source/drain diffusion layers through the first plug; a second interconnection connected to the second plug; and a capacitor electrode located above a gate electrode of the MISFET. The first interconnection is formed not above the lower capacitor electrode, while the second interconnection is formed above the upper capacitor electrode. A plug connecting the first interconnection and another interconnection is not provided at an upper location of the one of the source/drain diffusion layers. The first interconnection is not provided at an upper location of the other of the source/drain diffusion layers. | 2011-04-07 |
20110079835 | SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL HAVING CHARGE ACCUMULATION LAYER - A semiconductor device includes MOS transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The MOS transistor and the capacitor element are formed on a first one of the element regions and a second one of the element regions, respectively. In the voltage generating circuit, current paths of the MOS transistors are series-connected and the capacitor elements are connected to the source or drain of the MOS transistors. The contact plug is formed on the source or the drain to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements. A distance between the gate and the contact plug both for a first one of the MOS transistors located in the final stage in the series connection is larger than that for a second one of the MOS transistors located in the initial stage in the series connection. | 2011-04-07 |
20110079836 | DRAM CELL WITH DOUBLE-GATE FIN-FET, DRAM CELL ARRAY AND FABRICATION METHOD THEREOF - A transistor structure includes a semiconductor substrate having a top surface and sidewalls extending downward from the top surface, wherein each of the sidewall comprises a vertical upper sidewall surface and a lower sidewall recess laterally etched into the semiconductor substrate. A trench fill dielectric region is inlaid into the top surface of the semiconductor substrate. Two source/drain regions are formed into the top surface of the semiconductor substrate and are sandwiched about the trench fill region. A buried gate electrode is embedded in the lower sidewall recess. A gate dielectric layer is formed on surface of the lower sidewall recess between the semiconductor substrate and the buried gate electrode. | 2011-04-07 |
20110079837 | CAPACITOR, METHOD OF INCREASING A CAPACITANCE AREA OF SAME, AND SYSTEM CONTAINING SAME - A capacitor includes a substrate ( | 2011-04-07 |
20110079838 | NON-VOLATILE MEMORY DEVICE - A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed. | 2011-04-07 |
20110079839 | Non-Volatile Memory Devices Having Reduced Susceptibility to Leakage of Stored Charges and Methods of Forming Same - Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode. The tunnel insulating layer is disposed over the substrate. The charge storage pattern is disposed over the tunnel insulating layer. The charge storage pattern has an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall. The blocking layer includes an insulating pattern covering the edge portion of the charge storage pattern, and a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. The gate electrode is disposed over the blocking layer, the gate electrode covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. | 2011-04-07 |
20110079840 | MEMORY CELL AND MANUFACTURING METHOD THEREOF AND MEMORY STRUCTURE - A memory cell is provided. The memory cell includes a substrate, an isolation layer, a gate, a charge storage structure, a first source/drain region, a second source/drain region and a channel layer. The isolation layer is disposed over the substrate. The gate is disposed over the isolation layer. The charge storage structure is disposed over the isolation layer and the gate. The first source/drain region is disposed over the charge storage structure at two sides of the gate. The second source/drain region is disposed over the charge storage structure at top of the gate. The channel layer is disposed over the charge storage structure at sidewall of the gate and is electrically connected with the first source/drain region and the second source/drain region. | 2011-04-07 |
20110079841 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device which has a CMOS inverter circuit and which can accomplish high-integration by configuring an inverter circuit with a columnar structural body. A semiconductor device includes a columnar structural body which is arranged on a substrate and which comprises a p-type silicon, an n-type silicon, and an oxide arranged between the p-type silicon and the n-type silicon and running in the vertical direction to the substrate, n-type high-concentration silicon layers arranged on and below the p-type silicon, p-type high-concentration silicon layers arrange on and below the n-type silicon, an insulator which surrounds the p-type silicon, the n-type silicon, and the oxide, and which serves as a gate insulator, and a conductive body which surrounds the insulator and which serves as a gate electrode. | 2011-04-07 |
20110079842 | SEMICONDUCTOR DEVICE - A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE is formed as a film at the same layer level as a source electrode SE electrically connected to a source region formed between adjacent stripe-shaped grooves and the gate electrode GE is constituted of a gate electrode portion G | 2011-04-07 |
20110079843 | POWER SEMICONDUCTOR DEVICES, METHODS, AND STRUCTURES WITH Embedded Dielectric Layers Containing Permanent Charges - Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region. | 2011-04-07 |
20110079844 | Trench mosfet with high cell density - A trench MOSFET with high cell density is disclosed where there is a heavily doped contact region on the top surface of mesas between a pair of gate trenches. The present invention can prevent the degradation of avalanche capability when shrinking the device in prior art. | 2011-04-07 |
20110079845 | Planar TMBS rectifier - A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench. An interconnect layer electrically contacts the semiconductor layer in the Schottky region so as to form a Schottky contact with the semiconductor layer. | 2011-04-07 |
20110079846 | HIGH VOLTAGE DEVICES, SYSTEMS, AND METHODS FOR FORMING THE HIGH VOLTAGE DEVICES - A high voltage (HV) device includes a gate dielectric structure over a substrate. The gate dielectric structure has a first portion and a second portion. The first portion has a first thickness and is over a first well region of a first dopant type in the substrate. The second portion has a second thickness and is over a second well region of a second dopant type. The first thickness is larger than the second thickness. A gate electrode is disposed over the gate dielectric structure. A metallic layer is over and coupled with the gate electrode. The metallic layer extends along a direction of a channel under the gate dielectric structure. At least one source/drain (S/D) region is disposed within the first well region of the first dopant type. | 2011-04-07 |
20110079847 | Semiconductor Device - Provided is a semiconductor device capable of easily setting a holding voltage with a low trigger voltage by locally forming a P-type diffusion layer between N-type source and drain diffusion layers of an NMOS transistor having a conventional drain structure used as an electrostatic protective element of the semiconductor device. | 2011-04-07 |
20110079848 | SEMICONDUCTOR DEVICE WITH DUMMY GATE ELECTRODE AND CORRESPONDING INTEGRATED CIRCUIT AND MANUFACTURING METHOD - A field effect transistor semiconductor device configuration is described, which is particularly suitable for use in DC: DC converters associated with logic circuitry. The device includes a first gate electrode ( | 2011-04-07 |
20110079849 | LATERAL-DIFFUSION METAL-OXIDE-SEMICONDUCTOR DEVICE - A lateral-diffusion metal-oxide-semiconductor device includes a source in a racetrack shaped active area, a first field oxide region isolating and surrounding the racetrack shaped active area, a racetrack shaped gate surrounding the source, and a drain disposed at one side of the gate opposite to the source. The source includes a P+ doping region in a P well and an N+ doping region butting on the P+ doping region. | 2011-04-07 |
20110079850 | SEMICONDUCTOR STRUCTURE INCLUDING HIGH VOLTAGE DEVICE - A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the substrate on a first side of the gate stack. A first isolation structure in the substrate, located on the first side of the gate stack, separates the channel and the first diffusion region. The high voltage device also includes a first drift region in the substrate coupling the channel to the first diffusion region, wherein the first drift region comprises a non-uniform depth profile conforming to a profile of the first isolation structure. | 2011-04-07 |
20110079851 | SPLIT LEVEL SHALLOW TRENCH ISOLATION FOR AREA EFFICIENT BODY CONTACTS IN SOI MOSFETS - Disclosed is an SOI device on a bulk silicon layer which has an FET region, a body contact region and an STI region. The FET region is made of an SOI layer and an overlying gate. The STI region includes a first STI layer separating the SOI device from an adjacent SOI device. The body contact region includes an extension of the SOI layer, a second STI layer on the extension and a body contact in contact with the extension. The first and second STI layers are contiguous and of different thicknesses so as to form a split level STI. | 2011-04-07 |
20110079852 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - The present disclosure provides a semiconductor device and method of fabricating a semiconductor device. In an embodiment, the semiconductor device is a finFET device. In an embodiment, the semiconductor device is a silicon on insulator (SOI) device. A method of fabricating the semiconductor device includes providing a substrate, forming an oxide layer on the substrate, forming a fin on a portion of the oxide layer, forming a high k dielectric layer on a portion of the oxide layer and on a portion of the fin, forming a tuned, stressed metal gate on the dielectric layer, and forming a poly-cap on the metal gate. The method of fabrication provided may allow use of SOI substrate or bulk silicon substrates. | 2011-04-07 |
20110079853 | LIQUID CRYSTAL DISPLAY AND FABRICATION METHOD THEREOF - A method for fabricating an LCD includes: providing a substrate with a thin film transistor (TFT) part defined thereon; forming a metallic film for a gate electrode on the substrate; etching the metallic film through a first printing process to form a gate electrode; sequentially forming a gate insulating layer, a semiconductor layer, and a metallic film for source and drain electrodes on the substrate; selectively etching the metallic film for source and drain electrodes, the semiconductor layer and the gate insulating layer through a second printing process to form a gate insulating layer pattern, a preliminary active pattern and a metallic film pattern which are sequentially stacked such that the gate insulating layer pattern is over-etched from the side of the preliminary active pattern; forming an insulating layer on the substrate with the metallic film pattern; etching the insulating layer to expose the metallic film pattern; forming a transparent conductive film on the metallic film pattern and a remaining insulating film; and selectively etching the transparent conductive film, the metallic film pattern, the preliminary active pattern to form an active pattern, a source electrode, a drain electrode, and a pixel electrode connected with the drain electrode. | 2011-04-07 |
20110079854 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same are described. A polysilicon layer is formed on a substrate. The polysilicon layer is doped with an N-type dopant. A portion of the polysilicon layer is then removed to form a plurality of dummy patterns. Each dummy pattern has a top, a bottom, and a neck arranged between the top and the bottom, where the width of the neck is narrower than that of the top. A dielectric layer is formed on the substrate to cover the substrate disposed between adjacent dummy patterns, and the top of each dummy pattern is exposed. Thereafter, the dummy patterns are removed to form a plurality of trenches in the dielectric layer. A plurality of gate structures is formed in the trenches, respectively. | 2011-04-07 |
20110079855 | MERGED FINFETS AND METHOD OF MANUFACTURING THE SAME - FinFETs are merged together by a metal. The method of manufacturing the FinFETs include forming a plurality of fin bodies on a substrate and merging the fin bodies with a metal. The method further includes implanting source and drain regions through the metal. | 2011-04-07 |
20110079856 | STRAINED STRUCTURE OF SEMICONDUCTOR DEVICE - The present disclosure provides a semiconductor device that includes a semiconductor substrate, a gate structure disposed on a surface of the substrate, and strained structures disposed in the substrate at either side of the gate structure and formed of a semiconductor material different from the semiconductor substrate. Each strained structure has a cross-sectional profile that includes a first portion that extends from the surface of substrate and a second portion that tapers from the first portion at an angle ranging from about 50° to about 70°. The angle is measured with respect to an axis parallel to the surface of the substrate. | 2011-04-07 |
20110079857 | Semiconductor devices and methods of manufacturing the same - In semiconductor devices, methods of forming the same, the semiconductor device include a first gate structure having a first gate oxide layer pattern, a first polysilicon layer pattern containing atoms larger than silicon and a first hard mask layer pattern on substrates under tensile stress. N-type impurity regions are formed under the surface of the substrate on both sides of the first gate structure. A second gate structure having a second gate oxide layer pattern, a second polysilicon layer pattern containing atoms smaller than silicon and a second hard mask layer pattern on substrates under compressive stress. Additionally, P-type impurity regions are formed under the surface of the substrate on both sides of the second gate structure. The semiconductor devices have good device properties. | 2011-04-07 |
20110079858 | SEMICONDUCTOR MEMORY DEVICE HAVING A SENSE AMPLIFIER CIRCUIT WITH DECREASED OFFSET - A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit. | 2011-04-07 |
20110079859 | SEMICONDUCTOR DEVICES INCLUDING FIN SHAPED SEMICONDUCTOR REGIONS AND STRESS INDUCING LAYERS - A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode. | 2011-04-07 |
20110079860 | TUNNEL FIELD EFFECT TRANSISTOR WITH IMPROVED SUBTHRESHOLD SWING - The present disclosure provides a tunnel field effect transistor (TFET) device comprising at least following segments: a highly doped drain region, a lowly doped up to undoped channel region being in contact with the drain region, the channel region having a longitudinal direction, a highly doped source region in contact with the channel region, the contact between the source region and the channel region forming a source-channel interface, a gate dielectric and a gate electrode covering along the longitudinal direction at least part of the source and channel regions, the gate electrode being situated onto the gate dielectric, not extending beyond the gate dielectric, wherein the effective gate dielectric thickness t | 2011-04-07 |
20110079861 | Advanced Transistors with Threshold Voltage Set Dopant Structures - An advanced transistor with threshold voltage set dopant structure includes a gate with length Lg and a well doped to have a first concentration of a dopant. A screening region is positioned between the well and the gate and has a second concentration of dopant greater than 5×10 | 2011-04-07 |
20110079862 | SELF-ALIGNED INSULATING ETCHSTOP LAYER ON A METAL CONTACT - A semiconductor device comprising a substrate having a transistor that includes a metal gate structure; a first oxide layer formed over the substrate; a silane layer formed on the first oxide layer; and a non-conductive metal oxide layer grown on the metal gate structure, wherein the silane layer inhibits nucleation and growth of the non-conductive metal oxide layer. | 2011-04-07 |
20110079863 | Micromechanical structure, method for manufacturing a micromechanical structure, and use of a micromechanical structure - A micromechanical structure which includes a substrate having a main plane of extension, and a seismic mass which is movable relative to the substrate. The micromechanical structure includes a fixed electrode which is connected to the substrate, and a counterelectrode which is connected to the seismic mass. The fixed electrode has a first fixed electrode region and a second fixed electrode region which is connected in an electrically conductive manner to the first fixed electrode region. The counterelectrode is partially situated between the first and the second fixed electrode region, perpendicular to the main plane of extension. | 2011-04-07 |
20110079864 | Low Profile Human Interface Device - A human interface device is provided, having a substrate. A strain sensitive die is coupled to the substrate wherein the die is capable of providing an electrical signal indicative of a force applied to the strain sensitive die. A force transfer element is positioned adjacent to the strain sensitive die and coupled to the strain sensitive die. A translation element is mechanically coupled to the force transfer element. An elastic element is at least partially surrounding the translation element and the force transfer element, wherein the elastic element provides the mechanical coupling between the translation element and the force transfer element. A force applied to the translation element causes stretching of the elastic element, wherein the stretching of the elastic element causes a force to be applied to the force transfer element; and wherein the force applied to the force transfer element by the elastic element is then applied to the strain sensitive die. | 2011-04-07 |
20110079865 | RADIATION DETECTION AND A METHOD OF MANUFACTURING A RADIATION DETECTOR - The invention relates to a radiation detector ( | 2011-04-07 |
20110079866 | SOLID-STATE IMAGE PICKUP DEVICE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - A method for manufacturing a solid-state image pickup device is provided. In this method, a pixel isolation member is formed in a semiconductor substrate including pixels, and the thickness of the substrate is reduced by CMP. For forming the pixel isolation member, a first pixel isolation member is formed by implanting impurity ions in a region of the substrate so that the pixels are disposed between portions of the region when viewed from a surface of the substrate. A second isolation member is also formed by forming a trench in a region of the substrate different from the first pixel isolation member so that the pixels are disposed between portions of the region, and then filling the trench with an electroconductive material harder to polish by CMP than the substrate. The CMP is performed on the rear side of the substrate using the second pixel isolation member as a stopper. | 2011-04-07 |
20110079867 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device capable of making reduction in reflection at the interface between a light guide and an incident unit consistent with improvement in condensing efficiency by the light guide is provided. The solid-state imaging device includes a substrate internally including a photoelectric conversion unit, and a condensing unit provided on an optical incident side of the substrate. A configuration satisfying relationships of |N | 2011-04-07 |
20110079868 | SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a solid-state imaging device includes a semiconductor substrate of a first conductive type having a diffusion layer region provided on a surface thereof, a diffusion layer of the first conductive type for a pixel separation whose bottom portion is formed at the deepest position of the diffusion layer region in a pixel region, and a first deep diffusion layer of the first conductive type provided at the deepest position of the diffusion layer region in a first peripheral logic region for electrically connecting the semiconductor substrate and the first peripheral logic region and having a first concentration gradient equal to that of the diffusion layer for pixel separation. | 2011-04-07 |
20110079869 | MULTIPLEXED OUTPUT TWO TERMINAL PHOTODIODE ARRAY FOR IMAGING APPLICATIONS AND RELATED FABRICATION PROCESS - A detector array for an imaging system may exploit the different sensitivities of array pixels to an incident flux of low energy photons with a wavelength falling near the high end of the range of sensitivity of the semiconductor. The detector array may provide the de-multiplexable spatial information. The detector array may include a two-terminal multi-pixel array of Schottky photodiodes electrically connected in parallel. | 2011-04-07 |
20110079870 | SEMICONDUCTOR DEVICE - This specification discloses a semiconductor device having higher electric strength. | 2011-04-07 |
20110079871 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate having a trench defining an active region. A wall oxide is formed on side walls of the active region extending in the longitudinal direction, and an element isolation layer is formed in the trenches. A method of manufacturing a semiconductor device includes forming line-shape first trenches on a semiconductor substrate so as to define an active region; forming a wall oxide on surfaces of the first trenches; forming a second trench which separates the active region into a plurality of active regions; and filling the trenches with an element isolation layer. | 2011-04-07 |
20110079872 | PASSIVE DEVICE, SEMICONDUCTOR MODULE, ELECTRONIC CIRCUIT BOARD, AND ELECTRONIC SYSTEM HAVING THE PASSIVE DEVICE, AND METHODS OF FABRICATING AND INSPECTING THE SEMICONDUCTOR MODULE - Provided are a passive device of a semiconductor module, a semiconductor module having the passive device, an electronic circuit board and electronic system having the passive device or semiconductor module, and methods of fabricating and inspecting the semiconductor module. The passive device of the semiconductor module includes a main body and at least two real electrodes disposed on one lateral surface of the main body. | 2011-04-07 |
20110079873 | SEMICONDUCTOR DEVICE - A semiconductor device includes a base insulating film on which a silicon fuse, silicon wiring patterns, and a silicon guard ring are formed. The silicon guard ring surrounds the silicon fuse and has silicon cutout parts so as not to contact the silicon wiring patterns. A via guard ring, which has via cutout parts located above the silicon cutout parts, is formed in an interlayer insulating film and on the silicon guard ring. A metal wiring guard ring is formed on the via guard ring and the interlayer insulating film. A silicon nitride film is formed on the interlayer insulating film so as to cover the metal wiring guard ring. An interface between the interlayer insulating film and the metal wiring guard ring at the via cutout parts is covered by the silicon nitride film. | 2011-04-07 |
20110079874 | ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION - An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material. | 2011-04-07 |
20110079875 | ANTI-FUSE AND METHOD FOR FORMING THE SAME, UNIT CELL OF NON VOLATILE MEMORY DEVICE WITH THE SAME - There is provided an anti-fuse, including a gate dielectric layer formed over a substrate, a gate electrode, including a body portion and one or more protruding portions extending from the body portion, the body portion and the one or more protruding portions being formed to contact on the gate dielectric layer, and a junction region formed in a portion of the substrate exposed by sidewalls of the one or more protruding portions. | 2011-04-07 |
20110079876 | Method of Manufacturing a Semiconductor Component and Structure - A semiconductor component and methods for manufacturing the semiconductor component that includes a monolithically integrated passive device. In accordance with embodiments, the monolithically integrated passive device includes an inductor formed from damascene structures. | 2011-04-07 |
20110079877 | MOUNTING CIRCUIT SUBSTRATE - A semiconductor package containing a field effect transistor (FET) used in a high frequency band includes a mounting circuit substrate on which the semiconductor device is mounted. The mounting circuit substrate has a gate wiring conductor, a drain wiring conductor, and a source wiring conductor, which are connected to the gate electrode, the drain electrode, and the source electrode, respectively, of the semiconductor device. The gate wiring conductor and the drain wiring conductor extend toward each other so that their adjacent or facing ends are in close proximity to each other, thereby increasing the capacitance between the gate wiring conductor and the drain wiring conductor. | 2011-04-07 |
20110079878 | FERROELECTRIC CAPACITOR ENCAPSULATED WITH A HYDROGEN BARRIER - An integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. A method for forming an integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. | 2011-04-07 |
20110079879 | Semiconductor Devices Including Capacitor Support Pads - A semiconductor device may include a semiconductor substrate and a plurality of first capacitor electrodes arranged in a plurality of parallel lines on the semiconductor substrate with each of the first capacitor electrodes extending away from the semiconductor substrate. A plurality of capacitor support pads may be provided with each capacitor support pad being connected to first capacitor electrodes of at least two adjacent parallel lines of the first capacitor electrodes and with adjacent capacitor support pads being spaced apart. A dielectric layer may be provided on each of the first capacitor electrodes, and a second capacitor electrode may be provided on the dielectric layer so that the dielectric layer is between the second capacitor electrode and each of the first capacitor electrodes. Related methods are also discussed. | 2011-04-07 |
20110079880 | SEMICONDUCTOR DEVICE - A serially-connected diode pair made of diodes having a high withstand voltage and a low on-resistance is formed based on a high withstand voltage vertical PNP bipolar transistor process technology. Two of the diode pairs are connected in parallel to form a bridge so that there is formed a high-efficiency full-wave rectifier circuit that is free from a leakage current due to a parasitic transistor. The serially-connected diode pair is formed by connecting a diode composed of a P type semiconductor substrate, that makes an anode, and an N type buried layer, that makes a cathode, and a diode composed of a P+ type conductive layer, that makes an anode, and an N type epitaxial layer, that makes a cathode, in series with an electrode AC | 2011-04-07 |
20110079881 | INTEGRATED CIRCUIT CHIP PROTECTED AGAINST LASER ATTACKS - An integrated circuit chip formed inside and on top of a semiconductor substrate and including: in the upper portion of the substrate, an active portion in which components are formed; and under the active portion and at a depth ranging between 5 and 50 μm from the upper surface of the substrate, an area comprising sites for gettering metal impurities and containing metal atoms at a concentration ranging between 10 | 2011-04-07 |
20110079882 | Wafer and a Method for Manufacturing a Wafer - A wafer includes a wafer frontside and a region adjacent to the device surface, wherein the region includes vacancy-oxygen complexes and the wafer frontside includes a predetermined surface structure to form thereon a device with a desired property. | 2011-04-07 |
20110079883 | FERROELECTRIC THIN FILM - Provided is a ferroelectric thin film formed on a substrate and having an amount of remanent polarization increased in its entirety. The ferroelectric thin film contains a perovskite-type metal oxide formed on a substrate, the ferroelectric thin film containing a column group formed of multiple columns each formed of a spinel-type metal oxide, in which the column group is in a state of standing in a direction perpendicular to a surface of the substrate, or in a state of slanting at a slant angle in a range of −10° or more to +10° or less with respect to the perpendicular direction. | 2011-04-07 |
20110079884 | Hydrogen Passivation of Integrated Circuits - An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer. | 2011-04-07 |
20110079885 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SHAPED LEAD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a package lead having a retention structure around a perimeter of the package lead with a first concave surface, a ridge, and a second concave surface; forming a die attach paddle adjacent the package lead and having an another retention structure around a perimeter of the die attach paddle with an another first concave surface, an another ridge, and an another second concave surface; attaching an integrated circuit die to the die attach paddle; connecting a conductive connector to the integrated circuit die and the package lead; and applying an encapsulation over the integrated circuit die, the encapsulation conformed to the retention structure and exposing a portion of the package lead. | 2011-04-07 |
20110079886 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package paddle; forming a pad extension having a spacing to the package paddle; forming a lead adjacent the pad extension, the pad extension between the package paddle and the lead; forming a conductive layer directly on and between the package paddle and the pad extension; and connecting an integrated circuit to the pad extension and the lead, the integrated circuit over the package paddle. | 2011-04-07 |
20110079887 | LEAD FRAME AND METHOD OF MANUFACTURING THE SAME - A lead frame having improved connectivity with a molded portion and a method of manufacturing the lead frame are provided. The lead frame includes a die pad on which a semiconductor chip is to be disposed; at least one lead portion arranged to be connected to the semiconductor chip; and at least one plating layer formed on at least one of the at least one lead portion and the die pad, wherein a top surface of the at least one plating layer has an uneven portion having a first average surface roughness. | 2011-04-07 |
20110079888 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PROTECTIVE COATING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a lead-frame having a die attach paddle and a contact pad connected by a link; mounting an integrated circuit die over the die attach paddle; molding a package body on the lead-frame and the integrated circuit die including leaving portions of the die attach paddle, the contact pad, and the link exposed from the package body; forming an exposed edge by etching away the link between the contact pad, and the die attach paddle; and depositing a solder-resistant layer on the exposed edge. | 2011-04-07 |