14th week of 2016 patent applcation highlights part 40 |
Patent application number | Title | Published |
20160099187 | 3D NAND STAIRCASE CD CONTROL BY USING INTERFEROMETRIC ENDPOINT DETECTION - Embodiments of the present disclosure provide methods for forming stair-like structures in manufacturing three dimensional (3D) stacking of semiconductor chips. In one example, a method includes performing a trimming process on a substrate to trim a patterned photoresist layer disposed on a film stack from a first width to a second width in a processing chamber, performing an etching process to etch a portion of the film stack exposed by the trimmed patterned photoresist layer, directing an optical signal to a surface of the trimmed patterned photoresist layer continuously during the trimming and the etching process, collecting a return reflected optical signal reflected from the trimmed patterned photoresist layer, determining a change of reflected intensify of the return reflected optical signal as collected; and calculating a photoresist thickness loss based on the change of the reflected intensity. | 2016-04-07 |
20160099188 | Semiconductor Device with Sensor Potential in the Active Region - A semiconductor device includes semiconductor body region and a surface region, the semiconductor body region including a first conductivity type first semiconductor region type and a second conductivity type second semiconductor region. The semiconductor device further includes: a first load contact structure included in the surface region and arranged for feeding a load current into the semiconductor body region; a first trench extending into the semiconductor body region and having a sensor electrode and a first dielectric, the first dielectric electrically insulating the sensor electrode from the second semiconductor region; an electrically conductive path electrically connecting the sensor electrode to the first semiconductor region; a first semiconductor path, wherein the first semiconductor region is electrically coupled to the first load contact structure by at least the first semiconductor path; a sensor contact structure included in the surface region and arranged for receiving an electrical potential of the sensor electrode. | 2016-04-07 |
20160099189 | Semiconductor Packages and Modules with Integrated Ferrite Material - A semiconductor package includes a lead frame having a die paddle and a plurality of leads including a gate lead spaced apart from the die paddle. The semiconductor package further includes a semiconductor die attached to the die paddle and having a plurality of pads including a gate pad, a plurality of electrical conductors connecting the pads to the leads, an encapsulant encasing the semiconductor die and a portion of the leads such that part of the leads are not covered by the encapsulant, and a ferrite material embedded in the encapsulant and surrounding a portion of the electrical conductor that connects the gate pad to the gate lead. A method of manufacturing the semiconductor package and a semiconductor module with integrated ferrite material are also provided. | 2016-04-07 |
20160099190 | UNDERFILL MATERIAL INCLUDING BLOCK COPOLYMER TO TUNE COEFFICIENT OF THERMAL EXPANSION AND TENSILE MODULUS - Embodiments of the present disclosure are directed toward underfill material including block copolymer. In one embodiment, an underfill material includes epoxy material and a copolymer including an epoxy-philic block and an epoxy-phobic block, wherein the epoxy-philic block is miscible in the epoxy material, the epoxy-phobic block is covalently bonded with the epoxy-philic block, the epoxy-phobic block is separated in a microphase domain within the epoxy material and the epoxy-philic block is configured to restrict thermal expansion or contraction of the epoxy material. | 2016-04-07 |
20160099191 | Package-on-Package with Via on Pad Connections - An interposer includes a core dielectric material, a conductive pipe penetrating through the core dielectric material, and a metal pad underlying the conductive pipe. The metal pad includes a center portion overlapped by a region encircled by the conductive pipe, and an outer portion in contact with the conductive pipe. A dielectric layer is underlying the core dielectric material and the metal pad. A via is in the dielectric layer, wherein the via is in physical contact with the center portion of the metal pad. | 2016-04-07 |
20160099192 | DUAL-SIDED RADIO-FREQUENCY PACKAGE HAVING BALL GRID ARRAY - Dual-sided radio-frequency package having ball grid array. In some embodiments, a packaged radio-frequency (RF) device may include a packaging substrate configured to receive a plurality of components, the packaging substrate including a first side and a second side. The packaged RF device also includes a shielded package implemented on the first side of the packaging substrate, the shielded package including an RF circuit, the shielded package configured to provide RF shielding for at least a portion of the RF circuit. The packaged RF device further includes a ball-grid array (BGA) implemented on the second side of the packaging substrate, the BGA defining a mounting volume on the second side of the packaging substrate and a component implemented within the mounting volume. | 2016-04-07 |
20160099193 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate having a main plane; a semiconductor element provided on the main plane of the semiconductor substrate; an electrode pad provided on the main plane of the semiconductor substrate and connected to the semiconductor element; a guard ring surrounding the semiconductor element and the electrode pad, and provided on the main plane of the semiconductor substrate; and an insulating film covering all region of a semiconductor of the main plane of the semiconductor substrate exposed inside the guard ring, wherein the insulating film is made of a water impermeable material. | 2016-04-07 |
20160099194 | SEMICONDUCTOR MODULE AND ELECTRICALLY-DRIVEN VEHICLE - A semiconductor module includes a first semiconductor element, a second semiconductor element, a first heat spreader electrically and thermally connected to the first semiconductor element, a second heat spreader electrically and thermally connected to the second semiconductor element, a DCB substrate including a first metal foil on a top surface of a ceramic insulating substrate and including a second metal foil on a bottom surface, the first metal foil being electrically and thermally joined to the first heat spreader and the second heat spreader, and a cooler thermally connected to the second metal foil of the DCB substrate. The first semiconductor element is disposed on an upstream side, and the second semiconductor element is disposed on a downstream side with respect to a flowing direction of a refrigerant of the cooler. An area of the second heat spreader is greater than an area of the first heat spreader. | 2016-04-07 |
20160099195 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package including a first substrate having an upper surface, a lower surface and a sidewall is provided. A sensing region or device region and a conducting pad are adjacent to the upper surface. A through-hole penetrates the first substrate. A redistribution layer extends from the lower surface into the through-hole and is electrically connected to the conducting pad. The redistribution layer further laterally extends from the lower surface to protrude from the sidewall. A method for forming the chip package is also provided. | 2016-04-07 |
20160099196 | Formation of Through Via Before Contact Processing - The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads. | 2016-04-07 |
20160099197 | SEMICONDUCTOR PACKAGE AND CIRCUIT SUBSTRATE FOR THE SEMICONDUCTOR PACKAGE - Provided is a circuit substrate for a semiconductor package used for mounting a plurality of semiconductor devices. The circuit substrate including: a first circuit substrate unit; and a second circuit substrate unit that is formed on the first circuit substrate unit, wherein Young's modulus of a first dielectric material composing the dielectric layer of the first circuit substrate unit is higher than Young's modulus of a second dielectric material composing the dielectric layer of the second circuit substrate unit, and a coefficient of thermal expansion of the first dielectric material composing the dielectric layer of the first circuit substrate unit is smaller than a coefficient of thermal expansion of the second dielectric material composing the dielectric layer of the second circuit substrate unit. | 2016-04-07 |
20160099198 | SEMICONDUCTOR PACKAGE APPARATUS - A semiconductor package apparatus includes a lead frame, a first semiconductor chip, a second semiconductor chip, a first connecting element, and a second connecting element. The lead frame includes a power input plate, a ground plate, a phase plate, and a phase detection plate. The second electrode of first semiconductor chip is disposed on the power input plate. The first electrode of second semiconductor chip is disposed on the ground plate. The first connecting element is disposed on the first semiconductor chip and the second semiconductor chip and electrically connects the first electrode of first semiconductor chip with the second electrode of second semiconductor chip. The second connecting element is disposed on the second semiconductor chip and phase plate and electrically connects the second electrode of second semiconductor chip with the phase plate. The first connecting element and the phase detection plate are electrically connected. | 2016-04-07 |
20160099199 | ELECTRONIC DEVICES WITH SOLDERABLE DIE STRUCTURES AND METHODS OF FORMATION OF SUCH DEVICES - An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer. | 2016-04-07 |
20160099200 | ALUMINUM ALLOY LEAD FRAME FOR A SEMICONDUCTOR DEVICE AND CORRESPONDING MANUFACTURING PROCESS - Described herein is a semiconductor device provided with: a die of semiconductor material; a lead frame, defining a support plate, which is designed to carry the die, and leads, which are designed to be electrically coupled to the die; and a package, of encapsulating material, which is designed to encapsulate the die and partially coming out of which are the leads. The lead frame has as constituent material an aluminum alloy comprising a percentage of silicon ranging between 1% and 1.5%. | 2016-04-07 |
20160099201 | INTEGRATED CIRCUIT DEVICES HAVING THROUGH-SILICON VIAS AND METHODS OF MANUFACTURING SUCH DEVICES - An integrated circuit device includes a semiconductor structure, a through-silicon-via (TSV) structure that penetrates through the semiconductor structure and a connection terminal connected to the TSV structure. A metal capping layer includes a flat capping portion that covers the bottom surface of the connection terminal and a wedge-shaped capping portion that is integrally connected to the flat capping portion and that partially covers a side wall of the connection terminal. The metal capping layer may be formed by an electroplating process in which the connection terminal is in contact with a metal strike electroplating solution while a pulse-type current is applied. | 2016-04-07 |
20160099202 | SEMICONDUCTOR PACKAGING STRUCTURE - A semiconductor packaging structure including a circuit board, a chip, and a paste is provided. The circuit board includes a base layer, a first circuit layer, and a second circuit layer. The base layer has a first surface, a second surface opposite to the first surface, and a recess located on the first surface. The first circuit layer is located on the first surface. The second circuit layer is located on the second surface. The chip is disposed on the first surface and is electrically connected to first circuit layer, where the recess is located on at least one side of the chip. The paste is filled between the chip and the first surface and filled in the recess, where the paste covers a side surface of the chip. | 2016-04-07 |
20160099203 | SEMICONDUCTOR STACK PACKAGES - A semiconductor stack package includes a printed circuit board (PCB), a first semiconductor chip, and a second semiconductor chip. The first and second semiconductor chips are disposed side-by-side on a first surface of the PCB to be spaced apart from each other. Each of the first and second semiconductor chips includes a command/address (CA) chip pad and a data input/output (DQ) chip pad. The CA chip pad of the first semiconductor chip is electrically coupled to the CA chip pad of the second semiconductor chip through a CA bonding wire. | 2016-04-07 |
20160099204 | PACKAGE SUBSTRATE, PACKAGE STRUCTURE, AND METHODS OF FABRICATING THE SAME - A package structure is provided, including: a board having a plurality of conductive traces; a plurality of conductive pads formed on the board and each having a height greater than a height of each of the conductive traces; and an electronic component disposed on and electrically connected to the conductive pads via a plurality of conductive elements, wherein at least one of the conductive traces is positioned in proximity of at least one of the conductive pads. Therefore, the conductive elements are prevented from being in contact with the conductive traces, and the problem that the conductive pads and the conductive traces are shorted is solved. The present invention further provides a method for fabricating the packaging substrate. | 2016-04-07 |
20160099205 | PACKAGE ON PACKAGE AND COMPUTING DEVICE INCLUDING THE SAME - A semiconductor package includes a printed circuit board (PCB), a chip bonded to the PCB, a mold protecting the chip and exposing a backside surface of the chip, via openings extending in the mold to expose first contacts bonded to the PCB, and at least one first marking inscribed in a marking region of the mold between the backside surface of the chip and the vias. The mold has an exposed molded underfill (eMUF) structure covering the sides of the chip while exposing the backside surface of the chip. A PoP package includes a top package stacked on and electrically connected to the semiconductor package. | 2016-04-07 |
20160099206 | WAFER LEVEL PACKAGING OF ELECTRONIC DEVICE - Wafer level packaged semiconductor device with enhanced heat dissipation properties. The semiconductor device includes a top and a bottom face and at least one metal pad is positioned on the top and the bottom faces. A top cover is affixed to the top face of the semiconductor device and a bottom cover is affixed to the bottom face of the semiconductor device. Vias extend through the top and bottom covers and an electroplated metal layer extends from an external face of the covers, through the visas to the metal pads on the semiconductor device. | 2016-04-07 |
20160099207 | Electronic Module Comprising a Plurality of Encapsulation Layers and a Method for Producing It - An electronic module includes a first insulation layer, at least one carrier having a first main surface, a second main surface situated opposite the first main surface, and side surfaces connecting the first and second main surfaces to one another, at least one semiconductor chip arranged on the second main surface of the carrier, wherein the semiconductor chip has contact elements, and a second insulation layer, which is arranged on the carrier and the semiconductor chip. | 2016-04-07 |
20160099208 | STACKED CONDUCTOR STRUCTURE AND METHODS FOR MANUFACTURE OF SAME - A circuit structure that includes a plurality of stacked conductor layers separated from each other by respective dielectric layers. The conductor layers may include a first set of conductor layers made of a first type conductor material and a second set of conductor layers made of a second type conductor material different from the first. A pair of conductor posts may traverse the stacked conductor layers. A first post may be electrically connected to the first set of conductor layers and electrically insulated from the second set of conductor layers. A second post electrically connected to the second set of conductor layers and electrically insulated from the first set of conductor layers. | 2016-04-07 |
20160099209 | MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A memory device includes a substrate, first and second wirings above the substrate, a third wiring above the first and second wirings, a fourth wiring above the third wiring, a first contact electrically connected between the first wiring and the fourth wiring, a first insulator on the first contact, and a second contact on the first insulator, the second contact being electrically connected between the second wiring and the third wiring. The first contact overlaps the second contact in a direction that is orthogonal to an upper surface of the substrate. | 2016-04-07 |
20160099210 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are a semiconductor package and a method of manufacturing the same, which allows a conductive path to be provided to connect upper and lower portions of the semiconductor package. A semiconductor package according to the present invention includes a semiconductor chip, a substrate including an accommodating portion to accommodate the semiconductor chip, a sealing material configured to mold the semiconductor chip and the substrate to be integrated, a through wiring configured to vertically pass through the substrate, a wiring portion configured to electrically connect the semiconductor chip and one side of the through wiring, and an external connection portion to electrically connected to the other side of the through wiring and configured to be able to be electrically connected to an outside, wherein a wiring layer of the wiring portion is provided to be connected to the through wiring. | 2016-04-07 |
20160099211 | SYSTEM ON CHIP - Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact. | 2016-04-07 |
20160099212 | Through Package Circuit in Fan-Out Wafer Level Package - A method and apparatus are provided for manufacturing a packaged electronic device ( | 2016-04-07 |
20160099213 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a package substrate with a cavity, a plurality of semiconductor chips vertically stacked in the cavity, a first insulating layer on a first surface of the package substrate, a first interconnection layer on the first insulating layer, a second insulating layer on a second surface of the package substrate opposite the first surface, and a second interconnection layer on the second insulating layer. | 2016-04-07 |
20160099214 | FLEXIBLE ELECTRONIC CIRCUITS WITH EMBEDDED INTEGRATED CIRCUIT DIE AND METHODS OF MAKING AND USING THE SAME - Flexible integrated circuit (IC) modules, flexible IC devices, and methods of making and using flexible IC modules are presented herein. A flexible integrated circuit module is disclosed which includes a flexible substrate and a semiconductor die attached to the flexible substrate. An encapsulating layer, which is attached to the flexible substrate, includes a thermoplastic resin and/or a polyimide adhesive encasing therein the semiconductor die. The encapsulating layer may be an acrylic-based thermally conductive and electrically isolating polyimide adhesive. Optionally, the encapsulating layer may be a B-stage FR-4 glass-reinforced epoxy thermoplastic polymer or copolymer or blend. The die may be embedded between two flexible substrates, each of which includes a layer of flexible polymer, such as a polyimide sheet, with two layers of conductive material, such as copper cladding, disposed on opposing sides of the layer of flexible polymer. | 2016-04-07 |
20160099215 | METHOD FOR MANUFACTURING DEVICE EMBEDDED SUBSTRATE, AND DEVICE EMBEDDED SUBSTRATE - In a method for manufacturing a device embedded substrate, a conductive via that penetrates a first insulating layer and a second insulating layer from an outer metal layer to reach a second terminal of an IC device is formed after forming the outer metal layer. | 2016-04-07 |
20160099216 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a dielectric layer positioned on the semiconductor substrate. The dielectric layer has a first recess. The semiconductor device structure includes a conductive structure filling the first recess. The conductive structure includes a first conductive layer and a second conductive layer. The first conductive layer is positioned over an inner wall and a bottom of the first recess. The first conductive layer has a second recess in the first recess. The second conductive layer fills the second recess. The first conductive layer and the second conductive layer include cobalt. The second conductive layer further includes at least one of sulfur, chlorine, boron, phosphorus, or nitrogen. | 2016-04-07 |
20160099217 | LINE LAYOUT AND METHOD OF SPACER SELF-ALIGNED QUADRUPLE PATTERNING FOR THE SAME - A line layout and a spacer self-aligned quadruple patterning method thereof are provided. The line layout includes a first line, a second line, a third line, and a fourth line. The second line and the third line are disposed between the first line and the fourth line. The first line, the second line, the third line, and the fourth line respectively extend in a first direction. An end segment of the second line and an end segment of the third line respectively include a first protrusion portions that extend in a second direction. The first protrusion portion of the end segment of the second line protrudes toward the first line. The first protrusion portion of the end segment of the third line protrudes toward the fourth line. | 2016-04-07 |
20160099218 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - Provided is a method of manufacturing a semiconductor package. The method includes mounting a semiconductor device on a substrate; disposing a mold on the substrate, wherein the mold is formed to cover the semiconductor device such that at least one inner side surface of the mold has a slope; providing a molding material into the mold to encapsulate the semiconductor device; removing the mold from the substrate; and forming an electromagnetic shielding (EMS) layer to cover a top surface and side surfaces of the molding material. | 2016-04-07 |
20160099219 | Semiconductor Device Having Features to Prevent Reverse Engineering - It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices. | 2016-04-07 |
20160099220 | HIGH ISOLATION WIDEBAND SWITCH - A high isolation wideband switch is disclosed. In one aspect, the switch includes an integrated circuit package having an integrated circuit die with a first plurality of leads that is positioned on a package substrate that has a second plurality of leads. The first leads of the integrated circuit die are connected to the second the leads of the package substrate via bond wires and a first electrical coupling occurs between the first leads and the integrated circuit die in response to an RF signal applied to the integrated circuit package. The bond wires have a second electrical coupling in response to the RF signal and the bond wires are arranged such that the second electrical coupling is matched to the first electrical coupling within a selected frequency band so as to reduce the overall electrical coupling of the integrated circuit package for RF signals within the selected frequency band. | 2016-04-07 |
20160099221 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a semiconductive substrate, a post passivation interconnect (PPI) and a polymer layer. The PPI is disposed above the semiconductive substrate and includes a landing area for receiving a conductor. The polymer layer is on the PPI, wherein the conductor is necking a turning point so as to include an oval portion being substantially surrounded by the polymer layer, and the oval portion of the conductor is disposed on the landing area of the PPI. | 2016-04-07 |
20160099222 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDER BUMP METALLIZATION AND METHOD OF MANUFACTURE THEREOF - An integrated circuit packaging system and method of manufacture thereof including: providing a substrate; forming contact pads on top of the substrate; forming a protection layer on top of the contact pads and the substrate; exposing the contact pads from the protection layer; printing under bump metallization (UBM) layers over the exposed contact pads extended over the protection layer with conductive inks; and forming bumps on top of the under bump metallization layers. It also including: printing an adhesion layer using conductive ink, wherein the adhesion layer comprises interconnected adhesion layer pads; forming additional under bump metallization (UBM) layers and bumps on top of the adhesion layer pads utilizing an electro-deposition process; and removing connections among the interconnected adhesion layer pads. | 2016-04-07 |
20160099223 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor structure includes receiving a substrate including a die pad disposed thereon; disposing a passivation over the substrate and around the die pad; disposing a polymer over the passivation; forming a post passivation interconnect (PPI) including an elongated portion and a via portion contacting with the die pad; depositing a metallic paste on the elongated portion of the PPI by a stencil; disposing a conductive bump over the metallic paste; and disposing a molding over the PPI and around the metallic paste and the conductive bump. | 2016-04-07 |
20160099224 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to the present invention includes an insulating substrate having a circuit pattern, semiconductor elements bonded on the circuit pattern with a brazing material, and a wiring terminal bonded with a brazing material on an electrode provided on each of the semiconductor elements on an opposite side of the circuit pattern, in which a part of the wiring terminal is in contact with the insulating substrate, and insulated from the circuit pattern. | 2016-04-07 |
20160099225 | Die Bonder and Bonding Method - A die bonder and a bonding method are provided that are capable of surely mounting a die on an intermediate stage and surely picking up the die from the intermediate stage and thus, are high in reliability. The die bonder is provided with the intermediate stage for mounting thereon the die picked up by the pickup head from a die supply unit. A mounting portion of the intermediate stage is provided with an uneven pattern including a plurality of mounting support protrusions having contact surfaces that flush contact the back surface of the die for supporting the die not to slip out of place, and a plurality of recesses formed between the mounting support protrusions. | 2016-04-07 |
20160099226 | CIRCUIT SUBSTRATE INTERCONNECT - A packaged integrated circuit (IC) includes a substrate including a first substrate pad disposed on a first side of the substrate, an IC die disposed on the first side of the substrate, and a first insulating layer molded over the IC die and the substrate. The IC die includes a first die pad on a side of the die opposite from a side of the die adjacent to the first side of the substrate. The first insulating layer includes a first channel extending through the first insulating layer to the first substrate pad, a second channel extending through the first insulating layer to the first die pad, conductive paste filling the first channel and in contact with the first substrate pad, and conductive paste filling the second channel and in contact with the die pad. | 2016-04-07 |
20160099227 | FLEXIBLE INTERCONNECTS FOR MODULES OF INTEGRATED CIRCUITS AND METHODS OF MAKING AND USING THE SAME - Flexible interconnects, flexible integrated circuit systems and devices, and methods of making and using flexible integrated circuitry are presented herein. A flexible integrated circuit system is disclosed which includes first and second discrete devices that are electrically connected by a discrete flexible interconnect. The first discrete devices includes a first flexible multi-layer integrated circuit (IC) package with a first electrical connection pad on an outer surface thereof. The second discrete device includes a second flexible multi-layer integrated circuit (IC) package with a second electrical connection pad on an outer surface thereof. The discrete flexible interconnect is attached to and electrically connects the first electrical connection pad of the first discrete device to the second electrical connection pad of the second discrete device. | 2016-04-07 |
20160099228 | METHOD AND APPARATUS FOR DIE-TO-DIE PAD CONTACT - A semiconductor device includes at least a first semiconductor die and a second semiconductor die. The first semiconductor dies comprises a first and second side, and includes at least a first contact pad located on the first side of the first semiconductor die. The second semiconductor die comprises a first and second side, and includes at least a second contact pad located on the first side of the second semiconductor die, wherein the first semiconductor die is stacked on the second semiconductor die and wherein the first side of the first semiconductor die faces the first side of the second semiconductor die. At least one voltage-guided conductive filament is created between the first contact pad and the second contact pad. | 2016-04-07 |
20160099229 | SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES, SEMICONDUCTOR PACKAGES INCLUDING THE SAME, METHODS OF MANUFACTURING THE SAME, ELECTRONIC SYSTEMS INCLUDING THE SAME, AND MEMORY CARDS INCLUDING THE SAME - A semiconductor device includes a substrate having a first surface and a second surface that are opposite to each other, a plurality of through electrodes penetrating the substrate and extending from the first surface to the second surface, front-side bumps disposed on the first surface and connected to odd-numbered through electrodes among the plurality of through electrodes, and backside bumps disposed on the second surface and connected to even-numbered through electrodes among the plurality of through electrodes. Related semiconductor packages, fabrication methods, electronic systems and memory cards are also provided. | 2016-04-07 |
20160099230 | MULTI-CHIP PACKAGE, TEST SYSTEM AND METHOD OF OPERATING THE SAME - A multi-chip package includes: a plurality of semiconductor chips that are coupled with each other through normal through silicon vias and repair through silicon vias; a state detection device suitable for detecting connection states of the normal through silicon vias and the repair through silicon vias; and a repair control device suitable for comparing the connection state of the normal through silicon vias with the connection state of the repair through silicon vias, and controlling whether to perform a repair operation. | 2016-04-07 |
20160099231 | SEMICONDUCTOR PACKAGE ASSEMBLY - The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package and a second semiconductor package stacked on the first semiconductor package. The first semiconductor package includes a first redistribution layer (RDL) structure. A first semiconductor die is coupled to the first RDL structure. A first molding compound surrounds the first semiconductor die, and is in contact with the RDL structure and the first semiconductor die. The second semiconductor package includes a second redistribution layer (RDL) structure. A first dynamic random access memory (DRAM) die without through silicon via (TSV) interconnects formed passing therethrough is coupled to the second RDL structure. | 2016-04-07 |
20160099232 | FINGERPRINT RECOGNITION SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A fingerprint recognition semiconductor device includes an insulation layer, a wiring pattern formed on a lower surface of the insulation layer, and a sensor element flip-chip-connected to the wiring pattern. The sensor element includes an active surface, including a sensor portion that recognizes a fingerprint, and a rear surface, located at a side opposite to the active surface. An encapsulation resin fills a gap between the lower surface of the insulation layer and an upper surface of a wiring substrate, facing the rear surface of the sensor element and connected to the wiring pattern by a connecting member. The entire active surface of the sensor element is covered by underfill formed between the active surface of the sensor element and the lower surface of the insulation layer. The insulation layer includes an upper surface, defining an uppermost surface and free from a wiring layer. | 2016-04-07 |
20160099233 | HETEROGENEOUS ANNEALING METHOD AND DEVICE - A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts. | 2016-04-07 |
20160099234 | USING INTERRUPTED THROUGH-SILICON-VIAS IN INTEGRATED CIRCUITS ADAPTED FOR STACKING - In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack. | 2016-04-07 |
20160099235 | METHOD OF MANUFACTURING A SINGLE LIGHT-EMITTING STRUCTURE - The instant disclosure provides a light-emitting module and a method of manufacturing a single light-emitting structure. The light-emitting module includes two identical light-emitting structures disposed on the same plane. One of the two light-emitting structures disposed on the plane is rotated by 180 degrees relative to the other light-emitting structure, and the two light-emitting structures are connected to each other. Each light-emitting structure includes a base, a conducting element, a light-emitting element and an encapsulation element. The conducting element includes a plurality of conductors separated from each other and passing through the base body, where the number of the conductors is N and N>1. The light-emitting element includes at least one light-emitting chip electrically connected between at least two of the conductors. The encapsulation element includes a transparent encapsulation body disposed on the base to cover the conducting element and the light-emitting element. | 2016-04-07 |
20160099236 | LIGHT EMITTING LAMP - Disclosed is a light emitting lamp including a light source module including at least one light source and a light guide layer disposed on a substrate burying the at least one light source, and a housing accommodating the light source module, and the at least one light source includes a body having a cavity, a first lead frame including one end exposed to the cavity and the other end passing through the body and exposed to one surface of the body, a second lead frame including one end exposed to one portion of the surface of the body, the other end exposed to the another portion of the surface of the body, and an intermediate part exposed to the cavity, and at least one light emitting chip including a first semiconductor layer, an active layer and a second semiconductor layer, and disposed on the first lead frame. | 2016-04-07 |
20160099237 | MICROELECTRONIC DIE PACKAGES WITH METAL LEADS, INCLUDING METAL LEADS FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS - Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing. | 2016-04-07 |
20160099238 | EMBEDDED PACKAGE AND METHOD THEREOF - The present invention discloses anew embedded package comprising: a pre-mold lead frame with a plurality of chips attached thereon, where the molding material fills the voids of the lead frame, no that the lead frame is entirely solid; a plurality of pins arranged around the lead frame; a metal clip attached on and electrically connecting the chips together; first laminate layer which covers the chips, the lead frame, a metal clip and pins; conductive plug and extension formed to connect an electrode of a chip to a corresponding pin or to connect the chips together. The new embedded package of the invention with a three-dimensional stack capacity improves the thickness, thermal and electrical properties and the flexible power and logic hybrid design. | 2016-04-07 |
20160099239 | METHODS, APPARATUS AND SYSTEM FOR REDUCTION OF POWER CONSUMPTION IN A SEMICONDUCTOR DEVICE - At least one method, apparatus and system disclosed herein involves performing power reduction process on a FinFET device. A first design is provided. The first design comprises a process mask definition, a FinFET device that comprises a plurality of fins characterized by said process mask, and a timing requirement relating to an operation of said FinFET device. A timing parameter of said operation of said FinFET device is determined. Based upon said timing parameter, a determination is made as to whether a drive capability of said FinFET device is above a level required to maintain said timing requirement. The process mask is modified for reducing at least one of said fins in response to said determining that said drive capability is above said level required to maintain said timing requirement. | 2016-04-07 |
20160099240 | INTEGRATED ELECTROSTATIC DISCHARGE (ESD) CLAMPING - A method of fabricating a laterally diffused metal-oxide-semiconductor (LDMOS) transistor device having a bipolar transistor for electrostatic discharge (ESD) protection includes doping a substrate to form a body region of the LDMOS transistor device in the substrate, the body region having a first conductivity type, forming a doped isolating region of the LDMOS transistor device in the substrate, the doped isolating region having a second conductivity type and surrounding a device area of the LDMOS transistor device in which the body region is disposed, forming a base contact region of the bipolar transistor, the base contact region being disposed within the body region and having the first conductivity type, and doping the substrate to form an isolation contact region for the doped isolating region that defines a collector region of the bipolar transistor, to form source and drain regions of the LDMOS transistor device in the substrate, and to form an emitter region of the bipolar transistor within the body region. | 2016-04-07 |
20160099241 | N-TYPE METAL OXIDE SEMICONDUCTOR (NMOS) TRANSISTOR FOR ELECTROSTATIC DISCHARGE (ESD) - One or more techniques or systems for forming an n-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD) are provided herein. In some embodiments, the NMOS transistor includes a first region, a first n-type plus (NP) region, a first p-type plus (PP) region, a second NP region, a second PP region, a shallow trench isolation (STI) region, and a gate stack. In some embodiments, the first PP region is between the first NP region and the second NP region. In some embodiments, the second NP region is between the first PP region and the second PP region, the gate stack is between the first PP region and the second NP region, the STI region is between the second NP region and the second PP region. Accordingly, the first PP region enables ESD current to discharge based on a low trigger voltage for the NMOS transistor. | 2016-04-07 |
20160099242 | SEMICONDUCTOR DEVICE EMPLOYING TRENCHES FOR ACTIVE GATE AND ISOLATION - A semiconductor device includes a semiconductor layer of a first conductivity type formed on a substrate; a first trench formed in the semiconductor layer including a first trench gate; a second trench formed in the semiconductor layer and extending into the substrate and including a second trench gate; a first transistor device formed in the semiconductor layer adjacent the first trench. The second trench encircles active area of the first transistor device to provide electrical isolation of the first transistor device. | 2016-04-07 |
20160099243 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact. | 2016-04-07 |
20160099244 | Methods of Forming Semiconductor Devices and Structures Thereof - Methods of forming semiconductor devices and structures thereof are disclosed. In some embodiments, a semiconductor device includes a substrate that includes fins. Gates are disposed over the fins, the gates being substantially perpendicular to the fins. A source/drain region is disposed on each of fins between two of the gates. A contact is coupled to the source/drain region between the two of the gates. The source/drain region comprises a first width, and the contact comprises a second width. The second width is substantially the same as the first width. | 2016-04-07 |
20160099245 | SEMICONDUCTOR DEVICES WITH SIDEWALL SPACERS OF EQUAL THICKNESS - Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack. | 2016-04-07 |
20160099246 | STRUCTURE AND METHOD TO INCREASE CONTACT AREA IN UNMERGED EPI INTEGRATION FOR CMOS FINFETS - Source/drain contact structures with increased contact areas for a multiple fin-based complementary metal oxide semiconductor field effect transistor (CMOSFET) having unmerged epitaxial source/drain regions and methods for forming such source/drain contact structures are provided by forming wrap-around source/drain contact structures for both n-type FinFETs and p-type FinFETs. Each of first source/drain contact structures for the n-type FinFETs includes at least one first conductive plug encapsulating epitaxial first source/drain regions on one side of a gate structure, while each of second source/drain contact structures for the p-type FinFETs includes at least a contact metal layer portion encapsulating epitaxial second source/drain regions on one side of the gate structure, and a second conductive plug located over a top surface of the contact metal layer portion. | 2016-04-07 |
20160099247 | SEMICONDUCTOR DEVICES WITH CAPACITORS - A semiconductor device includes bottom electrodes two-dimensionally arranged on a substrate and transistors connected to the bottom electrodes, respectively. Each of the bottom electrodes may include first side surfaces facing each other in a first direction and second side surfaces facing each other in a second direction crossing the first direction. At least one of the first and second side surfaces may have a concave shape, when viewed in a plan view. | 2016-04-07 |
20160099248 | SEMICONDUCTOR MEMORY DEVICE WITH IMPROVED ACTIVE AREA/WORD LINE LAYOUT - One semiconductor device includes a bit line extending in a straight line in an X direction, a first and a second horizontal active region extending in the X direction, and a sloped active region arranged between the first and the second horizontal regions and inclined with respect to the X direction, an active region arranged at the center of a bit line impurity diffusion region, a first word line arranged in the first horizontal active region segment, a second word line arranged in the second horizontal active region segment, and a third and a fourth word line arranged in the sloped active region segment next to each other with the bit line impurity diffusion region interposed therebetween. | 2016-04-07 |
20160099249 | INTEGRATED FIN AND STRAP STRUCTURE FOR AN ACCESS TRANSISTOR OF A TRENCH CAPACITOR - At least one dielectric pad layer is formed on a semiconductor-on-insulator (SOI) substrate. A deep trench is formed in the SOI substrate, and a combination of an outer electrode, a node dielectric, and an inner electrode are formed such that the top surface of the inner electrode is recessed below the top surface of a buried insulator layer of the SOI substrate. Selective epitaxy is performed to fill a cavity overlying the inner electrode with an epitaxial semiconductor material portion. A top semiconductor material layer and the epitaxial semiconductor material portion are patterned to form a fin structure including a portion of the top semiconductor material layer and a portion of the epitaxial semiconductor material portion. The epitaxial semiconductor material portion functions as a conductive strap structure between the inner electrode and a semiconductor device to be formed on the fin structure. | 2016-04-07 |
20160099250 | THREE DIMENSIONAL NAND DEVICE WITH SILICON GERMANIUM HETEROSTRUCTURE CHANNEL - A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, forming an at least one opening in the stack, forming at least a portion of a memory film in the at least one opening and forming a first portion of a semiconductor channel followed by forming a second portion of the semiconductor channel in the at least one opening. The second portion of the semiconductor channel comprises silicon and germanium and contains more germanium than a first portion of the semiconductor channel which is located closer to the memory film than the second portion. | 2016-04-07 |
20160099251 | SEMICONDUCTOR DEVICE - An insulating film, which is sandwiched between a gate electrode formed on an SOI layer constituting an SOI substrate and an epitaxial layer formed on the SOI layer and including a high-concentration diffusion region and is formed in contact with a side wall of the gate electrode, is set as a target of dielectric breakdown in a write operation in an anti-fuse element. | 2016-04-07 |
20160099252 | MEMORY HAVING A CONTINUOUS CHANNEL - The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate. | 2016-04-07 |
20160099253 | METHOD OF INTEGRATING A CHARGE-TRAPPING GATE STACK INTO A CMOS FLOW - A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack, wherein the cap layer comprises a multi-layer cap layer including at least a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer; patterning the cap layer and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to oxidize the first cap layer to form a blocking oxide overlying the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described. | 2016-04-07 |
20160099254 | Memory Hole Structure in Three Dimensional Memory - In a three dimensional nonvolatile memory, memory holes extend vertically through two or more physical levels in which memory cells are formed. Memory hole structures are formed in memory holes to include vertical channels. Vertical trenches are subsequently formed to divide memory hole structures into two or more vertical NAND strings. | 2016-04-07 |
20160099255 | THREE DIMENSIONAL STACKED SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A 3D stacked semiconductor structure is provided, comprising a plurality of multi-layered pillars formed on a substrate and spaced apart from each other, a plurality of first conductors formed between the adjacent multi-layered pillars, a plurality of charging-trapping layers formed on the substrate and on the sidewalls of the multi-layered pillars for separating the first conductor and the multi-layered pillars, and a second conductor formed on the first conductors and on the charging-trapping layers. One of the multi-layered pillars comprises a plurality of insulating layers and a plurality of conductive layers arranged alternately. The top surfaces of the first conductors are higher than the top surfaces of the multi-layered pillars so as to create a plurality of receiving trenches respectively on the multi-layered pillars. The second conductor fills up the receiving trenches on the multi-layered pillars. | 2016-04-07 |
20160099256 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a substrate; a memory cell array including a plurality of memory cells and stacked on the substrate; a first transistor; an interlayer insulating layer covering the first transistor; and a first contact portion. The first transistor includes a first gate insulating film which is disposed on the substrate, a first gate electrode which is disposed on the first gate insulating film, and a first semiconductor layer which includes an upper surface at a higher position than an interface between the substrate and the first gate insulating film and a bottom surface at a deeper position than the interface between the substrate and the first gate insulating film. The first contact portion penetrates the interlayer insulating layer to reach the first semiconductor layer and connects the plurality of memory cells and the first transistor electrically. | 2016-04-07 |
20160099257 | THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A thin film transistor includes an active pattern formed on a substrate; a gate pattern formed on the active pattern and comprising a gate electrode and a gate line; a gate insulating layer disposed between the gate pattern and the active pattern; a source electrode that overlaps a first side of the active pattern and contacts a data line; a drain electrode that overlaps a second side of the active pattern and is separated from the source electrode; a channel area formed in an area where the gate line and an active line of the active pattern overlap each other; and a gate line modifying unit formed in the channel area by changing a linear shape of the gate line. | 2016-04-07 |
20160099258 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - To provide a novel semiconductor device or a semiconductor device capable of operating at high speed. The semiconductor device includes a plurality of circuits each having a function of storing data and a wiring EL. The plurality of circuits each include a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and the capacitor. The first transistor includes an oxide semiconductor in a channel formation region. The wiring EL has a function of a back-gate of the first transistor. A potential for selecting the plurality of circuits is supplied to the wiring EL. Thus, data stored in the plurality of circuits is erased. | 2016-04-07 |
20160099259 | Wiring Layer and Manufacturing Method Therefor - To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor. | 2016-04-07 |
20160099260 | DISPLAY PANEL - A display panel includes a substrate, a plurality of first signal lines, a plurality of second signal lines, a plurality of pixel units, a plurality of transmitting lines, and a driving chip. The transmitting lines are disposed on the substrate and electrically connected to the second signal lines. The driving chip includes a plurality of first pins, a plurality of second pins, and a driving circuit. The first pins are electrically connected to the first signal lines, and the second pins are electrically connected to the transmitting lines. The first pins and the second pins are disposed alternately and evenly, such that the first signal lines and the transmitting lines do not intersect each other. The transmitting lines are disposed on the substrate evenly. | 2016-04-07 |
20160099261 | Metal Wiring and Method of Manufacturing the Same, and Metal Wiring Substrate and Method of Manufacturing the Same - A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle α in accordance with the bias power density, the ICP power density, the temperature of lower electrode, the pressure, the total flow rate of etching gas, or the ratio of oxygen or chlorine in etching gas. The thus formed metal wiring has less fluctuation in width or length and can satisfactorily deal with an increase in size of substrate. | 2016-04-07 |
20160099262 | Hybrid Pixel Control Circuits for Light-Emitting Diode Display - An electronic device may include a display. The display may be formed by an array of light-emitting diodes mounted to the surface of a substrate. The light-emitting diodes may be inorganic light-emitting diodes formed from separate crystalline semiconductor structures. An array of pixel control circuits may be used to control light emission from the light-emitting diodes. Each pixel control circuit may be used to supply drive signals to a respective set of the light-emitting diodes. The pixel control circuits may each have a silicon integrated circuit that includes transistors such as emission enable transistors and drive transistors for supplying the drive signals and may each have thin-film semiconducting oxide transistors that are coupled to the integrated circuit and that serve as switching transistors. | 2016-04-07 |
20160099263 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a display device and a method of manufacturing of the display device. The display device includes a substrate subjected to a primary preprocess; a conductor formed on the substrate and subjected to a secondary preprocess; and an insulating layer formed on the substrate and the conductor, in which the primary preprocess is performed for a surface energy of the first substrate higher than a first reference value and the secondary preprocess is performed for a surface energy of the conductor lower than a second reference value. | 2016-04-07 |
20160099264 | SYSTEM AND METHOD OF MANUFACTURING A THIN FILM TRANSISTOR SUBSTRATE - In a method of manufacturing a thin film transistor substrate, a first metal layer is formed on a first surface of a base substrate. The base substrate is cooled by contacting the first metal layer with a first cooling plate and by contacting a second surface of the base substrate with a second cooling plate. The first and second surfaces of the base substrate face opposite directions. A gate electrode is formed by patterning the first metal layer. A source electrode and a drain electrode are formed. The source electrode is spaced apart from the drain electrode. The source and drain electrodes partially overlap the gate electrode. A pixel electrode electrically connected to the drain electrode is formed. | 2016-04-07 |
20160099265 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus includes a base substrate, a pixel on the base substrate, and a color filter part between the base substrate and the pixel. The pixel includes a cover layer defining a TSC (Tunnel Shaped Cavity) on the base substrate, an image display part provided in the TSC, and first and second electrodes which apply an electric field to the image display part. | 2016-04-07 |
20160099266 | SELF-ALIGNED ISOLATION STRUCTURES AND LIGHT FILTERS - An image sensor includes a semiconductor layer with a plurality of photodiodes. A plurality of isolation structures is disposed in the back side of the semiconductor layer between individual photodiodes in the plurality of photodiodes. The plurality of isolation structures extend into the back side of the semiconductor layer a first depth and extend out of the back side of the semiconductor layer a first length. A plurality of light filters is disposed proximate to the back side of the semiconductor layer such that the plurality of isolation structures is disposed between individual light filters in the plurality of light filters. An antireflection coating is also disposed between the semiconductor layer and the plurality of light filters. | 2016-04-07 |
20160099267 | CMOS IMAGE SENSOR FOR REDUCING DEAD ZONE - An image sensor such as a complementary metal-oxide-semiconductor (CMOS) image sensor and a method of manufacturing the same are provided. The CMOS image sensor includes: a semiconductor substrate including a first surface and a third surface formed by removing a part of the semiconductor substrate from a second surface opposite to the first surface; a plurality of active regions which are formed between the first surface and the third surface and each of which includes a photoelectric conversion element generating charges in response to light input through the third surface; and an isolation region vertically formed from either of the first and third surfaces to isolate the active regions from one another. When the CMOS image sensor is viewed from the above of the third surface, each of the active regions may have round corners and concave sides. | 2016-04-07 |
20160099268 | IMAGING APPARATUS AND IMAGING SYSTEM - Provided is an imaging apparatus, including a pixel region in which a plurality of pixels are arranged, the plurality of pixels each including: a plurality of photoelectric converters configured to generate charges corresponding to an amount of incident light; a plurality of charge holding portions arranged correspondingly to the plurality of photoelectric converters and configured to hold charges generated by the plurality of photoelectric converters respectively; and a light condensing portion arranged so as to be shared by the plurality of photoelectric converters and configured to guide the incident light to the plurality of photoelectric converters. In the imaging apparatus, a height (Vb) of a first potential barrier between two charge holding portions included in the a pixel is lower than a height (Va) of a second potential barrier between two charge holding portions included in different pixels. | 2016-04-07 |
20160099269 | Fully Differential Output Swing for Analog Array Based Charge Mode Readout used in a CMOS Image Sensor - Disclosed herein are novel charge mode readout circuits and associated methods of signal processing. The devices and methods of the invention allow for the improved processing of stored signals by a charge mode readout amplifier, wherein the readout level may be shifted to a desired range and wherein a fully differential output swing may be imparted. The invention advantageously employs a single pair of capacitors to serve the dual roles of modulating amplifier gain and level shifting the output. | 2016-04-07 |
20160099270 | IMAGE-SENSOR STRUCTURES - An image-sensor structure is provided. The image-sensor structure includes a substrate, a plurality of photoelectric conversion units formed in the substrate, and a plurality of color filter patterns including a red filter pattern having a first refractive index, a green filter pattern having a second refractive index and a blue filter pattern having a third refractive index formed above the substrate and the photoelectric conversion units, wherein at least one color filter pattern contains a component having a specific refractive index such that the second refractive index of the green filter pattern is higher than the first refractive index of the red filter pattern and the third refractive index of the blue filter pattern. | 2016-04-07 |
20160099271 | INFRARED IMAGE SENSOR - An image sensor includes a substrate, dual-waveband photosensitive devices, at least one infrared photosensitive device, a transparent dielectric layer, at least one infrared band-pass filter, a color filter layer and a micro-lens layer. The dual-waveband photosensitive devices are disposed in the substrate, and each dual-waveband photosensitive device is configured to sense an infrared light and one visible light. The infrared photosensitive device is disposed in the substrate, in which the dual-waveband photosensitive devices and the infrared photosensitive device are arranged in an array. The transparent dielectric layer is disposed over the dual-waveband photosensitive devices and the infrared photosensitive device. The infrared band-pass filter is disposed in the transparent dielectric layer and corresponds to the infrared photosensitive device. The color filter layer is disposed to cover the transparent dielectric layer and the infrared band-pass filter. The micro-lens layer is disposed on the color filter layer. | 2016-04-07 |
20160099272 | STACKED FILTER AND IMAGE SENSOR CONTAINING THE SAME - A stacked filter for an image sensor including an infrared (IR) pixel is provided. The stacked filter includes a first filter layer disposed at the IR pixel. The first filter layer allows light with wavelengths of a first band to be transmitted through. The stacked filter further includes a second filter layer stacked with the first filter layer. The second filter layer allows light with wavelengths of a second band to be transmitted through. The first band partially overlaps the second band at wavelengths of a third band. The third band is narrower than the first band and the second band. The stacked filter allows light with the wavelengths of the third band to be transmitted through. Furthermore, an image sensor containing a stacked filter is also provided. | 2016-04-07 |
20160099273 | IMAGERS WITH DEPTH SENSING CAPABILITIES - An imager may include depth sensing pixels that provide an asymmetrical angular response to incident light. The depth sensing pixels may each include a substrate region formed from a photosensitive portion and a non-photosensitive portion. The depth sensing pixels may include mechanisms that prevent regions of the substrate from receiving incident light. Depth sensing pixel pairs may be formed from depth sensing pixels that have different asymmetrical angular responses. Each of the depth sensing pixel pairs may effectively divide the corresponding imaging lens into separate portions. Depth information for each depth sensing pixel pair may be determined based on the difference between output signals of the depth sensing pixels of that depth sensing pixel pair. The imager may be formed from various combinations of depth sensing pixel pairs and color sensing pixel pairs arranged in a Bayer pattern or other desired patterns. | 2016-04-07 |
20160099274 | 3D HIGH RESOLUTION X-RAY SENSOR WITH INTEGRATED SCINTILLATOR GRID - Various embodiments of a 3D high resolution X-ray sensor are described. In one aspect, an indirect X-ray sensor includes a silicon wafer that includes an array of photodiodes thereon with each of the photodiodes having a contact on a front side of the silicon wafer and self-aligned with a respective grid hole of an array of grid holes that are on a back side of the silicon wafer. Each of the grid holes is filled with a scintillator configured to convert beams of X-ray into light. The indirect X-ray sensor also includes one or more silicon dies with an array of photo-sensing circuits each of which including a contact at a top surface of the one or more silicon dies. Contact on each of the photodiodes is aligned and bonded to contact of a respective photo-sensing circuit of the array of photo-sensing circuits of the one or more silicon dies. | 2016-04-07 |
20160099275 | SOLID-STATE IMAGING DEVICE AND CAMERA SYSTEM - There is provided a solid-state imaging device including a wafer in which a guard ring with conductivity in an insulation film layered on a first conductivity type substrate is formed between an edge portion of at least a first chip, out of the first chip and a second chip of a layered chip, and a scribe line region, at least two second conductivity type layers are formed at an interval within a region corresponding to the guard ring, in the first conductivity type substrate, and the guard ring includes a first guard ring part connected to one of the second conductivity type layers on a chip edge portion side, and a second guard ring part connected to another one of the second conductivity type layers on a scribe line side. | 2016-04-07 |
20160099276 | IMAGE SENSOR WITH HYBRID HETEROSTRUCTURE - An image sensor architecture provides an SNR in excess of 100 dB, without requiring the use of a mechanical shutter. The circuit components for an active pixel sensor array are separated and arranged vertically in at least two different layers in a hybrid chip structure. The top layer is preferably manufactured using a low-noise PMOS manufacturing process, and includes the photodiode and amplifier circuitry for each pixel. A bottom layer is preferably manufactured using a standard CMOS process, and includes the NMOS pixel circuit components and any digital circuitry required for signal processing. By forming the top layer in a PMOS process optimized for forming low-noise pixels, the pixel performance can be greatly improved, compared to using CMOS. In addition, since the digital circuitry is now separated from the imaging circuitry, it can be formed using a standard CMOS process, which has been optimized for circuit speed and manufacturing cost. By combining the two layers into a stacked structure, the top layer (and any intermediate layer(s)) acts to optically shield the lower layer, thereby allowing charge to be stored and shielded without the need for a mechanical shutter. | 2016-04-07 |
20160099277 | 3D HIGH RESOLUTION X-RAY SENSOR WITH INTEGRATED SCINTILLATOR GRID - Various embodiments of a 3D high resolution X-ray sensor are described. In one aspect, an indirect X-ray sensor includes a silicon wafer that includes an array of photodiodes thereon with each of the photodiodes having a contact on a front side of the silicon wafer and self-aligned with a respective grid hole of an array of grid holes that are on a back side of the silicon wafer. Each of the grid holes is filled with a scintillator configured to convert beams of X-ray into light. The indirect X-ray sensor also includes one or more silicon dies with an array of photo-sensing circuits each of which including a contact at a top surface of the one or more silicon dies. Contact on each of the photodiodes is aligned and bonded to contact of a respective photo-sensing circuit of the array of photo-sensing circuits of the one or more silicon dies. | 2016-04-07 |
20160099278 | BACK-ILLUMINATED INTEGRATED IMAGING DEVICE WITH SIMPLIFIED INTERCONNECT ROUTING - A back-illuminated integrated imaging device is formed from a semiconductor substrate including a zone of pixels bounded by capacitive deep trench isolations. A peripheral zone is located outside the zone of pixels. A continuous electrically conductive layer forms, in the zone of pixels, an electrode in a trench for each capacitive deep trench isolation, and forms, in the peripheral zone, a redistribution layer for electrically coupling the electrode to a biasing contact pad. The electrode is located in the trench between a trench dielectric and at least one material for filling the trench. | 2016-04-07 |
20160099279 | IMAGE SENSOR WITH DEEP WELL STRUCTURE AND FABRICATION METHOD THEREOF - An image sensor device includes a substrate having a first conductivity type. A plurality of photo-sensing regions including a first, a second, and a third photo-sensing regions corresponding to the R, G, B pixels are provided on the substrate. An insulation structure is disposed on the substrate to separate the photo-sensing regions from one another. A photodiode structure is formed within each photo-sensing region. A deep well structure having a second conductivity type. The deep well structure only overlaps with the second and third photo-sensing regions. The deep well structure does not overlap with the first photo-sensing region. | 2016-04-07 |
20160099280 | IMAGE SENSORS AND METHODS OF FORMING THE SAME - An image sensor is provided. The image sensor includes a red (R) pixel, a green (G) pixel, a blue (B) pixel and an infrared (IR) pixel, and R, G and B filters respectively disposed at the R, G and B pixels. The image sensor also includes an IR pass filter disposed at the IR pixel and an IR filter stacked with the R, G and B filters, wherein the IR filter cuts off at least IR light with a specific wavelength. Furthermore, a method of forming an image sensor is also provided. | 2016-04-07 |
20160099281 | 3D HIGH RESOLUTION X-RAY SENSOR WITH INTEGRATED SCINTILLATOR GRID - Various embodiments of a 3D high resolution X-ray sensor are described. In one aspect, an indirect X-ray sensor includes a silicon wafer that includes an array of photodiodes thereon with each of the photodiodes having a contact on a front side of the silicon wafer and self-aligned with a respective grid hole of an array of grid holes that are on a back side of the silicon wafer. Each of the grid holes is filled with a scintillator configured to convert beams of X-ray into light. The indirect X-ray sensor also includes one or more silicon dies with an array of photo-sensing circuits each of which including a contact at a top surface of the one or more silicon dies. Contact on each of the photodiodes is aligned and bonded to contact of a respective photo-sensing circuit of the array of photo-sensing circuits of the one or more silicon dies. | 2016-04-07 |
20160099282 | 3D HIGH RESOLUTION X-RAY SENSOR WITH INTEGRATED SCINTILLATOR GRID - Various embodiments of a 3D high resolution X-ray sensor are described. In one aspect, an indirect X-ray sensor includes a silicon wafer that includes an array of photodiodes thereon with each of the photodiodes having a contact on a front side of the silicon wafer and self-aligned with a respective grid hole of an array of grid holes that are on a back side of the silicon wafer. Each of the grid holes is filled with a scintillator configured to convert beams of X-ray into light. The indirect X-ray sensor also includes one or more silicon dies with an array of photo-sensing circuits each of which including a contact at a top surface of the one or more silicon dies. Contact on each of the photodiodes is aligned and bonded to contact of a respective photo-sensing circuit of the array of photo-sensing circuits of the one or more silicon dies. | 2016-04-07 |
20160099283 | PHOTOSENSOR WITH CHANNEL REGION HAVING CENTER CONTACT - A pixel cell includes a charge accumulation region having a second doping polarity buried completely in a semiconductor substrate having a first doping polarity beneath a first surface. The charge accumulation region accumulates image charge in response to light directed through a second surface. A channel region is disposed in the semiconductor substrate between the first surface and the charge accumulation region. A variable resistance of the channel region is responsive to the image charge accumulated in the charge accumulation region. A center contact coupled to a central portion of the channel region through the first surface to provide a radial current path through the channel region between the central portion of the channel region and a periphery of the channel region around the charge accumulation region to the semiconductor substrate. A readout signal responsive to the image charge in the charge accumulation region is provided at the center contact. | 2016-04-07 |
20160099284 | MINIATURE WAFER-LEVEL CAMERA MODULES - In one aspect, a method includes providing a lens substrate having an array of lenses. The lens substrate includes an overflow region next to each lens of the array. Each overflow region includes an overflow lens material. The method also includes separating the lens substrate into a plurality of smaller lens substrates. Each of the smaller lens substrates has one of the single lens and the plurality of stacked lenses. Separating the lens substrate into the smaller lens substrates may include removing or substantially removing the overflow regions. In one aspect, the method may be performed as a method of making a miniature camera module. Other methods are also described, as are miniature camera modules. | 2016-04-07 |
20160099285 | METHOD FOR MANUFACTURING SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING CAMERA MODULE - Certain embodiments provide a method for manufacturing a solid-state imaging device including: forming a sensor chip fixed to a supporting substrate by a first adhesive; peeling off the sensor chip from the supporting substrate by softening the first adhesive; and fixing the peeled off sensor chip onto a curved surface of a mounting body to allow the sensor chip to be curved along the curved surface. | 2016-04-07 |
20160099286 | SEMICONDUCTOR DEVICE INCLUDING IMAGE PICK UP DEVICE - The performance of a semiconductor device is improved by preventing 1/f noise from being generated in a peripheral transistor, in the case where the occupation area of photodiodes, which are included in each of a plurality of pixels that form an image pickup device, is expanded. In the semiconductor device, the gate electrode of an amplification transistor is formed by both a gate electrode part over an active region and a large width part that covers the boundary between the active region and an element isolation region and the active region near the boundary and that has a gate length larger than that of the gate electrode part. | 2016-04-07 |