14th week of 2022 patent applcation highlights part 47 |
Patent application number | Title | Published |
20220109038 | DISPLAY DEVICE - A display device according to an embodiment of the present disclosure includes a display panel including a display region and a non-display region, and a sensor unit which is disposed on the display panel and includes a sensing region and a non-sensing region. The sensor unit includes a touch sensor unit which detects a touch input in the sensing region and a photo sensor unit which detects ambient illuminance. | 2022-04-07 |
20220109039 | DISPLAY APPARATUS - A display apparatus includes: a substrate including a main display area, a component area, and a peripheral area; a plurality of main pixel electrodes in the main display area of the substrate; a plurality of auxiliary pixel electrodes in the component area of the substrate; an auxiliary opposite electrode over the auxiliary pixel electrodes, overlapping the auxiliary pixel electrodes, and including a plurality of openings between the auxiliary pixel electrodes; and a shield layer below the auxiliary pixel electrodes and including a plurality of opening portions that overlap the openings of the auxiliary opposite electrode. | 2022-04-07 |
20220109040 | DISPLAY PANEL AND DISPLAY APPARATUS INCLUDING THE SAME - A display panel includes: a display area including a main display area, and a component area; a peripheral area; a plurality of main pixel circuits at the main display area; a plurality of main gate lines extending in a first direction, and connected to the main pixel circuits; a plurality of main data lines extending in a second direction, and connected to the main pixel circuits; a plurality of auxiliary display elements at the component area; a plurality of auxiliary pixel circuits at the periphery area, and connected to the auxiliary display elements; a plurality of auxiliary gate lines connected to the auxiliary pixel circuits, and to main gate lines that are adjacent to the component area in the first direction; and a plurality of auxiliary data lines connected to the auxiliary pixel circuits, and to main data lines that are adjacent to the component area in the second direction. | 2022-04-07 |
20220109041 | DISPLAY DEVICE - A display device includes a display panel including a bending area and a non-bending area adjacent to the bending area, a base substrate disposed under the display panel and including a through-hole overlapping the bending area, a conductive part filling the through-hole, a flexible printed circuit board including a first surface connected to the conductive part and second a surface opposite to the first surface, a first film contacting the first surface of the flexible printed circuit board overlapping the non-bending area, and a protection member contacting an upper surface of the first film. | 2022-04-07 |
20220109042 | DISPLAY PANEL AND DISPLAY DEVICE INCLUDING THE SAME - A display device includes a substrate, a first barrier layer on the substrate, a lower pattern on the first barrier layer and having a mesh shape defining a disconnection area, a second barrier layer on the first barrier layer, covering the lower pattern, and contacting the first barrier layer in the disconnection area, and a first active pattern on the second barrier layer and overlapping the lower pattern, a gate electrode on the first active pattern and overlapping the lower pattern, a first gate line on the first active pattern extending in a first direction, a second active pattern on the first gate line, a second gate line on the second active pattern extending in the first direction, and a data line on the second gate line extending in a second direction crossing the first direction. | 2022-04-07 |
20220109043 | DISPLAY APPARATUS - A display apparatus includes: a plurality of pixel circuits at a display area, the display area having a non-quadrangular shape; a first signal line extending on the display area in a first direction, and electrically connected to a first pixel circuit from among the plurality of pixel circuits; a first voltage line extending on the display area in the first direction; a first load compensation capacitor adjacent to an end portion of the first signal line and an end portion of the first voltage line; a test circuit outside the display area; an output line electrically connected to the test circuit; and a connection portion configured to electrically connect the output line, the first signal line, and an electrode of the first load compensation capacitor to each other. | 2022-04-07 |
20220109044 | SEMICONDUCTOR DEVICE - A semiconductor substrate has a transistor region, a diode region, and an outer peripheral region. The transistor region is divided into a plurality of transistor unit cell regions by a plurality of gate electrodes each having a stripe shape, and the diode region is divided into a plurality of diode unit cell regions by the plurality of gate electrodes. Each of the plurality of transistor unit cell regions has a third semiconductor layer of a first conductivity type provided on a first main surface side of the semiconductor substrate, a fourth semiconductor layer of a second conductivity type selectively provided on an upper layer part of the third semiconductor layer, and a fifth semiconductor layer. | 2022-04-07 |
20220109045 | Isolation Method To Enable Continuous Channel Layer - A method of isolating sections of the channel layer in a SOI workpiece is disclosed. Rather than etching material to create trenches, which are then filled with a dielectric material, ions are implanted into portions of the channel layer to transform these implanted regions from silicon or silicon germanium into an electrically insulating material. These ions may comprise at least one isolating species, such as oxygen, nitrogen, carbon or boron. This eliminates various processes from the fabrication sequence, including an etching process and a deposition process. Advantageously, this approach also results in greater axial strain in the channel layer, since the channel layer is continuous across the workpiece. | 2022-04-07 |
20220109046 | SEMICONDUCTOR DEVICE HAVING STEPPED MULTI-STACK TRANSISTOR STRUCTURE - A semiconductor device include: a substrate; a 1 | 2022-04-07 |
20220109047 | CROSSING MULTI-STACK NANOSHEET STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate; a 1 | 2022-04-07 |
20220109048 | High Voltage Gallium Nitride Field Effect Transistor - A gallium nitride (GaN) semiconductor device has first and second electrodes connected to a top metal layer disposed in complementary first and second irregular shapes, each irregular shape including a wide connection area at a first end, a tapered area, and a narrow area at a second end. The first and second irregular shapes are arranged adjacent each other along complementary edges such that a gap between the complementary edges is of substantially constant width. The first and second wide connection areas include pads for wire bond or land grid array electrical connections to external circuitry. The first and second irregular shapes for source and drain metal of a field effect transistor (FET) or high electron mobility transistor (HEMT) allows the width of the gate finger to be short so that electrical current injected from the gate can reach all portions of the gate fingers efficiently during high frequency switching, making the topology suitable for high voltage power devices. | 2022-04-07 |
20220109049 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a trench, a gate insulating film, a gate electrode, and an interlayer insulating film. The first semiconductor layer and the second semiconductor layer constitute a first-conductivity-type semiconductor layer and in a deep region of the first-conductivity-type semiconductor layer at least 1 μm from an interface with the third semiconductor layer, a maximum value of a concentration of aluminum is less than 3.0×10 | 2022-04-07 |
20220109050 | MOS-Based Power Semiconductor Device Having Increased Current Carrying Area and Method of Fabricating Same - A semiconductor device includes at least a first lateral MOSFET formed on a semiconductor substrate. The first lateral MOSFET has an interface defined by a plurality of trenches along which the current flow can be modulated by a perpendicular electric field. The portion of the interface lies on a plane substantially perpendicular to the plane of the substrate. The interface is configured such that at least a portion of the current flow along the portion of the interface that lies on a plane substantially perpendicular to the plane of the substrate is in a direction substantially parallel to the plane of the substrate. | 2022-04-07 |
20220109051 | SUPERLATTICE STRUCTURE INCLUDING TWO-DIMENSIONAL MATERIAL AND DEVICE INCLUDING THE SUPERLATTICE STRUCTURE - Provided are a superlattice structure including a two-dimensional material and a device including the superlattice structure. The superlattice structure may include at least two different two-dimensional (2D) materials bonded to each other in a lateral direction, and an interfacial region of the at least two 2D materials may be strained. The superlattice structure may have a bandgap adjusted by the interfacial region that is strained. The at least two 2D materials may include first and second 2D materials. The first 2D material may have a first bandgap in an intrinsic state thereof. The second 2D material may have a second bandgap in an intrinsic state thereof. An interfacial region of the first and second 2D materials and an adjacent region may have a third bandgap between the first bandgap and the second bandgap. | 2022-04-07 |
20220109052 | GRAPHENE-BASED TFT COMPRISING NITROGEN-DOPED GRAPHENE LAYER AS ACTIVE LAYER - Disclosed is a high-quality and high-functional graphene-based TFT, including: a gate electrode, a gate insulating layer disposed on the gate electrode; an active layer including a nitrogen-doped graphene layer, on which disposed in a partial region of the gate insulating layer; a first electrode disposed on a region of one side of the active layer; and a second electrode disposed on a region of the other side of the active layer. The present invention allows obtaining the TFT having excellent characteristics by directly growing graphene on a Ti layer, implementing damages with remote plasma, and doping with nitrogen gas to fabricate a graphene active layer. | 2022-04-07 |
20220109053 | OPTIMIZED CONTACT STRUCTURE - Disclosed are optimized contract structures and fabrication techniques thereof. At least one aspect includes a semiconductor die. The semiconductor die includes a substrate and a contact disposed within the substrate. The contact includes a first portion with a first vertical cross-section having a first cross-sectional area. The first vertical cross-section has a first width and a first height. The contact also includes a second portion with a second vertical cross-section having a second cross-sectional area less than the first cross-sectional area. The second vertical cross-section includes a lower portion having the first width and a second height less than the first height, and an upper portion disposed above the lower portion and having a second width less than the first width and having a third height less than the first height. | 2022-04-07 |
20220109054 | HIGH VOLTAGE FIELD EFFECT TRANSISTOR WITH VERTICAL CURRENT PATHS AND METHOD OF MAKING THE SAME - A field effect transistor for a high voltage operation can include vertical current paths, which may include vertical surface regions of a pedestal semiconductor portion that protrudes above a base semiconductor portion. The pedestal semiconductor portion can be formed by etching a semiconductor material layer employing a gate structure as an etch mask. A dielectric gate spacer can be formed on sidewalls of the pedestal semiconductor portion. A source region and a drain region may be formed underneath top surfaces of the base semiconductor portion. Alternatively, epitaxial semiconductor material portions can be grown on the top surfaces of the base semiconductor portions, and a source region and a drain region can be formed therein. Alternatively, a source region and a drain region can be formed within via cavities in a planarization dielectric layer. | 2022-04-07 |
20220109055 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes, first and second source/drain patterns on an active pattern and spaced apart from each other, a first source/drain contact on the first source/drain pattern and including a first source/drain barrier film and a first source/drain filling film on the first source/drain barrier film, a second source/drain contact on the second source/drain pattern, and a gate structure on the active pattern between the first and second source/drain contacts and including a gate electrode, wherein a top surface of the first source/drain contact is lower than a top surface of the gate structure, and a height from a top surface of the active pattern to a top surface of the first source/drain barrier film is less than a height from the top surface of the active pattern to a top surface of the first source/drain filling film. | 2022-04-07 |
20220109056 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a III-V material layer and a gate structure. The gate structure includes a first portion and a second portion on the first portion. The first portion is on the III-V material layer. The first portion has a first surface and a second surface opposite to the first surface and adjacent to the III-V material layer. A length of the second surface of the first portion of the gate structure is less than a length of the first surface of the first portion of the gate structure. A length of the second portion of the gate structure is less than the length of the first portion of the gate structure. | 2022-04-07 |
20220109057 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Disclosed are a semiconductor device and a method of fabricating the same. The device may include a substrate, an active pattern in an upper portion of the substrate and is extending in a first direction, a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction, a first gate spacer covering a side surface of the gate electrode, a first inhibition layer between the gate electrode and the first gate spacer, and a gate insulating layer between the gate electrode and the active pattern. The gate insulating layer may include a high-k dielectric layer and a gate oxide layer. The gate oxide layer may be between the high-k dielectric layer and the active pattern. The high-k dielectric layer may be between the gate oxide layer and the gate electrode. | 2022-04-07 |
20220109058 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a second barrier layer on the first barrier layer; forming a first hard mask on the second barrier layer; removing the first hard mask and the second barrier layer to form a recess; and forming a p-type semiconductor layer in the recess. | 2022-04-07 |
20220109059 | LOW TEMPERATURE POLYCRYSTALLINE SEMICONDUCTOR DEVICE AMD MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device includes steps of (i) forming a buffer layer of an insulating material on a substrate, (ii) forming a seed layer of catalyst material containing Ni on the buffer layer, (iii) forming, on the buffer layer, an amorphous intrinsic silicon layer for forming a channel, (iv) forming, on the amorphous intrinsic silicon layer, a non-intrinsic silicon layer for forming a source and/or drain, (v) forming a metal layer on the non-intrinsic silicon layer, and (vi) performing metal induced crystallization (MIC) process for crystallization of the amorphous intrinsic silicon layer and the amorphous non-intrinsic silicon layer, and activation of the amorphous non-intrinsic silicon layer to form a conductive area. | 2022-04-07 |
20220109060 | Semiconductor Device and Method - Methods are disclosed for forming a multi-layer structure including highly controlled diffusion interfaces between alternating layers of different semiconductor materials. According to embodiments, during a deposition of semiconductor layers, the process is controlled to remain at low temperatures such that an inter-diffusion rate between the materials of the deposited layers is managed to provide diffusion interfaces with abrupt Si/SiGe interfaces. The highly controlled interfaces and first and second layers provide a multi-layer structure with improved etching selectivity. In an embodiment, a gate all-around (GAA) transistor is formed with horizontal nanowires (NWs) from the multi-layer structure with improved etching selectivity. In embodiments, horizontal NWs of a GAA transistor may be formed with substantially the same size diameters and silicon germanium (SiGe) NWs may be formed with “all-in-one” silicon (Si) caps. | 2022-04-07 |
20220109061 | SEMICONDUCTOR DEVICE - In plan view of an RC-IGBT, a boundary region has an occupancy rate of an n | 2022-04-07 |
20220109062 | SEMICONDUCTOR DEVICE | 2022-04-07 |
20220109063 | SEMICONDUCTOR DEVICE - A transistor and a diode are formed on a common semiconductor substrate; the semiconductor substrate has a transistor region and an outer peripheral region surrounding it; the transistor region is divided into a plurality of channel regions and a plurality of non-channel regions by a plurality of gate electrodes each having a stripe shape; each of the plurality of non-channel regions has a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fifth semiconductor layer, a first electrode, and a second electrode; the third semiconductor layer and the fifth semiconductor layer are electrically connected to the second electrode via a contact hole; and the fifth semiconductor layer is selectively provided not to be in contact with an impurity layer of a first conductivity type that is provided in the outer peripheral region and defines a boundary with a cell region. | 2022-04-07 |
20220109064 | SEMICONDUCTOR MATERIALS AND DEVICES INCLUDING III-NITRIDE LAYERS INTEGRATED WITH SCANDIUM ALUMINUM NITRIDE | 2022-04-07 |
20220109065 | ACTIVE PATTERN STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - An active pattern structure includes a lower active pattern protruding from an upper surface of a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a buffer structure on the lower active pattern, at least a portion of which may include aluminum silicon oxide, and an upper active pattern on the buffer structure. | 2022-04-07 |
20220109066 | DUAL SILICIDE WRAP-AROUND CONTACTS FOR SEMICONDUCTOR DEVICES - Low-resistivity dual silicide contacts for aggressively scaled semiconductor devices. A semiconductor device includes a first raised feature in a n-type channel field effect transistor (NFET) region on a substrate, a first n-type doped epitaxial semiconductor material wrapped around the first raised feature, a first metal silicide contact layer wrapped around the first n-type doped epitaxial semiconductor material, a second raised feature in p-type channel field effect transistor (PFET) region on the substrate, a second p-type epitaxial semiconductor material wrapped around the second raised feature, and a second metal silicide contact layer wrapped around the second p-type doped epitaxial semiconductor material. The first metal silicide contact layer can include a titanium silicide and the second metal silicide contact layer can include a ruthenium silicide. | 2022-04-07 |
20220109067 | FINFET TRANSISTOR - A semiconductor device includes a semiconductor substrate having isolation regions formed therein and a fin-shaped semiconductor structure protruding vertically above the isolation regions and extending laterally in a first direction. The device additionally includes a gate dielectric wrapping a channel region of the fin-shaped semiconductor structure and a gate electrode wrapping the gate dielectric. The channel region is interposed in the first direction between a source region and a drain region and has sloped sidewalls and a width that continuously decreases from a base towards a peak of the channel region. The channel region comprises a volume inversion region having a height greater than about 25% of a total height of the channel region. | 2022-04-07 |
20220109068 | FIELD ELECTRODE TERMINATION STRUCTURE FOR TRENCH-BASED TRANSISTOR DEVICES - A semiconductor device includes: a trench formed in a surface of a semiconductor substrate and extending lengthwise in a direction parallel to the surface; a body region adjoining the trench; a source region adjoining the trench above the body region; a drift region adjoining the trench below the body region; a field electrode in a lower part of the trench and separated from the substrate; and a gate electrode in an upper part of the trench and separated from the substrate and the field electrode. A first section of the field electrode is buried below the gate electrode in the trench. A second section of the field electrode transitions upward from the first section in a direction toward the surface. The separation between the second section and the gate electrode is greater than or equal to the separation between the first section and the gate electrode. | 2022-04-07 |
20220109069 | SEMICONDUCTOR TRANSISTORS ON MULTI-LAYERED SUBSTRATES - A semiconductor device is provided, which includes a multi-layered substrate, a first doped region, a second doped region, and a gate structure. The multi-layered substrate has a device layer over an isolation layer and the device layer includes a first region having a first substrate thickness and a second region having a second substrate thickness that is lesser than the first substrate thickness. The first doped region is in the first region and the second doped region is in the second region. The gate structure is between the first and second doped regions. | 2022-04-07 |
20220109070 | HIGH VOLTAGE FIELD EFFECT TRANSISTOR WITH VERTICAL CURRENT PATHS AND METHOD OF MAKING THE SAME - A field effect transistor for a high voltage operation can include vertical current paths, which may include vertical surface regions of a pedestal semiconductor portion that protrudes above a base semiconductor portion. The pedestal semiconductor portion can be formed by etching a semiconductor material layer employing a gate structure as an etch mask. A dielectric gate spacer can be formed on sidewalls of the pedestal semiconductor portion. A source region and a drain region may be formed underneath top surfaces of the base semiconductor portion. Alternatively, epitaxial semiconductor material portions can be grown on the top surfaces of the base semiconductor portions, and a source region and a drain region can be formed therein. Alternatively, a source region and a drain region can be formed within via cavities in a planarization dielectric layer. | 2022-04-07 |
20220109071 | HIGH VOLTAGE FIELD EFFECT TRANSISTOR WITH VERTICAL CURRENT PATHS AND METHOD OF MAKING THE SAME - A field effect transistor for a high voltage operation can include vertical current paths, which may include vertical surface regions of a pedestal semiconductor portion that protrudes above a base semiconductor portion. The pedestal semiconductor portion can be formed by etching a semiconductor material layer employing a gate structure as an etch mask. A dielectric gate spacer can be formed on sidewalls of the pedestal semiconductor portion. A source region and a drain region may be formed underneath top surfaces of the base semiconductor portion. Alternatively, epitaxial semiconductor material portions can be grown on the top surfaces of the base semiconductor portions, and a source region and a drain region can be formed therein. Alternatively, a source region and a drain region can be formed within via cavities in a planarization dielectric layer. | 2022-04-07 |
20220109072 | REDUCING BAND-TO-BAND TUNNELING IN SEMICONDUCTOR DEVICES - Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials. | 2022-04-07 |
20220109073 | PASSIVATION LAYER AND PREPARATION METHOD THEREOF, FLEXIBLE THIN FILM TRANSISTOR AND PREPARATION METHOD THEREOF, AND ARRAY SUBSTRATE - The present disclosure discloses a passivation layer and a preparation method thereof, a flexible thin film transistor and a preparation method thereof, and an array substrate. The passivation layer of the present disclosure is a self-assembled monolayer formed by hydrophobic substances with a melting point of less than 100° C. The flexible thin film transistor of the present disclosure comprises a flexible substrate, a gate electrode, a gate dielectric layer, an active layer, a source-drain electrode layer and the passivation layer of the present disclosure. | 2022-04-07 |
20220109074 | FERROELECTRIC-ASSISTED TUNNELING SELECTOR DEVICE - A selector device may include a first electrode, a tunneling layer, and a ferroelectric layer. The tunneling layer may be between the first electrode and the ferroelectric layer, and a thickness and dielectric constant of the tunneling layer relative to a thickness and dielectric constant of the ferroelectric layer may cause a depolarizing electric field induced in the first tunneling layer to be greater than or approximately equal to an electric field induced in an opposite direction by ferroelectric dipoles in the ferroelectric layer when a voltage is applied across the selector device. The device may also include a second electrode, and the ferroelectric layer may be between the tunneling layer and the second electrode. A second ing layer may also be added between the ferroelectric layer and the second electrode for bipolar selectors. | 2022-04-07 |
20220109075 | OPTOELECTRONIC MODULE PACKAGE - An optoelectronic module. In some embodiments, the optoelectronic module includes: a substrate; a digital integrated circuit, on an upper surface of the substrate; and a frame, secured in a pocket of the substrate. The pocket is in a lower surface of the substrate, and the substrate includes an insulating layer, and a plurality of conductive traces. | 2022-04-07 |
20220109076 | INFRARED SENSOR USING CARBON NANOTUBES AND METHOD FOR MANUFACTURING SAME - An object of the present invention is to provide an infrared sensor having a high TCR value, and a method for manufacturing the infrared sensor. The infrared sensor comprises a substrate, a first electrode on the substrate, a second electrode spaced from the first electrode on the substrate, and a carbon nanotube layer electrically connected with the first electrode and the second electrode, wherein the carbon nanotube layer comprises semiconducting carbon nanotubes in an amount more than 66% by mass based on the total amount of carbon nanotubes and 60% or more of the carbon nanotubes contained in the carbon nanotube layer have a diameter within a range of 0.6 to 1.5 nm and a length within a range of 100 nm to 5 μm. | 2022-04-07 |
20220109077 | SOLAR CELL - The present invention relates to a method for manufacturing a solar cell, the method comprising the steps of: preparing a substrate; forming an adhesive layer on the substrate; and forming, on the adhesive layer, a perovskite solar cell having a perovskite absorption layer, wherein an optical treatment step of providing light is performed at least once between the step of preparing the substrate and the step of forming the perovskite solar cell. | 2022-04-07 |
20220109078 | SEMI-TRANSPARENT MULTI-CELL PHOTOVOLTAIC DEVICE - A semi-transparent photovoltaic module comprises a basic 2D pattern representing an arrangement of an electrically conductive zone and electrically non-conductive zones such that any point in the electrically conductive zone is electrically connected to any other point of the zone and the electrically conductive zone is a regular or pseudo-regular structure formed by an elementary geometrical figure. The module additionally comprises one or more active isolation lines and a plurality of non-functional isolation lines that are mutually parallel. | 2022-04-07 |
20220109079 | PHOTODIODE STRUCTURED PHOTOSENSITIVE IMAGING SURFACES, METHODS AND APPARATUS - In an example, a photosensitive imaging surface is provided by an extended photodiode structure. | 2022-04-07 |
20220109080 | SEMICONDUCTOR LIGHT-RECEIVING ELEMENT AND METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT-RECEIVING ELEMENT - A semiconductor light-receiving element ( | 2022-04-07 |
20220109081 | TRANSFER SUBSTRATE - A transfer substrate for an element includes a plurality of projection portions projecting from a first surface of an elastic body, and a first groove portion and a second groove portion. Each of the first groove portion and the second groove portion is depressed internally from the first surface of the elastic body and extends in a first direction. A depth of the second groove portion is greater than a depth of the first groove portion. Further, the first groove portion and the second groove portion are provided between the plurality of projection portions. | 2022-04-07 |
20220109082 | OPTOELECTRONIC SEMICONDUCTOR COMPONENT - A method of producing an optoelectronic semiconductor component includes providing a carrier; arranging at least one optoelectronic semiconductor chip at a top side of the carrier, wherein the semiconductor chip includes semiconductor layers deposited on a substrate; forming a shaped body around the at least one optoelectronic semiconductor chip, wherein the shaped body surrounds all side areas of the at least one optoelectronic semiconductor chip and at least some of the layers deposited on the substrate are free of the shaped body such that these layers are not covered or completely exposed; and removing the carrier. | 2022-04-07 |
20220109083 | LIGHT EMITTING ELEMENT, MANUFACTURING METHOD FOR LIGHT EMITTING ELEMENT, AND DISPLAY DEVICE INCLUDING THE SAME - A light emitting element includes a first surface corresponding to an end of the light emitting element, a second surface corresponding to another end of the light emitting element, a first semiconductor layer adjacent to the first surface, the first semiconductor layer including a first type of semiconductor, a second semiconductor layer adjacent to the second surface, the second semiconductor layer including a second type of semiconductor different from the first type of semiconductor, and an active layer disposed between the first semiconductor layer and the second semiconductor layer. An area of the first surface is larger than an area of the second surface, and a distance between the first surface and the second surface is shorter than a length defined by the first surface. | 2022-04-07 |
20220109084 | ELECTRONIC DEVICE - An electronic device including a first substrate, a second substrate, a light-emitting element, and a piezoelectric element is provided. The light-emitting element is disposed between the first substrate and the second substrate. The piezoelectric element is disposed between the first substrate and the second substrate. The piezoelectric element includes a piezoelectric layer having an opening, and the light-emitting element is disposed in the opening. | 2022-04-07 |
20220109085 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device includes a first electrode and a second electrode spaced apart from each other on a substrate, a light-emitting element disposed between the first electrode and the second electrode on the substrate, a third electrode disposed on the first electrode and an end of the light-emitting element, a fourth electrode disposed on the second electrode and another end of the light-emitting element, a first insulation pattern disposed on the third electrode, and a second insulation pattern disposed on the first insulation pattern. An end of the first insulation pattern corresponding to the end of the light-emitting element protrudes toward the another end of the light-emitting element further than an end of the third electrode, and the second insulation pattern fills a space adjacent to the end of the third electrode and formed under the first insulation pattern. | 2022-04-07 |
20220109086 | SEMICONDUCTOR DEVICE FOR TRANSMITTING ELECTROMAGNETIC RADIATION AND METHOD FOR PRODUCTION THEREOF - A semiconductor device for emitting electromagnetic radiation, and to a method of producing the same, which can be used as a semiconductor-based, structured light source. The semiconductor device comprises a layer stack structure composed of an n-doped layer, an active layer and a p-doped layer, as well as a connection structure comprising conductor layers and at least one insulator layer, the conductor layers being arranged, parallel to and spaced apart from one another, along a first direction that is parallel to the active layer of the layer stack structure, and at least one insulator layer being arranged between at least two conductor layers, one or more conductor layers being electrically connected to the p-doped layer of the layer stack structure. | 2022-04-07 |
20220109087 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device includes a plurality of pixels, a first bank defining light emission regions of the plurality of pixels, a first electrode and a second electrode which are spaced apart from each other in each of the light emission regions, and a plurality of light emitting elements disposed between the first electrode and the second electrode. The first bank, the first electrode, and the second electrode include a same material. | 2022-04-07 |
20220109088 | LIGHT EMITTING MODULE - A light emitting module including a substrate, a first light emitting part disposed on the substrate, and a second light emitting part disposed on the substrate and spaced apart from the first light emitting part by an isolation trench between the first and the second light emitting parts, in which the first light emitting part and the second light emitting part include a first light emitting region and a second light emitting region, respectively, the second light emitting region being spaced apart from the first light emitting region, each of the first and second light emitting parts further includes a wavelength conversion layer covering the first and second light emitting regions, the wavelength conversion layers further include a barrier layer, and the isolation trench and the barrier layer vertically overlap each other on the base substrate. | 2022-04-07 |
20220109089 | LIGHT-EMITTING DIODE PACKAGE AND ELECTRONIC DEVICE INCLUDING THE SAME - A light-emitting diode (LED) package includes an LED chip on a substrate, an adhesive phosphor film on the LED chip, a cell lens on the adhesive phosphor film, and a lateral reflective layer covering respective lateral surfaces of the LED chip, the adhesive phosphor film, and the cell lens, a lateral surface of the lateral reflective layer being coplanar with a lateral surface of the substrate. | 2022-04-07 |
20220109090 | LIGHT-EMITTING APPARATUS AND MANUFACTURING METHOD THEREOF - A light-emitting apparatus including a circuit substrate and a light-emitting device is provided. The circuit substrate includes a first electrode and a second electrode. The light-emitting device is disposed on a first surface of the circuit substrate. The light-emitting device includes a first conductive terminal and a second conductive terminal. The first conductive terminal and the second conductive terminal are embedded between the first electrode and the second electrode. In a first direction, there is a first distance between an inner edge of the first electrode and an inner edge of the second electrode, there is a second distance between an outer edge of the first conductive terminal and an outer edge of the second conductive terminal, and the first distance is greater than or equal to the second distance. | 2022-04-07 |
20220109091 | INTEGRATED CIRCUIT DEVICE PACKAGE - An example apparatus includes: an integrated circuit including a first surface and terminals; a package including: a housing around the integrated circuit, the housing exposing the first surface; and an electrical interconnect including a second surface and an opening, the second surface electrically coupled to the terminals, the second surface mechanically coupled to the housing, the opening configured to expose the first surface. | 2022-04-07 |
20220109092 | DISPLAY DEVICE HAVING A PLURALITY OF MAIN PADS, A PLURALITY OF REDUNDANT PADS, AND A LIGHT-EMITTING DEVICE IN A DISPLAY AREA - An electronic device is provided. The electronic device includes a substrate, a plurality of signal lines and a plurality of units. The signal lines are disposed on the substrate. The units are disposed on the substrate. At least one of the units includes a first main pad, a first redundant pad, and an electronic component including a first electrode. In addition, one of the signal lines is electrically connected to the first electrode of the electronic component, the first main pad and the first redundant pad. | 2022-04-07 |
20220109093 | LIGHT-EMITTING DIODE MODULE AND ASSEMBLY WITH A LIGHT-EMITTING DIODE MODULE - In one embodiment, the light-emitting diode module comprises a carrier and a plurality of light-emitting diodes. Thereby, several types of light-emitting diodes are present. The light-emitting diodes can be controlled individually or in groups electrically independently of one another. The light-emitting diodes each comprise a first and a second electrical contact. The carrier comprises several electrically conductive main layers, between each of which there is an electrically insulating intermediate layer. The contacts of the light-emitting diodes are attached to a carrier upper side on one of the first main layers. Starting from the first contacts, electrical through-connections are each connected directly to a carrier underside with a last main layer of the main layers. Starting from the second contacts, electrical through-connection each terminate at a penultimate main layer of the main layers, wherein the penultimate main layer is located inside the carrier. | 2022-04-07 |
20220109094 | THERMOELECTRIC SYSTEMS AND METHODS OF APPLYING THE SAME - Provided herein is a thermoelectric system for generating electricity using ambient temperature oscillations (e.g., between day and night time). The thermoelectric system may comprise a first heat exchanger, a thermoelectric generator, one or more heat conducting units, a second heat exchanger, and a container configured to (i) contain the second heat exchanger and a thermal storage material and (ii) insulate the thermal storage material from an external to the container. | 2022-04-07 |
20220109095 | Ion Milling for Frequency Tuning of Superconducting Qubits - A method of modifying a resonant frequency of a quantum device includes generating an ion beam having a beam energy and exposing a surface of the quantum device to the ion beam for an exposure time. The ion beam is incident onto the quantum device at an oblique angle that is less than 90 degrees as measured from the surface of the quantum device. The quantum device includes a Josephson junction, the ion beam exposing the quantum device proximate to the Josephson junction to modify a property of the Josephson junction, the property being associated with the resonant frequency of the quantum device. | 2022-04-07 |
20220109096 | PIEZOELECTRIC FILM - Provided is a piezoelectric film capable of realizing an electroacoustic conversion film or the like in which the durability is high and a sufficient sound pressure with respect to an input operating voltage is obtained. The piezoelectric film is a piezoelectric film including a polymer-based piezoelectric composite material which contains piezoelectric particles in a matrix containing a polymer material, and electrode layers which are provided on both surfaces of the polymer-based piezoelectric composite material, in which in a case where a cross section of the piezoelectric film in a thickness direction is observed with a scanning electron microscope, the polymer-based piezoelectric composite material is divided into two equal regions in the thickness direction, and void volumes of the two regions are measured, a ratio of the void volume obtained by dividing the void volume of the region with a larger void volume by the void volume of the region with a smaller void volume is 1.2 or greater. | 2022-04-07 |
20220109097 | PIEZOELECTRIC ACTUATOR AND MICROFLUIDIC DEVICE - A piezoelectric actuator includes a deflectable membrane and a piezoelectric element attached to a part of the deflectable membrane for exerting a mechanical force on the deflectable membrane. The piezoelectric element is operable to perform an expansion and a contraction motion depending on an electric field applied to the piezoelectric element. The piezoelectric element leaves open a central region of the deflectable membrane and has a peripheral outline that does not coincide with an outline of the deflectable membrane. | 2022-04-07 |
20220109098 | PIEZOELECTRIC FILM - Provided is a piezoelectric film capable of realizing a piezoelectric speaker in which a high sound pressure is obtained, a sufficient sound pressure characteristic is obtained in a wide frequency band, and generation of a chattering sound particularly in a low sound can be suppressed. The piezoelectric film is a piezoelectric film including a polymer-based piezoelectric composite material which contains piezoelectric particles in a matrix containing a polymer material, and electrode layers which are laminated on both surfaces of the polymer-based piezoelectric composite material, in which a variation coefficient of a destructive force of a laminate having the polymer-based piezoelectric composite material and the electrode layers in a plane direction is 0.25 or less. | 2022-04-07 |
20220109099 | PILLAR-BASED MEMORY HARDMASK SMOOTHING AND STRESS REDUCTION - A method for fabricating a semiconductor device includes forming a conductive shell layer along a memory stack and a patterned hardmask disposed on the memory stack, and etching the patterned hardmask, the conductive shell layer and the memory stack to form a structure including a central core surrounded by a conductive outer shell disposed on a patterned memory stack. | 2022-04-07 |
20220109100 | IN-PLANE MAGNETIZED SPIN-ORBIT MAGNETIC DEVICE - An in-plane magnetized spin-orbit magnetic device is provided. The in-plane magnetized spin-orbit magnetic device includes a heavy metal layer, an upper electrode and a magnetic tunnel junction. The magnetic tunnel junction is disposed between the heavy metal layer and the upper electrode. The magnetic tunnel junction includes a free layer and a pinned layer. The free layer is disposed on the heavy metal layer, and the free layer has a first film plane area. The pinned layer is disposed on the free layer, and the pinned layer has a second film plane area. There is a preset angle between a long axis direction of a film plane shape of the free layer and a long axis direction of a film plane shape of the pinned layer, and the first film plane area is larger than the second film plane area. | 2022-04-07 |
20220109101 | INTEGRATED DEVICE AND NEUROMORPHIC DEVICE - According to an embodiment, there is provided an integrated device including: a substrate; and a laminated structure stacked on the substrate, in which the laminated structure includes a first element group and a second element group disposed at a position farther from the substrate than the first element group, each of the first element group and the second element group includes a plurality of domain wall movement elements, each of the plurality of domain wall movement elements includes a domain wall movement layer, a ferromagnetic layer, and a non-magnetic layer interposed between the domain wall movement layer and the ferromagnetic layer, and each of the domain wall movement elements belonging to the second element group has a lower critical current density required for moving a domain wall of the domain wall movement layer than each of the domain wall movement elements belonging to the first element group. | 2022-04-07 |
20220109102 | MAGNETIC DOMAIN WALL MOVEMENT ELEMENT AND MAGNETIC ARRAY - A magnetic domain wall movement element according to the present embodiment includes a magnetoresistance effect element that has a reference layer, a nonmagnetic layer, and a magnetic domain wall movement layer in order from a side closer to a substrate; and a first magnetization fixed layer and a second magnetization fixed layer which are each in contact with the magnetic domain wall movement layer and are separated from each other, wherein the magnetic domain wall movement layer includes a plurality of ferromagnetic layers and a plurality of insertion layers sandwiched between the plurality of ferromagnetic layers, wherein the ferromagnetic layer contains Co and Fe and has perpendicular magnetic anisotropy, and wherein, when writing is performed, a write current is allowed to flow between the first magnetization fixed layer and the second magnetization fixed layer along the magnetic domain wall movement layer. | 2022-04-07 |
20220109103 | MAGNETIC MEMORY DEVICE USING DOPED SEMICONDUCTOR LAYER - Magnetic memory devices are provided. The devices comprise a first ferromagnetic layer, a second ferromagnetic layer, and a tunnel barrier layer composed of a doped semiconductor (instead of an insulator or a dielectric) between the first and second ferromagnetic layers and forming at least one ferromagnetic-doped semiconductor interface. | 2022-04-07 |
20220109104 | FABRICATION METHOD OF MEMORY DEVICE - A method for fabricating memory device includes: providing a substrate having a bottom electrode layer therein, forming a buffer layer and a mask layer on the buffer layer over the substrate, in contact with the bottom electrode layer, performing an advanced oxidation process on a sidewall of the buffer layer to form a resistive layer, which surrounds the whole sidewall of the buffer layer and extends upward vertically from the substrate, and forming, over the substrate, a noble metal layer and a top electrode layer on the noble metal layer, fully covering the resistive layer and the mask layer. | 2022-04-07 |
20220109105 | APPLICATION OF NANOPARTICLES FOR PLASMON ENERGY EXTRACTION IN ORGANIC DEVICES - Techniques are provided for depositing a monolayer of nanoparticles over an OLED or comparable device. In combination with an enhancement layer disposed within a threshold distance of an emissive layer of the OLED, the nanoparticles may be used to provide a nanopatch antenna or otherwise improve the performance of the OLED. | 2022-04-07 |
20220109106 | Symmetric Charge Transfer Compounds for Organic Photovoltaics - The present disclosure is related to organic acceptor-donor-acceptor compounds as non-fullerene acceptors for use in organic photovoltaics. | 2022-04-07 |
20220109107 | LIGHT EMITTING DEVICE COMPOSITION AND LIGHT EMITTING DEVICE CONTAINING THE SAME - A composition which is useful for producing a light emitting device of which initial deterioration is suppressed and a light emitting device formed using the composition are described. The composition contains a host material and a guest material blended therein; the host material contains an aromatic compound having a condensed ring skeleton in which only three or more benzene rings are condensed, the guest material contains a compound having a heterocyclic group containing a carbon atom and at least one selected from a boron atom, a nitrogen atom, a phosphorus atom, an oxygen atom, a sulfur atom and a selenium atom in the ring, and the total amount of silicon atoms contained in the host material and in the guest material is over 0 ppm by mass and 28 ppm by mass or less with respect to the total amount of the host material and the guest material. | 2022-04-07 |
20220109108 | LIGHT EMITTING DEVICE AND POLYCYCLIC COMPOUND FOR THE SAME - A light emitting device includes a first electrode, a second electrode disposed on the first electrode, and at least one functional layer disposed between the first electrode and the second electrode. The at least one functional layer includes a polycyclic compound represented by Formula 1, thereby providing a light emitting device having high luminous efficiency and improved life characteristics. | 2022-04-07 |
20220109109 | ORGANIC ELECTROLUMINESCENT COMPOUND, A PLURALITY OF HOST MATERIALS AND ORGANIC ELECTROLUMINESCENT DEVICE COMPRISING THE SAME - The present disclosure relates to an organic electroluminescent compound represented by formula 1′ or 2′, a plurality of host materials comprising at least one first host compound and at least one second host compound, and an organic electroluminescent device comprising the same. By comprising the organic electroluminescent compound or the specific combination of compounds according to the present disclosure as a host material(s), it is possible to provide an organic electroluminescent device having improved driving voltage, luminous efficiency, power efficiency and/or lifetime properties. | 2022-04-07 |
20220109110 | ORGANIC ELECTROLUMINESCENT COMPOUND AND ORGANIC ELECTROLUMINESCENT DEVICE COMPRISING THE SAME - The present disclosure relates to an organic electroluminescent compound represented by formula 1, and an organic electroluminescent device comprising the same. By comprising the organic electroluminescent compound of the present disclosure, it is possible to provide an organic electroluminescent device having improved driving voltage, luminous efficiency, lifetime properties, and/or power efficiency. | 2022-04-07 |
20220109111 | HETEROCYCLIC COMPOUND AND ORGANIC LIGHT-EMITTING DIODE COMPRISING SAME - The present specification relates to a heterocyclic compound represented by Chemical Formula 1, and an organic light emitting device comprising the same. | 2022-04-07 |
20220109112 | ORGANIC LIGHT EMITTING DEVICE - The present disclosure relates to an organic light emitting device. In particular, the present disclosure relates to an organic light emitting diode and an organic light emitting device each of which includes at least one emitting material layer comprising an anthracene-based host substituted with at least one deuterium and a boron-based dopant, at least one electron blocking layer comprising an amine-based compound substituted with at least one spiro-aryl group, and optionally at least one hole blocking layer comprising at least one of an azine-based compound and a benzimidazole-based compound. The organic light emitting diode and the organic light emitting device has improved luminous efficiency and enhanced luminous lifespan. | 2022-04-07 |
20220109113 | Thermally Activated Delayed Fluorescent Material Based on 9,10-Dihydro-9,9-dimethylacridine Analogues for Prolonging Device Longevity - Thermally activated delayed fluorescent compounds and uses thereof are described. The thermally activated delayed fluorescent compounds are an analogues of 9,10-dihydro-9,9-dimethylacridine compounds. | 2022-04-07 |
20220109114 | ORGANIC LIGHT EMITTING DEVICE - An organic light emitting device comprising an anode, a cathode, and one or more organic material layers that are provided between the anode and the cathode and include a compound represented by Chemical Formula 1 and a compound represented by Chemical Formula 2. | 2022-04-07 |
20220109115 | POLYCYCLIC COMPOUND, AND AN ORGANIC ELECTROLUMINESCENCE DEVICE COMPRISING THE POLYCYCLIC COMPOUND - Specific polycyclic compounds of the general formula (I) and a process for their preparation, a material for an organic electroluminescence device comprising said compound, an organic electroluminescence device comprising said compound, an electronic equipment comprising said organic electroluminescence device, and the use of compounds according to general formula (I) in an organic electroluminescence device. | 2022-04-07 |
20220109116 | MATERIALS FOR ELECTRONIC DEVICES - The present application concerns compounds for use in electronic devices, processes for preparing the compounds, and electronic devices comprising the compounds. | 2022-04-07 |
20220109117 | PHOTOELECTRIC CONVERSION ELEMENT, IMAGING ELEMENT, OPTICAL SENSOR, AND MATERIAL FOR PHOTOELECTRIC CONVERSION ELEMENT - An object of the present invention is to provide a photoelectric conversion element that exhibits stable performance even though a compositional ratio of a photoelectric conversion film fluctuates in a case of manufacturing the photoelectric conversion film by vapor deposition. In addition, an imaging element, an optical sensor, and a material for a photoelectric conversion element are provided. The photoelectric conversion element of the present invention includes a conductive film, a photoelectric conversion film, and a transparent conductive film in this order, in which the photoelectric conversion film contains a compound represented by Formula (1) and an n-type semiconductor material. | 2022-04-07 |
20220109118 | LIGHT-EMITTING MATERIAL WITH A POLYCYCLIC LIGAND - Provided is a light-emitting material with polycyclic ligand. The light-emitting material is a metal complex with polycyclic ligand and may be used as a light-emitting material in an electroluminescent device. While maintaining a very narrow FWHM, these novel metal complexes can better adjust the light-emitting color of the device, reduce the driving voltage of the device or maintain the driving voltage at a low level, improve device efficiency, greatly increase the lifetime of the device, and provide better device performance. Further provided are an electroluminescent device and a compound composition. | 2022-04-07 |
20220109119 | Light-Emitting Device, Energy Donor Material, Light-Emitting Apparatus, Display Device, Lighting Device, and Electronic Device - A novel light-emitting device is provided. The light-emitting device includes a first electrode, a second electrode, and a light-emitting layer between the first electrode and the second electrode. The light-emitting layer includes an organometallic complex emitting phosphorescence at room temperature and a light-emitting material emitting fluorescence. The organometallic complex includes a ligand with at least one first substituent selected from a branched alkyl group having 3 to 12 carbon atoms, a substituted or unsubstituted cycloalkyl group having 3 to 10 carbon atoms in a ring, and a trialkylsilyl group having 3 to 12 carbon atoms. An absorption spectrum of the light-emitting material has the longest-wavelength edge at a first wavelength λabs (nm), and a phosphorescence spectrum of the organometallic complex has the shortest-wavelength edge at a second wavelength λp (nm). The first wavelength λabs (nm) is longer than the second wavelength λp (nm). | 2022-04-07 |
20220109120 | ORGANIC ELECTROLUMINESCENT MATERIALS AND DEVICES - A compound comprising a ligand L | 2022-04-07 |
20220109121 | ORGANIC ELECTROLUMINESCENCE DEVICE - An organic electroluminescence device of an embodiment includes a first electrode, a hole transport region on the first electrode, an emission layer on the hole transport region, an electron transport region on the emission layer, and a second electrode on the electron transport region, wherein the emission layer includes a first host compound represented by Formula 1, a second host compound represented by Formula 2, and a dopant compound comprising an organometallic complex including Pt, Au, or Cu as a central metal element, and may show improved life characteristics. | 2022-04-07 |
20220109122 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus includes a substrate, a pixel definition layer arranged over the substrate and including at least one opening area, and an organic emission layer arranged over the pixel definition layer and covering the opening area, wherein a center of the opening area and a center of the organic emission layer are arranged at different positions in a plan view. | 2022-04-07 |
20220109123 | DISPLAY DEVICE - A display device according to an embodiment may include a first substrate including an array of pixels, a second substrate coupled to the first substrate, and a sealing member between the first substrate and the second substrate. The second substrate may include a base substrate including a display area overlapping the array of pixels and a peripheral area around the display area; a first compensation structure in the peripheral area, on the base substrate, at least partially overlapping the sealing member, and including an organic material; a second compensation structure in the peripheral area, on the base substrate, spaced apart from the first compensation structure, at least partially overlapping the sealing member, and including the same material as that of the first compensation structure, and a first capping layer covering the first and second compensation structures and including an inorganic material. | 2022-04-07 |
20220109124 | Display Device - A display device includes an encapsulating structure disposed on an array substrate, a bottom cover accommodating therein the array substrate and the encapsulating structure, and at least one heat dissipation pattern disposed between the encapsulating structure and the bottom cover. The heat dissipation pattern may include a porous framework layer and a heat emission layer composed of particles coated on the framework layer. This heat dissipation pattern may allow heat transfer from the encapsulating structure to the bottom cover to be performed more quickly and efficiently. | 2022-04-07 |
20220109125 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device are provided. A projected pattern of an active layer on a substrate is adjusted to make a projection area of a gate electrode layer on the substrate remain within a projection area of the active layer on the substrate, thereby eliminating side channels of the active layer existing in current display panels and further preventing a hump phenomenon caused by a separation of a main channel from side channels in an I-V curve, which is caused by inconsistent film-forming thicknesses of a gate insulating layer in the side channel and the main channel areas. | 2022-04-07 |
20220109126 | SURFACE PROTECTION FILM AND METHOD FOR MANUFACTURING ORGANIC LIGHT-EMITTING ELECTRONIC DEVICE - The present application relates to a surface protective film and a method for manufacturing an organic light emitting electronic device. | 2022-04-07 |
20220109127 | DISPLAY APPARATUS - Provided is a display apparatus. The display apparatus includes a display module configured to define a display surface on a plane. The display module includes a display panel having a plurality of display elements configured to display an image on the display surface and a pattern layer having a plurality of diffraction patterns arranged at an interval on the display panel. The diffraction patters are arranged to diffract at least a portion of incident light. At least a portion of the diffraction patterns has a width different from that of each of remaining diffraction patterns. | 2022-04-07 |
20220109128 | WAVELENGTH SELECTIVE ABSORPTION FILTER AND ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE - There are provided a wavelength selective absorption filter including a resin, and four types of dyes A to D each having a main absorption wavelength range in different specific wavelength regions, in which an absorbance Ab (λ) of the wavelength selective absorption filter at a wavelength λ nm satisfies specific Relational Expressions (I) to (VI), and an organic electroluminescent display device. | 2022-04-07 |
20220109129 | ORGANIC ELECTROLUMINESCENCE ELEMENT INCLUDING CARRIER INJECTION AMOUNT CONTROL ELECTRODE - An organic electroluminescence element in an embodiment according to the present invention includes a first electrode, a third electrode including a region overlapping the first electrode, a first insulating layer between the first electrode and the third electrode, a second insulating layer between the first insulating layer and the third electrode, an electron transfer layer between the first insulating layer and the third electrode, a light emitting layer, containing an organic electroluminescence material, between the electron transfer layer and the third electrode, and a second electrode located between the first insulating layer and the second insulating layer and electrically connected with the electron transfer layer. The organic electroluminescence element includes an overlap region where the third electrode, the light emitting layer, the electron transfer layer, the first insulating layer and the first electrode overlap each other in an opening of the second insulating layer. | 2022-04-07 |
20220109130 | NON-FLEXIBLE SUBSTRATE HAVING BASE LAYER, FLEXIBLE DISPLAY DEVICE AND METHOD FOR PRODUCING SAME - In a non-flexible substrate ( | 2022-04-07 |
20220109131 | BATTERY MODULE AND METHODS OF ASSEMBLY - A battery module and a method of assembling a battery module are provided. The method includes selectively applying a light-cure adhesive to recesses in a first side of a carrier layer and inserting battery cells into respective recesses. The method further includes exposing the first side of the carrier layer to light to at least partially cure the light-cure adhesive with the carrier layer in a first orientation, moving the carrier layer into a second orientation, and exposing a second opposite side of the carrier layer to light to fully cure the light-cure adhesive. The recesses may include a sidewall having crush points spaced apart along the sidewall and a bottom portion having an opening between a pair of crush points, where adhesive is not disposed between the pair of crush points. | 2022-04-07 |
20220109132 | BATTERY MODULE SUPPORT BEAM - A battery support beam and battery module including the battery support beam are provided. The battery support beam includes a first end, a second end opposite the first end, and a battery support section between the first end and the second end. The battery support section includes a plurality of cylindrical sleeves arranged in a predetermined pattern, each having a cylindrical sidewall having an open-ended top and an open-ended bottom. Each of the cylindrical sidewalls is configured to be arranged around a cylindrical middle section of one of a plurality of cylindrical battery cells. The battery module includes a plurality of cylindrical battery cells including a plurality of groups of battery cells arranged in the predetermined pattern. The battery module further includes a battery support section for each of the plurality of groups of battery cells. | 2022-04-07 |
20220109134 | BATTERY TERMINAL - A battery terminal connector assembly for attaching to a terminal post of a battery includes a biasing portion and a post engagement portion. The biasing portion has a first terminal post receiving opening. A biasing wall extends about a circumference of the first terminal post receiving opening. The post engagement portion has a second terminal post receiving opening for receiving the battery terminal post therein. Engagement walls extend about a circumference of the second terminal post receiving opening. The biasing portion is movable relative to the post engagement portion between a first insertion position and a second termination position. As the biasing portion is moved from the first insertion position to the second termination position, the biasing wall engages the engagement walls and moves the engagement walls into mechanical and electrical engagement with the battery terminal post positioned in the second terminal receiving opening of the post engagement portion. | 2022-04-07 |
20220109135 | WEDGE BATTERY TERMINAL - A battery terminal connector assembly includes a first post engagement portion and a second post engagement portion. The first post engagement portion has a first opening for receiving the battery terminal post therein. The second post engagement portion has a second opening for receiving the battery terminal post therein. The first post engagement portion is movable relative to the second post engagement portion and the first post engagement portion and the second post engagement portion are movable relative to the battery terminal post as the first post engagement portion and the second post engagement portion are moved between a first insertion position and a second termination position. | 2022-04-07 |
20220109136 | ELECTRODE ASSEMBLY AND METHOD OF MAKING THE SAME - Disclosed herein is a method comprising disposing a slurry comprising an organic binder, an optional conductive filler, an optional solvent and an active material on a current collector; wherein the active material comprises a labile metal ion; removing the optional solvent to form a dry electrode; firing the dry electrode at a temperature of at least 200° C.; and carbonizing the organic binder to form a carbonized layer. | 2022-04-07 |
20220109137 | METHOD FOR PRODUCING AN ELECTRODE SHEET - A method for producing an electrode sheet includes a first feeding process, a roll press process, and a second feeding process, which are performed in this order. At least one of a first tension per unit area obtained by dividing a tension applied to the electrode sheet in a longitudinal direction in the first feeding process by a cross-sectional area of the electrode sheet being fed in the first feeding process and a second tension per unit area obtained by dividing a tension applied to the electrode sheet in a longitudinal direction in the second feeding process by a cross-sectional area of the electrode sheet being fed in the second feeding process is 5.0 MPa or less. | 2022-04-07 |
20220109138 | MANUFACTURING SYSTEM OF COMPRESSED STRIP-SHAPED ELECTRODE PLATE - This manufacturing method is a method of manufacturing a compressed strip-shaped electrode plate. The method includes: a preliminary compression step of forming a pre-compressed strip-shaped electrode plate by roll-pressing an uncompressed strip-shaped electrode plate in which an uncompressed active material layer that is not yet compressed is formed on a current collector foil; an attraction and removal step of attracting and removing fine particles of active material particles from near a surface of a pre-compressed active material layer by an attracting magnet that is disposed so as to be separated from the pre-compressed active material layer in a thickness direction; and a main compression step of obtaining the compressed strip-shaped electrode plate by roll-pressing a particle-removed strip-shaped electrode plate from which the fine particles have been removed. | 2022-04-07 |