15th week of 2015 patent applcation highlights part 12 |
Patent application number | Title | Published |
20150097197 | FINFET WITH SIGMA CAVITY WITH MULTIPLE EPITAXIAL MATERIAL REGIONS - Embodiments of the present invention provide an improved finFET and methods of fabrication. A sigma cavity is used with an n-type finFET to allow multiple epitaxial layers to be disposed adjacent to a finFET gate. In some embodiments, stacking faults may be formed in the epitaxial layers using a stress memorization technique. | 2015-04-09 |
20150097198 | Surface Light Source - In at least one embodiment, a surface light source includes one or a more optoelectronic semiconductor chips having a radiation main side for generating a primary radiation. A scattering body is disposed downstream of the radiation main side along a main emission direction of the semiconductor chips. The scatting body is designed for scattering the primary radiation. A main emission direction of the scattering body is oriented obliquely with respect to the main emission direction of the semiconductor chip. | 2015-04-09 |
20150097199 | LED ASSEMBLY - This disclosure discloses an LED assembly. The LED assembly comprises a transparent substrate; a first phosphor layer; a transparent mount, having a plurality of trenches substantially in parallel to each other, wherein the first phosphor layer is positioned between the transparent substrate and the transparent mount; an LED chip, mounted on an area of the transparent mount, wherein the area is located substantially between the trenches; and a second phosphor layer inside the trenches. | 2015-04-09 |
20150097200 | SOLID STATE LIGHTING APPARATUS WITH HIGH SCOTOPIC / PHOTOPIC (S/P) RATIO - Solid state light emitting apparatuses include blue LEDs (including but not limited to a combination of short wavelength and long wavelength blue LEDs) to stimulate green lumiphors, with supplemental emissions by either red lumiphors and/or red solid state light emitters, to provide aggregate emissions with high S/P ratio (e.g., at least 1.95) and favorably high color rendering values (e.g., 85 or greater), preferably in combination with high brightness and high luminous efficacy. In certain embodiments, a solid state light emitting apparatus may be devoid of a LED having a peak wavelength of from 470-599 nm and/or devoid of lumiphors peak wavelengths in the yellow range. Multiple LEDs may be arranged in an emitter package. | 2015-04-09 |
20150097201 | Light Emitting Device Comprising Chip-on-board Package substrate and method for manufacturing - [Problem] To provide a chip-on-board light emitting device and a method for manufacturing the same such that even though the light emitting device is a chip-on-board light emitting device, it is possible to improve color rendering thereof without excessively reducing the amount of light emission and without installing special circuit patterns or performing current control. [Solution] A chip-on-board light emitting device in which a plurality of LED elements are mounted directly on a package substrate includes a circuit pattern formed on the package substrate, the circuit pattern including a plurality of mounting sections on which the plurality of LED elements are mounted and an anode electrode and cathode electrode pair. The LED elements mounted on the circuit pattern include a plurality of types of LED elements having different emission wavelengths and temperature characteristics, so that by utilizing the temperature characteristics of the plurality of types of LED elements, the device as a whole has a greater average color rendering index (Ra) at an operating temperature than at a ordinary temperature. | 2015-04-09 |
20150097202 | LIGHT-EMITTING DIODE - A light-emitting diode (LED) is provided. An LED die includes a first semiconductor layer, a light-emitting layer, a second semiconductor layer, a first electrode and a second electrode. At least a part of the first semiconductor is exposed from the light emitting layer and the second semiconductor layer. The first electrode and the second electrode is disposed on top of the exposed first semiconductor layer and the second semiconductor layer respectively. At least two metal pads are disposed on top of the first electrode and the second electrode of the LED die respectively. Each of the metal pads has a side surface. A fluorescent layer is disposed on a surface of the LED die. The fluorescent layer directly contacts with the side surfaces of the metal pads and fills a gap between the metal pads. | 2015-04-09 |
20150097203 | DIE EMITTING WHITE LIGHT - Various methods and apparatuses are disclosed. A method may include disposing at least one die on a location on a carrier substrate, forming at least one stud bump on each of at least one die, forming a phosphor layer on the at least one stud bump and the at least one die, removing a top portion of the phosphor layer to expose the at least one stud bump, and removing a side portion of the phosphor layer located between two adjacent dies. An apparatus may include a die comprising top, bottom, and side surfaces. A phosphor layer may be disposed on the top, bottom, and side surfaces of the die. The phosphor layer may have substantially equal thicknesses on the top and side surfaces of the die as well as one or more stud bumps disposed on the top surface of the die. | 2015-04-09 |
20150097204 | METHOD OF PRODUCING CRYSTALLINE SUBSTRATE HAVING CONCAVE-CONVEX STRUCTURE - A method of producing the crystalline substrate having a concave-convex structure includes: (A) forming a transfer film by forming a concave-convex film on a support film on the surface having a concave-convex pattern thereon so that thickness of the residual film of the concave-convex film is 0.01 to 1 μm, the concave-convex pattern of the support film having concave parts with a width of 0.05 to 100 μm, a depth of 0.05 to 10 μm, and a ratio of the depth of the concave part to the width of the concave part of up to 1.5, (B) disposing the transfer film on the crystalline substrate, and transferring the concave-convex film onto the crystalline substrate to produce a crystalline substrate having the concave-convex film thereon, (C) etching the crystalline substrate having the concave-convex film thereon to form a concave-convex structure on the surface of a crystalline substrate. | 2015-04-09 |
20150097205 | LIGHT EMITTING DIODE HAVING MAGNETIC STRUCTURE AND METHOD OF FABRICATING THE SAME - A light emitting diode including a magnetic structure and a method of fabricating the same are disclosed. The magnetic structure composed of passivation layers and a magnetic layer is disposed inside a luminous structure composed of an active layer and a semiconductor layer. In the light emitting diode, the magnetic structure including the magnetic layer is disposed on a side surface of the active layer to improve recombination rate of charge carriers for light emission by increasing influence of a magnetic field applied to the active layer. In addition, the light emitting diode according to the present invention allows change in position of the magnetic structure including the magnetic layer depending upon an etched shape of the luminous structure, thereby realizing various magnetic field distributions. | 2015-04-09 |
20150097206 | METHOD OF MANUFACTURING PACKAGE COMPONENT FOR LIGHT EMITTING DIODE AND PACKAGE STRUCTURE THEREOF - A method of manufacturing package component for light emitting diode (LED) is disclosed. At least one LED is disposed on a substrate inside a photocuring resin, wherein the LED is covered completely by the substrate and the photocuring resin. Power is provided to the LED to make the LED emit plural light beams such that a portion of the photocuring resin is cured by the light beams to obtain a male mold. A separation process is performed to separate the male mold and the other portion of the photocuring resin, the LED and the substrate. A rollover process is performed to manufacture the female mold by the male mold, wherein the female mold has at least one accommodation space with a shape identical to that of the male mold. A forming process is performed to form a package component with a shape identical to that of the male mold. | 2015-04-09 |
20150097207 | SEMICONDUCTOR CHIP STRUCTURE - A semiconductor chip structure including a semiconductor chip having a pair of electrodes is disclosed. The electrodes have different conductivity types for electrical connection, respectively. A thermoelectric cooling material layer is disposed within each of the pair of electrodes, respectively. | 2015-04-09 |
20150097208 | COMPOSITE RESIN AND ELECTRONIC DEVICE - According to one embodiment, a composite resin includes a resin component; and a plurality of first powder bodies dispersed in the resin component. Each of the first powder bodies has a nonlinear current-voltage characteristic having a decreasing resistance as a voltage increases. The first powder body is a polycrystalline powder body including a plurality of primary particles bound via a grain boundary. A component different from a major component of the primary particles exists in a higher concentration in the grain boundary than in an interior of the primary particles. | 2015-04-09 |
20150097209 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device including a Si (110) substrate, a buffer layer, a first type doped semiconductor layer, a light-emitting layer and a second type doped semiconductor layer is provided. The Si (110) substrate has a plurality of trenches. Each trench at least extends along a first direction, and the first direction is parallel to a <1-10> crystal direction of the Si (110) substrate. The buffer layer is located on the Si (110) substrate and exposes the trenches. The first type doped semiconductor layer is located on the buffer layer and covers the trenches. The light-emitting layer is located on the first type doped semiconductor layer. The second type doped semiconductor layer is located on the light-emitting layer. A fabrication method of a semiconductor device is also provided. | 2015-04-09 |
20150097210 | COPLANAR INTEGRATION OF A DIRECT-BANDGAP CHIP INTO A SILICON PHOTONIC DEVICE - A method for fabricating a composite device comprises providing a platform, providing a chip, and bonding the chip to the platform. The platform has a base layer and a device layer above the base layer. An opening in the device layer exposes a portion of the base layer. The chip is bonded to the portion of the base layer exposed by the opening in the device layer. A portion of the chip extends above the platform and is removed. | 2015-04-09 |
20150097211 | STRUCTURES FOR BONDING A DIRECT-BANDGAP CHIP TO A SILICON PHOTONIC DEVICE - A composite photonic device comprises a platform, a chip, and a contact layer. The platform comprises silicon. The chip is made of a III-V material. The contact layer has indentations to help control a flow of solder during bonding of the platform with the chip. In some embodiments, pedestals are placed under an optical path to prevent solder from flowing between the chip and the platform at the optical path. | 2015-04-09 |
20150097212 | SEMICONDUCTOR DEVICE WITH RELAXATION REDUCTION LINER AND ASSOCIATED METHODS - A method for forming a semiconductor device includes forming a mask layer on a stressed semiconductor layer of a stressed, semiconductor-on-insulator wafer. An isolation trench bounding the stressed semiconductor layer is formed. The isolation trench extends through the mask layer and into the SOI wafer past an oxide layer thereof. A dielectric body is formed in the isolation trench. A relaxation reduction liner is formed on the dielectric body and on an adjacent sidewall of the stressed semiconductor layer. The mask layer on the stressed semiconductor layer is removed. | 2015-04-09 |
20150097213 | IMAGE SENSOR AND PIXELS INCLUDING VERTICAL OVERFLOW DRAIN - Embodiments of an apparatus comprising a pixel array including a plurality of pixels formed in a substrate having a front surface and a back surface, each pixel including a photosensitive region formed at or near the front surface and extending into the substrate a selected depth from the front surface. A filter array is coupled to the pixel array, the filter array including a plurality of individual filters each optically coupled to a corresponding photosensitive region, and a vertical overflow drain (VOD) is positioned in the substrate between the back surface and the photosensitive region of at least one pixel in the array. | 2015-04-09 |
20150097214 | STRUCTURES, APPARATUSES AND METHODS FOR FABRICATING SENSORS IN MULTI-LAYER STRUCTURES - Structures, apparatuses, and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first substrate, a first device layer, a second device layer and a third device layer. The first device layer may be on the first substrate and include a switch. The second device layer may be on the first device layer and include a sensing device. The third device layer may include one or more inter-level connection structures configured to electrically connect the switch to the sensing device. The switch may be configured to be electrically turned on in response to a selection signal. The sensing device may be configured to generate an output signal in response to the switch being turned on. | 2015-04-09 |
20150097215 | MECHANISMS FOR FORMING MICRO-ELECTRO MECHANICAL SYSTEM DEVICE - Embodiments of mechanisms for forming a micro-electro mechanical system (MEMS) device are provided. The MEMS device includes a CMOS substrate and a MEMS substrate bonded with the CMOS substrate. The CMOS substrate includes a semiconductor substrate, a first dielectric layer formed over the semiconductor substrate, and a plurality of conductive pads formed in the first dielectric layer. The MEMS substrate includes a semiconductor layer having a movable element and a second dielectric layer formed between the semiconductor layer and the CMOS substrate. The MEMS substrate also includes a closed chamber surrounding the movable element. The MEMS substrate further includes a blocking layer formed between the closed chamber and the first dielectric layer of the CMOS substrate. The blocking layer is configured to block gas, coming from the first dielectric layer, from entering the closed chamber. | 2015-04-09 |
20150097216 | SEMICONDUCTOR DEVICE WITH NON-LINEAR SURFACE - A semiconductor device includes a channel having a first linear surface and a first non-linear surface. The first non-linear surface defines a first external angle of about 80 degrees to about 100 degrees and a second external angle of about 80 degrees to about 100 degrees. The semiconductor device includes a dielectric region covering the channel between a source region and a drain region. The semiconductor device includes a gate electrode covering the dielectric region between the source region and the drain region. | 2015-04-09 |
20150097217 | SEMICONDUCTOR ATTENUATED FINS - A semiconductor device includes a semiconductor substrate and attenuated semiconductor fins (e.g. FinFET fins) that include an outer portion that is a composite of a first material and a second material, an inner portion that is the second material, and an attenuation portion that is an attenuated composite of the first and second materials. The attenuation portion may be formed by diffusing the first material into a plurality of fins made of the second material. The attenuated composite attenuates from a first composite to a second composite, the first composite comprising a majority of the first material, the second composite comprising a majority of the second material. The outer portion may be located on the fin perimeter and the inner portion may be located central to the fin. The first material may be Germanium, the second material may be Silicon, and the attenuated composite may be attenuated Silicon Germanium. | 2015-04-09 |
20150097218 | SEMICONDUCTOR DEVICE WITH NON-LINEAR SURFACE - A semiconductor device includes a first channel having a first linear surface and a first non-linear surface. The semiconductor device includes a first dielectric region surrounding the first channel. The semiconductor device includes a second channel having a third linear surface and a third non-linear surface. The semiconductor device includes a second dielectric region surrounding the second channel. The semiconductor device includes a gate electrode surrounding the first dielectric region and the second dielectric region. | 2015-04-09 |
20150097219 | IMAGE CAPTURING DEVICE - An image capturing device includes an intermediate region located between a pixel circuit region and a peripheral circuit region and forming a boundary with the pixel circuit region and the peripheral circuit region. The pixel circuit region, the peripheral circuit region, and the intermediate region are provided with a semiconductor layer, a first wiring layer on the semiconductor layer, and a second wiring layer located away from the semiconductor layer relative to the first wiring layer. Pixel circuits and a peripheral circuit are connected via one of at least the first wiring layer and the second wiring layer in the intermediate region. The area occupancy of the one wiring layer in the intermediate region relative to a total area thereof is between 0.5 times and 1.5 times the area occupancy of the one wiring layer in the pixel circuit region relative to a total area thereof. | 2015-04-09 |
20150097220 | FIN-SHAPED FIELD EFFECT TRANSISTOR AND CAPACITOR STRUCTURES - A fin-shaped field-effect transistor device is provided. The fin-shaped field effect transistor device may include a semiconductor substrate having a top and a bottom surface. The fin-shaped field effect transistor device may also include a fin structure disposed on the top surface of the semiconductor substrate, where the fin structure includes a first sidewall and a second sidewall opposite of the first sidewall. The first sidewall is adjacent to a first region of the top surface of the semiconductor substrate and the second sidewall is adjacent to a second region of the top surface of the semiconductor substrate. The fin-shaped field effect transistor device may also include an insulation layer disposed above the fin structure and the first and second regions of the top surface. The fin-shaped field effect transistor device may also include a conductor structure disposed above and adjacent to the insulation layer. | 2015-04-09 |
20150097221 | POWER FET WITH A RESONANT TRANSISTOR GATE - A semiconductor FET provides a resonant gate and source and drain electrodes, wherein the resonant gate is electromagnetically resonant at one or more predetermined frequencies. | 2015-04-09 |
20150097222 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. A channel layer is formed on a substrate. The channel layer is extended in a first direction substantially perpendicular to an upper surface of the substrate. A ground selection line is formed on a first region of the channel layer. A plurality of word lines is formed on a second region of the channel layer. A plurality of string selection lines is formed on a third region of the channel layer. The second region of the channel layer includes a first conductivity type dopant. The first, second and third regions of the channel layer are disposed along the first direction. | 2015-04-09 |
20150097223 | METHOD AND APPARATUS FOR CONTROLLING GATE DIMENSIONS OF MEMORY DEVICES - A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein the memory gate structure comprises a memory gate electrode and a memory gate spacer, and wherein the memory gate spacer is over the memory gate electrode, a charge storage layer formed between the control gate structure and the memory gate structure, wherein the charge storage layer is an L-shaped structure, a first spacer along a sidewall of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure. | 2015-04-09 |
20150097224 | BURIED TRENCH ISOLATION IN INTEGRATED CIRCUITS - A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is positioned between first and second devices and comprises a first filled portion and a second filled portion. The first filled portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. | 2015-04-09 |
20150097225 | TRENCH GATE TRENCH FIELD PLATE SEMI-VERTICAL SEMI-LATERAL MOSFET - A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical drain contact region, separated from the vertical drift region by at least one instance of the deep trench structures. Dopants are implanted into the vertical drain contact regions and the semiconductor device is annealed so that the implanted dopants diffuse proximate to a bottom of the deep trench structures. The vertical drain contact regions make electrical contact to the proximate vertical drift region at the bottom of the intervening deep trench structure. At least one gate, body region and source region are formed above the drift region at, or proximate to, a top surface of a substrate of the semiconductor device. The deep trench structures are spaced so as to form RESURF regions for the drift region. | 2015-04-09 |
20150097226 | FIELD EFFECT DEVICE WITH ENHANCED GATE DIELECTRIC STRUCTURE - A vertically oriented field effect device has a body and an enhance gate structure. The body includes a JFET (junction field effect transistor) region disposed between junction implants that extend into the body from a top surface of the body. The gate structure includes a supplemental gate dielectric, a primary gate dielectric, and a gate contact. The supplemental gate dielectric is formed over the top surface of the body above the JFET region, such that the supplemental dielectric is separated from the junction implants by a gap. The primary gate dielectric is formed over the supplemental gate dielectric, above the gap over the top surface of the body, and over at least a portion of the junction implants. The gate contact is formed over the primary gate dielectric. | 2015-04-09 |
20150097227 | SEMICONDUCTOR DEVICE WITH REDUCED GATE LENGTH - A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate region surrounding the channel region. The gate region includes a gate electrode. A gate electrode length of the gate electrode is less than about 10 nm. A method of forming a semiconductor device is provided. | 2015-04-09 |
20150097228 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method for fabricating a semiconductor device, which includes the following steps. First, a substrate having at least one transistor is provided. A first insulation layer is formed to cover the transistor. The first insulation layer is patterned to form at least one opening, wherein a part of the transistor is exposed by the opening. At last, an epitaxy is formed in the opening to cover the part of the transistor. | 2015-04-09 |
20150097229 | 3-D NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A three-dimensional (3-D) nonvolatile memory device includes channel layers protruding perpendicular to a surface of a substrate, interlayer insulating layers and conductive layer patterns alternately formed to surround each of the channel layers, a slit formed between the channel layers, the slit penetrating the interlayer insulating layers and the conductive layer patterns, and an etch-stop layer formed on the surface of the substrate at the bottom of the slit. | 2015-04-09 |
20150097230 | TRENCH GATE TRENCH FIELD PLATE VERTICAL MOSFET - A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions. | 2015-04-09 |
20150097231 | VERTICAL TRENCH MOSFET DEVICE IN INTEGRATED POWER TECHNOLOGIES - A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define at least one vertical drift region bounded on at least two opposite sides by the deep trench structures. The deep trench structures include dielectric liners. The deep trench structures are spaced so as to form RESURF regions for the drift region. Vertical gates are formed in vertically oriented gate trenches in the dielectric liners of the deep trench structures, abutting the vertical drift regions. A body implant mask for implanting dopants for the transistor body is also used as an etch mask for forming the vertically oriented gate trenches in the dielectric liners. | 2015-04-09 |
20150097232 | DUAL GATE OXIDE TRENCH MOSFET WITH CHANNEL STOP TRENCH - A semiconductor device has a plurality of gate electrodes over a gate insulator layer formed in active trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the semiconductor substrate and electrically connected to the gate electrodes. The first gate runner abuts and surrounds the active region. A second gate runner is connected to the first gate runner to make contact to a gate metal. A dielectric filled trench surrounds the first and second gate runners and the active region and a highly doped channel stop region is formed under the dielectric filled trench. | 2015-04-09 |
20150097233 | Semiconductor Device and Method of Manufacturing the Same - A semiconductor device includes a vertical IGFET in a first area of a semiconductor body, the vertical IGFET having a drift zone between a body zone and a drain electrode, the drift zone having a vertical dopant profile of a first conductivity type being a superposition of a first dopant profile declining with increasing distance from the drain electrode and dominating the vertical dopant profile in a first zone next to the drain electrode and a second dopant profile being a broadened peak dopant profile and dominating the vertical dopant profile in a second zone next to the body zone. | 2015-04-09 |
20150097234 | HALF-BRIDGE CIRCUIT INCLUDING A LOW-SIDE TRANSISTOR AND A LEVEL SHIFTER TRANSISTOR INTEGRATED IN A COMMON SEMICONDUCTOR BODY - A half-bridge circuit includes a low-side transistor and a high-side transistor each having a load path and a control terminal, and a high-side drive circuit having a level shifter with a level shifter transistor. The low-side transistor and the level shifter transistor are integrated in a common semiconductor body. | 2015-04-09 |
20150097235 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. The device includes a plurality of gates formed on a surface of a substrate, a plurality of sidewalls formed on side surfaces of the gates, a Sigma-shaped recess formed in the substrate between adjacent gates, a SiGe seed layer formed on an inner surface of the Sigma-shaped recess, boron-doped bulk SiGe formed on a surface of the SiGe seed layer, with the boron-doped bulk SiGe filling the Sigma-shaped recess, and a boron-doped SiGe regeneration layer formed in a first recess beneath the surface of the substrate. The first recess is formed by etching a portion of the SiGe seed layer and the boron-doped bulk SiGe in the Sigma-shaped recess, and the boron-doped SiGe regeneration layer has a higher concentration of boron than the SiGe seed layer or the boron-doped bulk SiGe. | 2015-04-09 |
20150097236 | Semiconductor Device And Method Of Fabricating Same - A lateral drain metal oxide semiconductor (LDMOS) device includes a well region having a second conductive type in a substrate, a body region having a first conductive type in the well region, a drift region having the second conductive type in the well region and spaced apart from the body region, a source region having the second conductive type in the body region, a drain region having the second conductive type in the drift region, a gate structure on the well region between the source region and the drain region, a shallow trench isolation (STI) structure in the drift region between the drain region and the source region, and a buried layer having the first conductive type in the well region under the drift region, a center of the buried layer being aligned with a center of the STI structure. | 2015-04-09 |
20150097237 | POWER SEMICONDUCTOR DEVICE - A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions. | 2015-04-09 |
20150097238 | Mergeable Semiconductor Device with Improved Reliability - A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite body region disposed in the semiconductor substrate and having a second conductivity type. The composite body region includes a first well region that extends laterally across the source and drain regions and a second well region disposed in the first well region. The drain region is disposed in the second well region such that charge carriers flow from the first well region into the second well region to reach the drain region. The second well region includes dopant of the first conductivity type to have a lower net dopant concentration level than the first well region. A pocket may be disposed in a drain extension region and configured to establish a depletion region along an edge of a gate structure. | 2015-04-09 |
20150097239 | Passivation Structure of Fin Field Effect Transistor - A FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower fin portion comprising a first semiconductor material having a first lattice constant; an upper fin portion comprising a second semiconductor material having a second lattice constant greater than the first lattice constant; a middle fin portion comprising a third semiconductor material having a third lattice constant between the first lattice constant and the second lattice constant; and a passivation structure surrounding the fin structure comprising a lower passivation portion surrounding the lower fin portion comprising a first oxynitride of the first semiconductor material; an upper passivation portion surrounding the upper fin portion comprising a second oxynitride of the second semiconductor material; and a middle passivation portion surrounding the middle fin portion comprising a third oxynitride of the third semiconductor material. | 2015-04-09 |
20150097240 | GROUNDING OF SILICON-ON-INSULATOR STRUCTURE - Devices and methods for forming a device are presented. The method includes providing a substrate having at least a first region and a second region prepared with isolation regions. The first region is referred to as a chip guarding area and the second region defines a chip region of which at least one transistor is to be formed. The substrate includes a top surface layer, a support substrate and an insulator layer in between them. A transistor is formed in the second region and a substrate contact structure is formed in the first region. The substrate contact structure passes through at least the top surface layer, insulator layer and isolation region and contacts a doped region in the support substrate. The substrate contact structure is connected to at least one conductive line with a desired potential to prevent charging of the support substrate at system level. | 2015-04-09 |
20150097241 | METHOD FOR RELAXING THE TRANSVERSE MECHANICAL STRESSES WITHIN THE ACTIVE REGION OF A MOS TRANSISTOR, AND CORRESPONDING INTEGRATED CIRCUIT - The transverse mechanical stress within the active region of a MOS transistor is relaxed by forming an insulating incursion, such as an insulated trench, within the active region of the MOS transistor. The insulated incursion is provided at least in a channel region of the MOS transistor so as to separate the channel region into two parts. The insulated incursion is configured to extend in a direction of a length of the MOS transistor. The insulated incursion may further extend into one or more of a source region or drain region located adjacent the channel region of the MOS transistor. | 2015-04-09 |
20150097242 | Channel Epitaxial Regrowth Flow (CRF) - A Fin-FET fabrication approach and structure are provided using channel epitaxial regrowth flow (CRF). The method includes forming a Fin-FET structure including a Si line on a substrate, shallow trench isolation (STI) oxide on both sides of the Si line on the substrate, and a poly wall on top of and across the STI oxide and the Si line, wherein the Si line is higher than the STI oxide from the substrate. The method further includes thinning the STI oxide and the Si line while maintaining about the same height ratio of the Si line and the STI oxide, and forming a spacer wall adjacent to both sides of the poly wall and further adjacent to Si and STI oxide side walls under the poly wall uncovered due thinning the STI oxide and the Si line. | 2015-04-09 |
20150097243 | SEMICONDUCTOR DEVICE INCLUDING SOI BUTTED JUNCTION TO REDUCE SHORT-CHANNEL PENALTY - A semiconductor device comprises first and second gate stacks formed on a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a dielectric layer interposed between a bulk substrate layer and an active semiconductor layer. A first extension implant portion is disposed adjacent to the first gate stack and a second extension implant portion is disposed adjacent to the second gate stack. A halo implant extends continuously about the trench. A butting implant extends between the trench and the dielectric layer. An epitaxial layer is formed at the exposed region such that the butting implant is interposed between the epitaxial layer and the dielectric layer. | 2015-04-09 |
20150097244 | SEMICONDUCTOR DEVICE WITH A BURIED OXIDE STACK FOR DUAL CHANNEL REGIONS AND ASSOCIATED METHODS - A method for making a semiconductor device includes forming a buried oxide stack on a semiconductor wafer. The buried oxide stack includes a first oxide layer, a nitride layer on the first oxide layer, and a second oxide layer on the nitride layer. A semiconductor layer is formed on the second oxide layer. First and second channel regions are formed in the semiconductor layer. | 2015-04-09 |
20150097245 | SELF-ALIGNED TRENCH ISOLATION IN INTEGRATED CIRCUITS - A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. The self-aligned placement of the buried trench isolation allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC. | 2015-04-09 |
20150097246 | INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME HAVING A REPLACEMENT GATE STRUCTURE - An integrated circuit includes a first FET structure and a second FET structure, both of which being formed over a silicon substrate. The first FET structure includes a high-k material layer, a layer of a first workfunction material formed over the high-k material layer, a layer of a barrier material formed over the first workfunction material layer; and a layer of a gate fill material formed over the barrier material layer. The entirety of the barrier material layer and the gate fill material layer are formed above the first workfunction material layer. The second FET structure includes a layer of the high-k material, a layer of a second workfunction material formed over the high-k material layer, a low-resistance material layer formed over the second workfunction material layer and a layer of the barrier material formed over the low-resistance material layer. | 2015-04-09 |
20150097247 | LATERAL BICMOS REPLACEMENT METAL GATE - A method of forming a semiconductor structure includes depositing a high-k dielectric layer within a first recess located between sidewall spacers of a first CMOS device and within a second recess located between sidewall spacers of a second CMOS device. A dummy titanium nitride layer is deposited on the high-k dielectric layer. Next, the high-k dielectric layer and the dummy titanium nitride layer are removed from the second recess in the second CMOS device. A silicon cap layer is deposited within the first recess and the second recess, the silicon cap layer is located above the high-k dielectric layer and dummy titanium nitride layer in the first CMOS device. Subsequently, dopants are implanted into the silicon cap layer located in the second recess of the second CMOS device. | 2015-04-09 |
20150097248 | SHALLOW TRENCH ISOLATION - The semiconductor structure includes a plurality of first insulators in a substrate, a common insulating layer surrounding the sidewall and the bottom of said first insulators in said substrate, and suspended portions of said substrate on said common insulating layer. | 2015-04-09 |
20150097249 | CROSS COUPLING GATE USING MULITPLE PATTERNING - Methodologies for forming a cross coupling gate and a resulting device are disclosed. Embodiments include: providing a plurality of gates extending vertically on a plurality of equally spaced horizontal positions of an IC; providing a cross-couple region of a gate of the plurality of gates, the cross-couple region including a portion of the gate extending from a first horizontal position of the horizontal positions to a second horizontal position of the horizontal positions; and providing at least one of the plurality of gates with an overlap of first and second segments of the at least one gate, the first and second segments being designated to be decomposed using different colors. | 2015-04-09 |
20150097250 | Semiconductor Devices and Methods for Fabricating the Same - Provided is a semiconductor device, which includes a first fin on a substrate, a first gate insulating layer including a first trench disposed on the first fin, a first work function adjusting layer in the first trench, a first barrier layer covering a top surface of the first work function adjusting layer; and an interlayer insulating layer on the first barrier layer. | 2015-04-09 |
20150097251 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed. | 2015-04-09 |
20150097252 | SIMPLIFIED GATE-FIRST HKMG MANUFACTURING FLOW - When forming field effect transistors according to the gate-first HKMG approach, the cap layer formed on top of the gate electrode had to be removed before the silicidation step, resulting in formation of a metal silicide layer on the surface of the gate electrode and of the source and drain regions of the transistor. The present disclosure improves the manufacturing flow by skipping the gate cap removal process. Metal silicide is only formed on the source and drain regions. The gate electrode is then contacted by forming an aperture through the gate material, leaving the surface of the gate metal layer exposed. | 2015-04-09 |
20150097253 | Sealed MEMS Devices with Multiple Chamber Pressures - A MEMS apparatus has a substrate, a cap forming first and second chambers with the base, and movable microstructure within the first and second chambers. To control pressures, the MEMS apparatus also has a first outgas structure within the first chamber. The first outgas structure produces a first pressure within the first chamber, which is isolated from the second chamber, which, like the first chamber, has a second pressure. The first pressure is different from that in the second pressure (e.g., a higher pressure or lower pressure). | 2015-04-09 |
20150097254 | MEMORY ELEMENT, METHOD OF MANUFACTURING THE SAME, AND MEMORY DEVICE - A memory element having a layer structure, the layer structure includes: a memory layer whose magnetization direction is changed in accordance with information; a magnetization-fixed layer having magnetization perpendicular to a film surface to be a basis of the information stored in the memory layer; and an intermediate layer made of a non-magnetic material, disposed between the memory layer and the magnetization-fixed layer, wherein at least a periphery of the memory layer is covered with a magnetic material through a non-magnetic material among the layer structure. | 2015-04-09 |
20150097255 | TUNNELING MAGNETO-RESISTIVE SENSORS WITH BUFFER LAYERS - In certain embodiments, a tunneling magneto-resistive (TMR) sensor includes a sensor stack positioned between a seed layer and a cap layer. The seed layer includes a first buffer layer that includes a non-magnetic nickel alloy. | 2015-04-09 |
20150097256 | SEMICONDUCTOR DEVICES INCLUDING AVALANCHE PHOTODETECTOR DIODES INTEGRATED ON WAVEGUIDES AND METHODS FOR FABRICATING THE SAME - Semiconductor devices and methods for fabricating semiconductor devices are provided. In one example, a method for fabricating a semiconductor device includes etching a trench into a waveguide layer in a detector region of a semiconductor substrate. An avalanche photodetector diode is formed about the trench. Forming the avalanche photodetector diode includes forming a multiplication region in the waveguide layer laterally adjacent to the trench. An absorption region is formed at least partially disposed in the trench. | 2015-04-09 |
20150097257 | INTEGRATED WAVEGUIDE STRUCTURE WITH PERFORATED CHIP EDGE SEAL - An integrated waveguide structure with perforated chip edge seal and methods of manufacture are disclosed herein. The structure includes a guard ring structure surrounding an active region of an integrated circuit chip. The structure further includes a gap in the guard ring structure which is located at a predetermined level of the integrated circuit chip. The structure further includes a waveguide structure formed on a substrate of the integrated circuit chip. The structure further includes a fiber optic optically coupled to the waveguide structure through the gap formed in the guard ring structure. | 2015-04-09 |
20150097258 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS - A semiconductor device includes a wiring layer that includes at least one low-dielectric rate interlayer insulating film layer; a guard ring that is formed by placing in series a wire and a via so as to be in contact with a through electrode, in a portion in which the through electrode passing through the wiring layer is formed; and the through electrode that is formed by being buried inside the guard ring. | 2015-04-09 |
20150097259 | CONDUCTIVE VIA STRUCTURE, PACKAGE STRUCTURE, AND PACKAGE OF PHOTOSENSITIVE DEVICE - Conductive plug structures suitable for stacked semiconductor device package is provided, wherein large contact region between the conductive plug structures and the corresponding pads of devices can be achieved, to reduce electrical impedance. Therefore, package structures such as photosensitive device packages using the conductive plug structures have superior electrical performance and reliability. | 2015-04-09 |
20150097260 | Single Silicon Wafer Micromachined Thermal Conduction Sensor - A single silicon wafer micromachined thermal conduction sensor is described. The sensor consists of a heat transfer cavity with a flat bottom and an arbitrary plane shape, which is created in a silicon substrate. A heated resistor with a temperature dependence resistance is deposed on a thin film bridge, which is the top of the cavity. A heat sink is the flat bottom of the cavity and parallel to the bridge completely. The heat transfer from the heated resistor to the heat sink is modulated by the change of the thermal conductivity of the gas or gas mixture filled in the cavity. This change can be measured to determine the composition concentration of the gas mixture or the pressure of the air in a vacuum system. | 2015-04-09 |
20150097261 | INTERCONNECT SYSTEM - An electrical contact and electrical interconnect network comprising graphene and a transition metal for a solid state device and an interconnect network for a circuit board or substrate are disclosed. | 2015-04-09 |
20150097262 | Semiconductor Diode with Trench Structures - A semiconductor diode includes a semiconductor body and trench structures extending from a surface of the semiconductor body into the semiconductor body. The semiconductor body includes a doped layer of a first conductivity type and a doped zone of a second conductivity type opposite to the first conductivity type. The doped zone is formed between the doped layer and a first surface of the semiconductor body. The trench structures are arranged between electrically connected portions of the semiconductor body. The trench structures do not include conductive structures that are both electrically insulated from the semiconductor body and electrically connected with another structure outside the trench structures. | 2015-04-09 |
20150097263 | METHOD AND APPARATUS FOR HIGH YIELD CONTACT INTEGRATION SCHEME - A methodology for forming contact areas by a multiple patterning process that provides increased yield and lower risk of contact-to-contact short at points of tight tip-to-tip spacing and the resulting device are disclosed. Embodiments include forming one or more trench patterning layers on a planarized surface of a wafer, forming one or more trenches in the one or more trench patterning layers, forming a block mask at one or more points along the one or more trenches, extending the one or more trenches down to a substrate level of the wafer, and removing the block mask from the one or more points. | 2015-04-09 |
20150097264 | DIODE STRING IMPLEMENTATION FOR ELECTROSTATIC DISCHARGE PROTECTION - A diode string having a plurality of diodes for ESD protection of a CMOS IC device comprises a first diode and a last diode in the diode string, wherein the first diode and the last diode are both formed on a bottom layer in a silicon substrate, and remaining diodes in the diode string. The remaining diodes are formed on a top layer placed on top of the bottom layer. The diode string further comprises a plurality of conductive lines that connect the first diode and the last diode on the bottom layer sequentially with the remaining diodes on the top layer to form a three dimensional ( | 2015-04-09 |
20150097265 | Semiconductor Device with Buried Conduction Path - A device includes a semiconductor substrate, emitter and collector regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite base region disposed in the semiconductor substrate, having a second conductivity type, and including a base contact region, a buried region through which a buried conduction path between the emitter and collector regions is formed during operation, and a base link region electrically connecting the base contact region and the buried region. The base link region has a dopant concentration level higher than the buried region and is disposed laterally between the emitter and collector regions. | 2015-04-09 |
20150097266 | HIGH PERFORMANCE E-FUSE FABRICATED WITH SUB-LITHOGRAPHIC DIMENSION - An electronic fuse link with lower programming current for high performance and self-aligned methods of forming the same. The invention provides a horizontal e-fuse structure in the middle of the line. A reduced fuse link width is achieved by spacers on sides of pair of dummy or active gates, to create sub-lithographic dimension between gates with spacers to confine a fuse link. A reduced height in the third dimension on the fuse link achieved by etching the link, thereby creating a fuse link having a sub-lithographic size in all dimensions. The fuse link is formed over an isolation region to enhanced heating and aid fuse blow. | 2015-04-09 |
20150097267 | INDUCTOR STRUCTURE WITH MAGNETIC MATERIAL AND METHOD FOR FORMING THE SAME - Embodiments of mechanisms of forming an inductor structure are provided. The inductor structure includes a substrate and a first dielectric layer formed over the substrate. The inductor structure includes a first metal layer formed in the first dielectric layer and a second dielectric layer over the first metal layer. The inductor structure further includes a magnetic layer formed over the first dielectric layer, and the magnetic layer has a top surface, a bottom surface and sidewall surfaces between the top surface and the bottom surface, and the sidewall surfaces have at least two intersection points. | 2015-04-09 |
20150097268 | INDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - An inductor structure includes a substrate, a protection layer, a patterned first conductive layer, copper bumps, a passivation layer, a diffusion barrier layer, and an oxidation barrier layer. The protection layer is located on the substrate. The bond pads of the substrate are respectively exposed through protection layer openings. The first conductive layer is located on the surfaces of the bond pads and the protection layer adjacent to the protection layer openings. The copper bumps are located on the first conductive layer. The passivation layer is located on the protection layer and the copper bumps. At least one of the copper bumps is exposed through a passivation layer opening. The diffusion barrier layer is located on the copper bump that is exposed through the passivation layer opening. The oxidation barrier layer is located on the diffusion barrier layer. | 2015-04-09 |
20150097269 | TRANSIENT VOLTAGE SUPPRESSION DEVICE AND MANUFACTURING METHOD THEREOF - The present invention discloses a transient voltage suppression (TVS) device and a manufacturing method thereof. The TVS device includes: a conductive layer; a P-type semiconductor substrate, which is formed on the conductive layer; an N-type buried layer, which is formed on the semiconductor substrate; a P-type lightly doped layer, which is formed on the buried layer; a P-type cap region, which is formed on the lightly doped layer; and an N-type reverse region, which is formed on the cap region, wherein a Zener diode includes the reverse region and the cap region, and an NPN bipolar junction transistor (BJT) includes the reverse region, the cap region, the lightly doped layer and the buried layer. | 2015-04-09 |
20150097270 | FINFET WITH RELAXED SILICON-GERMANIUM FINS - A method of forming a semiconductor structure includes forming a first fin in a p-FET device region of a semiconductor substrate and a second fin in an n-FET device region of the semiconductor substrate substantially parallel to the first fin. The first fin and the second fin each comprise a strained semiconductor material. Next, the second fin is amorphized to form a relaxed fin by implanting ions into the second fin while protecting the first fin. | 2015-04-09 |
20150097271 | SELF-HEALING CRACK STOP STRUCTURE - A self-healing crack stop structure and methods of manufacture are disclosed herein. The structure comprises a crack stop structure formed in one or more dielectric layers and surrounding an active region of an integrated circuit chip. The crack stop comprises self healing material which, upon propagation of a crack, is structured to seal the crack and prevent further propagation of the crack. | 2015-04-09 |
20150097272 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a carrier, several dies disposed on a surface of the carrier and several scribing lines defined on the surface of the carrier. The scribing lines include several continuous lines along a first direction and several discontinuous lines along a second direction. Further, a method of dies singulation includes providing a carrier, disposing several dies on a surface of the carrier according to several scribing lines including several continuous lines along a first direction and several discontinuous lines along a second direction, cutting the carrier according to the continuous lines along the first direction, and cutting the carrier according to the discontinuous lines along the second direction. | 2015-04-09 |
20150097273 | METHOD AND STRUCTURE OF FORMING BACKSIDE THROUGH SILICON VIA CONNECTIONS - A method, and the resulting structure, to make a thinned substrate with backside redistribution wiring connected to through silicon vias of varying height. The method includes thinning a backside of a substrate to expose through silicon vias. Then a thick insulator stack, including an etch stop layer, is deposited and planarized. With a planar insulating surface in place, openings in the insulator stack can be formed by etching. The etch stop layer in the dielectric stack accommodates the differing heights vias. The etch stop is removed and a conductor having a liner is formed in the opening. The method gives a unique structure in which a liner around the bottom of the through silicon via remains in tact. Thus, the liner of the via and a liner of the conductor meet to form a double liner at the via/conductor junction. | 2015-04-09 |
20150097274 | THROUGH-SILICON VIA STRUCTURE AND METHOD FOR IMPROVING BEOL DIELECTRIC PERFORMANCE - An improved through-silicon via (TSV) is disclosed. A semiconductor substrate has a a back-end-of-line (BEOL) stack formed thereon. The BEOL stack and semiconductor substrate has a TSV cavity formed thereon. A conformal protective layer is disposed on the interior surface of the TSV cavity, along the BEOL stack and partway into the semiconductor substrate. The conformal protective layer serves to protect the dielectric layers within the BEOL stack during subsequent processing, improving the integrated circuit quality and product yield. | 2015-04-09 |
20150097275 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a substrate-side electrode layer, an intermediate electrode layer, and a front-side electrode layer. The substrate includes a semiconductor layer and a projection portion, the projection portion being formed on a surface of the semiconductor layer. The substrate-side electrode layer is provided on the projection portion. The intermediate electrode layer extends from on a part of the substrate-side electrode layer, which part of the substrate-side electrode layer is located on the projection portion, to just above a region of the substrate in which region the projection portion is not provided. The front-side electrode layer is provided on a surface of the intermediate electrode layer. A Young's modulus E1 of the substrate-side electrode layer, a Young's modulus E2 of the intermediate electrode layer, and a Young's modulus E3 of the front-side electrode layer satisfy a relationship of E3>E1>E2. | 2015-04-09 |
20150097276 | ETCHING OXIDE-NITRIDE STACKS USING C4F6H2 - An article having alternating oxide layers and nitride layers is etched by an etch process. The etch process includes providing a first gas comprising C | 2015-04-09 |
20150097277 | FAN-OUT SEMICONDUCTOR PACKAGE WITH COPPER PILLAR BUMPS - A system-in-package includes a package carrier; a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier, wherein a plurality of contact pads are situated on the die face; a second semiconductor die mounted on the package carrier and adjacent to the first semiconductor die; a rewiring laminate structure between the first semiconductor die and the package carrier, the rewiring laminate structure comprising a re-routed metal layer, wherein at least a portion of the re-routed metal layer projects beyond the die edge; and a plurality of copper pillar bumps arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier. | 2015-04-09 |
20150097278 | SURFACE MOUNT SEMICONDUCTOR DEVICE WITH ADDITIONAL BOTTOM FACE CONTACTS - Assembling a surface mount semiconductor device includes providing a lead frame structure with peripheral leads and additional bottom face contacts integral with frame members. Outer portions of the bottom face contact members are interposed between inner portions of adjacent pairs of the peripheral leads. A package body is formed by encapsulating the lead frame structure in which the frame members are positioned outside a side edge surface. The peripheral leads and the bottom face contact members project between the side edge surface of the package body and the frame members. The frame members are cut and the peripheral leads and the bottom face contact members are separated and electrically isolated from each other. | 2015-04-09 |
20150097279 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor chip including a main surface electrode; a first mounting lead; a second mounting lead; a connection lead which overlaps with the main surface electrode, the first mounting lead and the second mounting lead when viewed in a thickness direction of the semiconductor chip and makes electrical conduction between the main surface electrode, the first mounting lead and the second mounting lead; and a resin portion which covers the semiconductor chip, the first mounting lead and the second mounting lead, wherein the resin portion has a resin bottom lying on the same plane as a bottom of the first mounting lead and a bottom of the second mounting lead. | 2015-04-09 |
20150097280 | HEAT CONDUCTIVE SUBSTRATE FOR INTEGRATED CIRCUIT PACKAGE - An integrated circuit package includes a substrate having a heat conducting portion integrally formed with a heat dissipating portion. First and second integrated circuit dies are mounted to opposite sides of the heat conducting portion of the substrate. The first and second integrated circuit dies may each be packaged as flip-chip configurations. Electrical connections between contact pads on the first and second integrated circuit dies may be formed through openings formed in the heat conducting portion of the substrate. The heat dissipating portion may be positioned externally from a location between the first and second integrated circuit dies so that it dissipates heat away from the integrated circuit package into the surrounding environment. | 2015-04-09 |
20150097281 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. The semiconductor device is a power semiconductor module of a liquid-cooled type, which substantially prevents a cooling liquid from leaking out without providing additional working on a casing and without a providing high precision in a process for forming a sealing member and a groove for fitting the sealing member. The semiconductor device has a groove for fitting a sealing member that is formed not at the casing but at the base plate. The sealing member and the groove have widths that bring the sealing member made of an elastic material into contact with side surfaces of the groove intermittently. | 2015-04-09 |
20150097282 | CHIP PACKAGES, CHIP ARRANGEMENTS, A CIRCUIT BOARD, AND METHODS FOR MANUFACTURING CHIP PACKAGES - A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material. | 2015-04-09 |
20150097283 | PLUG VIA FORMATION WITH GRID FEATURES IN THE PASSIVATION LAYER - Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. Via openings extend through the passivation layer from a top surface of the passivation layer to a metal line in the passivation layer. A conductive layer is formed on the top surface of the passivation layer and within each via opening. When the passivation layer and the conductive layer are planarized, a plug is formed that includes sections in the via openings. Each section is coupled with the metal line. | 2015-04-09 |
20150097284 | Bowl-shaped solder structure - An apparatus relating generally to a substrate is disclosed. In this apparatus, a first metal layer is on the substrate. The first metal layer has an opening. The opening of the first metal layer has a bottom and one or more sides extending from the bottom. A second metal layer is on the first metal layer. The first metal layer and the second metal layer provide a bowl-shaped structure. An inner surface of the bowl-shaped structure is defined responsive to the opening of the first metal layer and the second metal layer thereon. The opening of the bowl-shaped structure is configured to receive and at least partially retain a bonding material during a reflow process. | 2015-04-09 |
20150097285 | SYSTEMS AND METHODS FOR BONDING SEMICONDUCTOR ELEMENTS - A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element, wherein the surfaces of each of the plurality of first conductive structures and the plurality of second conductive structures include aluminum; and (b) ultrasonically bonding ones of the first conductive structures to respective ones of the second conductive structures. | 2015-04-09 |
20150097286 | CHIP PACKAGE AND METHOD FOR FABRICATING THE SAME - A chip package includes a packaging substrate, a semiconductor chip, and a plurality of conductive structures. The semiconductor chip has a central region and an edge region that surrounds the central region. The conductive structures are between the packaging substrate and the semiconductor chip. The conductive structures have different heights, and the heights of the conductive structures are gradually increased from the central region of the semiconductor chip to the edge region of the semiconductor chip, such that a distance between the edge region of the semiconductor chip and the packaging substrate is greater than a distance between the central region of the semiconductor chip and the packaging substrate. | 2015-04-09 |
20150097287 | Electrical Connections for Chip Scale Packaging - Electrical connections for chip scale packaging are disclosed. In one embodiment, a semiconductor device includes a post-passivation layer disposed over a substrate, the substrate having a first direction of coefficient of thermal expansion mismatch. The semiconductor device includes a first opening through the post-passivation layer, the first opening comprising a plurality of elongated apertures. A longest of the plurality of elongated apertures comprises a first dimension, wherein the first dimension is aligned substantially perpendicular to the first direction of coefficient of thermal expansion mismatch. | 2015-04-09 |
20150097288 | High Density Dielectric Etch Stop Layer - A method of manufacturing an integrated circuit device includes forming an inter-level dielectric layer over a semiconductor substrate, forming a transformative layer over the inter-level dielectric layer, forming a protective layer over the transformative layer without allowing the transformative layer to undergo a substantive transformation, and after forming the protective layer, causing the transformative layer to undergo a volume-increasing transformation. The volume-increasing transformation produces a high density material that provides an effective etch stop. | 2015-04-09 |
20150097289 | HYBRID PHOTONIC AND ELECTRONIC INTEGRATED CIRCUITS - A sequence of processing steps presented herein is used to embed an optical signal path within an array of nanowires, using only one lithography step. Using the techniques disclosed, it is not necessary to mask electrical features while forming optical features, and vice versa. Instead, optical and electrical signal paths can be created substantially simultaneously in the same masking cycle. This is made possible by a disparity in the widths of the respective features, the optical signal paths being significantly wider than the electrical ones. Using a damascene process, the structures of disparate widths are plated with metal that over-fills narrow trenches and under-fills a wide trench. An optical cladding material can then be deposited into the trench so as to surround an optical core for light transmission. | 2015-04-09 |
20150097290 | COMPOSITE METAL TRANSMISSION LINE BRIDGE STRUCTURE FOR MONOLITHIC MICROWAVE INTEGRATED CIRCUITS (MMICs) - A structure having first and second electrical conductors disposed on a surface of the structure and a bridging conductor connected between the first electrical conductor and the second electrical conductor with portions disposed over the surface of the structure. The bridging conductor includes a plurality of stacked, multi-metal layers, each one of the multi-metal layers having: an electrically conductive layer; and a pair of barrier metal layers, the electrically conductive layer being disposed between and in direct contact with the pair of barrier metal layers. | 2015-04-09 |
20150097291 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH CAPPING LAYERS BETWEEN METAL CONTACTS AND INTERCONNECTS - Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a metal contact structure, an electrically conductive capping layer formed on the metal contact structure, and a conductive via electrically connected to the metal contact structure through the electrically conductive capping layer. | 2015-04-09 |
20150097292 | INTERCONNECTS HAVING SEALING STRUCTURES TO ENABLE SELECTIVE METAL CAPPING LAYERS - Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect. | 2015-04-09 |
20150097293 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming an insulating material layer over a workpiece, patterning an upper portion of the insulating material layer with a conductive line pattern, and forming a stop layer comprising a metal oxide or a metal nitride over the patterned insulating material layer. A masking material is formed over the stop layer, and the masking material is patterned with a via pattern. The via pattern of the masking material is transferred to a lower portion of the insulating material layer. | 2015-04-09 |
20150097294 | METHOD FOR PROCESSING A WAFER AND WAFER STRUCTURE - A method for processing a wafer in accordance with various embodiments may include: removing wafer material from an inner portion of the wafer to form a structure at an edge region of the wafer to at least partially surround the inner portion of the wafer, and printing material into the inner portion of the wafer using the structure as a printing mask. A method for processing a wafer in accordance with various embodiments may include: providing a carrier and a wafer, the wafer having a first side and a second side opposite the first side, the first side of the wafer being attached to the carrier, the second side having a structure at an edge region of the wafer, the structure at least partially surrounding an inner portion of the wafer; and printing material onto at least a portion of the second side of the wafer. | 2015-04-09 |
20150097295 | Semiconductor Device and Method of Forming Conductive Layer Over Substrate with Vents to Channel Bump Material and Reduce Interconnect Voids - A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A first conductive layer having first and second segments is formed over a surface of the substrate with a first vent separating an end of the first segment and the second segment and a second vent separating an end of the second segment and the first segment. A second conductive layer is formed over the surface of the substrate to electrically connect the first segment and second segment. The thickness of the second conductive layer can be less than a thickness of the first conductive layer to form the first vent and second vent. The semiconductor die is mounted to the substrate with the bumps aligned to the first segment and second segment. Bump material from reflow of the bumps is channeled into the first vent and second vent. | 2015-04-09 |
20150097296 | MULTI-DIE STACK STRUCTURE - A multi-die stack structure including N dies stacked vertically is described. N is an integer larger than or equal to 2. Each die includes N die-specific input pads, wherein a specific pad among the N pads is for the input of the die. The specific pad of each die above the bottom die is electrically connected with a different pad of the bottom die other than the specific pad of the bottom die, via at least one TSV and, when not being in the die neighboring to the bottom die, also via a different pad of each underlying die above the bottom die. The specific pad of the bottom die is electrically connected with at least one pad of the overlying die(s) that is not the specific pad of any overlying die and not any pad electrically connected with the specific pad of any overlying die. | 2015-04-09 |