15th week of 2013 patent applcation highlights part 16 |
Patent application number | Title | Published |
20130088222 | SYSTEM AND METHOD FOR MEASURING WRINKLE DEPTH IN A COMPOSITE STRUCTURE - In accordance with one embodiment, a method is provided for non-destructive examination of a composite structure having a non-conductive surface and a conductive substrate. The method may include applying an alternating current to a probe having a coil conductor, scanning the probe across the non-conductive surface to induce eddy currents in the conductive substrate, and measuring changes in an electrical property of the probe in response to changes in the eddy currents indicative of variations in the depth of the conductive substrate. | 2013-04-11 |
20130088223 | TWO-CORE OPTICAL FIBER MAGNETIC FIELD SENSOR - A two-core optical fiber magnetic field sensor is configured from at least a light incidence/emission unit; a lens; a magnetic garnet; and a reflector, wherein the lens and the magnetic garnet are disposed between the light incidence/emission end of the light incidence/emission unit and the reflector; a light beam is emitted from one optical fiber; the light beam is reflected by the reflector after being transmitted through the lens and the magnetic garnet; the light beam is transmitted again through the magnetic garnet and the lens after the reflection; and incident on the other optical fiber, the light beam is emitted again from the other optical fiber, and reflected by the reflector after being transmitted through the lens and the magnetic garnet; and the light beam is transmitted again through the magnetic garnet and the lens after the reflection and incident again on the one optical fiber. | 2013-04-11 |
20130088224 | QUANTUM COMPUTER - Values of quantum bits used for a quantum computer is stabilized and the number of quantum bits per element is set to be 100 or more while ensuring quantum state stability during calculation of the quantum bits, quantum state controllability, and capability of achieving large-scale integration of quantum bits. Quantum calculation is performed as generating a spin vortex | 2013-04-11 |
20130088225 | System for Reconstructing MRI Images Acquired in Parallel - A system for parallel image processing in MR imaging comprises multiple MR imaging RF coils for individually receiving MR imaging data representing a slice of patient anatomy. An MR imaging system uses the multiple RF coils for acquiring corresponding multiple image data sets of the slice. An image data processor comprises at least one processing device conditioned for, deriving a first set of weights for generating a calibration data set comprising a subset of k-space data of composite image data representing the multiple image data sets. The at least one processing device uses the calibration data set in generating a first MR image data set, deriving a second set of weights using the calibration data set and the generated first MR image data set and uses the second set of weights in generating a second MR image data set representing a single image having a reduced set of data components relative to the first composite MR image data set. | 2013-04-11 |
20130088226 | MRI WITH FAT SUPPRESSION USING FAT DECOUPLING RF DURING PRE-SEQUENCE SHIMMING - A magnetic resonance imaging (MRI) system and method uses an MRI gantry having a static magnet structure, controllable gradient magnet structures and at least one radio frequency (RF) coil for transmitting and receiving RF signals to and from an imaging volume. Control circuits are configured to control gradient magnetic fields generated by the gradient magnet structures, to transmit/receive RF signals to and from the at least one RF coil and to process RF signals received during a diagnostic MRI scan to produce displayable images of structures located within the imaging volume. The control circuits are configured to include a preparatory fat decoupling RF pulse as part of a patient ROI (region of interest) shimming sequence effected prior to a fat suppression type of diagnostic MRI data acquisition scan sequence. | 2013-04-11 |
20130088227 | MAGNETIC RESONANCE-BASED METHOD AND SYSTEM FOR DETERMINATION OF OXYGEN SATURATION IN FLOWING BLOOD - A method and system for determination of oxygen saturation in blood flowing in a vessel using magnetic resonance (MR). An MR image sequence is acquired with different echo time (TE) encoding, and different Fourier velocity encoding (FVE). A Fourier transformation is applied along the velocity dimension to determine a velocity distribution of tissue signals in each voxel of the image sequence. Tissue signals indicative of moving tissues are separated from tissue signals indicative of static tissue, based on the velocity distribution. Oxygen saturation in blood may then be determined using only the tissue signals indicative of flowing blood. | 2013-04-11 |
20130088228 | METHOD AND APPARATUS FOR MAGNETIC RESONANCE IMAGING - In a method and apparatus for magnetic resonance (MR) imaging, a magnetization of nuclear spins in a subject is prepared in multiple preparation modules of an acquisition sequence. MR signals are acquired with at least one imaging module of the sequence. Spoiler gradient fields are generated in the multiple preparation modules in order to affect a transverse magnetization of the spins. The spoiler gradient fields that are applied in at least two different preparation modules are spatially varied along different directions. Spoiler gradient moments of the spoiler gradient fields are selected so that, for at least one of three orthogonal spatial directions, a weighted sum of the spoiler gradient moments that are applied along this spatial direction satisfies a threshold condition. | 2013-04-11 |
20130088229 | Magnetic Resonance Examination with Instrument Detection - An magnetic resonance examination system for examination of an object comprises an RF system to generate an RF transmission field and gradient system to generate temporary magnet gradient fields. A control module includes a sequence controller to control the RF system and the gradient system to produce acquisition sequences including RF pulses and magnetic gradient pulses to generate magnetic resonance signals. The sequence controller is configured to produce an detection scan including a steady state gradient echo acquisition sequence to generate steady state gradient echo signals and an RF spoiled echo acquisition sequence to produce RF spoiled echo signals. The control module further including an analysis unit to compare the gradient echo signals to the RF spoiled echo signals and for detection of an instrument in the object from the comparison of the gradient echoes and the RF spoiled echoes. | 2013-04-11 |
20130088230 | METHOD OF RECONSTRUCTING A MAGNETIC RESONANCE IMAGE OF AN OBJECT CONSIDERING HIGHER-ORDER DYNAMIC FIELDS - The invention relates to a method of acquiring a magnetic resonance image of an object employing spatial encoding by a gradient field, said gradient field comprising non-linear gradient field components, the method comprising: selecting ( | 2013-04-11 |
20130088231 | MAGNETIC RESONANCE SYSTEM AND METHOD FOR FREQUENCY CALIBRATIONN OF THE MAGNETIC RESONANCE SYSTEM - In a method for frequency calibration in a magnetic resonance system in a volume section containing an unknown number of determined substances, the predetermined volume section is excited with RF pulses and subsequent echo signals are recorded at different times and spectral information is determined for each of the echo signals, from which a peak value in the spectral information and an associated relaxation time are determined. Dependent on the relaxation time, a substance is determined for each peak value. A frequency adjustment substance dependent of the magnetic resonance system is then implemented. Multiple peak values in the spectral information of the echo signals can be determined. | 2013-04-11 |
20130088232 | Solid-State NMR Spectrometer, Sample Holder Therefor, and Method of Solid-State NMR Spectroscopy - A high-resolution solid-state NMR spectrometer which can measure a disklike sample. The spectrometer includes: a stator having an air bearing disposed within the static magnetic field, the rotor being disposed in the stator; and an engaging mechanism mounted in a one-end portion of the rotor and detachably holding a sample holder that holds the disklike sample. | 2013-04-11 |
20130088233 | Shield for Electronic Circuit - A metal structure includes a plurality of non-contiguous subsections on a substrate. The subsections are at least partially capacitively connected to one another. This is achieved by the subsections having overlaps on both sides of the substrate and/or by the subsections being connected to one another by capacitors. The capacitive coupling produced constitutes a short circuit for high frequencies and an open circuit for low frequencies. This results in the frequency-selective surface. | 2013-04-11 |
20130088234 | GRADIENT COIL POWER SUPPLY AND A MAGNETIC RESONANCE IMAGING SYSTEM - A gradient coil power supply ( | 2013-04-11 |
20130088235 | Method for Acquiring and Processing Marine Seismic Data to Extract and Constructively use the Up-Going and Down-Going Wave-fields Emitted by the Source(s) - A method for acquisition and processing of marine seismic signals to extract up-going and down- going wave-fields from a seismic energy source includes deploying at least two marine seismic energy sources at different depths in a body of water. These seismic energy sources are actuated with known time delays that are varied from shot record to shot record. Seismic signals from sources deployed at different depths are recorded simultaneously, Seismic energy corresponding to each of the sources is extracted from the recorded seismic signals. Up-going and down-going wave-fields are extracted from the sources deployed at different depths using the extracted seismic energy therefrom. A method includes the separated up-going and down-going wave-fields are propagated to a water surface or a common reference, the up-going or the down-going wave-field is 180 degree phase shifted, and the signals from these modified up-going and down-going wave-fields are summed. | 2013-04-11 |
20130088236 | BATTERY-MONITORING DEVICE - A battery-monitoring device that monitors a state of charge of each battery cell constituting a battery is provided, including: a voltage detection circuit that individually detects a voltage of the battery cell; a voltage comparison circuit that individually compares the voltage of the battery cell and a threshold voltage, and outputs a signal having a first level when the voltage of the battery cell is equal to or greater than the threshold voltage, and a signal having a second level when the voltage of the battery cell is less than the threshold voltage; and a determination unit that determines the overcharged state of the battery cell when at least one condition is satisfied from among two conditions of: a voltage detection value which is input from the voltage detection circuit being equal to or greater than a threshold; and a signal which is input from the voltage comparison circuit being a first level. | 2013-04-11 |
20130088237 | BATTERY-MONITORING DEVICE - The present invention provides a battery-monitoring device is provided that monitors a voltage state of each battery cell constituting a battery, including: a voltage detection circuit; a management circuit which manages voltage detection data of each battery cell using the voltage detection circuit; a communication mode converter which is connected to the voltage detection circuit through a first communication line for communicating using a clock synchronous communication mode, and is connected to the management circuit through a second communication line for communicating using a clock asynchronous communication mode; and an insulating element which is interposed in the second communication line, wherein the communication mode converter transmits the voltage detection data, received from each of the voltage detection circuits through the first communication line, through the second communication line to the management circuit. | 2013-04-11 |
20130088238 | Differential Current Measurements to Determine ION Current in the Presence of Leakage Current - An ion chamber provides a current representative of its characteristics as affected by external conditions, e.g., clean air or smoke. A direct current (DC) voltage is applied to the ion chamber at a first polarity and the resulting current through the ion chamber and parasitic leakage current is measured at the first polarity, then the DC voltage is applied to the ion chamber at a second polarity opposite the first polarity, and the resulting current through the ion chamber and parasitic leakage current is measured at the second polarity. Since substantially no current flows through the ion chamber at the second polarity, the common mode parasitic leakage current contribution may be removed from the total current measurement by subtracting the current measured at the second polarity from the current measured at the first polarity, resulting in just the current through the ion chamber. | 2013-04-11 |
20130088239 | FAULT-TYPE IDENTIFICATION FOR ELECTRIC POWER DELIVERY SYSTEMS - Disclosed herein are systems and methods for identifying a fault type in an electric power delivery system using an angle difference between a total zero-sequence current and a total negative-sequence current and a comparison of phase-to-phase currents against a threshold. The angle difference falls into one of a number of predetermined angle difference sectors. Each sector is associated with a phase-to-ground fault type and a phase-to-phase-to-ground fault type or two phase-to-phase-to-ground fault types. The phase-to-phase current(s) of the indicated phase-to-phase-to-ground fault type(s) associated with the sector are compared with a threshold to determine which of the fault types of the sector is the actual fault type. The threshold may be a multiple of a maximum phase-to-phase current. | 2013-04-11 |
20130088240 | METHOD AND APPARATUS FOR DETERMINING AN INSULATION RESISTANCE IN GROUNDED IT SYSTEMS - The invention relates to a method and an apparatus for determining an actual insulation resistance R | 2013-04-11 |
20130088241 | FAILURE DETECTING APPARATUS FOR SIGNAL DETECTION APPARATUS - A failure detecting apparatus that detects an isolation failure between a plurality of coils included in a signal detection apparatus. The failure detecting apparatus includes a voltage applying unit that applies a DC voltage to a coil in the plurality of coils; a differential signal generating unit that generates a differential signal from a voltage at the coil and a predetermined voltage; a threshold voltage setting circuit that outputs a threshold voltage; and a comparator that compares the differential signal with the threshold voltage, thereby detecting whether or not an isolation failure exists. The differential signal generating unit includes either first setting unit for setting an absolute value of the differential signal to be amplified with a predetermined gain or second setting unit for setting the predetermined voltage to be different from a ground potential, and the predetermined gain is set to a value different from one and zero. | 2013-04-11 |
20130088242 | Microcontroller with Sequencer Driven Analog-to-Digital Converter - An automated sequencer for a microcontroller is provided which makes a CVD conversion process a hardware function. The sequencer controls the charging/discharging of the sensor and ADC sample-and-hold capacitances, as well as the voltage division process. It also initiates the ADC conversion, with an optional second conversion for greater resolution, or a differential conversion | 2013-04-11 |
20130088243 | POSITION SENSING HEAD WITH REDUNDANCY - A position sensing head combines a sensing element and a simplified electronic module to enable operation with one wire, in addition to a circuit common, for providing power and transmitting a signal, while separating the sensing head from signal conditioning circuits by over 10 meters. The simplicity of the electronic module allows the use of basic electronic components that operate at more than 225° C. The signal is a variable frequency impressed onto the one wire, which can be read by a frequency meter. Another signal, such as a position or temperature, can be impressed onto the one wire at the same time as the first signal. The second signal is of a different frequency range so that it will not interfere with the first. A demodulator circuit can separate the two signals. The sensing element construction allows for locating up to three active elements measuring the same target. | 2013-04-11 |
20130088244 | VARIABLE CAPACITANCE SENSORS AND METHODS OF MAKING THE SAME - A variable capacitance sensor includes a first conductive electrode comprising electrically interconnected first conductive sheets; a second conductive electrode comprising electrically interconnected second conductive sheets, wherein the first conductive sheets are at least partially interleaved with the second conductive sheets, and wherein the second conductive electrode is electrically insulated from the first conductive electrode; and microporous dielectric material at least partially disposed between and contacting the first conductive sheets and the second conductive sheets. A method of making a variable capacitance sensor by replacing ceramic in a ceramic capacitor with a microporous material is also disclosed. | 2013-04-11 |
20130088245 | Capacitive Inspection Of EUV Photomasks - Methods and systems for generating an indication of a changing electrostatic field between a sense electrode of a capacitance sensing integrated circuit and a specimen under inspection are presented. The capacitance sensing integrated circuit is an integrated circuit that includes a number of sense electrodes and sense electronics. By fabricating the elements of the capacitance sensing integrated circuit as a single microelectronic chip, the sense electrodes can be miniaturized to sizes that enable inspection of fine line patterns common in modern semiconductor manufacturing. In one embodiment, the sense electrodes are metallic contacts. In another embodiment the sense electrodes are field effect transistors (FETs) with a floating gate. The sense electronics generate an indication of the changing electrostatic field between each sense electrode and a specimen under inspection as the specimen is scanned relative to the capacitance sensing integrated circuit. | 2013-04-11 |
20130088246 | Microcontroller with Optimized ADC Controller - An analog-to-digital (ADC) controller is used in combination with a digital processor of a microcontroller to control the operation of capacitance measurements using the capacitive voltage division (CVD) method. The ADC controller handles the CVD measurement process instead of the digital processor having to run additional program steps for controlling charging and discharging of a capacitive touch sensor and sample and hold capacitor, then coupling these two capacitors together, and measuring the resulting voltage charge thereon in determining the capacitance thereof. The ADC controller may be programmable and its programmable parameters stored in registers. | 2013-04-11 |
20130088247 | READOUT APPARATUS AND READOUT METHOD FOR SENSOR ARRAY - A readout apparatus and a readout method for a sensor array are provided. The readout apparatus includes a switching circuit, a control unit, a gain circuit and an offset compensating circuit. The control unit controls the switching circuit to perform a switching operation for selecting a target sensor from a plurality of sensors of the sensor array. The gain circuit selectively senses the target sensor according the switching operation of the switching circuit, and gains the sensing result to output a gained sensing value of the target sensor. The control unit further dynamically decides a compensating value according the switching operation. The offset compensating circuit adjusts the gained sensing value for outputting a compensated sensing value of the target sensor in accordance with the compensating value. | 2013-04-11 |
20130088248 | DETERMINATION OF SERIES RESISTANCE OF AN ARRAY OF CAPACITIVE ELEMENTS - A circuit for determination of a resistance of an array of capacitive elements includes a reference ring oscillator circuit, the reference ring oscillator circuit being loaded with low-loss capacitive elements; an array test ring oscillator circuit, the array test ring oscillator circuit being loaded with the array of capacitive elements; and a resistance determination module, the resistance determination module configured to determine the resistance of the array of capacitive elements based on data from the reference ring oscillator circuit and the array test ring oscillator circuit. | 2013-04-11 |
20130088249 | METHOD OF DETECTING A FAULT WITH THE MEANS FOR DE-ICING A PROBE FOR MEASURING A PHYSICAL PARAMETER - A method of detecting a fault in a de-icer probe for measuring a physical parameter on an airplane engine, the method including: prior to starting an engine, measuring a first value of the physical parameter with help of the probe; activating the probe de-icer; at an end of a determined duration from a start of de-icing, measuring a second value of the parameter with help of the probe; and comparing the first and second values and generating a fault signal if the difference between the first and second values is less than a determined threshold. | 2013-04-11 |
20130088250 | CONTACT APPARATUS AND SEMICONDUCTOR TEST EQUIPMENT USING THE SAME - A contact apparatus includes a pusher having first and second surfaces, the first surface being connected to a pressure unit, stoppers protruding from edges of the second surface of the pusher away from the pressure unit, a pusher block having first and second surfaces facing each other, the first surface facing the pusher, and the second surface being connected to a semiconductor device, coupling members connecting the pusher to the pusher block, and a connector disposed between the pusher and the pusher block, at least part of a surface of the connector being circular, and the circular surface making a point contact with the pusher or the pusher block. | 2013-04-11 |
20130088251 | PROBE CARD AND MANUFACTURING METHOD THEREOF - There are provided a probe substrate and a manufacturing method thereof that may prevent an electrode pad bonded with a probe pin from being released from the probe substrate. The probe card includes: a ceramic substrate having at least one electrode pad on one surface thereof; and a probe pin bonded to the electrode pad, and the electrode pad has a larger dimension than a bonding surface of the probe pin. | 2013-04-11 |
20130088252 | METHOD FOR DIAGNOSIS OF CONTACTS OF A PHOTOVOLTAIC SYSTEM AND APPARATUS - A method for monitoring of contacts of a photovoltaic system includes injection of a test signal having a plurality of frequencies, into the photovoltaic system, and determining a generator impedance of the photovoltaic system by evaluating a response signal associated with the test signal. The method further includes monitoring of contacts of the photovoltaic system independently of operating states of the photovoltaic system by modelling of an alternating-current response of the photovoltaic system based on the determined generator impedance, wherein the modelling is specific to at least two different operating states of the photovoltaic system. | 2013-04-11 |
20130088253 | Methods for Testing Manufactured Products - The problem of high test cost of manufactured goods can be partially solved by lowering the percentage of the goods to be tested methodically while keeping the total defective portion of the goods expressed in DPPM below a preset target value. The method includes identifying a first test that is capable of screening out enough parts that would fail a second test so that the portion of the parts to be tested second test can be reduced. The number of parts screened out by the first test determines if the reduced testing scheme would violate the preset DPPM target value. | 2013-04-11 |
20130088254 | METHOD FOR TESTING INTEGRATED CIRCUITS WITH HYSTERESIS - A system and method for testing circuits. A generated input voltage waveform for a first phase of a test may use transitions with a voltage swing between expected low and high trigger points for an integrated circuit (IC) with hysteresis. A generated input voltage waveform for a second phase of the test may use transitions with a voltage swing between the expected low trigger point and a high sub-threshold value. The high sub-threshold value may be a tolerable voltage difference below the expected high trigger point. A generated input voltage waveform for a third phase of the test may use transitions with a voltage swing between the expected high trigger point and a low sub-threshold value. The low sub-threshold value may be a tolerable voltage difference above the expected low trigger point. The expected trigger points and sub-threshold values may be found from earlier characterization studies for the IC. | 2013-04-11 |
20130088255 | STACKED SEMICONDUCTOR DEVICES - A stacked semiconductor device includes a first and a second semiconductor device. A first major surface of each of the first and second devices which includes the active circuitry directly face each other. The first major surface of each of the devices includes a beveled edge on at least one edge, and a probe pad which extends onto the beveled edge. A first opening is located between the beveled edges of the first and second devices on a vertical side of the stacked semiconductor device. | 2013-04-11 |
20130088256 | CRITICAL-PATH CIRCUIT FOR PERFORMANCE MONITORING - An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied. | 2013-04-11 |
20130088257 | SEMICONDUCTOR DEVICE HAVING IMPEDANCE CALIBRATION FUNCTION TO DATA OUTPUT BUFFER AND SEMICONDUCTOR MODULE HAVING THE SAME - Disclosed herein is a semiconductor device that includes a first transistor unit coupled to the data terminal, and a plurality of second transistor units coupled to the calibration terminal. The first transistor unit includes a plurality of first transistors having a first conductivity type connected in parallel to each other so that an impedance of the first transistor unit is adjustable. Each of the second transistor units includes a plurality of second transistors having the first conductivity type connected in parallel to each other so that an impedance of each of the second transistor units is adjustable. The semiconductor device further includes an impedance control circuit that reflects the impedance of each of the second transistor units to the first transistor unit. | 2013-04-11 |
20130088258 | SEMICONDUCTOR DEVICE INCLUDING OUTPUT CIRCUIT CONSTITUTED OF PLURAL UNIT BUFFER CIRCUITS IN WHICH IMPEDANCE THEREOF ARE ADJUSTABLE - The semiconductor device comprises an output circuit that includes a plurality of unit buffer circuits each of which has an adjustable impedance, a control circuit that selectively activates one or ones of the unit buffer circuits, and an impedance adjustment unit that adjusts the impedances of the unit buffer circuits and includes a power line, a replica circuit, which has a replica impedance that is substantially equal to the adjustable impedance of each of the unit buffer circuits, and a load current generation circuit, which changes current flowing therethrough in accordance with the number of activated the one or ones of the unit buffer circuits. The replica circuit and the load current generation circuit are connected in common to the power line. | 2013-04-11 |
20130088259 | Circuits and Methods for Programmable Transistor Array - A programmable transistor array circuit is disclosed comprising a semiconductor substrate; and a plurality of basic transistor units (BTUs) arranged in rows and columns of uniformly spaced cells, the BTUs further comprising PMOS transistor units (PTUs), NMOS transistor units (NTUs) and dummy transistor units (DTUs) each BTU having conductors arranged in a single direction running through the BTUs and the conductors being uniformly spaced with respect to each other. The arrangement of the BTUs is subject to restricted design rules. Logical transistor units (LTUs) are formed from the BTUs using first and second layers of metallization. Additional embodiments are disclosed incorporating the programmable transistor array circuit. | 2013-04-11 |
20130088260 | LATCH CIRCUIT, FLIP-FLOP CIRCUIT, AND DIVIDER - A latch circuit switches a differential operation performed by a differential operation circuit including a first logic circuit, a second logic circuit, a third logic circuit, and a fourth logic circuit and a single end operation performed by a single end operation circuit according to a logic level of an inputted selection signal. The latch circuit performs an operation to output an input signal and an inverted input signal without change from a first output terminal and a second output terminal of the latch circuit, respectively, and an operation to set the input signal and the inverted input signal in a hold state in the differential operation and performs an operation to output the input signal from the first output terminal without change and an operation to set the input signal in a hold state in the single end operation, according to a clock signal and an inverted clock signal. | 2013-04-11 |
20130088261 | LOW LEAKAGE SPARE GATES FOR INTEGRATED CIRCUITS - Devices, systems, methods, and other embodiments associated with spare gates are described. In one embodiment, a spare gate in an integrated circuit has a disconnected discharge path to minimize or eliminate current leakage. | 2013-04-11 |
20130088262 | LOW VOLTAGE COMPARATOR CIRCUITS - Circuits that operate with power supplies of less than 1 Volt are presented. More particularly, circuits that operate with supply voltages near or lower than the threshold voltage of the transistors in those circuits are presented. Various circuits and embodiments such as operational transconductance amplifiers, biasing circuits, integrators, continuous-time sigma delta modulators, track-and-bold circuits, and others are presented. The techniques and circuits can be used in a wide range of applications and various transistors from metal-oxide-semiconductor to bipolar junction transistors may implement the techniques presented herein. | 2013-04-11 |
20130088263 | ELECTRIC CHARGE FLOW CIRCUIT FOR A TIME MEASUREMENT - A charge flow circuit for a time measurement, including a plurality of elementary capacitive elements electrically in series, each elementary capacitive element leaking through its dielectric space. | 2013-04-11 |
20130088264 | System, Drivers for Switches and Methods for Synchronizing Measurements of Analog-to-Digital Converters - A driver for a switch includes a primary side having a trigger input and a secondary side comprising an analog-to-digital converter (ADC). The primary side and the secondary side are separated by a galvanic isolation barrier and communicate via a communication circuit. The primary side is configured to receive a trigger signal at the trigger input and forward the trigger signal to the ADC of the secondary side of the driver via the communication circuit. The ADC is configured to start a measurement upon receiving the trigger signal. | 2013-04-11 |
20130088265 | GATE DRIVER ON ARRAY, SHIFTING REGESTER AND DISPLAY SCREEN - The embodiment of the present disclosure relates to a technical field of liquid crystal display, and particularly, to a gate driver on array, a shifting register and a display screen. The gate driver on array comprises: a first TFT, a second TFT, a third TFT, a fourth TFT, a capacitor and a pulling-down module, the pulling-down module is connected among a first clock signal input terminal, a second clock signal input terminal, a first node and an output terminal, and is connected with a low voltage signal terminal, for maintaining the first node and the output terminal being in a low level during a non-operation period of the gate driver on array. Thus, the gate driver on array may achieve a bidirectional scan by designing the functions of the input terminal and the reset terminal in the gate driver on array as being implemented symmetrically, without changing a charging-discharging characteristic of nodes, which ensures a reliability and stabilization of the circuit. | 2013-04-11 |
20130088266 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second power elements and first and second driving circuits. The semiconductor device also includes a resistor having a first end connected to the first power element and a second end connected to the first driving circuit. Furthermore, the semiconductor device includes a switching element connected between the first driving circuit and the first end of the resistor, and turned ON and OFF. When a first input signal is an OFF signal, the first driving circuit causes the first power element to become turned OFF, and when the first input signal is an OFF signal or when a second input signal is an ON signal, the switching element is turned ON. | 2013-04-11 |
20130088267 | APPARATUS FOR REDUCING SIMULTANEOUS SWITCHING NOISE - The invention provides an electronic device for reducing simultaneous switching noise (SSN). The electronic device includes: a driver, driving an external device according to an input signal, and including: an input end, receiving the input signal; a positive output end, coupled to an external capacitor of the external device; and a negative output end, coupled to a variable capacitor; and a loading calibration circuit, generating an adjusting signal to adjust a first capacitance of the variable capacitor so as to make the first capacitance approximately equal to a second capacitance of the external capacitor. | 2013-04-11 |
20130088268 | Multi-Phase Clock Generation System and Clock Calibration Method Thereof - A multi-phase clock generation system and a clock calibration method thereof. The multi-phase clock generation system comprises an input module, a frequency division module and a control module. The input module inputs a reference clock signal with a clock period. The frequency division module according to the reference clock signal produces a phase clock signal with a frequency magnification relationship. The control module divides the phase clock signal into a plurality of clock intervals. There is a clock interval between two adjacent phase clock signals, and each of the plurality of clock intervals has a phase time delay. The control module controls a first phase clock signal of the plurality of phase clock signals to align with a last phase clock signal. The control module sequentially arranges each of the plurality of phase clock signals according to the phase time delay. | 2013-04-11 |
20130088269 | IMPLEMENTING CONTROL VOLTAGE MIRROR - A circuit for implementing a control voltage mirror for phase error and jitter performance optimization and a design structure on which the subject circuit resides are provided. The control voltage mirror is used with a phase locked loop filter utilizing a thin oxide filter capacitor connected to a control voltage and a distal side of the capacitor connected to a voltage reference. The control voltage mirror includes an operational amplifier holding voltage across the capacitor to be near or at zero volts, substantially eliminating capacitor leakage current to provide phase error and jitter performance optimization. | 2013-04-11 |
20130088270 | METHOD AND APPARATUS FOR DETERMINING DUTY CYCLE OF A CLOCK IN A CIRCUIT USING A CONFIGURABLE PHASE LOCKED LOOP - An embodiment of the invention discloses phase shifting a second clock signal by a phase increment with respect to a first clock signal, where the first clock signal and the second clock signal have the same periods. The first clock signal is sampled with the second clock signal, and the output of the sample indicates whether the sample of the first clock signal is at a logic one state or a logic zero state. A count of logic one samples is incremented if the sample of the first clock signal is at a logic one state. The process of phase shifting the second clock signal and sampling the first clock signal is repetitively performed to a maximum number of samples. | 2013-04-11 |
20130088271 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A semiconductor memory device includes a clock period reflector configured to reflect time corresponding to period information of an internal clock signal to an input data signal, a data-clock converter configured to generate a synchronization clock signal having phases corresponding to an output signal of the clock period reflector, and a synchronization output unit configured to synchronize and output the input data signal in response to the synchronization clock signal. | 2013-04-11 |
20130088272 | LOW CONSUMPTION FLIP-FLOP CIRCUIT WITH DATA RETENTION AND METHOD THEREOF - The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated. | 2013-04-11 |
20130088273 | SEMI-DYNAMIC FLIP-FLOP WITH PARTIALLY FLOATING EVALUATION WINDOW - Implementations of the present disclosure involve a semi-dynamic flip-flop circuit incorporating a partially floating evaluation window that provides a faster data to output delay, a PMOS keeper device may be placed in series with an existing keeper circuit of the semi-dynamic flip-flop circuit. The gate of the PMOS series keeper device may be connected to a shut-off signal of the semi-dynamic flip-flop circuit that provides a three gate delay, self-timed positive pulse to control the keeper circuit. The PMOS series keeper device effectively turns off the keeper circuit when the clock signal rises but turns in back on after a three gate delay to sustain the precharge state of the dynamic node. The effective turning on and off of the keeper circuit portion may decrease the data to output delay of the flip-flop, resulting in higher performing microprocessors. | 2013-04-11 |
20130088274 | PHASE INTERPOLATOR, MULTI-PHASE INTERPOLATION DEVICE, INTERPOLATED CLOCK GENERATING METHOD AND MULTI-PHASE CLOCK GENERATING METHOD - A phase interpolator, multi-phase interpolation device, interpolated clock generating method and multi-phase clock generating method is related to a phase interpolator with a differential to single-ended converter, a load circuit, two differential pairs, a current source and at least a switch pair. By using the switch pair to control the current providing for the two differential pairs from the current source, and through regulating the load of the load circuit and/or the reference current of the current source, the intersection of a first signal and a second signal is in the overlap duration between a first input clock and a second input clock, so that uniform multi-phase output clock signal can be interpolated. | 2013-04-11 |
20130088275 | DYNAMIC VOLTAGE DROP AWARE CLOCK INSERTION TOOL - A clock tree power decoupling system includes a pre-decoupling processor that provides a clock tree that supports a critical timing path condition. The clock tree power decoupling system also includes a clock tree power decoupler having a clock tree module that identifies clock buffers in the clock tree corresponding to synchronous start and end points of the critical timing path condition, and a power decoupling module that inserts a decoupling capacitance proximate the clock buffers in the clock tree, wherein the decoupling capacitance is sized to rectify the critical timing path condition. The clock tree power decoupling system additionally includes a post-decoupling processor that provides a power-decoupled clock-inserted database employing the decoupling capacitance. A method of clock tree power decoupling is also provided. | 2013-04-11 |
20130088276 | DRIVER OUTPUT PAD LEAKAGE CURRENT COMPENSATION - A device includes a sense circuit configured to detect a leakage current from a driver output pad. A current mirror responds to the sense circuit and compensates for the leakage current detected at the driver output pad. A scaled compensation circuit can supply compensation current to the current mirror. | 2013-04-11 |
20130088277 | GENERATION OF BAND-LIMITED NOISE WITH TUNABLE CREST FACTOR - A method for generating a signal having a defined bandwidth and a desired crest factor is disclosed. The signal is composed of a number of individual sinusoidal signals, each having an amplitude and a frequency. The method includes determining an exponent to be used in a specific exponential function and corresponding to the desired crest factor, the exponent being determined based on an a priori known relationship between crest factor and exponent; calculating a phase value for each sinusoidal signal using the specific exponential function and the previously determined exponent; and superposing the sinusoidal signals to obtain the signal having the desired crest factor, whereby the phases of the individual signals are maintained. | 2013-04-11 |
20130088278 | CONNECTION DEVICE - A connection device for connecting a load to a power supply, comprising at least first and second current control devices arranged in parallel between the power supply and the load, and a controller arranged to switch the current control devices on in sequence for temporally overlapping on periods. | 2013-04-11 |
20130088279 | Power Converter - The present invention provides a power converter including a power semiconductor device, a driver circuit section that outputs a driving signal for driving the power semiconductor device, a buffer circuit section that includes a PNP transistor and an NPN transistor and that outputs a gate voltage for driving the power semiconductor device, a first delay circuit section that receives the driving signal and that generates a first delay signal on the basis of the received driving signal, a first MOSFET that has a drain electrode connected with the output of the buffer circuit section and that is driven on the basis of the first delay signal. A current flows through the buffer circuit section and the first MOSFET on the basis of the received driving signal, the first delay circuit section outputs the first delay signal after the buffer circuit section exits the transient state and turns on, and the gate voltage is applied to the power semiconductor device from the buffer circuit section to turn the power semiconductor device on by the switching operation of the first MOSFET based on the first delay signal. | 2013-04-11 |
20130088280 | HIGH POWER SEMICONDUCTOR ELECTRONIC COMPONENTS WITH INCREASED RELIABILITY - An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor. | 2013-04-11 |
20130088281 | TOUCH PANEL AND MANUFACTURING METHOD THEREOF - A touch panel includes a substrate, a transparent conductive layer, a conductive decoration pad, a decoration layer and an opaque conductive layer. The transparent conductive layer is disposed on the substrate, and the conductive decoration pad is disposed on the transparent conductive layer. The decoration layer is disposed on the conductive decoration pad and the transparent conductive layer, and has an opening located on the conductive decoration pad. The opaque conductive layer is disposed on the decoration layer and electrically connected with the transparent conductive layer through the opening and the conductive decoration pad. | 2013-04-11 |
20130088282 | APPARATUS AND METHOD FOR SUPPLYING POWER TO 300 PIN MSA 40GB TRANSPONDER - The disclosure provides a method and an apparatus for supplying power to a 300 PIN MSA 40 Gb TRANSPONDER. The apparatus comprises a power control module ( | 2013-04-11 |
20130088283 | TYPE-SWITCHING TRANSISTORS, ELECTRONIC DEVICES INCLUDING THE SAME, AND METHODS OF OPERATING THE TYPE-SWITCHING TRANSISTORS AND ELECTRONIC DEVICES - Type-switching transistors, electronic devices including the same, and methods of operating thereof are provided. A type-switching transistor may include a plurality of gates corresponding to a channel layer. The plurality of gates may include a first gate for switching a type of the transistor and a second gate for controlling ON/OFF characteristics of the channel layer. The first and second gates may be disposed on one side of the channel layer so that the channel layer is not disposed between the first and second gates. | 2013-04-11 |
20130088284 | SEMICONDUCTOR DEVICE - A semiconductor device includes a precharge circuit configured to precharge a voltage output node, a boosting circuit configured to boost a voltage at the voltage output node by a predetermined level after the voltage output node is precharged, and a voltage supply circuit configured to supply a pumping voltage to increase the voltage at the voltage output node to a target level. | 2013-04-11 |
20130088285 | DC VOLTAGE CONVERSION CIRCUIT OF LIQUID CRYSTAL DISPLAY APPARATUS - Disclosed is a DC voltage conversion circuit of a liquid crystal display apparatus, including: a main pumping circuit including a plurality of thin film transistors and configured to output voltage for driving a liquid crystal display apparatus when the plurality of thin film transistors are alternately turned on or off; and a switch control signal generator configured to control voltages applied to gates of the plurality of thin film transistors by inversion of a clock signal, in which each thin film transistor is turned on when positive gate-source voltage is applied thereto, and turned off when negative gate-source voltage is applied thereto. | 2013-04-11 |
20130088286 | METHOD OF GENERATING MULTIPLE CURRENT SOURCES FROM A SINGLE REFERENCE RESISTOR - A differential voltage controlled current source generating one or more output currents is based upon a single external resistor. The differential voltage controlled current source may generate an output current that is proportional to a received differential voltage and a bias current with the use of a single external resistor. The technique may be used to generate multiple accurate and process independent current sources. The current sources may be a zero temperature coefficient (ZTC) current, a proportional to absolute temperature (PTAT) current, or an inversely proportional to absolute temperature (NTAT) current. The output of the current sources may be inversely proportional to the resistance of the external resistor. | 2013-04-11 |
20130088287 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING ANALOG SWITCH - A semiconductor device has an analog switch, in which a P channel transistor and an N channel transistor are connected in parallel between an input terminal and an output terminal; a variable voltage circuit, which variably generates, according to an input voltage applied to the input terminal, potentials of a first gate voltage and first back gate voltage of the P channel transistor and of a second gate voltage and second back gate voltage of the N channel transistor; and a control circuit, which supplies to the variable voltage circuit a control signal controlling the analog switch to be conducting or non-conducting. In response to the control signal causing the analog switch to be conducting, the variable voltage circuit outputs the variable-generated first gate voltage and second gate voltage to the respective gates of the P channel transistor and N channel transistor. | 2013-04-11 |
20130088288 | INTEGRATED MAGNETIC FIELD SENSOR-CONTROLLED SWITCH DEVICES - Embodiments relate to integrated magnetic field sensor-controlled switch devices, such as transistors, current sources, and power switches, among others. In an embodiment, a magnetic switch and a load switch are integrated in a single integrated circuit device. In embodiments, the device can also include integrated load protection and load diagnostics. Embodiments can provide load switching and optional simultaneous logic signaling, for example to update a microcontroller or electronic control unit (ECU), while reducing space and complexity and thereby cost. | 2013-04-11 |
20130088289 | SEMICONDUCTOR CHIP PACKAGE INCLUDING VOLTAGE GENERATION CIRCUIT WITH REDUCED POWER NOISE - A semiconductor chip package illuminates and minimizes a power noise generated from a voltage generation circuit in the semiconductor chip package includes an integrated circuit chip with a voltage generation circuit that receives an external voltage to generate a supply voltage to be used in an internal circuit and a connection terminal connected to an output node of the voltage generation circuit, and a mounting substrate including a noise eliminator electrically connected to the connection terminal to reduce a power noise of the supply voltage and a mounting substrate to mount the integrated circuit chip to package the integrated circuit chip as the semiconductor chip package. | 2013-04-11 |
20130088290 | Measurement of the Output Current of an Amplifier Circuit - An amplifier circuit includes a first and a second switching element connected in parallel between a first and a second voltage potential and are actuated in the amplifier mode in a clocked manner. A capacitive element is connected in parallel to at least one of the two switching elements, a measuring circuit for measuring the switching edges occurring during switching of the switching elements, and a current-determining circuit for determining the output current by means of the measured switching edges. | 2013-04-11 |
20130088291 | COMBINED FILTER AND TRANSCONDUCTANCE AMPLIFIER - Embodiments of circuitry, which includes an operational transconductance amplifier and a passive circuit, are disclosed. The passive circuit is coupled to the operational transconductance amplifier. Further, the passive circuit receives an input signal and the operational transconductance amplifier provides an output current, such that the passive circuit and the OTA high-pass filter and integrate the input signal to provide the output signal. | 2013-04-11 |
20130088292 | SOLID-STATE IMAGING APPARATUS - A solid-state imaging apparatus includes: an amplifier circuit configured to amplify a signal from pixel; and a reference signal generating circuit configured to generate a ramp signal, wherein feedback capacitor elements having the same structure are electrically connected to a capacitive feedback type amplifier of the amplifier circuit and to a capacitive feedback type amplifier of the reference signal generating circuit respectively, and a connecting configuration between an amplifier of the amplifier circuit and the feedback capacitor element and a connecting configuration between an amplifier of the reference signal generating circuit and the feedback capacitor element are the same. | 2013-04-11 |
20130088293 | METHOD AND APPARATUS FOR PROGRAMMABLE GAIN CONTROL USEFUL WITH DIGITAL TO ANALOG CONVERTER - A programmable gain controller (PGC) useful with a digital to analog converter is coupled to an input node providing a current source that is variable with a level of an input signal such as time sampled audio data, and multiple switches controlled to function as a digital gain control. Each switch is configured to selectively steer a variable fraction of the current provided by a current source to either a current sink node or to an output node of the PGC to provide at least one scaled current. An amplifier is coupled to an output of the PGC. The amplifier is configured to convert scaled current(s) to at least one output signal having an amplitude that is a function of both the input signal level and the digital gain input signal. Controlling the gain by steering current at the analog portion of the apparatus conserves circuit space and reduces noise. | 2013-04-11 |
20130088294 | Attenuating Non-Linear Noise in An Amplifier with Alternating DC -offset Correction - An amplifier may include two or more pulse-width modulators controlling respective sets of switches to produce an amplified version of a source signal. A positive DC-offset based on the source signal may be applied to the pulse-width modulator controlling one respective set of switches, and an equal value negative DC-offset may be applied to the pulse-width modulator controlling the other respective set of switches, to provide an effective offset between the respective points in time of the rising/falling edges of the different pulse-width modulated control signals. The addition of alternating positive and negative DC-offset values doesn't affect the output load, and doesn't degrade the signal. The DC-offsets may be added at a frequency selected to be beyond the signal baseband, and the value of the small input signal level may be determined using an RMS level comparator or similar measurement technique. | 2013-04-11 |
20130088295 | Multi-Band Power Amplifier - A power amplifier ( | 2013-04-11 |
20130088296 | Attenuating Noise and Cross-Talk in an Audio System by Offsetting Outputs In Phase - An amplifier may include two or more pulse-width modulators (PWMs) controlling respective sets of switches to produce an amplified version of a source signal. The clocking for the amplifier may be controlled to delay signal processing within the PWMs relative to one another in time, thereby providing an effective time offset between the respective edge transitions of the controlling signals provided to the respective sets of switches. The PWMs may count down to zero from the next PWM duty-cycle value when a new data sample is detected, beginning a new count for each new sample, with the PWM outputting a pulse when the counter value is nonzero. A “data-sample-ready” signal may be decoded from a master counter, which may be clocked based on the high speed PWM clock, and the decode value may be adjusted to determine when the PWM should initialize to the next data sample. | 2013-04-11 |
20130088297 | PWM Re-Clocking Scheme To Reject Accumulated Asynchronous Jitter - An amplifier may use pulse-width modulators controlling respective sets of switches to produce an amplified version of a source signal. A phase locked loop in the amplifier may generate a differential clock signal. A first processing element operating according to a first supply voltage may generate a PWM signal representative of the source signal, and also generate a clock enable signal corresponding to the differential clock signal. A second processing element (PE2) may receive the differential clock signal, the PWM signal, and the clock enable signal, and level shift the PWM signal and the clock enable signal to operate according to a second supply voltage, and may generate a resampling clock signal from the differential clock signal according to the level shifted clock enable signal. The PE2 may provide a PWM output signal representative of the source signal by resampling the level shifted PWM signal with the resampling clock signal. | 2013-04-11 |
20130088298 | HIGH PERFORMANCE CLASS AB OPERATIONAL AMPLIFIER - A class AB operational amplifier includes an input stage, an output stage and a level shifter stage to control the quiescent current of the output stage and to transfer the signal from the input stage to the output stage, and a control circuit of the level shifter stage. The control circuit includes a transistor differential pair having a differential input terminals and the differential voltage at the differential terminals of the differential pair controls the level shifter stage. | 2013-04-11 |
20130088299 | Power Amplifier with Matching Transformer - Aspects of a system for a power amplifier with an on-package matching transformer may include a DC/DC converter that enables generation of a bias voltage level within an IC die based on an amplitude of an input signal to a PA circuit within the IC die. The bias voltage level may be applied to a transformer, which is external to the IC die but internal to an IC package containing the IC die and/or a circuit board containing the IC package. One or more amplifier bias voltage levels, derived from the bias voltage level applied to the transformer, may be applied to the PA circuit. | 2013-04-11 |
20130088300 | ACCUMULATOR-TYPE FRACTIONAL N-PLL SYNTHESIZER AND CONTROL METHOD THEREOF - There are provided an accumulator-type fractional N-PLL synthesizer for suppressing the fractional spurious caused by periodically switching a frequency division number of a fractional frequency divider, and a control method thereof. In an accumulator-type fractional N-PLL synthesizer ( | 2013-04-11 |
20130088301 | Oscillator circuit and method of providing an oscillator output signal - The present invention is directed to an oscillator circuit comprising an oscillator input for providing an input signal, a first integrator circuit comprising a first integrator capacitor and a first integrator output, a comparator, a discharge circuit for discharging said first integrator capacitor once per cycle of said oscillator circuit, and an oscillator output for providing an output signal, wherein said oscillator circuit further comprises a second integrator circuit comprising a second integrator capacitor and a second integrator output, and wherein said oscillator circuit is arranged for allowing said input signal to be subsequently integrated by said first and second integrator circuit in an alternating manner, and for providing said integrated output signal of said first and second integrator circuit subsequently to said comparator in said alternating manner. | 2013-04-11 |
20130088302 | VOLTAGE-CONTROLLED OSCILLATOR DEVICE AND METHOD OF CORRECTING VOLTAGE-CONTROLLED OSCILLATOR - The present application discloses a voltage-controlled oscillator device and a method of correcting the voltage-controlled oscillator. The voltage-controlled oscillator device comprises predistortion module, configured to predistort an input voltage to obtain a predistorted voltage; and a voltage-controlled oscillator, configured to generate an output signal with a corresponding oscillation frequency according to the predistorted voltage, wherein the predistortion module corrects a non-linear characteristic of the voltage-controlled oscillator, so that there is a linear relationship between the input voltage and the oscillation frequency of the output signal. The voltage-controlled oscillator device may be applied to a phase-locked circuit in a communication system. | 2013-04-11 |
20130088303 | APPARATUS, AND ASSOCIATED METHOD, FOR FORMING A SYNTHESIZED OSCILLATING SIGNAL - An apparatus, and an associated method, for synthesizing a discrete-valued oscillating signal. Input parameters are provided that are determinative of the frequency, gain, and phase characteristics of the resultant, oscillating signal. The discrete-valued, oscillating signal is combinable with another signal to form a mixed signal of a desired frequency, gain, and phase characteristic using a single complex multiplication operation. | 2013-04-11 |
20130088304 | ANTENNA FEED STRUCTURE - A feed structure for a wearable antenna incorporates a microstrip transmission line designed for mounting on opposite sides of a fabric. The transmission line has a perforated ground plane which reduces capacitance and offers an appropriate impedance, even when the fabric is thin, and allows the use of a relatively robust line conductor having a width of 3 mm or 5 mm or more. The ground plane can be extended to provide the ground plane of a balun and the material of that ground plane can in turn be extended to provide the wearable antenna. | 2013-04-11 |
20130088305 | LADDER ACOUSTIC WAVE FILTER DEVICE AND BRANCHING FILTER - A ladder acoustic wave filter device is constructed such that ripples in the pass band are suppressed, and insertion loss is small in both of a high frequency side portion and a low frequency side portion of the pass band. Apodization weighting is applied to a series-arm-side IDT electrode. Busbars of the series-arm-side IDT electrode are configured so that in an acoustic wave propagation direction, a distance in an overlap width direction between the busbars becomes shorter as the overlap width of electrode fingers becomes smaller. Each of a pair of comb-shaped electrodes of a parallel-arm-side IDT electrode further includes a plurality of dummy electrodes that extend from a busbar and are opposed to electrode fingers of the other comb-shaped electrode in the overlap width direction. The parallel-arm-side IDT electrode is a normal IDT electrode in which the overlap width is constant. | 2013-04-11 |
20130088306 | OPEN CIRCUIT COMMON JUNCTION FEED FOR DUPLEXER - The present disclosure relates to microwave cavity filters used in cellular communication systems. More specifically, in one aspect, the present disclosure relates to the integration of combline cavity filters directly with antenna elements without galvanic connections. In another aspect, the present disclosure relates methods for loading combline filters without contact. | 2013-04-11 |
20130088307 | ORTHOMODE TRANSDUCER - An orthomode transducer (OMT) operable in a broadband (e.g. >30%), including a frequency above ˜30 GHz, with an isolation better than −50 dB, cross-polarizations better than −40 dB, an insertion loss between −0.1 and −0.3 dB for both polarizations, and return losses better than −25 dB can be produced substantially or entirely from CNC machining, comprises a turnstile for coupling a polarization diplexed waveguide with four waveguide paths; and two E-plane Y junctions each for coupling initially oppositely directed pairs of the waveguide paths such that each waveguide path has a same electrical length from the turnstile to the E-plane Y junctions as the waveguide path with which it is paired, such that the OMT is formed in 3-6 blocks, including a single block having a substantially planar mating surface that includes the matching feature, and defines one side of initial segments of the four waveguide paths. Reproducibility of these OMTs has been shown. | 2013-04-11 |
20130088308 | ACOUSTIC WAVE FILTER - Disclosed is a pass band type acoustic wave filter capable of obtaining an excellent attenuation characteristic in attenuation bands, in which an IDT electrode having a meander structure is used as at least one of the input-side electrode and the output-side electrode, and the attenuation band is provided over/under the pass band. An electrode having a meander structure in which a plurality of IDT blocks are connected to each other in series between the input port or the output port and the ground port is arranged as the input-side IDT electrode and the output-side IDT electrode, and the electrode finger between the neighboring IDT blocks is removed, so as to suppress excitation of an undesired acoustic wave. | 2013-04-11 |
20130088309 | RING RESONATOR AND FILTER HAVING THE SAME - Disclosed are a resonator configured by a microstrip line and a filter. A ring resonator in accordance with an embodiment of the present invention includes a ring resonant unit configured by a microstrip line; and a via connecting the resonant unit with a ground surface. In accordance with the embodiment of the present invention, the ring resonator configured by a microstrip line including a via and a filter, thereby providing a smaller and cheaper resonator and filter. | 2013-04-11 |
20130088310 | CIRCUIT BREAKER HAVING AN UNLOCKING MECHANISM AND METHODS OF OPERATING SAME - Embodiments provide an electronic circuit breaker. The electronic circuit breaker has a moveable contact arm having a moveable main electrical contact, and a lockout mechanism operable to contact the moveable contact arm and block motion of thereof, the lockout mechanism having a lockout latch with one or more pivot joints, a moveable stop, and an offset engagement portion, the moveable stop adapted to contact the moveable contact arm, and an unlock actuator providing an unlock force at the engagement portion causing lockout latch pivoting and release of the moveable contact arm. Also disclosed are secondary electrical contacts configured to engage each other in the ON configuration, with a leaf spring operably supporting a moveable one of the secondary contacts, the leaf spring configured to be flexed to close the secondary contacts. A method of operating the electronic circuit breaker is provided, as are other aspects. | 2013-04-11 |
20130088311 | CONTACT SWITCHING DEVICE - An object of the present invention is to provide a contact switching device having a smaller height dimension. For this, there is provided a contact switching device in which a movable iron core ( | 2013-04-11 |
20130088312 | ELECTROMAGNETIC RELAY - An electromagnetic relay includes a fixed iron core; a movable iron core disposed opposing to the fixed iron core; a coil for generating a magnetic force when energized to make the movable iron core attracted by the fixed iron core; a movable contact coupled with the movable iron core; a fixed contact disposed opposing to the movable contact; and a reset spring for resetting the movable iron core when the coil is de-energized. The movable iron core includes a base body to which an expanding force of the reset spring is applied and a movable member provided independently from the base body. The movable member is attracted by the fixed iron core when the coil is energized to move integrally with the base body, and is reset by the expanding force of the reset spring when the coil is de-energized to slide independently from the base body. | 2013-04-11 |
20130088313 | SUPERCONDUCTING MAGNET APPARATUS AND CONTROL METHOD THEREOF - Provided are a superconducting magnet apparatus with a switch that automatically connects or disconnects an external power source to a superconducting coil, and a method of controlling the same. The superconducting magnet apparatus includes a superconducting coil that generates a magnetic field when an electric current from an external power source is applied thereto, and a switch that supplies or shuts off an electric current output from the external power source by connecting or disconnecting the superconducting coil to the external power source. | 2013-04-11 |
20130088314 | Electrical Transformer Assembly - A support frame for an electrical transformer assembly, comprising two loop-shaped parts, each loop-shaped part having a plurality of limbs, each limb having a peripheral recessed portion in which a primary electrical coil is mountable, and at least one secondary coil is mountable in piggyback on the primary electrical coil, one limb of each loop-shaped part having a straight section. The frame also includes an adjustable attaching means for attaching one of the loop-shaped parts with respect to the other loop-shaped part and adjusting a distance therebetween, so that only the straight sections are adjacent and form a central leg, the central leg being for receiving a magnetic core distinct from the attaching means. The frame provides a means and a method to efficiently secure adjacent windings in a circular core transformer kernel. | 2013-04-11 |
20130088315 | TRANSFORMER WITH ARBITRARILY SMALL LEAKAGE-INDUCTANCE APPARATUS AND METHOD - An electrical transformer is provided having a toroidal core; a plurality of wraps of a low impedance transmission line the low impedance transmission line including a transmission pair of first and second conductors such that the transformer creates a magnetic flux confined to interfaces between said first and second conductors and does not extend to the toroidal core, and the transformer having a coupling coefficient K arbitrarily close to 1 and a value of leakage inductance L | 2013-04-11 |
20130088316 | ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF - An electronic component that can be prevented from being mounted on a circuit board with inclination, and a manufacturing method thereof are provided. An electronic component is mountable on a circuit board including a first land and a second land. The electronic component includes outer electrodes on a lower surface of a stack to be arranged along a direction and are connectable to the first land and the second land, respectively. With the eletronic component mounted to the circuit board, respective contact surfaces of the outer electrodes to the first land and the second land have a structure being symmetric about a line parallel to the direction, and each respective contact surface is divided into a plurality of portions. | 2013-04-11 |
20130088317 | REACTOR AND METHOD OF MANUFACTURING THE SAME - An annular core ( | 2013-04-11 |
20130088318 | REACTOR AND METHOD FOR PRODUCING SAME | 2013-04-11 |
20130088319 | CHIP THERMISTOR AND METHOD OF MANUFACTURING SAME - A chip thermistor has a thermistor portion including a ceramic material containing respective metal oxides of Mn, Ni, and Co as major ingredients; a pair of composite portions including a composite material of Ag—Pd, and respective metal oxides of Mn, Ni, and Co and arranged on both sides of the thermistor portion so as to sandwich in the thermistor portion between the composite portions; and external electrodes connected to the pair of composite portions, respectively. In this manner, the pair of composite portions are used as bulk electrodes and, for this reason, the resistance of the chip thermistor can be adjusted mainly with consideration to the resistance in the thermistor portion without need for much consideration to the distance between the external electrodes and other factors. | 2013-04-11 |
20130088320 | Wireless Network Hotel Room Management System - A wireless network hotel room management system includes a communications network. The system includes a computer connected to the communications network and includes a memory configured to store programming and a processor to execute the programming. A guest room unit is situated in each guest room and is in data communication with the network. A housekeeping module is in communication with the network. The computer monitors real time status of the room. Each guest unit is configured to receive projected absence data from a guest and to communicate the same to the computer through the communications network. Programming executed by the processor determines if received projected absence data is indicative that a guest will be gone long enough for housekeeping to clean the room and, if so, communicates a housekeeping order. The system includes a room reservation module for reserving a room and receiving a room key. | 2013-04-11 |
20130088321 | METHODS AND SYSTEMS FOR USING RFID IN BIOLOGICAL FIELD - Biological reagent carrier devices and methods are disclosed, which employ RFID techniques to associate information with biological reagents. | 2013-04-11 |