15th week of 2013 patent applcation highlights part 33 |
Patent application number | Title | Published |
20130089924 | CULTURE APPARATUS HAVING HEATERS - A culture apparatus includes a heat insulating box main body having an inner box and a heat insulating door, a culture vessel, a duct and a circulation blower forcing convection of a gas such as air in the culture vessel, a humidifying pan disposed on a bottom portion of the culture vessel within the duct, and heaters disposed on the outer side of the inner box and on the inner side of the heat insulating door, for heating the inside of the culture vessel. The culture apparatus is configured such that a rapid heater is provided on the downstream side of the circulation blower inside the duct, and the rapid heater is activated if a temperature in the culture vessel is decreased below a prescribed temperature, thereby rapidly regaining the prescribed temperature. | 2013-04-11 |
20130089925 | TEMPERATURE CONTROLLING SURFACES AND SUPPORT STRUCTURES - A heat exchange module for use in a chemical, pharmaceutical or biological reactor system can include a body configured to be disposed in the reactor system having an inner replaceable reactant container is disclosed. The body can further include at least one thermally conductive surface adapted to contact the inner replaceable reactant container to facilitate heat transfer. Furthermore, the heat exchange module can include a heat exchanger disposed within the module body and can include a fluid circulation path through which a heat exchange fluid can be circulated. | 2013-04-11 |
20130089926 | METHOD FOR DIFFERENTIATING HUMAN NEURAL PROGENITOR CELLS INTO DOPAMINERGIC NEURONS, AND MEDIUM FOR DIFFERENTIATION THEREOF - The present invention provides a method for differentiating human neural progenitor cells into dopaminergic neurons, comprising the step of culturing human neural progenitor cells in a medium containing fusaric acid. In addition, the present invention provides a medium for differentiation of human neural progenitor cells into dopaminergic neurons. | 2013-04-11 |
20130089927 | Hematopoietic Cell E-Selectin/L-Selectin Ligand Polypeptides and Methods of Use Thereof - The invention features methods and compositions for treating hematopoietic disorders, inflammatory conditions, and cancer and providing stem cell therapy in a mammal. | 2013-04-11 |
20130089928 | Serum-Free Chemically Defined Cell Culture Medium - Embodiments of chemically defined cell culture media containing nutrients and growth factors free of any serum for culturing cells such as mesenchymal stem cells and methods of using embodiments of the cell culture medium for expanding cell populations such as mesenchymal stem cells while maintaining a pluripotent phenotype and methods of inducing chondrogenesis and osteogenesis of mesenchymal stem cells by admixing differentiation factors into embodiments of the cell culture medium. | 2013-04-11 |
20130089929 | MICRODEVICE FOR FUSING CELLS - A microdevice for fusing cells, the microdevice including: a substrate; a first electrode array including a plurality of first electrodes, and disposed on the substrate; a microwell array including a plurality of microwells formed respectively at locations corresponding to the plurality of first electrodes, and disposed on the first electrode array; a second electrode disposed above the plurality of microwells, and including a microchannel having a predetermined height; inlet and outlet holes mutually spaced apart from the microchannel; and a power supply unit applying voltage to the plurality of first electrodes and the second electrode. Accordingly, a cell trapped in the microwell and a cell disposed on the microwell are aligned in a line between the first and second electrodes, and thus the two cells having different traits are smoothly fused in a one-to-one manner when an electric shock is applied to the two cells. | 2013-04-11 |
20130089930 | MICRODEVICE FOR FUSING CELLS - A microdevice for fusing cells including: a microchannel layer including a main microchannel and a plurality of sub-microchannels branched from one end of the main microchannel; a plurality of first electrodes formed on one side of the main microchannel; a plurality of second electrodes formed on the other side of the main microchannel and each second electrode facing the each of the first electrodes; a thin film disposed on the microchannel layer and covering the main microchannel; an upper cover including an air inflow passage for connecting a top of the thin film and the outside of the microdevice; and a power supply unit for applying voltage to the plurality of first and second electrodes. | 2013-04-11 |
20130089931 | MICRODEVICE FOR FUSING CELLS - A microdevice for fusing cells including: a membrane with a plurality of pores having a diameter smaller than the smallest diameter among the first kind of cells and second kind of cells; a first chamber where the first cell is located and a second chamber where the second cell is located, wherein the membrane is disposed therebetween; a first electrode combined to the first chamber; a second electrode combined to the second chamber; and a power generator applying a voltage to the first and second electrodes. Accordingly, the first and second cells across the membrane may be arranged in a one-to-one manner between the first and second electrodes, and thus the first and second cells having different traits may be smoothly fused in a one-to-one manner when electric signals are sequentially applied thereto. | 2013-04-11 |
20130089932 | FET Sensor and Methods for Detecting Melamine - The present invention provides a device and methods for the detection and quantification melamine in a sample by rapid and specific electrochemical detection. The present invention includes using a field-effect transistor (FET) biosensor having an open Si channel with a melamine antigen, or hapten, or an antibody, anchored via a linker molecule such as self assembled monolayer to the surface of the gate dielectric of the said open Si channel. The anchoring molecule having the capability of detecting melamine directly or indirectly by selectively binding melamine antibodies, which changes a field-effect on a Si channel, causing a change in conductivity of the FET. This change in conductivity can be measured and is used to determine the presence or absence of melamine in a sample compared to a standard signal or pre-measured database. | 2013-04-11 |
20130089933 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE, AND METHOD FOR FABRICATING DISPLAY DEVICE - A method for fabricating a semiconductor device includes a first step of forming, on a first substrate, a first element region in which a plurality of elements are collectively arranged, a second step of relocating the plurality of elements formed on the first substrate to a holding member in the same arrangement as in the first element region to have the plurality of elements held on the holding member, a third step of rearranging the plurality of elements held on the holding member and having the plurality of elements held on an intermediate substrate, thereby forming a second element region having a shape different from a shape of the first element region on the intermediate substrate, and a fourth step of dispersing the plurality of elements held on the intermediate substrate and adhering the plurality of elements to a second substrate. | 2013-04-11 |
20130089934 | Material Delivery System and Method - A system and method for controlling saturated vapor pressure of a precursor material is provided. An embodiment comprises generating a calibration curve and utilizing the calibration curve to control a temperature of the precursor material in order to control its saturated vapor pressure. Alternatively, the calibration curve may be substituted for a real time sensor which can take readings in real time and adjust the temperature and saturated vapor pressure based upon the real time readings. | 2013-04-11 |
20130089935 | OVERLAY AND SEMICONDUCTOR PROCESS CONTROL USING A WAFER GEOMETRY METRIC - The present invention may include acquiring a wafer shape value at a plurality of points of a wafer surface at a first and second process level, generating a wafer shape change value at each of the points, generating a set of slope of shape change values at each of the points, calculating a set of process tool correctables utilizing the generated set of slope of shape change values, generating a set of slope shape change residuals (SSCRs) by calculating a slope of shape change residual value at each of the points utilizing the set of process tool correctables, defining a plurality of metric analysis regions distributed across the surface, and then generating one or more residual slope shape change metrics for each metric analysis region based on one or more SSCRs within each metric analysis region. | 2013-04-11 |
20130089936 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A plurality of SiC semiconductor chips are mounted on a mounting substrate (S | 2013-04-11 |
20130089937 | METHOD AND APPARATUS FOR ACCURATE DIE-TO-WAFER BONDING - A method of light-emitting diode (LED) packaging includes coupling a number of LED dies to corresponding bonding pads on a sub-mount. A mold apparatus having concave recesses housing LED dies is placed over the sub-mount. The sub-mount, the LED dies, and the mold apparatus are heated in a thermal reflow process to bond the LED dies to the bonding pads. Each recess substantially restricts shifting of the LED die with respect to the bonding pad during the heating. | 2013-04-11 |
20130089938 | METHOD FOR MAKING LIGHT EMITTING DIODE - A method for making light emitting diode is provided. The method includes following steps. A light emitting diode chip is provided, wherein the light emitting diode chip comprises a first semiconductor layer, an active layer and a second semiconductor layers stacked together in that order. A patterned mask layer is located on a surface of the first semiconductor layer, wherein the patterned mask layer includes a number of bar-shaped protruding structures aligned side by side, and a slot is defined between each two adjacent protruding structures to expose a portion of the first semiconductor layer. The exposed portion of the first semiconductor layer is etched to form a protruding pair. A number of M-shaped three-dimensional nano-structures are formed by removing the mask layer. A first electrode is electrically connected with the first semiconductor layer. A second electrode is electrically connected with the second semiconductor layer. | 2013-04-11 |
20130089939 | METHOD FOR MAKING LIGHT EMITTING DIODE - A method for making light emitting diode is provided. The method includes following steps. A light emitting diode chip is provided, the light emitting diode includes a first semiconductor layer, an active layer and a second semiconductor layers stacked on a surface of a substrate in that order. A patterned mask layer is located on the second semiconductor layer, and the patterned mask layer includes a number of bar-shaped protruding structures aligned side by side. The second semiconductor layer is etched to form a number of three-dimensional nano-structures preform. The mask layer is removed to form a number of M-shaped three-dimensional nano-structures. The second semiconductor layer and the active layer are etched to expose a portion of the first semiconductor layer. A first electrode is electrically connected with the first semiconductor layer. A second electrode is electrically connected with the second semiconductor layer. | 2013-04-11 |
20130089940 | METHOD OF MANUFACTURING DISPLAY UNIT - A method of manufacturing a display unit includes: forming, on a substrate, a thin-film transistor having an oxide semiconductor layer; and forming, above the thin-film transistor, a display region that includes a plurality of display elements. The oxide semiconductor layer is formed using a sputtering method in which a target and the substrate are opposed to each other. The target is made of an oxide semiconductor and includes a plurality of divided portions that are jointed in a planar form. A spacing interval between two joints that are formed by the plurality of divided portions and are side-by-side with one another of the target is equal to or less than a width of a luminance distribution arising in the display region in a direction substantially orthogonal to the joints. | 2013-04-11 |
20130089941 | VAPOR DEPOSITION METHOD, VAPOR DEPOSITION DEVICE AND ORGANIC EL DISPLAY DEVICE - A vapor deposition source ( | 2013-04-11 |
20130089942 | METHOD FOR PRODUCING A SOLAR CELL - A method for producing a solar cell from a silicon substrate, which has a first main surface, used in normal application as an incident light side and a second main surface, used as the back surface, having a passivating layer on the second main surface, includes the steps: applying an oxygen-containing layer onto the second main surface of the silicon substrate, and heating the silicon substrate to a temperature of at least 800° C. to densify the oxide-containing layer and for the oxidation of the boundary surface between the oxide-containing layer and the second main surface of the silicon substrate to form a thermal oxide, an oxygen source giving off oxygen for the oxidation. | 2013-04-11 |
20130089943 | METHOD OF MANUFACTURING A SOLAR CELL - An embodiment of the present disclosure provides method of manufacturing a solar cell. The method comprises the steps of providing a silicon substrate, forming a P-N junction structure in the silicon substrate, forming an oxide layer for passivating the surface defect of the substrate that has a low reflectivity for AM1.5G solar spectrum, and forming a plurality of metal electrodes on the silicon substrate. | 2013-04-11 |
20130089944 | SOLAR CELL SILICON WAFER PROCESS - In the production of silicon solar cells wherein the process includes a dopant diffusion to form a pn junction, a back surface field layer, or a front surface field layer, resulting in the formation of a doped glass surface, a HF vapor etch is utilized to remove the doped glass layer and expose the wafer surface. The exposed surface is subjected to an oxygen treatment for predetermined times and temperatures to alter the surface state. The HF vapor etch followed by the oxygen treatment, or chemical oxidation, results in significant improvement in solar cell electrical properties. | 2013-04-11 |
20130089945 | METHOD OF MANUFACTURING SOLID-STATE IMAGE SENSOR - A method of manufacturing a solid-state image sensor having photoelectric conversion elements and one or more MOS transistors are formed on a semiconductor substrate is provided. The method includes forming a resist pattern having an opening and a shielding portion over the substrate; and implanting ions in the substrate through the opening. When the substrate is viewed from a direction, an isolation region that is positioned between accumulation regions adjacent to one another is exposed in the opening, and when viewed from a different direction, a channel region of the MOS transistors is exposed in the opening, and the isolation region is shielded by the shielding portion. Ions irradiated in the direction are implanted in the isolation region, and ions irradiated in the different direction are implanted in the channel region. | 2013-04-11 |
20130089946 | WAVELENGTH CONVERSION FILM HAVING PRESSURE SENSITIVE ADHESIVE LAYER TO ENHANCE SOLAR HARVESTING EFFICIENCY - Described herein are wavelength conversion films that are easy-to-apply to solar cells, solar panels, or photovoltaic devices using an adhesive layer. The wavelength conversion films include a wavelength conversion layer with a photostable chromophore and are useful for improving the solar harvesting efficiency of solar cells, solar panels, and photovoltaic devices. | 2013-04-11 |
20130089947 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Manufacturing a semiconductor device includes preparing a structure including a semiconductor substrate having a first region and a second region, a first insulating film arranged on the first region, a second insulating film arranged on the first insulating film, a third insulating film arranged on the second insulating film, a fourth insulating film arranged on the second region, a fifth insulating film arranged on the fourth insulating film, and a sixth insulating film arranged on the fifth insulating film, etching the second insulating film and the first insulating film under different etching conditions after etching the third insulating film, and continuously etching the fifth insulating film and the fourth insulating film under the same etching conditions after etching the sixth insulating film. | 2013-04-11 |
20130089948 | VAPOR TRANSPORT DEPOSITION METHOD AND SYSTEM FOR MATERIAL CO-DEPOSITION - An improved feeder system and method for vapor transport deposition that includes at least two vaporizers couple to a common distributor for vaporizing and co-depositing at least any two vaporizable materials as a material layer on a substrate. Composition of the material layer can be controlled by changing the flow of vapors from the respective vaporizers into the distributor to adjust the proportion of respective vapors in the combined vapor prior to deposition. Flow of the vapors from the respective vaporizers into the distributor may be controlled by adjusting the flow of carrier gas transporting the raw material into the vaporizer and/or by adjusting the vibration speed and/or amplitude of the powder feeders that process the raw material. | 2013-04-11 |
20130089949 | Method for Reducing Forming Voltage in Resistive Random Access Memory - Methods for producing RRAM resistive switching elements having reduced forming voltage include preventing formation of interfacial layers, and creating electronic defects in a dielectric film. Suppressing interfacial layers in an electrode reduces forming voltage. Electronic defects in a dielectric film foster formation of conductive pathways. | 2013-04-11 |
20130089950 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even in a thin film transistor with improved field effect mobility. In a thin film transistor using an oxide semiconductor layer, by forming a semiconductor layer having higher electrical conductivity and a smaller thickness than the oxide semiconductor layer between the oxide semiconductor layer and a gate insulating layer, field effect mobility of the thin film transistor can be improved, and increase in off current can be suppressed. | 2013-04-11 |
20130089951 | Wafer Level Packaging Using a Lead-Frame - Wafer level packaging using a lead-frame. When used to package two or more chips, a final product having QFN package-like finish. The final product will also have a performance rivaling or exceeding that of a corresponding monolithic chip because of the very close connection of the two or more chips and the ability to tailor the fabrication processing of each chip to only that required for the devices on that chip. The wafer level packaging can also be used to package monolithic chips, as well as chips having active devices on one chip and passive devices on a second chip. Various exemplary embodiments are disclosed. | 2013-04-11 |
20130089952 | Packaging Process Tools and Packaging Methods for Semiconductor Devices - Packaging process tools and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure including a frame. The frame includes a plurality of apertures adapted to retain a plurality of integrated circuit dies therein. The frame includes at least one hollow region. | 2013-04-11 |
20130089953 | Wafer Level Packaging Using a Lead-Frame - Wafer level packaging using a lead-frame. When used to package two or more chips, a final product having QFN package-like finish. The final product will also have a performance rivaling or exceeding that of a corresponding monolithic chip because of the very close connection of the two or more chips and the ability to tailor the fabrication processing of each chip to only that required for the devices on that chip. The wafer level packaging can also be used to package monolithic chips, as well as chips having active devices on one chip and passive devices on a second chip. Various exemplary embodiments are disclosed. | 2013-04-11 |
20130089954 | METHOD OF FABRICATING ELECTRONIC DEVICE HAVING FLEXIBLE DEVICE - There is provided a method of fabricating an electronic device having a flexible device, which is fabricated using a support substrate by Joule-heating induced film separation (JIFS). A method of fabricating an electronic device having a flexible device includes providing a support substrate, coating a conductive layer on one surface of the support substrate, forming a plastic substrate on the other surface of the support substrate, forming one or more thin-film transistors (TFTs) on the plastic substrate, forming an electronic device electrically connected to any one of the TFTs, and separating the plastic substrate from the conductive layer by generating Joule-heating through application of an electric field to the conductive layer. Accordingly, the flexible device can be separated from the support substrate without deformation of the support substrate and degradation of the electronic device. Since the separation time is short, it is easy to fabricate a large-area device, and the fabrication yield can be improved. | 2013-04-11 |
20130089955 | PROCESS FOR ENCAPSULATING A MICRO-DEVICE BY ATTACHING A CAP AND DEPOSITING GETTER THROUGH THE CAP - Process for encapsulating a micro-device in a cavity formed between one first and one second substrate, comprising at least the steps of:
| 2013-04-11 |
20130089956 | Patterning Contacts in Carbon Nanotube Devices - A method to fabricate a carbon nanotube (CNT)-based transistor includes providing a substrate having a CNT disposed over a surface; forming a protective electrically insulating layer over the CNT and forming a first multi-layer resist stack (MLRS) over the protective electrically insulating layer. The first MLRS includes a bottom layer, an intermediate layer and a top layer of resist. The method further includes patterning and selectively removing a portion of the first MLRS to define an opening for a gate stack while leaving the bottom layer; selectively removing a portion of the protective electrically insulating layer within the opening to expose a first portion of the CNT; forming the gate stack within the opening and upon the exposed first portion of the carbon nanotube, followed by formation of source and drain contacts also in accordance with the inventive method so as to expose second and third portions of the CNT. | 2013-04-11 |
20130089957 | FIN FIELD-EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING PROCESS THEREOF - A fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate. The high-k metal gate is formed on the substrate and the fin channel. A process of manufacturing the fin field-effect transistor structure includes the following steps. Firstly, a polysilicon pseudo gate structure is formed on the substrate and a surface of the fin channel. By using the polysilicon pseudo gate structure as a mask, a source/drain region is formed in the fin channel. After the polysilicon pseudo gate structure is removed, a high-k dielectric layer and a metal gate layer are successively formed. Afterwards, a planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced. | 2013-04-11 |
20130089958 | Finlike Structures and Methods of Making Same - Semiconductor materials, particularly III-V materials used to form, e.g., a finlike structure can suffer structural damage during chemical mechanical polishing steps. This damage can be reduced or eliminated by oxidizing the damaged surface of the material and then etching away the oxidized material. The etching step can be accomplished simultaneously with a step of etching back a patterned oxide layers, such as a shallow trench isolation layer. | 2013-04-11 |
20130089959 | Controlling the Shape of Source/Drain Regions in FinFETs - An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness. | 2013-04-11 |
20130089960 | MANUFACTURING METHOD FOR HIGH VOLTAGE TRANSISTOR - A manufacturing method for a high voltage transistor includes the following steps. A substrate is provided. A P-type epitaxial (P-epi) layer is provided above the substrate. An N-well is formed in the P-epi layer. A P-well is formed in the P-epi layer. Field oxide (FOX) layers are formed above the P-epi layer. A gate oxide (GOX) layer is formed between the FOX layers. P-type implants are doped into the P-well or N-type implants are doped into the N-well to adjust an electrical function of the high voltage transistor. | 2013-04-11 |
20130089961 | Methods of Forming Semiconductor Devices Including an Epitaxial Layer and Semiconductor Devices Formed Thereby - Methods of forming a semiconductor device are provided. The methods may include forming an epitaxial layer by growing a crystalline layer using a semiconductor source gas in a reaction chamber, and by etching the crystalline layer using an etching gas in the reaction chamber. | 2013-04-11 |
20130089962 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate is provided. A gate structure is formed on the substrate. A spacer is formed on the substrate beside the gate structure. The spacer includes a first spacer and a second spacer located on the external surface of the first spacer. A first etching process is performed to etch and form at least a recess in the substrate beside the spacer and entirely remove the second spacer. The etching rate of the first etching process to the first spacer is lower than the etching rate of the first etching process to the second spacer. An epitaxial layer is formed in the recess. | 2013-04-11 |
20130089963 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A drain of a first transistor is formed by performing ion implantation on a semiconductor substrate using a first member as a mask for a gate electrode of the first transistor. Further, ion implantation is performed on the gate electrode of the second transistor after thinning a second member. | 2013-04-11 |
20130089964 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A lower electrode includes a metal-containing oxide layer having a thickness of 2 nm or less on the surface layer. A metal-containing oxide layer is formed by oxidizing the surface of the lower electrode. A dielectric film includes a first phase appearing at room temperature in the bulk state and a second phase appearing at a higher temperature than that in the first phase in the bulk state. The second phase has a higher relative permittivity than that of the first phase. | 2013-04-11 |
20130089965 | RESISTIVE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Provided are resistive memory devices and methods of fabricating the same. The resistive memory devices and the methods are advantageous for high integration because they can provide a multilayer memory cell structure. Also, the parallel conductive lines of adjacent layers do not overlap each other in the vertical direction, thus reducing errors in program/erase operations. | 2013-04-11 |
20130089966 | Methods of Processing Units Comprising Crystalline Materials, and Methods of Forming Semiconductor-On-Insulator Constructions - Some embodiments include methods of processing a unit containing crystalline material. A damage region may be formed within the crystalline material, and a portion of the unit may be above the damage region. A chuck may be used to bend the unit and thereby induce cleavage along the damage region to form a structure from the portion of the unit above the damage region. Some embodiments include methods of forming semiconductor-on-insulator constructions. A unit may be formed to have dielectric material over monocrystalline semiconductor material. A damage region may be formed within the monocrystalline semiconductor material, and a portion of the monocrystalline semiconductor material may be between the damage region and the dielectric material. The unit may be incorporated into an assembly with a handle component, and a chuck may be used to contort the assembly and thereby induce cleavage along the damage region. | 2013-04-11 |
20130089967 | TEMPORARY ADHESIVE COMPOSITION AND METHOD FOR MANUFACTURING THIN WAFER USING THE SAME - The present invention is a temporary adhesive composition comprising: (A) non-aromatic saturated hydrocarbon group-containing organopolysiloxane; (B) an antioxidant; and (C) an organic solvent, wherein the component (A) corresponds to 100 parts by mass, the component (B) corresponds to 0.5 to 5 parts by mass, and the component (C) corresponds to 10 to 1000 parts by mass. There can be provided a temporary adhesive composition that has excellent thermal stability while maintaining solvent resistance and a method for manufacturing a thin wafer using this. | 2013-04-11 |
20130089968 | METHOD FOR FINISHING SILICON ON INSULATOR SUBSTRATES - A process for finishing an as transferred layer on a semiconductor-on-insulator structure or a semiconductor-on-glass (or other insulator substrate) structure is provided by removing the damaged surface portion of a semiconductor layer while a leaving a smooth, finished semiconductor film on the glass. The damaged surface layer is treated with an oxygen plasma to oxidize the damaged layer and convert the damaged layer into an oxide layer. The oxide layer is then stripped in a wet bath, such as hydrofluoric acid bath, thereby removing the damaged portion of the semiconductor layer. The damaged layer may be an ion implantation damaged layer resulting from a thin film transfer processes used to make the semiconductor-on-insulator structure or the semiconductor-on-glass structure. | 2013-04-11 |
20130089969 | Method for Slicing a Substrate Wafer - A method for slicing a monocrystalline semiconductor layer ( | 2013-04-11 |
20130089970 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To provide a method of manufacturing a semiconductor device including a step of attaching a surface protective tape onto the surface of a wafer which has completed the wafer process, a step of subjecting the back surface of the wafer to back grinding, and a step of attaching a peeling assist tape onto the surface protective tape while vacuum-adsorbing the back surface of the wafer to apply a tension to the assist tape, thereby separating the surface protective tape from the wafer, wherein a vacuum suction system has a peripheral suction system for the peripheral part of the wafer and an internal suction system for the internal region of the wafer. | 2013-04-11 |
20130089971 | DEVICES INCLUDING, METHODS USING, AND COMPOSITIONS OF REFLOWABLE GETTERS - Methods for protecting circuit device materials, optoelectronic devices, and caps using a reflowable getter are described. The methods, devices and caps provide advantages because they enable modification of the shape and activity of the getter after sealing of the device. Some embodiments of the invention provide a solid composition comprising a reactive material and a phase changing material. The combination of the reactive material and phase changing material is placed in the cavity of an electronic device. After sealing the device by conventional means (epoxy seal for example), the device is subjected to thermal or electromagnetic energy so that the phase changing material becomes liquid, and consequently: exposes the reactive material to the atmosphere of the cavity, distributes the getter more equally within the cavity, and provides enhanced protection of sensitive parts of the device by flowing onto and covering these parts, with a thin layer of material. | 2013-04-11 |
20130089972 | METHOD FOR FORMING NANOCRYSTALLINE SILICON FILM - Provided is a method for forming a nanocrystalline silicon film that can be deposited on a substrate while maintaining a high degree of crystallinity at low temperatures. The method includes performing plasma treatment on a substrate, and forming a nanocrystalline silicon film by depositing the nanocrystalline silicon film on the substrate. | 2013-04-11 |
20130089973 | METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE - A method of manufacturing a nitride semiconductor device includes the step of forming a second nitride semiconductor layer having an inclined facet by metal-organic chemical vapor deposition, in which a molar flow ratio of a group V element gas to a group III element gas that are supplied to a growth chamber of a metal-organic chemical vapor deposition growth apparatus is set at 240 or less. | 2013-04-11 |
20130089974 | METHOD OF MANUFACTURING A NON-VOLATILE MEMORY DEVICE HAVING A VERTICAL STRUCTURE - A method of manufacturing a non-volatile memory device, wherein the method includes: alternately stacking interlayer sacrificial layers and interlayer insulating layers on a substrate; forming a plurality of first openings that pass through the interlayer sacrificial layers and the interlayer insulating layers to expose a first portion of the substrate; forming a semiconductor region on a side wall and a lower surface of each of the first openings; forming an embedded insulating layer in each of the first openings; forming a first conductive layer on the embedded insulating layer inside each of the first openings; forming a second opening exposing a second portion of the substrate and forming an impurity region on the second portion; forming a metal layer to cover the first conductive layer and the impurity region; and forming the metal layer into a metal silicide layer. | 2013-04-11 |
20130089975 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device having a MOS transistor, includes forming a gate electrode material layer on a first insulating film formed on a semiconductor substrate, forming an etching mask on the gate electrode material layer, forming a gate electrode by patterning the gate electrode material layer such that a protective film that protects at least a lower portion of a side face of the gate electrode and a portion of the first insulating film, which is adjacent to the side face, is formed while the gate electrode material layer is patterned, forming a second insulating film on the semiconductor substrate on which the gate electrode is formed, and forming an interlayer insulation film on the second insulating film. | 2013-04-11 |
20130089976 | FUSE STRUCTURE FOR HIGH INTEGRATED SEMICONDUCTOR DEVICE - The present invention provides a technology capable of improving an operation reliability of a semiconductor device. Particularly, a fuse material which constitutes the copper can be prevented from migrating being locked in the recesses or the grooves after a blowing process. A semiconductor device includes an insulating layer including a concave-convex-shaped upper part; and a fuse formed on the insulating layer. | 2013-04-11 |
20130089977 | METHOD FOR FORMING HIGH DENSITY PATTERNS - In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in an integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching. | 2013-04-11 |
20130089978 | INTEGRATED CIRCUIT USING FDSOI TECHNOLOGY, WITH WELL SHARING AND MEANS FOR BIASING OPPOSITELY DOPED GROUND PLANES PRESENT IN A SAME WELL - A manufacture includes an IC comprising a stacking of a semiconducting substrate, a buried insulating layer, and a semiconducting layer, a first electronic component formed in and/or on the semiconductor layer, a bias circuit to generate a first bias voltage, first and second via-type interconnections, to which the bias circuit applies a same bias voltage equal to the first bias voltage, a first insulation trench separating the first electronic component from the first and second interconnections, a first ground plane having a first type of doping, placed beneath the buried insulating layer plumb with the first electronic component, and extending beneath the first insulation trench and up into contact the first interconnection, and a first well having a second type of doping opposite that of the first type, plumb with the first ground plane, and extending beneath the first insulation trench and up into contact with the second interconnection. | 2013-04-11 |
20130089979 | SEMICONDUCTOR DEVICE HAVING A MULTILEVEL INTERCONNECT STRUCTURE AND METHOD FOR FABRICATING THE SAME - A multilevel interconnect structure in a semiconductor device and methods for fabricating the same are described. The multilevel interconnect structure in the semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere. | 2013-04-11 |
20130089980 | MOSFET INTEGRATED CIRCUIT HAVING DOPED CONDUCTIVE INTERCONNECTS AND METHODS FOR ITS MANUFACTURE - An integrated circuit device having doped conductive contacts, and methods for its fabrication, are provided. One such method involves depositing a dielectric layer on the surface of a silicon semiconductor substrate, and photolithographically patterning a plurality of contact trenches on the dielectric layer. A tantalum barrier is deposited in the trenches, followed by a copper seed layer. The trenches are then plated with copper, including an overburden. A layer of doping material is deposited atop the overburden, and diffused into the copper by a heat treatment process. The overburden is then removed through chemical mechanical planarization, resulting in usable conductive interconnects in the trenches. | 2013-04-11 |
20130089981 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The invention provides a method of manufacturing a semiconductor device, capable of forming, on a silicon layer, a nickel mono-silicide layer having a low resistance value and a desirable flatness. The method includes depositing a platinum-containing nickel layer that covers the silicon layer formed on the substrate, and that has crystallinity lower in a portion thereof close to the silicon layer than in a portion remote from the silicon layer, and forming a nickel mono-silicide layer at the interface between the silicon layer and the platinum-containing nickel layer by heating the substrate. | 2013-04-11 |
20130089982 | Method of Fabricating a Substrate Having Conductive Through Holes - A method of fabricating a substrate having a plurality of conductive through holes is disclosed. Release films are formed on opposite sides of a substrate, and a plurality of through holes penetrating the release films and the substrate are formed. A first metal layer is formed on the release films and the sidewall of each of the through holes prior to removing the release films and the first metal layer thereon. A second metal layer is formed on the first metal layer on the sidewalls of the through holes by electroless plating. Compared to the prior art, the method is simpler and cheaper to carry out while the conductive through holes and a surface circuit layer thereof are fabricated separately, thereby avoiding disadvantage of forming a circuit layer on the surface of the substrate too thick. | 2013-04-11 |
20130089983 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method includes forming a hole penetrating from one surface of a substrate to an electrode formed on the other surface of the substrate; forming an organic insulating film in the hole; removing at least a part of the organic insulating film formed in a bottom portion of the hole and not the organic insulating film formed on a side wall portion of the hole, to expose the electrode; cleaning an exposed surface of the electrode by using plasma of an inert gas; filling a conductive metal in the hole; removing at least a part of a surface of the organic insulating film by the reaction of oxygen plasma; and annealing the substrate in a dysoxidative atmosphere. | 2013-04-11 |
20130089984 | SIDEWALL IMAGE TRANSFER PROCESS WITH MULTIPLE CRITICAL DIMENSIONS - Embodiment of the present invention provides a method of forming a semiconductor device in a sidewall image transfer process with multiple critical dimensions. The method includes forming a multi-level dielectric layer over a plurality of mandrels, the multi-level dielectric layer having a plurality of regions covering the plurality of mandrels, the plurality of regions of the multi-level dielectric layer having different thicknesses; etching the plurality of regions of the multi-level dielectric layer into spacers by applying a directional etching process, the spacers being formed next to sidewalls of the plurality of mandrels and having different widths corresponding to the different thicknesses of the plurality of regions of the multi-level dielectric layer; removing the plurality of mandrels in-between the spacers; and transferring bottom images of the spacers into one or more layers underneath the spacers. | 2013-04-11 |
20130089985 | Enhancing Transistor Performance by Reducing Exposure to Oxygen Plasma in a Dual Stress Liner Approach - When forming strain-inducing dielectric material layers above transistors of different conductivity type, the patterning of at least one strain-inducing dielectric material may be accomplished on the basis of a process sequence in which a negative influence of a fluorine species in an oxygen plasma upon removing the resist mask is avoided or at least significantly suppressed. For example, a substantially oxygen-free plasma process may be applied for removing the resist material. | 2013-04-11 |
20130089986 | METHOD OF FORMING PATTERNS OF SEMICONDUCTOR DEVICE - A method of forming patterns of a semiconductor device may include forming a photoresist layer that includes a photo acid generator (PAG) and a photo base generator (PBG), generating an acid from the PAG in a first exposed portion of the photoresist layer by first-exposing the photoresist layer, and generating a base from the PBG in a second exposed portion of the photoresist layer by second-exposing a part of the first exposed portion and neutralizing the acid. The method may also include baking the photoresist layer after the first and second-exposing and deblocking the photoresist layer of the first exposed portion in which the acid is generated to form a deblocked photoresist layer, and forming a photoresist pattern by removing the deblocked photoresist layer by using a developer. | 2013-04-11 |
20130089987 | Method of barc removal in semiconductor device manufacturing - A method of removing a high molecular weight organic-comprising hard mask or BARC from a surface of a porous low k dielectric material, where a change in the dielectric constant of the low k dielectric material is less than about 5% after application of the method. The method comprises exposing the organic-comprising hard mask or BARC to nitric acid vapor which contains at least 68% by mass HNO | 2013-04-11 |
20130089988 | SELECTIVE ETCH OF SILICON BY WAY OF METASTABLE HYDROGEN TERMINATION - Methods of etching exposed silicon on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and a hydrogen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the exposed regions of silicon. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon while very slowly removing other exposed materials. The silicon selectivity results, in part, from a preponderance of hydrogen-containing precursor in the remote plasma which hydrogen terminates surfaces on the patterned heterogeneous structures. A much lower flow of the fluorine-containing precursor progressively substitutes fluorine for hydrogen on the hydrogen-terminated silicon thereby selectively removing silicon from exposed regions of silicon. The methods may be used to selectively remove silicon far faster than silicon oxide, silicon nitride and a variety of metal-containing materials. | 2013-04-11 |
20130089989 | WIRING HARNESS FOR TOWING A VEHICLE - A wiring substrate connects an electrical system of a towed vehicle to an electrical system of a towing vehicle and includes a wiring connector configured to connect to a connector from a wiring harness of the towed vehicle, a first set of connections to connect to tail light assemblies in the towed vehicles, a second set of connections to connect to vehicle signal connections in the towed vehicle, the first and second sets of connections electrically coupled on the wiring substrate by at least one diode, and a third set of connections to connect to the towing vehicle. A towing connector connects an electrical system of a towed vehicle to an electrical system of a towing vehicle and includes a first connector configured to provide connection to a native vehicle wiring harness of the towed vehicle, a second connector arranged to provide connection to wires of the towing vehicle, a wiring substrate having conductive traces connecting selected wires from the first connector to the second connector, and diodes residing on the wiring substrate in an electrical path form by the conductive traces. | 2013-04-11 |
20130089990 | Modular Interconnection System - A modular interconnection system in the form of a releasable modular interconnect is provided. The releasable modular interconnect may include a substrate with a plurality of releasable contact regions, where each releasable contact region may be positioned to overlay a respective terminal of a power cell. The releasable modular interconnect may also include at least one conductive interconnect member affixed to the substrate, where the conductive interconnect member includes at least a one conductive releasable contact disposed within a releasable contact region of the substrate. The conductive releasable contact may be positioned to form a releasable electrical connection with a terminal of a power cell when a force is applied to the first releasable contact region in a direction toward the terminal of the power cell. Additional and related methods and apparatuses are also provided. | 2013-04-11 |
20130089991 | RECEPTACLE CONNECTOR AND AN ELECTRICAL CONNECTOR USING THE SAME - A receptacle connector used as an electrical connector. The receptacle connector includes: a housing in which a receiving space is formed, a connection target being inserted in the receiving space; a plurality of contacts being arranged parallel to one another, having a plurality of signal line contacts and a plurality of ground contacts, and being placed with every two adjacent signal line contacts for transmitting signals interposed between two ground contacts; a supporting member made of an electrically-insulating synthetic resin material, and configured to integrally support and fix thereto the plurality of contacts; and a common contact made of a conductive resin material and configured to be provided with a certain gap from each of the plurality of ground contacts to electrically connect the plurality of ground contacts. The plurality of contacts integrated together by the supporting member are received in the receiving space. | 2013-04-11 |
20130089992 | STRUCTURE FOR STACKING PRINTED BOARD ASSEMBLIES IN ELECTRONIC DEVICE - A structure for stacking Printed Board Assemblies (PBAs) in an electronic device is provided. The structure for stacking PBAs in an electronic device includes a clip mounted on a main Printed Circuit Board (PCB), a sub-PCB including a ground portion, a sub-PBA including the sub-PCB, and a clip header mounted on a lower part of the sub-PBA, wherein the clip header is inserted into the clip. Therefore, electronic components mounted on a main PCB can be shielded from outer electromagnetic waves while reducing material costs without using a shield can, and a sub-PBA can be stacked on the main PBA. | 2013-04-11 |
20130089993 | ELECTRICAL CONNECTOR WITH INTERFACE GROUNDING FEATURE - An electrical connector that includes a connector body having a conductive surface configured to oppose an engagement side of a mating connector. The electrical connector also includes electrical terminals that are held by the connector body and located in an array along the conductive surface. Adjacent terminals are separated by gaps that collectively form an interwoven reception region along the conductive surface between the electrical terminals. The electrical connector also includes ground contacts that are coupled to the conductive surface and are located in corresponding gaps. The ground contacts include flex portions that are configured to be compressed between the conductive surface and the engagement side of the mating connector when the mating connector is coupled to the electrical connector during a mating operation. The ground contacts are configured to electrically couple the conductive surface and the mating connector. | 2013-04-11 |
20130089994 | SPLIT ELECTRICAL GROUNDING BUSHING WITH CONTINUOUS INSULATION - A split electrical grounding bushing having adjacent bushing portions with insulating bushing portions having guard tabs covering a gap formed between the insulating bushing portions creating a continuous insulating ring. The bushing portions are connected by a hinge permitting the bushing to be placed over electrical conductors or wires after being installed. Gaps in the insulating bushing portion are covered by attached guard tabs improving the safety of a split electrical bushing. The split electrical bushing is placed on a distal end of an electrical conduit. The split bushing may be an electrical grounding bushing providing an electrical ground connection. | 2013-04-11 |
20130089995 | LATCHING CONNECTOR WITH REMOTE RELEASE - In one aspect the present disclosure provides a latching connector. The latching connector comprises a housing that is configured to engage with a mating connector along a coupling axis. The housing includes a lever connected to the housing. The lever is configured to selectively disengage the latching connector from the mating connector. The housing further includes an extending member connected to the lever. | 2013-04-11 |
20130089996 | POWER TERMINAL CONNECTOR AND SYSTEM - A power terminal connector includes a multi-layered buss bar that has a first mounting portion, a second mounting portion and a flexible section between the first and second mounting portions. The flexible section has multiple layers of metal sheets in a stacked configuration. A first terminal assembly is coupled to the first mounting portion and a second terminal assembly is coupled to the second mounting portion. The first and second terminal assemblies are coupled to corresponding pins of corresponding power terminals. The multi-layered buss bar is configured to electrically interconnect the power terminals coupled to the first and second terminal assemblies. | 2013-04-11 |
20130089997 | POWER CABLE CONNECTOR - A power cable connector includes a housing having a mating end and a cable end. The housing has a chamber extending between the mating end and the cable end. The housing has an engagement feature configured to engage a socket connector extending from a substrate. A flat cable is received in the chamber. The flat cable extends from the cable end. The flat cable has a mating portion extending from the mating end. The mating portion is configured to be received in the socket connector such that the flat cable directly engages a power terminal of the socket connector. | 2013-04-11 |
20130089998 | WIRELESS INTERNET DEVICE - Embodiments of the present invention disclose a wireless Internet device. The wireless Internet device includes a device body ( | 2013-04-11 |
20130089999 | Locking Apparatus for Electric Vehicle Charging Connector - A security apparatus for preventing unauthorized disengagement of a charging connector from a charge port of an electric vehicle, for example during the battery charging process. A lock member is disposed on the electric vehicle and is movable between a locked position wherein it inhibits disengagement of the charging connector from the charge port and an unlocked position wherein it allows disengagement of the connector from the port. A locking actuator located adjacent to the charge port is manually actuatable to move the lock member to the locked position. An unlock actuator disposed inside a vehicle cabin is manually actuatable to move the lock member to the unlocked position. This ensures that only a person with access to the interior of the vehicle can unlock and disengage the charging connector from the vehicle. | 2013-04-11 |
20130090000 | POWER TERMINAL CONNECTOR AND SYSTEM - A power terminal connector having a terminal body that has a socket configured to receive, and be electrically connected to, a pin of a power terminal. A spring clip is coupled to the terminal body. The spring clip is movable between a locking position and a clearance position. The spring clip is configured to engage the pin of the power terminal in the locking position to secure the power terminal connector to the power terminal. The spring clip is configured to be disengaged from the pin of the power terminal in the clearance position. A cap is coupled to the terminal body. The cap is coupled to the spring clip to move the spring clip between the locking position and the clearance position as the cap is actuated. | 2013-04-11 |
20130090001 | CONNECTOR GUIDE MEMBER AND ELECTRICAL CONNECTOR DEVICE HAVING THE SAME - A connector guide member is provided for guiding a connector attached on a circuit board to a mating connector attached on another circuit board when the connector is connected to the mating connector. The connector guide member includes a positioning member that sets a position of the connector relative to the mating connector; an engaging member that locks to the connector while the positioning member positions the connector, and a guiding member that guides a guided portion provided on the mating connector. | 2013-04-11 |
20130090002 | Connecting Device for a Magnetic System of an Imaging System - A connecting device for a magnetic system of an imaging system includes a holding element for connection of the connecting device to a power supply connection of the magnetic system, and a connecting element for connection of the connecting device to a power supply cable for operation of the magnetic system. The connecting device also includes an oscillation damping device having a spring element. The oscillation damping device is operable to dampen oscillations of the magnetic system that act on the connecting device by way of the holding element, with respect to the connecting element. | 2013-04-11 |
20130090003 | PLUG CONNECTION HAVING INCREASED VIBRATION RESISTANCE - A plug connection between at least one cable connector and a terminal housing includes an electrical plug connection having at least one socket on the terminal housing for inserting the cable connector, a non-electrical plug connection being provided between the at least one cable connector and the terminal housing in addition to the electrical plug connection. | 2013-04-11 |
20130090004 | Universal ground adapter for marine cables - An electrical conduit ground device is provided for electrically and environmentally shielding an electric cable. The device includes a conduit having a receiving end through which the cable passes axially; an internal seal that inserts into the receiving end; a gland boss that inserts into the receiving end; an external seal that inserts into the boss and extends axially outward from the receiving end; and a grounding assembly disposed between the internal and external seals. The assembly includes an adapter for providing electrical grounding contact between the cable and the swage tube; a space-retainer for structurally supporting the adapter; and a washer for axially separating the internal and external seals. The adapter is provided for electrically connecting an interior surface of a conduit and an external surface of a cable. The adapter includes an electrically conductive and mechanically flexible sheet having first and second edges that can face each other, the sheet being configured to form an annulus that mechanically contacts the external surface of the cable and a periphery that mechanically contacts the inner surface of the conduit. | 2013-04-11 |
20130090005 | SUPPORT STRUCTURE FOR TELECOMMUNICATION JACKS - In the field of telecommunication and data transmission, a jack support structure for fixing a plurality of modular telecommunications jacks on a patch panel. The jack support structure has at least two parallel rows of jack cavities, and fixing means for fixing the jack support structure on a patch panel, characterized by the fixing means being positioned only between two adjacent rows. | 2013-04-11 |
20130090006 | Compact adapter to be used as a battery substitute - A compact adapter for providing electrical power to a battery-operated device. The power is derived when the adapter is connected to a common and widely-used AC-DC transformer. The highly portable adapter universally replaces the need for batteries and can be quickly installed in the battery compartment where a battery would otherwise be placed. | 2013-04-11 |
20130090007 | TERMINAL BOX FOR SOLAR CELL MODULE - A box body ( | 2013-04-11 |
20130090008 | COAXIAL CABLE CONNECTOR STRUCTURE - A coaxial cable connector structure including a sleeve and an annular nut on the front end of the sleeve is disclosed, wherein an inner tube is disposed inside the sleeve for connecting the coaxial cable, and a spring is disposed on the bottom of the annular nut for the end surface of the connection base towards the annular nut to contact the spring and electrically connect the inner tube when the connection base is screwed into the annular nut, so that the coaxial cable connector structure can transmit signals when it is not completely screwed onto the connection base, and provide the effect of vibration suppression from the compressed spring having its two ends abutted against the bottom of the annular nut and the end surface of the connection base by the elastic restoring force when the connection base is completely screwed onto the connection base. | 2013-04-11 |
20130090009 | POWER CONNECTOR SYSTEM - A touch safe right angle power connector includes a header assembly that includes a conductive pin, an inner shroud that surrounds the pin, and an outer shroud that surrounds the inner shroud. The inner shroud has slots therethrough. The power connector includes a power terminal connector having a plug housing that has a cavity and an insert assembly that is received in the cavity. The insert assembly has a terminal body configured to be terminated to an end of a conductor of a power cable and is electrically connected to the pin of the header assembly. The insert assembly has a dielectric insert that holds the terminal body. The insert assembly has a shield that surrounds the dielectric insert and provides shielding for the terminal body. The plug housing has optional ribs which are received in corresponding slots to orient the power terminal with respect to the header assembly. | 2013-04-11 |
20130090010 | Surge Protector Components Having a Plurality of Spark Gap Members Between a Central Conductor and an Outer Housing - A coaxial connector includes a surge protection component including a plurality of elongated members, a body portion that is configured to receive the surge protection component such that the elongated members extend along an outer surface thereof, and a center conductor disposed inside the body portion and spaced apart from the surge protection component so as to create a gap therebetween | 2013-04-11 |
20130090011 | Backward Compatible Connectivity for High Data Rate Applications - The present invention provides a communication jack for connecting to one of a first plug and a second plug. The jack includes a housing, plug interface contacts, and coupling circuitry. The plug interface contacts are at least partially within said housing and include a plurality of contact pairs having at least a first contact pair and a second contact pair. The coupling circuitry is configured for engaging said first contact pair and said second contact pair when said first plug is inserted into said housing. The coupling circuitry is configured for disengaging from said first contact pair and said second contact pair when said second plug is inserted into said housing. | 2013-04-11 |
20130090012 | CONNECTOR HAVING OPTIMIZED TIP - A connector having an optimized tip is disclosed. The tip may be optimized to facilitate insulating the connector and/or providing a low friction surface to facilitate insertion. The tip may be optimized with a non-conducting and/or low friction end cap configured to be positioned over the tip. | 2013-04-11 |
20130090013 | ELECTRICAL CONNECTOR FOR LOW PROFILE APPLICATION - An electrical connector for electrically connecting a central processing unit (CPU) to a printed circuit board (PCB) comprises an insulating housing having a plurality of passageways extending from a top surface to a bottom surface and a plurality of terminals received in the corresponding passageways. Each terminal includes a horizontal base portion with a solder ball attached thereto, a pair of upper legs extending upwardly from one end of the base portion and a pair of lower legs extending downwardly from the other end of the base portion. The upper legs abut against the top surface of the insulating housing and the lower legs abut against the bottom surface of the insulating housing for retaining the terminals in the insulating housing. | 2013-04-11 |
20130090014 | CIRCUIT BOARD FOR AN ELECTRICAL CONNECTOR - A circuit board includes a substrate having upper and lower sides, and first and second conductive vias extending between the upper and lower sides. The first and second conductive vias include circular outer profiles. The circuit board also includes a differential pair of conductive traces, which includes a first conductive trace having first upper and lower segments disposed on the upper and lower sides, respectively. The first upper and lower segments are electrically connected together through the first conductive via. The first upper segment is curved around the second conductive via such that the first upper segment follows the circular outer profile of the second conductive via. The differential pair of conductive traces also includes a second conductive trace having second upper and lower segments disposed on the upper and lower sides, respectively. The second upper and lower segments are electrically connected together through the second conductive via. The first upper segment crosses over the second lower segment. The second lower segment is curved around the first conductive via such that the second lower segment follows the circular outer profile of the first conductive via. | 2013-04-11 |
20130090015 | Double Male Adaptor - A male adaptor device is disclosed that is designed for connecting a female receptacle to a wall receptacle. The male adaptor device comprises a housing unit that encases a two-pronged male plug and a three-pronged male plug, wherein the two-pronged male plug and the three-pronged male plug are in electrical communication with one another. The two-pronged male plug is typically secured to and recessed in a first end of the housing unit. Further, the three-pronged male plug is typically secured to a second end of the housing unit. The male adaptor device also comprises a cap utilized to cover the three-pronged male plug in the second end of the housing unit. The male adaptor device further comprises an on/off power switch and a female receptacle positioned on an outside surface of the housing unit. | 2013-04-11 |
20130090016 | CARD EDGE CONNECTOR - A card edge connector includes an insulating body having a base body, multiple first terminals, and multiple second terminals. A first body and a second body extend from a front end of the base body sequentially from bottom to top. Multiple recessed first receiving slots are disposed at the first body. A recessed first retaining slot is disposed at the first body and a side wall of each of the first receiving slots. Each of the first terminals has a first retaining portion retained in the first retaining slot with a first connecting portion bent and extends laterally thereof. A first elastic section extends forwards from the first connecting portion and located in the first receiving slot. A first contact arm extends forwards from the rear end of the first elastic section and has a first contact portion which enters the first insertion space. | 2013-04-11 |
20130090017 | CONNECTOR CONSTRUCTIONS FOR ELECTRONIC APPLICATIONS - An electronic wiping torsional connector for use in connecting to mating contacts on an insulating base. The connector includes a plurality of contacts | 2013-04-11 |
20130090018 | CABLE CONNECTOR - Disclosed is a cable connector. The cable connector includes a female base coupled to a circuit board; a male base which is coupled to the female base has channels for inserting cables; and conductive terminals respectively coupled to the circuit board and the cables. The female base includes a bottom plate, two side walls, and a rear wall. A first engaging part and a second engaging part are respectively disposed at a front and a rear of the side walls. A first coordinating protrusion and a second coordinating protrusion are disposed at the male base respectively corresponding to the first engaging part and the second engaging part. The first engaging parts and the second engaging parts are respectively engaged with the first coordinating protrusions and the second coordinating protrusions. The cable connector of the present invention has a stable structure and a steady electrical connection. | 2013-04-11 |
20130090019 | Electrical Connector - An electrical connector includes a first connector which includes a first insulating body and first terminals disposed in the first insulating body with one end thereof being exposed outside for connecting with one external connector, a second connector which includes a second insulating body and second terminals disposed in the second insulating body with one end thereof being exposed outside for connecting with another different external connector, and a shell enclosing the first connector and the second connector and looped from a metal plate with a matching mouth being freely opened for the convenience of the insertion of the external connectors to connect with the first connector or the second connector, wherein the first connector and the second connector are connected together by molding the first insulating body and the second insulating body integrally in a single mold. | 2013-04-11 |
20130090020 | ELECTRONIC CONNECTOR WITH DOUBLE INSERTING INTERFACES BACKGROUND - An electronic connector having double inserting interfaces includes a housing, two plugs, a connecting unit and a linking element. Each of the plugs has several terminals to form an inserting interface. The linking element is interconnected between the two plugs. The connecting unit includes cross wires comprising several first conductive wire portions and several second conductive wire portions, which respectively spatially correspond to the respective terminals of each of the plugs. When the electronic connector is inserted into a connector socket, one of the plugs protrudes beyond another and enters the connector socket, thereby electrically connects with the contact terminals of the connector socket via its inserting interface and also electrically connects with the another plug, while another plug electrically connects with the corresponding conductive wire portion of the connecting unit. Thus, the orientation for insertion does not need to be considered. | 2013-04-11 |
20130090021 | CONNECTION MEMBER, SOCKET MODULE, SOCKET AND METHOD FOR MANUFACTURING CONNECTION MEMBER - A connection member to be inserted into a through-hole of a socket module that is electrically connected between an electronic component and a substrate, the connection member includes: a first end portion that is connected to the electronic component; a second end portion that is connected to the substrate; a plurality of upper flexure portions that correspond to projections of a waveform arranged near the electronic component; and a plurality of lower flexure portions that correspond to projections of the waveform arranged near the substrate; wherein the connection member is a single conductor member with elasticity and is formed in the shape of the waveform. | 2013-04-11 |
20130090022 | LEAD FRAME, METHOD OF MANUFACTURING A CONTACT GROUP, AND CONNECTOR - By using a lead frame as an intermediate member, a contact group of a connector is manufactured. The lead frame includes a plurality of first leads arranged on a plane and spaced from one another, a plurality of pairs of second leads, each pair being arranged on the plane between the first leads, and a connecting portion connecting the first and the second leads on one end side. The second leads have a pitch which is greater on the other end side than that on the one end side to make the second leads approach the first leads on the other end side, respectively. The lead frame further includes bridge portions connecting approached ones of the first and the second leads to each other at a portion where an interval between the first and the second leads is reduced. | 2013-04-11 |
20130090023 | BATTERY CONTACT FOR AN ELECTRONIC DEVICE - According to embodiments of the present invention, an electronic device includes a first electrical conductor located in a shell. The first electrical conductor has a vertical portion and a horizontal portion at the bottom of the vertical portion. A cap has a second electrical conductor and can be mated with the shell. After mating, the second electrical conductor contacts the horizontal portion of the first electrical conductor. | 2013-04-11 |