15th week of 2012 patent applcation highlights part 35 |
Patent application number | Title | Published |
20120088301 | FACTOR TAKING PART IN TRANSCRIPTION CONTROL - HDART binds with HDAC (histone deacetylase) and function as a repressor. HDART directly binds with Skip functioning as a transcription co-activator of a nuclear receptor to repress the transcription of the nuclear receptor. Moreover, HDART is one of transcription co-repressors of nuclear receptor, and binds with HDAC thereby enabling intense repression of transcription through the histone deacetylization of HDAC. On the other hand, a dominant negative peptide of HDART can be obtained, and it has been confirmed that this peptide activates transcription contrary to the HDART protein of the full length. Especially, the transcription activity of retinoic acid receptor with this peptide has an activity exceeding all-trans retinoic acid (ATRA). | 2012-04-12 |
20120088302 | Cell Culture - A method for determining the effect of a plurality of culture conditions on a cell, comprising the steps of a) providing a first set of groups of cell units each comprising one or more cells, and exposing said groups to desired culture conditions; (b) pooling two or more of said groups to form at least one second pool; (c) subdividing the second pool to create a further set of groups of cell units; (d) exposing said further groups to desired culture conditions; (e) optionally, repeating steps (b)-(d) iteratively as required; and (f) optionally assessing the effect on a given cell unit of the culture conditions to which it has been exposed. | 2012-04-12 |
20120088303 | PEPTIDE FRACTIONS PROMOTING GROWTH AND SYNTHESIS OF DESIRED PRODUCT(S) INTO CELL AND/OR TISSUE CULTURE - The invention relates to preparing and/or supplementing a cell or tissue culture medium. In particular, said invention relates to a serum-free and/or protein-free cell culture medium comprising peptide fractions isolated from rapseeds, in particular rapseeds cakes. A method for the production of a cell culture comprising said peptide fractions and for the use thereof is also disclosed. | 2012-04-12 |
20120088304 | METHODS OF GENERATING CELLS EXHIBITING PHENOTYPIC PLASTICITY - The present invention relates to cellular differentiation and, in particular to hybrid cells that exhibit phenotypic plasticity and methods for producing these cells. The invention also relates to methods for generating specific cells of a desired phenotype. The invention still further relates to methods of producing hybrid cells with a capacity to de-differentiate into an earlier progenitor state. The invention further contemplates the use of hybrid cells in a range of applications, for example tissue generation. | 2012-04-12 |
20120088305 | MASS SPECTROMETRIC DETERMINATION OF EICOSAPENTAENOIC ACID AND DOCOSAHEXAENOIC ACID - The invention relates to the detection of DHA and EPA. In a particular aspect, the invention relates to methods for detecting DHA and EPA by mass spectrometry. | 2012-04-12 |
20120088306 | Method Of Assaying Noble Metals - Provided is a method of assaying noble metals in a mineral and/or ceramic matrix in the content range from 0.03 to 500 mg/kg. The method comprises dry thermal treatment of a homogenized sample in a reducing atmosphere, extraction in an oxidizing medium, and atomic spectrometric quantification of the noble metals by means of ICP-QMS. | 2012-04-12 |
20120088307 | Methods and Compositions for Analyzing Proteins - Methods, compositions and kits are disclosed for determining one or more target polypeptides in a sample where the target polypeptides have undergone a post-translational modification. | 2012-04-12 |
20120088308 | Detection Apparatus for Biological Materials and Methods of Making and Using the Same - Method that includes providing plurality of test sites each having first and second layers respectively including inorganic first and second surface sites forming parts of interior of a well, the surface sites having positions and thicknesses being configured for locating thereon portion of unidentified amino acid-containing molecules; exposing each of a first plurality of the test sites to a fluid containing a different one of plurality of pre-identified amino acid-containing molecules and determining bonding signatures onto each of first plurality of test sites; exposing each of second plurality of test sites to another fluid containing unidentified amino acid-containing molecule and determining bonding signatures onto second plurality of test sites; and comparing bonding signatures to determine or exclude identity of unidentified amino acid-containing molecule. | 2012-04-12 |
20120088309 | SYSTEMS AND METHODS FOR SAMPLE COLLECTION - A tube assembly, system and method for biological sample collection. In one embodiment, the tube assembly of the present disclosure includes a first tube, a second tube, a mechanism for securing the first and second tubes. The securing mechanism orients the first ends of the first and second tubes in a manner such that the first end of the second tube extends beyond the first end of the first tube to create an interstitial space between the outer diameter of the first tube and the inner diameter of the second tube, | 2012-04-12 |
20120088310 | DEVICE FOR CUTTING A SAMPLE CARRIER - A device for receiving a sample carrier is provided. The device includes an opening for receiving part of the sample carrier and a cutter for removing a part of the sample carrier. The cutter is coupled to a lid, which is movable to allow the cutter to make an incision in the sample carrier and, at the same time, to close at least part of the opening left open after receipt of the sample carrier. The disclosure further relates to a system comprising such a device and a method for operating such a device. | 2012-04-12 |
20120088311 | Immuno-Detection of a Cancerous State in a Subject - The present invention is based on the finding that antibodies raised against a fragment of PAR1-released peptide may be used to detect in a bodily fluid sample from a subject a marker associated with cancer state, if said subject has cancer. Thus, the present invention provides the methods and packages for conducting one or more of the following: determining a cancerous state in a subject, the method comprises determining binding of an antibody raised against a protease-activated receptor 1 (PAR1) released peptide or a fragment derived therefrom to a marker within a fluid sample obtained from said subject, wherein binding of said antibody to said marker being indicative of a cancerous state; determining severity of a cancerous state in a subject comprising determining level of binding of an antibody raised against PAR1 released peptide or a fragment derived therefrom to a marker within a fluid sample obtained from said subject, and comparing the level of binding with the level of prior determined standards that correlate level of antibody binding to PAR1 released peptide with severity of cancerous state; and determining the effectiveness of a therapeutic treatment of a subject with an anti-cancer agent to the subject comprising determining the level of binding of an antibody raised against PAR1 released peptide or a fragment derived therefrom to a marker within a fluid sample obtained from said subject in two or more successive time points, one or more time points are during the therapeutic treatment, wherein a difference in the level being indicative of effectiveness of therapeutic treatment. | 2012-04-12 |
20120088312 | VINCRISTINE IMMUNOASSAY - Novel conjugates and immunogens derived from vincristine and antibodies generated by these immunogens are useful in immunoassays for the quantification and monitoring of vincristine in biological fluids. | 2012-04-12 |
20120088313 | METHOD FOR DETECTING SUBSTANCE IN BIOLOGICAL SAMPLE - The present invention provides a method for detecting a substance in a biological sample, a carrier for using in the method, and a kit. The method of the present invention includes 1) providing a carrier on which a biotin-binding protein is bound and providing a biotinylated protein by biotinylating a protein that specifically binds to a substance to be detected; 2) binding the biotinylated protein to the carrier provided in step 1) to produce a biotinylated protein-bound carrier; 3) mixing (a) a biological sample, and (b-i) a cell homogenate extract prepared from cells of the same species as that of the host cells used for expressing, for example, the biotin-binding protein in step 1), and a biotin-binding protein, or (b-ii) a cell homogenate extract prepared from cells of the same species as that of the host cells used for expressing, for example, the biotin-binding protein in step 1) and genetically engineered to express a biotin-binding protein, and adding the mixture to the biotinylated protein-bound carrier produced in step 2); and 4) detecting the substance specifically bound to the biotinylated protein. | 2012-04-12 |
20120088314 | ASSAY FOR MONITORING ACTIVITY OF FRIZZLED RECEPTORS - The present invention relates to cell free assays for measuring receptor activity, especially for measuring a constitutive or a non-constitutive activity of frizzled receptors and uses thereof. The present invention further concerns a method for measuring a constitutive or non-constitutive activity of a frizzled receptor and a method for obtaining an active frizzled receptor ligand. | 2012-04-12 |
20120088315 | DEVICE HAVING SELF-ASSEMBLED-MONOLAYER - A device for bio-sensing applications is disclosed, comprising a substrate such as a semiconductor chip having Cu electrodes thereon, and a self assembled monolayer bonded to at least one of the Cu electrodes, wherein molecules of the self-assembled monolayer comprise a head group which bonds to Cu, a carbon-comprising chain comprising a chain of at least 12 C atoms, and a terminal group which is hydrophilic and for binding a bio-receptor. The terminal group is hydrophilic to allow binding to the bio-receptor, and inclusion of the carbon-comprising chain, limits or avoids corrosion of the copper. Also disclosed is a method of providing such a device, activating the terminal group and coupling a bio-receptor to the activated terminal group. Disclosure further extends to use of such a device for bio-sensing applications. | 2012-04-12 |
20120088316 | SYSTEM AND METHOD FOR WAFER BACK-GRINDING CONTROL - In a system or method for controlling wafer back-grinding, a chuck table has a surface for supporting a semiconductor wafer during a back-grinding process, one or more holes in the surface, and one or more sensors disposed in the one or more holes for monitoring a parameter during back-grinding. A computer-implemented process control tool is coupled to receive one or mote outputs from the one or more sensors and control the back-grinding process based on the received one or more outputs. | 2012-04-12 |
20120088317 | PROCESSING METHOD OF SILICON SUBSTRATE AND PROCESS FOR PRODUCING LIQUID EJECTION HEAD - A processing method of a silicon substrate, including forming on a back surface of a silicon substrate an etching mask layer having an opening portion, measuring a thickness of the silicon substrate, irradiating the opening portion in the etching mask layer with laser from the back surface of the silicon substrate to form in the silicon substrate a modified layer with a thickness that is varied according to the measured thickness of the silicon substrate, carrying out anisotropic etching with regard to the silicon substrate having the modified layer formed therein to form in the back surface a depressed portion which does not pass through the silicon substrate and which has a bottom surface in the silicon substrate, and carrying out dry etching in the depressed portion to form a through-hole passing from the bottom surface of the depressed portion to a front surface of the silicon substrate. | 2012-04-12 |
20120088318 | Method for Fabricating a Vertical Light-Emitting Diode with High Brightness - A method for fabricating a vertical light-emitting diode comprises forming a stack including a plurality of epitaxial layers on a patterned first substrate, placing a second substrate on the stack, removing the first substrate to expose the first surface, planarizing a first surface of the stack that was in contact with the patterned first substrate and has a pattern corresponding to a pattern provided on the first substrate to form a planarized second surface, and forming a first electrode in contact with a side of the second substrate that is opposite to the stack, and a second electrode in contact with the second surface of the stack. A roughening step can be performed to form uneven surface portions on a region of the second surface for improving light emission through the second surface of the stack. | 2012-04-12 |
20120088319 | Light source with hybrid coating, device including light source with hybrid coating, and/or methods of making the same - Certain example embodiments of this invention relate to techniques for improving the performance of Lambertian and non-Lambertian light sources. In certain example embodiments, this is accomplished by (1) providing an organic-inorganic hybrid material on LEDs (which in certain example embodiments may be a high index of refraction material), (2) enhancing the light scattering ability of the LEDs (e.g., by fractal embossing, patterning, or the like, and/or by providing randomly dispersed elements thereon), and/or (3) improving performance through advanced cooling techniques. In certain example instances, performance enhancements may include, for example, better color production (e.g., in terms of a high CRI), better light production (e.g., in terms of lumens and non-Lambertian lighting), higher internal and/or external efficiency, etc. | 2012-04-12 |
20120088320 | Method of forming polymer-dispersed liquid crystal film including dichroic dye - In a method of forming a polymer-dispersed liquid crystal (PDLC) film, the presence of dichroic dye in a polymer may be prevented or reduced by diffusing dichroic dye into a PDLC layer, and a PDLC display device having improved visibility may be formed. | 2012-04-12 |
20120088321 | Efficient LED Array - An efficient LED array. In an aspect, an LED apparatus includes a metal substrate having a reflective surface, and LED chips mounted directly to the reflective surface to allow for thermal dissipation, and wherein at least a portion of the LED chips are spaced apart from each other to allow light to reflect from a portion of the reflective surface that is located between the portion of the LED chips. In another aspect, a method includes configuring a metal substrate to have a reflective surface, and mounting a plurality of LED chips directly to the reflective surface of the metal substrate to allow for thermal dissipation, and wherein at least a portion of the LED chips are spaced apart from each other to allow light to reflect from a portion of the reflective surface that is located between the portion of the LED chips. | 2012-04-12 |
20120088322 | DICING-FREE LED FABRICATION - Provided is a method of fabricating a light-emitting diode (LED) device. The method includes providing a substrate having opposite first and second sides. A semiconductor layer is formed on the first side of the substrate. The method includes forming a photoresist layer over the semiconductor layer. The method includes patterning the photoresist layer into a plurality of photoresist components. The photoresist components are separated by openings. The method includes filling the openings with a plurality of thermally conductive components. The method includes separating the semiconductor layer into a plurality of dies using a radiation process that is performed to the substrate from the second side. Each of the first regions of the substrate is aligned with one of the conductive components. | 2012-04-12 |
20120088323 | METHOD FOR FORMING LIGHT GUIDE LAYER IN SEMICONDUCTOR SUBSTRATE - A method for forming a light guide layer with improved transmission reliability in a semiconductor substrate, the method including forming a trench in the semiconductor substrate, forming a cladding layer and a preliminary light guide layer in the trench such that only one of opposite side end portions of the preliminary light guide layer is in contact with an inner sidewall of the trench, and performing a thermal treatment on the substrate to change the preliminary light guide layer into the light guide layer. | 2012-04-12 |
20120088324 | Method for Manufacturing Evaporation Donor Substrate and Light-Emitting Device - An evaporation donor substrate which enables only a desired evaporation material to be evaporated at the time of deposition by an evaporation method, and capable of reduction in manufacturing cost by increase in use efficiency of the evaporation material and deposition with high uniformity. An evaporation donor substrate capable of controlling laser light so that a desired position of an evaporation donor substrate is irradiated with the laser light in accordance with the wavelength of the emitted laser light at the time of evaporation. Specifically, an evaporation donor substrate in which a region which reflects laser light and a region which absorbs laser light at the time of irradiation with laser light having a wavelength of greater than or equal to 400 nm and less than or equal to 600 nm at the time of evaporation are formed. | 2012-04-12 |
20120088325 | MANUFACTURING METHOD OF DISPLAY DEVICE - Disclosed is a manufacturing method of a liquid crystal display device where first color filters, second color filters and third color filters which are formed adjacent to each other are provided, the first color filter and the second color filter are patterned in such a manner that one edge portion of the second color filter overlaps an edge portion of the first color filter, and the second color filter and the third color filter are patterned in such a manner that an edge portion of the third color filter overlaps the other edge portion of the second color filter wherein in an exposure step for patterning the second color filter, an exposure quantity in a region corresponding to one edge portion and an exposure quantity in a region corresponding to the other edge portion differ from each other. | 2012-04-12 |
20120088326 | GROUP-III NITRIDE SEMICONDUCTOR LASER DEVICE, AND METHOD OF FABRICATING GROUP-III NITRIDE SEMICONDUCTOR LASER DEVICE - A method of fabricating a group-III nitride semiconductor laser device includes: preparing a substrate of a hexagonal group-III nitride semiconductor, where the substrate has a semipolar primary surface; forming a substrate product having a laser structure, an anode electrode and a cathode electrode, where the laser structure includes the substrate and a semiconductor region, and where the semiconductor region is formed on the semipolar primary surface; scribing a first surface of the substrate product in part in a direction of the a-axis of the hexagonal group-III nitride semiconductor; and carrying out breakup of the substrate product by press against a second surface of the substrate product, to form another substrate product and a laser bar. | 2012-04-12 |
20120088327 | Methods of Soldering to High Efficiency Thin Film Solar Panels - Methods for forming a thin film solar cell are provided. In one aspect, a thin film solar cell is formed by providing a back contact comprising a reflective material and an interface metal, applying a solder paste slurry that include a paste flux and metal particles to the interface metal and soldering at least one buss wire to back contact. | 2012-04-12 |
20120088328 | NON-VOLATILE RESISTIVE-SWITCHING MEMORIES - Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set operation of at least one volt per one hundred angstroms of a thickness of the metal oxide, and has a leakage current density less than 40 amps per square centimeter (A/cm | 2012-04-12 |
20120088329 | SEMICONDUCTOR MULTI-PROJECT OR MULTI-PRODUCT WAFER PROCESS - The embodiment provides a semiconductor MP wafer process including processing a plurality of MP wafers in a lot or batch with a first process step. The plurality of the MP wafers is split into an MP wafer group- | 2012-04-12 |
20120088330 | AIRGAP MICRO-SPRING INTERCONNECT WITH BONDED UNDERFILL SEAL - A method of assembling a package includes aligning a pad chip with a spring chip to form at least one interconnect in an interconnect area, adhering the pad chip to the spring chip so that there is a gap between the pad chip and the spring chip, dispensing underfill material into the gap to seal the interconnect area from an environment external to the package, and curing the underfill material to form a solid mold. | 2012-04-12 |
20120088331 | WAFER LEVEL STACK DIE PACKAGE - This document discusses, among other things, apparatus and methods for an IC package including first and a second discrete components fabricated into a semiconductor substrate. The first and second discrete components can be adjacent to one another in the semiconductor substrate, and an integrated circuit die can be mounted on the semiconductor substrate and coupled to the first and second discrete components. | 2012-04-12 |
20120088332 | Semiconductor Package and Method of Manufacturing the Same - A method of forming a semiconductor package includes attaching a semiconductor substrate on a support substrate, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region that separates respective ones of the semiconductor chips. A first cutting groove is formed that has a first kerf width between first and second ones of the plurality of first semiconductor chips. A plurality of second semiconductor chips is attached to the plurality of first semiconductor chips. A molding layer is formed so as to fill the first cutting groove and a second cutting groove having a second kerf width that is less than the first kerf width is formed in the molding layer so as to form individual molding layers covering one of the plurality of first semiconductor chips and one of the plurality of second semiconductor chips. | 2012-04-12 |
20120088333 | DICING/DIE-BONDING FILM, METHOD OF FIXING CHIPPED WORK AND SEMICONDUCTOR DEVICE - A dicing/die-bonding film including a pressure-sensitive adhesive layer ( | 2012-04-12 |
20120088334 | METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - Disclosed herein is a method for manufacturing a semiconductor package which uses a base member | 2012-04-12 |
20120088335 | MANUFACTURING METHOD OF THE ELECTRONIC COMPONENT - Manufacturing method of an electronic component including connecting one lead of a pair of leads to a surface parallel with a pn connection layer of an electronic element having a structure where the p-type layer and the n-type layer are connected by the pn connection layer provided between the p-type layer and the n-type layer, connecting another lead to another surface parallel with the pn connection layer; and forming a supporting part of the pair of the leads that is connected to and supporting the electronic element, and an electrode part functioning as an electrode, by bending the pair of the leads to an outside. | 2012-04-12 |
20120088336 | SEMICONDUCTOR PACKAGE HAVING AN IMPROVED CONNECTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package having an improved connection structure and a method for manufacturing the same is described. The semiconductor package includes a substrate having a substrate body, connection pads that are located on one surface of the substrate body, and ball lands that are located on the other surface of the substrate body opposite the one surface. The ball lands are electrically connected to the connection pads. A semiconductor chip having bumps that are formed to correspond to the connection pads is connected to the substrate. An anisotropic conductive member having an insulation element is interposed between the substrate and the semiconductor chip to connect the substrate and the semiconductor chip. Electrically flowable conductive particles within the insulation element flow in the insulation element according to applied electric fields so as to arrange the electrically flowable conductive particles between the connection pads and the bumps. | 2012-04-12 |
20120088337 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, includes the steps of mounting a lead frame in a recessed portion of a lower die, bringing the lower die and an upper die to overlap each other so that a portion for sliding the lead frame slides the lead frame toward injection surfaces, the sliding portion being formed on the recessed portion of the lower die or on the recessed portion of the upper die, clamping the lower die and the upper die together so that at least one projection formed on the upper die crushes down an end portion of the lead frame so as to form lateral projections on the left and right sides of the gate, the lateral projections blocking up the gap between the injection surfaces and the lead frame, and injecting a molding resin through the gate. | 2012-04-12 |
20120088338 | INTEGRATED CIRCUIT TAMPERING PROTECTION AND REVERSE ENGINEERING PREVENTION COATINGS AND METHODS - A method of protecting an electronics package is discussed along with devices formed by the method. The method involves providing at least one electronic component that requires protecting from tampering and/or reverse engineering. Further, the method includes mixing into a liquid glass material at least one of high durability micro-particles or high-durability nano-particles, to form a coating material. Further still, the method includes depositing the coating material onto the electronic component and curing the coating material deposited. | 2012-04-12 |
20120088339 | Vertical Semiconductor Device with Thinned Substrate - A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region. | 2012-04-12 |
20120088340 | THIN FILM TRANSISTOR, METHOD OF FABRICATING THE SAME, AND ORGANIC LIGHTING EMITTING DIODE DISPLAY DEVICE INCLUDING THE SAME - A thin film transistor, a method of fabricating the same, and an organic light emitting diode display device including the same. The thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate, including a channel region, source/drain regions, and a body contact region; a gate insulating layer disposed on the semiconductor layer so as to expose the body contact region; a gate electrode disposed on the gate insulating layer, so as to contact the body contact region; an interlayer insulating layer disposed on the gate electrode; and source/drain electrodes disposed on the interlayer insulating layer and electrically connected to the source/drain regions. The body contact region is formed in an edge of the semiconductor layer. | 2012-04-12 |
20120088341 | Methods Of Manufacturing High Electron Mobility Transistors - The methods may include forming a first material layer on a substrate, increasing electric resistance of the first material layer, and forming a source pattern and a drain pattern, which are spaced apart from each other, on the first material layer, a band gap of the source and drain patterns greater than a band gap of a first material layer. | 2012-04-12 |
20120088342 | Methods of Fabricating Devices Including Source/Drain Region with Abrupt Junction Profile - Provided are methods of fabricating a semiconductor device including a metal oxide semiconductor (MOS) transistor. The methods include forming a gate pattern on a semiconductor substrate. The semiconductor substrate is etched using the gate pattern as an etching mask to form a pair of active trenches spaced apart from each other in the semiconductor substrate. Epitaxial layers are formed in the active trenches, respectively. The respective epitaxial layers are formed by sequentially stacking first and second layers. The first and second layers are formed of a semiconductor layer having a lattice constant greater than the semiconductor substrate, and a composition ratio of the second layer is different from that of the first layer. Semiconductor devices having the first and second layers are also provided. | 2012-04-12 |
20120088343 | METHOD OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICE - A vertical semiconductor device, a DRAM device, and associated methods, the vertical semiconductor device including single crystalline active bodies vertically disposed on an upper surface of a single crystalline substrate, each of the single crystalline active bodies having a first active portion on the substrate and a second active portion on the first active portion, and the first active portion having a first width smaller than a second width of the second active portion, a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate, a gate electrode on the gate insulating layer, the gate electrode having a linear shape surrounding the active bodies, a first impurity region in the upper surface of the substrate under the active bodies, and a second impurity region in the second active portion. | 2012-04-12 |
20120088344 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING AN EPITAXY REGION - A method is described what includes providing a substrate having a first trench and a second trench. An epitaxy material (crystalline material) is formed in the first trench and in the second trench. The top surface of the epitaxy material in the first trench is noncollinear with a top surface of the epitaxy material in the second trench. An amorphous semiconductor layer is formed on the crystalline material. Subsequently, the amorphous layer is converted, in part or in whole, into the crystalline semiconductor material. In an embodiment, a planarization process after the conversion provides crystalline regions having a coplanar top surface. | 2012-04-12 |
20120088345 | METHOD OF FORMING SILICIDE FOR CONTACT PLUGS - A method for forming silicide is provided. First, a substrate is provided. Second, a gate structure is formed on the substrate which includes a silicon layer, a gate dielectric layer and at least one spacer. Then, a pair of source and drain is formed in the substrate and adjacent to the gate structure. Later, an interlayer dielectric layer is formed to cover the gate structure, the source and the drain. Afterwards, the interlayer dielectric layer is selectively removed to expose the gate structure. Next, multiple contact holes are formed in the interlayer dielectric layer to expose part of the substrate. Afterwards, the exposed substrate is converted to form silicide. | 2012-04-12 |
20120088346 | THIN FILM TRANSISTORS IN PIXEL AND DRIVING PORTIONS CHARACTERIZED BY SURFACE ROUGHNESS - A thin film transistor and a fabrication method thereof, in which one excimer laser annealing (ELA) makes a pixel portion and a driver portion different from each other in surface roughness and grain size. The thin film transistor includes: a substrate including a pixel portion and a driver portion; a first semiconductor layer disposed in the pixel portion and having a first surface roughness; and a second semiconductor layer disposed in the driver portion and having a second surface roughness smaller than the first surface roughness. | 2012-04-12 |
20120088347 | Methods Of Manufacturing Non-Volatile Phase-Change Memory Devices - Methods of manufacturing non-volatile memory devices may include separating first phase-change material groups and second phase-change material groups, which have different sizes, from a target including phase-change materials and faulting a phase-change material layer on an object by using the first phase-change material groups and the second phase-change material groups. | 2012-04-12 |
20120088348 | Methods of Forming Patterns in Semiconductor Constructions, Methods of Forming Container Capacitors, and Methods of Forming Reticles Configured for Imprint Lithography - The invention includes methods of forming reticles configured for imprint lithography, methods of forming capacitor container openings, and methods in which capacitor container openings are incorporated into DRAM arrays. An exemplary method of forming a reticle includes formation of a radiation-imageable layer over a material. A lattice pattern is then formed within the radiation-imageable layer, with the lattice pattern defining a plurality of islands of the radiation-imageable layer. The lattice-patterned radiation-imageable layer is utilized as a mask while subjecting the material under the lattice-patterned layer to an etch which transfers the lattice pattern into the material. The etch forms a plurality of pillars which extend only partially into the material, with the pillars being spaced from one another by gaps. The gaps are subsequently narrowed with a second material which only partially fills the gaps. | 2012-04-12 |
20120088349 | METHODS OF FABRICATING FIN STRUCTURES - There is provided fin methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins. | 2012-04-12 |
20120088350 | METHOD FOR MOLECULAR BONDING OF SILICON AND GLASS SUBSTRATES - The present invention concerns a method for bonding a first substrate having a first surface to a second substrate having a second surface. This method includes the steps of holding the first substrate by at least two support points, positioning the first substrate and the second substrate so that the first surface and the second surface face each other, deforming the first substrate by applying between at least one pressure point and the two support points a strain toward the second substrate, bringing the deformed first surface and the second surface into contact, and progressively releasing the strain to facilitate bonding of the substrates while minimizing or avoiding the trapping of air bubbles between the substrates. | 2012-04-12 |
20120088351 | METHOD FOR TRANSFERRING AT LEAST ONE MICRO-TECHNOLOGICAL LAYER - A method for transferring a micro-technological layer includes preparing a substrate having a porous layer buried beneath a useful surface, forming an embrittled zone between it and the surface, bonding the substrate to a supporting substrate, causing detachment at the porous layer by mechanical stress to obtain a first substrate remnant, and a bare surfaced detached layer joined to the supporting substrate, performing technological steps on the bared surface of the detached layer, bonding the detached layer, by the surface to which the technological steps had been applied, to a second supporting substrate, causing detachment, at the embrittled zone, by heat treatment to obtain a detached layer remnant joined to the second supporting substrate, and the detached layer remnant joined to the first supporting substrate. | 2012-04-12 |
20120088352 | PROCESS FOR ASSEMBLING SUBSTRATES WITH LOW-TEMPERATURE HEAT TREATMENTS - The invention relates to a process for producing a bond between a first and a second substrate. The process includes preparing surfaces of the substrates to be assembled, and attaching the surfaces to form an assembly of these two surfaces, by direct molecular bonding. The assembly is then heat treated, which includes maintaining the temperature within the range of 50° C. to 100° C. for at least one hour. | 2012-04-12 |
20120088353 | SEMICONDUCTOR DEVICE WITH A CHARGE CARRIER COMPENSATION STRUCTURE IN A SEMICONDUCTOR BODY AND METHOD FOR ITS PRODUCTION - A semiconductor device with a charge carrier compensation structure in a semiconductor body and to a method for its production. The semiconductor body includes drift zones of a first conduction type and charge compensation zones of a second conduction type complementing the first conduction type. The drift zones include a semiconductor material applied in epitaxial growth zones, wherein the epitaxial growth zones include an epitaxially grown semiconductor material which is non-doped to lightly doped. Towards the substrate, the epitaxial growth zones are provided with a first conduction type incorporated by ion implantation over the entire surface and with selectively introduced doping material zones of a second, complementary conduction type. Towards the front side, the epitaxial growth zones are provided with a second, complementary conduction type incorporated by ion implantation over the entire surface and with selectively introduced doping material zones of the first conduction type. | 2012-04-12 |
20120088354 | WORKPIECE DIVIDING METHOD - In a semiconductor wafer with a supporting tape attached to the back side of the wafer, a coating member having a refractive index close to that of the supporting tape is formed on a pear-skin surface of the supporting tape to thereby planarize the pear-skin surface. Thereafter, a pulsed laser beam is applied from the upper side of the coating member to the semiconductor wafer in the condition where the focal point of the pulsed laser beam is set at a predetermined depth in the semiconductor wafer. Accordingly, the pulsed laser beam can be sufficiently focused inside the semiconductor wafer to thereby well form a modified layer inside the semiconductor wafer. | 2012-04-12 |
20120088355 | SEMICONDUCTOR DEVICE AND STRUCTURE - A method of manufacturing a semiconductor wafer, the method comprising: a first monocrystalline layer comprising semiconductor regions, overlaying the first monocrystalline layer with an isolation layer; preparing a second monocrystalline layer comprising semiconductor regions overlying the isolation layer; and etching portions of the first monocrystalline layer as part of forming at least one transistor on said first monocrystalline layer. | 2012-04-12 |
20120088356 | INTEGRATED PLATFORM FOR IN-SITU DOPING AND ACTIVATION OF SUBSTRATES - An integrated platform for processing substrates, comprising: a vacuum substrate transfer chamber; a doping chamber coupled to the vacuum substrate transfer chamber, the doping chamber configured to implant or deposit dopant elements in or on a surface of a substrate; a dopant activation chamber coupled to the vacuum substrate transfer chamber, the dopant activation chamber configured to anneal the substrate and activate the dopant elements; and a controller configured to control the integrated platform, the controller comprising a computer readable media having instructions stored thereon that, when executed by the controller, causes the integrated platform to perform a method, the method comprising: doping a substrate with one or more dopant elements in the doping chamber; transferring the substrate under vacuum to the dopant activation chamber; and annealing the substrate in the dopant activation chamber to activate the dopant elements. | 2012-04-12 |
20120088357 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is disclosed. The method forms a semiconductor device including a workpiece structure having a first region and second region located adjacent to the first region formed therein. The first region includes a first pattern and the second region includes a second pattern having at least a greater pattern width or a smaller aspect ratio than the first pattern. The method includes forming the first pattern by providing a first film having a first contact angle at a top portion thereof and the second pattern by providing a second film having a second contact angle less than the first contact angle at a top portion thereof; cleaning the first and the second regions by a chemical liquid; rinsing the cleaned first and the second regions by a rinse liquid; and drying the rinsed first and the second regions. | 2012-04-12 |
20120088358 | Methods of Forming Gates of Semiconductor Devices - Methods of forming gates of semiconductor devices are provided. The methods may include forming a first recess in a first substrate region having a first conductivity type and forming a second recess in a second substrate region having a second conductivity type. The methods may also include forming a high-k layer in the first and second recesses. The methods may further include providing a first metal on the high-k layer in the first and second substrate regions, the first metal being provided within the second recess. The methods may additionally include removing at least portions of the first metal from the second recess while protecting materials within the first recess from removal. The methods may also include, after removing at least portions of the first metal from the second recess, providing a second metal within the second recess. | 2012-04-12 |
20120088359 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Example embodiments relate to a method for manufacturing a semiconductor device, wherein a metal gate electrode therein may be formed without a void in a lower portion of the metal gate electrode. The method may include providing a substrate, forming a dummy gate electrode on the substrate, forming a gate spacer on the substrate to be contiguous to the dummy gate electrode, forming a first recess by simultaneously removing a portion of the dummy gate electrode and a portion of the gate spacer, the first recess having an upper end wider than a lower end, forming a second recess by removing the dummy gate electrode remaining after forming the first recess, and forming a metal gate electrode by depositing a metal to fill the first and second recesses. | 2012-04-12 |
20120088360 | Methods of Fabricating Semiconductor Devices - Methods of manufacturing a semiconductor device including a multi-layer of dielectric layers may include forming a metal oxide layer on a semiconductor substrate and forming a multi-layer of silicate layers including metal atoms and silicon atoms, on the metal oxide layer. The multi-layer of silicate layers may include at least two metallic silicate layers having different silicon concentrations, which are a ratio of silicon atoms among all metal atoms and silicon atoms included in the metallic silicate layer. | 2012-04-12 |
20120088361 | FUSE PART IN SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A fuse part in a semiconductor device has a plurality of fuse lines extended along a first direction with a given width along a second direction. The fuse part includes a first conductive pattern having a space part formed in a fuse line region over a substrate, wherein portions of the first conductive pattern are spaced apart by the space part along the first direction. The fuse part includes a first insulation pattern formed over the space part, the first insulation pattern having a width smaller than a width of the first conductive pattern along the second direction and a thickness greater than a thickness of the first conductive pattern, and a second conductive pattern formed over the first insulation pattern, the second conductive pattern having a width greater than the width of the first insulation pattern along the second direction. | 2012-04-12 |
20120088362 | Thermal Compressive Bond Head - A method includes allowing a work piece having a solder bump to contact a bond head; heating the bond head until the solder bump is melted; and conducting a cooling media into the bond head to cool the solder bump and to solidify the solder bump. | 2012-04-12 |
20120088363 | METHOD AND SYSTEM FOR FORMING CONDUCTIVE BUMPING WITH COPPER INTERCONNECTION - A method for making an integrated circuit system with one or more copper interconnects that are conductively connected with a substrate includes depositing and patterning a first dielectric layer to form a first via and filling the first via through the first dielectric layer with a copper material. The method further includes depositing and patterning a second dielectric layer in contact with the first dielectric layer to form a second via, and forming a diffusion barrier layer. Moreover, the method includes depositing and patterning a photoresist layer on the diffusion barrier layer, and at least partially filling the second via with a gold material. The gold material is conductively connected to the copper material through the diffusion barrier layer. The method further includes removing the photoresist and the diffusion barrier layer not covering by the gold material. Additionally, the method includes conductively connecting the gold material with the substrate. | 2012-04-12 |
20120088364 | SEMICONDUCTOR DEVICE AND THE METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate; a metal electrode wiring laminate on the semiconductor substrate, the metal electrode wiring laminate being patterned with a predetermined wiring pattern; the metal electrode wiring laminate including an undercoating barrier metal laminate and aluminum or aluminum alloy film on the undercoating barrier metal laminate; and organic passivation film covering the metal electrode wiring laminate, wherein the barrier metal laminate is a three-layered laminate including titanium films sandwiching a titanium nitride film. The semiconductor device according to the invention facilitates improving the moisture resistance of the portion of the barrier metal laminate exposed temporarily in the manufacturing process, facilitates employing only one passivation film, facilitates preventing the failures caused by cracks from occurring and the failures caused by Si nodules remaining in the aluminum alloy from increasing. | 2012-04-12 |
20120088365 | TECHNIQUE FOR FORMING METAL LINES IN A SEMICONDUCTOR BY ADAPTING THE TEMPERATURE DEPENDENCE OF THE LINE RESISTANCE - By moderately introducing defects into a highly conductive material, such as copper, the resistance versus temperature behavior may be significantly modified so that enhanced electromigration behavior and/or electrical performance may be obtained in metallization structures of advanced semiconductor devices. The defect-related portion of the resistance may be moderately increased so as to change the slope of the resistance versus temperature curve, thereby allowing the incorporation of impurity atoms for enhancing the electromigration endurance while not unduly increasing the overall resistance at the operating temperature or even reducing the corresponding resistance at the specified operating temperature. Thus, by appropriately designing the electrical resistance for a target operating temperature, both the electromigration behavior and the electrical performance may be enhanced. | 2012-04-12 |
20120088366 | CMP Retaining Ring with Soft Retaining Ring Insert - A wafer carrier adapted to further reduce the edge effect and allow a wafer to be uniformly polished across its entire surface, with a retaining ring made from very hard materials such as PEEK, PET or polycarbonate with a hardness in the range of 80 to 85 Shore D, while the inner surface or insert is made of polyurethane or other material with a hardness in the range of 85 to 95 Shore A. | 2012-04-12 |
20120088367 | SEMICONDUCTOR DEVICE AND STRUCTURE - A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate; preparing a first monocrystalline layer comprising semiconductor regions; preparing a second monocrystalline layer comprising semiconductor regions overlying the first monocrystalline layer; and etching portions of said first monocrystalline layer and portions of said second monocrystalline layer as part of forming at least one transistor on said first monocrystalline layer. | 2012-04-12 |
20120088368 | METHOD OF SELECTIVELY REMOVING PATTERNED HARD MASK - A method of selectively removing a patterned hard mask is described. A substrate with a patterned target layer thereon is provided, wherein the patterned target layer includes a first target pattern and at least one second target pattern, and the patterned hard mask includes a first mask pattern on the first target pattern and a second mask pattern on the at least one second target pattern. A first photoresist layer is formed covering the first mask pattern. The sidewall of the at least one second target pattern is covered by a second photoresist layer. The second mask pattern is removed using the first photoresist layer and the second photoresist layer as a mask. | 2012-04-12 |
20120088369 | Atomic Layer Deposition Of Photoresist Materials And Hard Mask Precursors - Methods for forming photoresists sensitive to radiation on substrate are provided. Atomic layer deposition methods of forming films (e.g., silicon-containing films) photoresists are described. The process can be repeated multiple times to deposit a plurality of silicon photoresist layers. Process of depositing photoresist and forming patterns in photoresist are also disclosed which utilize carbon containing underlayers such as amorphous carbon layers. | 2012-04-12 |
20120088370 | Substrate Processing System with Multiple Processing Devices Deployed in Shared Ambient Environment and Associated Methods - A plurality of substrate processing devices are disposed in a separated manner within a shared ambient environment. A conveyance device is disposed within the shared ambient environment and is defined to move a substrate through and between each of the substrate processing devices in a continuous manner. Some substrate processing devices are defined to perform dry substrate processing operations in which an energized reactive environment is created in exposure to the substrate in an absence of liquid material. Some substrate processing devices are defined to perform wet substrate processing operations in which at least one material in a liquid state is applied to the substrate. In one embodiment, a complementary pair of dry and wet substrate processing devices are disposed in the shared ambient environment in a sequential manner relative to movement of the substrate by the conveyance device. | 2012-04-12 |
20120088371 | METHODS FOR ETCHING SUBSTRATES USING PULSED DC VOLTAGE - Methods for etching substrates using a pulsed DC voltage are provided herein. In some embodiments, a method for method for etching a substrate disposed on a substrate support within a process chamber may include providing a process gas to the process chamber; forming a plasma from the process gas; applying a pulsed DC voltage to a first electrode disposed within the process chamber; and etching the substrate while applying the pulsed DC voltage. | 2012-04-12 |
20120088372 | METHOD OF FORMING MICRO-PORE STRUCTURES OR TRENCH STRUCTURES ON SURFACE OF SILICON WAFER SUBSTRATE - A method of forming micro-pore structures or trench structures on a surface of a silicon wafer substrate comprises (A) forming at least a noble-metal alloy particle on the surface of the silicon wafer substrate; and (B) then followed by employing a chemical wet etching on the surface of the silicon wafer substrate. During the processes, noble-metal alloy particle is used to catalyze the oxidation of the silicon wafer substrate surface in contact therewith, and an etchant is used to simultaneous etch the silicon dioxide to result in local micro-etching at the surface of the silicon wafer substrate, thereby forming micro-pore structures or trench structures on the surface of the silicon wafer substrate. The method increases the power conversion efficiency of the solar cells and reduces the manufacturing costs so as to increase the production benefits of the solar cells. | 2012-04-12 |
20120088373 | METHODS OF FORMING TITANIUM SILICON OXIDE - A dielectric containing a titanium silicon oxide film and a method of fabricating such a dielectric provide a dielectric for use in a variety of electronic devices. Embodiments may include a dielectric containing a titanium silicon oxide film arranged as one or more monolayers. Embodiments may include structures for capacitors, transistors, memory devices, and electronic systems with dielectrics containing a titanium silicon oxide film, and methods for forming such structures. | 2012-04-12 |
20120088374 | HBT and Field Effect Transistor Integration - Methods and systems for fabricating an integrated BiFET using two separate growth procedures are disclosed. Performance of the method fabricates the FET portion of the BiFET in a first fabrication environment. Performance of the method fabricates the HBT portion of the BiFET in a second fabrication environment. By separating the fabrication of the FET portion and the HBT portion in two or more separate reactors, the optimum device performance can be achieved for both devices. | 2012-04-12 |
20120088375 | CARD EDGE CONNECTOR WITH IMPROVED CENTRAL SLOT - A card edge connector includes an elongated housing extending along an elongated direction thereof, and having a first housing half, a second housing half being discrete from the first housing half, and a central slot formed between the first and the second housing halves. A plurality of contacts are retained in the housing, and each has a contact portion protruding into the central slot. A width of the central slot could be adjusted before mounting the card edge connector to a mother board for receiving different daughter boards with different thicknesses. | 2012-04-12 |
20120088376 | SPLIT FLEX CABLE - A cable assembly for interconnecting a plurality of circuit boards together by using a connector assembly connected to each of the circuit boards. The cable assembly includes a first cable having a first end part and a second cable having a second end part. A first periphery of the first end part has a plurality of first half vias that collectively form a column along a width direction of the connector assembly. A second periphery of the second end part has a plurality of second half vias that collectively form a column along the width direction of the connector assembly. The first and second end parts are coupled together to form a connecting unit, such that the first half vias and the second half vias are joined together to form full vias. | 2012-04-12 |
20120088377 | METHOD AND DEVICE OF ELECTROMAGNETICS - A method and device for electromagnetic shielding is disclosed. An example arrangement includes a first and a second printed circuit board arranged adjacently and having an electromagnetic shield cover. An electrically conductive plug electrically provides an interconnection of the electromagnetic shielding. | 2012-04-12 |
20120088378 | COMPOSITE CONTACT FOR FINE PITCH ELECTRICAL INTERCONNECT ASSEMBLY - An electrical interconnect assembly for electrically interconnecting terminals on a first circuit member with terminals on a second circuit member. The electrical interconnect assembly includes a housing having a plurality of through openings extending between a first surface and a second surface. A plurality of composite contacts are positioned in a plurality of the through openings. The composite contacts include a conductive member having a central portion and at least first and second interface portions. One or more polymeric layers extend along at least the central portion conductive member. One or more coupling features on the composite contacts engage with the housing. At least one engagement feature formed in the polymeric layers proximate the first interface portion mechanically couples with the terminals on the first circuit member. | 2012-04-12 |
20120088379 | STRADDLE MOUNT CONNECTOR - A straddle mount connector includes a housing that has a mating end and a mounting end configured to be mounted to an edge of a circuit board. Contacts are held by the housing with the contacts extending from the mounting end that are configured to be terminated to the circuit board. The contacts are arranged at the mating end and are configured for mating with a corresponding mating component. A comb extends from the mounting end of the housing that has a plurality of fingers separated from one another by a gap. The comb is positioned such that the fingers are positioned between corresponding contacts and the contacts are positioned within corresponding gaps. | 2012-04-12 |
20120088380 | ELECTRIC GROUND CLAMP WITH PIVOTED JAWS AND SINGLE ATTACHED ADJUSTING BOLT AND TERMINAL BLOCK - An adjustable ground clamp for easy positioning onto electric conduits of different diameters and grounding multiple electrical devices. A first and a second jaw are pivotally connected and have differently angled jaw surfaces. A distal end of the first jaw has an elongated hole and a distal end of the second jaw has a curved fork having a slot for receiving a bolt with a cylindrical nut. A fastener connects a ground conductor or wire to the ground clamp. A terminal block accepts ground conductors from multiple different electrical devices. The jaws may be easily separated for placement of an electrical conduit without separating or detaching any parts from the ground clamp, making attachment to an electrical conduit quick, easy, and secure. The terminal block permits different electrical devices to be grounded with a single ground clamp. | 2012-04-12 |
20120088381 | CONNECTOR CONTACT FOR TUBULAR CENTER CONDUCTOR - A contact assembly comprising: a contact pin having a first end and a second end, the contact pin including a ramped portion, and a contact sleeve retainably attached to the first end of the contact pin, the contact sleeve having a flanged end and a non-flanged end, wherein the contact sleeve includes a one or more fingers, wherein, when in a first position, clearance exists between the contact sleeve and the contact pin, wherein, when in a second position, the one or more fingers of the contact sleeve engage an inner surface of a tubular center conductor to increase a moving force required to displace the contact assembly within the tubular center conductor is provided. An associated method is also provided. | 2012-04-12 |
20120088382 | ELECTRIC VEHICLE CHARGE CORD LOCK - A charge cord lock system for a vehicle having rechargeable batteries. The system includes a charging receptacle; and a charge cord assembly having a charge plug slidably received in the charging receptacle and including a recess defining a retention flange. The system also includes a cord lock including a catch mounted to a plunger, with the plunger mounted to an actuator that moves the plunger toward and away from the charging receptacle, the catch engaged with the retention flange when the plunger is in an extended position and not engaged with the retention flange when the plunger is in a retracted position; and a controller in communication with a door lock mechanism and the actuator to cause the plunger to move to the retracted position when a door unlock signal is received and to cause the plunger to move to the extended position when a door lock signal is received. | 2012-04-12 |
20120088383 | CARD CONNECTOR - A card connector includes an insulating housing, a shell covering on the insulating housing to define a card receiving space between the cover and the insulating housing for being inserted into a card along an insertion direction, a plurality of contacts received in the insulating housing and extended into the card receiving space, a first switch terminal and a second switch respectively positioned at a right side of the insulating housing. The first switch terminal includes a main section extended along the insertion direction, a first straight section and a second straight section successively and slantwise extended into the card receiving space form a free end of the first main section to respectively define a first slope and a second slope relative to the main section. The second switch terminal includes a contacting section extending beside the first straight section. The second slope is larger than the first slope. | 2012-04-12 |
20120088384 | POWER-FEED CONNECTOR - A power-feed connector comprises a tubular case that has a front end opening portion; a connector body that is housed in the tubular case and can slide along a center axis direction of the tubular case; and an operating mechanism that operates the sliding of the connector body along the center axis direction, wherein the operating mechanism at least comprises an operating lever that is pivotally supported at the tubular case rotatably and a first end of which protrudes outside of the tubular case, and a conversion mechanism that converts a rotating force of the operating lever generated by moving the first end only into a force in the center axis direction of the tubular case; and a moving direction of the first end of the operating lever is coincident with a moving direction of the connector body which moves in association with the rotation of the operating lever. | 2012-04-12 |
20120088385 | Submersible Electrical Connector - A connector for use underwater or in a wet or severe environment comprises first and second connector parts adapted to be interengaged to establish an electrical connection. The first connector part has at least one pin, and the second connector part has at least one electrical contact for engagement by the pin when the connector parts are interengaged. The pin comprises an axially extending electrically conductive portion and an axially extending electrically insulating sleeve around said conductive portion, and the pin is supported by and projects axially forwardly from a support whereby its insulating sleeve is exposed along a longitudinally extending portion thereof to ambient conditions when the connector parts are disengaged. The connector part has a protective rigid metal sleeve member arranged to extend at least partly along the first portion of the insulating sleeve and at least partly along the second portion thereof. | 2012-04-12 |
20120088386 | HERMAPHRODITIC ELECTRICAL CONNECTOR - A hermaphroditic electrical connector assembly comprises a first connector ( | 2012-04-12 |
20120088387 | POSITIVE SAFETY LATCH - An electronic connector latch system provides safety via an internally hidden latch that requires a correctly sized pin to open. The described system is positive, in that it provides a “deadbolt” style latching wherein the pull out force is perpendicular to direction of opening the latch, and latching occurs on both sides of the locking post. The system is still user friendly in that mating the two connectors together can be accomplished without any tools. Mating is achieved with a simple insertion of the mating connector. The latch is captured inside the plastic unit housing, and a stamped sheet metal spring provides high cycle life. | 2012-04-12 |
20120088388 | EDGE CONNECTOR - An edge connector is disclosed, having a configuration in which board contacting portions of terminals coming into contact with both ends of the board are displaced, an overall spring portion of each terminal applying an biasing force to the board contacting portions are displaced, and the surface of a cover member displacing the spring portion is configured as a sloped surface. Due to this configuration, it is possible to apply a stable biasing force to the board contacting portion without plastically deforming the terminals and to bring the board contacting portion of the terminal into secure contact with the board even when the thickness of the board varies greatly. | 2012-04-12 |
20120088389 | CONNECTOR - A connector ( | 2012-04-12 |
20120088390 | CABLE CONNECTOR ASSEMBLY - A cable connector assembly includes a connector and an enclosure. The connector includes a securing plate and a guiding member attached to the securing plate. The enclosure includes a mounting plate and an elastic clipping portion disposed on the mounting plate. A flange is located on the clipping portion. The elastic clipping portion is engaged with the securing plate, and the flange abuts the guiding member. | 2012-04-12 |
20120088391 | CONNECTOR - Front ends of the locking strips ( | 2012-04-12 |
20120088392 | METHOD AND APPARATUS FOR LOCKING A NETWORK CABLE IN A JACK - A method and apparatus provide for a physically small, simple, and inexpensive securing of a conventional RJ45 or similar plug into a conventional jack. A tab lock is configured to slide forward and backward along the plug, wherein when the tab lock is slid forward, a distally extending tongue reaches underneath a release lever to hinder the bending of the release lever. In this way a latch coupled to the release lever is prevented from un-latching with a corresponding latch in the jack. When the tab lock slides backward the tongue is removed from underneath the release lever and the plug may be removed from the jack. The tab lock further provides for visual identification of a particular plug. | 2012-04-12 |
20120088393 | CAM CLAMP FOR ELECTRICAL CONNECTOR - A connector may include a first member having a first bore therethrough. A second member having a second bore therethrough may be configured to align with the first bore in the first member. A cam clamp may be provided for securing the first member to the second member. The cam clamp may include a pin having a head and a shaft, wherein the shaft extends through the first bore and the second bore. A compression element may be positioned between the first bore and a head on the pin. A cam member may be rotatably mounted to an end of the shaft opposing the head and configured to move between a first position and a second position. The cam clamp may be configured to secure the second member to the first member when the cam member is rotated from the first position to the second position. | 2012-04-12 |
20120088394 | Electrical Connection Clamp - A connection clamp for electrically connecting at least two electrical conductors includes at least one power carrying element, at least one substantially W-shaped spring and at least one spring receiver. The power carrying element includes at least two side walls, each respectively including at least one electrical contact surface at their insides oriented towards one another. The spring is arranged between the side walls. The arms of the spring are respectively arranged at a slant angle relative to the respectively adjacent side wall. The spring ends are configured as pull safety edges. An electrical conductor is insertable between a spring end and a side wall and the conductor is pressed against the contact surface through the spring force. | 2012-04-12 |
20120088395 | PLUG-IN CONNECTOR AS RECEPTACLE FOR A MULTI-WIRE CABLE - The invention pertains to a plug-connector for insertion of a multi-wire cable, wherein the wires are attached with the clamping-cutting technique. The plug-in connector exhibits a substrate and a plurality of clamping-cutting devices configured on the substrate and suitable for the insertion of wires. A first subset of the plurality of clamping-cutting devices is located on top of the substrate, while a second subset of the plurality of clamping-cutting devices is located at the bottom of the substrate. The plug-in connector furthermore exhibits wiring flaps suitable for the hinged insertion of the wires into the clamping-cutting devices. | 2012-04-12 |
20120088396 | LEAD WIRE FOR CONNECTING TO TAB ELECTRODE - A disposable tab electrode has core elements that include an adhesive conductive laminate layer and a logo sticker layer with a penetrating hole for contacting a sensor electrode. A protecting film is put around both ends of the core elements. As a result, the disposable tab electrode can be made inexpensively, stored hygienically for a long time and used easily. A lead wire for connecting to the tab electrode has a projection on one end of a sensor electrode that is adhered onto the conductive laminate layer of the disposable tab electrode. The projection is fixed to the lead wire body by a fixing member. As a result, expensive Ag-AgCl electrode sensors can be used repeatedly. The lead wire can have a nipper self-contained or integrated with the lead wire body to prevent the lead wire from separating from the disposable tab electrode during use. | 2012-04-12 |
20120088397 | LIGHT EMITTING DIODE LIGHT BAR MODULE WITH ELECTRICAL CONNECTORS FORMED BY INJECTION MOLDING - The present disclosure relates to methods for fabricating electrical connectors of a waterproof connector-heat sink assembly of a LED light bar module using injection molding. The methods include matching the coefficient of thermal expansion (CTE) of injection molding materials for the connectors and heat sinks. A heat sink and conductor pins are inserted into an injection mold and the injection molding materials are injected into the injection mold. An integrated connector-heat sink assembly is formed when the injection molding materials of the connectors form a waterproof seal with the heat sink when the injection molding materials solidify. Placement of the heat sink and conductor pins inside the injection mold is controlled to ensure that adhesive bonding between the injection molding materials and the heat sink is stronger than a maximum shear force. | 2012-04-12 |
20120088398 | JUMPER ASSEMBLY - A jumper assembly includes a jumper and a connecting member. An opening is defined in a first end of the jumper, with connected conductive portions installed in the opening. Two spaced hooking holes are defined in a second end of the jumper opposite to the first end. The connecting member is made of insulative material. Two spaced hooks protrude from a first end of the connecting member, to respectively engage in the hooking holes of the jumper. Two spaced inserting holes are defined in a second end of the connecting member opposite to the first end of the connecting member. | 2012-04-12 |
20120088399 | Quick Plug - An architecture is presented that provides a detachable outlet system for switching and changing outlets and switches with ease. The detachable outlet system comprises a receptacle, wherein a male adapter is secured to the receptacle. The detachable outlet system also comprises a gang box wired to comprise a female adapter, wherein the female adapter is positioned internal to the gang box. The gang box can further include a protective plate secured to the front of the gang box, and a spacer plate secured to the protective plate. The male adapter is then aligned with the female adapter of the gang box, and a user exhibits a pushing force to insert the receptacle into the gang box. Once the female and male adapters are matingly secured together in electrical communication, a faceplate can be positioned over the receptacle and secured into place. | 2012-04-12 |
20120088400 | Multiplex Receptacle Adapter - A modular electrical receptacle wherein more than one of the modular electrical receptacles can be connected to form a larger receptacle connected to a single source of power. The modular electrical receptacle includes a housing having a front surface with a first and a second electrical outlet. The housing further includes a first tab extending from a first end and a second end extending from a second end for securing the modular receptacle to an in-wall electrical box. The housing further includes a power link, such as a conductive extension, for connecting directly to another module and providing the other module with access to the single source of power. The power link can be three links for connecting a positive line, a neutral line and a ground line to another module. The housing also includes a coupler for connecting the housing to a power link of another module. | 2012-04-12 |