15th week of 2010 patent applcation highlights part 15 |
Patent application number | Title | Published |
20100090196 | Optical semiconductor device and manufacturing method of the same - A side barrier is provided between columnar dots each constituted by directly stacking respective quantum dots in seven or more layers. Out of respective side barrier layers composing the side barrier, each of the lower side barrier layers (four layers of the undermost layer to the fourth layer from the bottom) is formed as a first side barrier layer into which a tensile strain is introduced, and each of the upper side barrier layers (three layers of the fifth Layer to the uppermost layer from the bottom) is formed as a second side barrier layer which has no strain. | 2010-04-15 |
20100090197 | METHOD OF MANUFACTURING SEMICONDUCTOR NANOWIRE SENSOR DEVICE AND SEMICONDUCTOR NANOWIRE SENSOR DEVICE MANUFACTURED ACCORDING TO THE METHOD - Provided are a method of manufacturing a semiconductor nanowire sensor device and a semiconductor nanowire sensor device manufactured according to the method. The method includes preparing a first conductive type single crystal semiconductor substrate, forming a line-shaped first conductive type single crystal pattern from the first conductive type single crystal semiconductor substrate, forming second conductive type epitaxial patterns on both sidewalls of the first conductive type single crystal pattern, and forming source and drain electrodes at both ends of the second conductive type epitaxial patterns. | 2010-04-15 |
20100090198 | Nanowire Field Effect Junction Diode - A nanowire field effect junction diode constructed on an insulating transparent substrate that allows form(s) of radiation such as visual light, ultraviolet radiation; or infrared radiation to pass. A nanowire is disposed on the insulating transparent substrate. An anode is connected to a first end of the nanowire and a cathode is connected to the second end of the nanowire. An oxide layer covers the nanowire. A first conducting gate is disposed on top of the oxide layer adjacent with a non-zero separation to the anode. A second conducting gate is disposed on top of the oxide layer adjacent with a non-zero separation to the cathode and adjacent with a non-zero separation the first conducting gate. A controllable PN junction may be dynamically formed along the nanowire channel by applying opposite gate voltages. Radiation striking the nanowire through the substrate creates a current the anode and cathode. | 2010-04-15 |
20100090199 | Organic Semiconductor Film Forming Method, Organic Semiconductor Film and Organic Thin Film Transistor - A method for forming an organic semiconductor film having a high carrier mobility is provided by having an average volatilization rate of a solvent within a prescribed range during a step of drying, at the time of applying a coating solution, which includes an organic semiconductor material and a non-halogen solvent, on a substrate. In such forming method, characteristic fluctuation in repeated use of the organic semiconductor film is suppressed, and an organic thin film transistor having an excellent film forming characteristic even on an insulator with reduced gate voltage threshold can be obtained. | 2010-04-15 |
20100090200 | ORGANIC THIN FILM TRANSISTORS - Organic thin film transistors with improved mobility are disclosed. The transistor contains two interfacial layers between the dielectric layer and the semiconducting layer. One interfacial layer is formed from a siloxane polymer or silsesquioxane polymer. The other interfacial layer is formed from an alkyl-containing silane of Formula (1): | 2010-04-15 |
20100090201 | ORGANIC THIN FILM TRANSISTORS - A thin film transistor having an improved gate dielectric layer is disclosed. The gate dielectric layer comprises a poly(hydroxyalkyl acrylate-co-acrylonitrile) based polymer. The resulting gate dielectric layer has a high dielectric constant and can be crosslinked. Higher gate dielectric layer thicknesses can be used to prevent current leakage while still having a large capacitance for low operating voltages. Methods for producing such gate dielectric layers and/or thin film transistors comprising the same are also disclosed. | 2010-04-15 |
20100090202 | ORGANIC TRANSISTOR ELEMENT, ITS MANUFACTURING METHOD, ORGANIC LIGHT-EMITTING TRANSISTOR, AND LIGHT-EMITTING DISPLAY DEVICE - In a method for manufacturing an organic transistor element, an electrode is subjected to wet etching into a predetermined pattern on an organic semiconductor layer. In the process for performing wet etching on the electrode so as to obtain a predetermined pattern, an etching liquid containing a dopant of the organic semiconductor layer is used to perform wet etching on the electrode and, simultaneously, the organic semiconductor layer is doped with the dopant. | 2010-04-15 |
20100090203 | Organic Light-Emitting Element, Organic Light-Emitting Transistor, and Light-Emitting Display Device - An organic light-emitting element comprises a large number of unit pixels each at least composed of a base, an auxiliary electrode, a first insulating layer to cover at least the auxiliary electrode, a charge injection layer on the first insulating electrode, laminated bodies each consisting of a first electrode and a second insulating layer and provided in a predetermined pattern, an organic light-emitting layer formed in regions where the laminated bodies are not provided, and a second electrode to cover at least the organic light-emitting layer. The unit pixel has first partitions provided to demarcate the organic light-emitting layer from other adjacent unit pixels and at least one or more second partitions to have a uniform coated thickness, and at least one of the first partition and the second partition is the laminated body. | 2010-04-15 |
20100090204 | ORGANIC SEMICONDUCTOR ELEMENT AND MANUFACTURE METHOD THEREOF - [Problems] To form an organic semiconductor layer more uniformly in a channel region by allowing formation of a pattern with a higher resolution in an organic semiconductor element. | 2010-04-15 |
20100090205 | ACTIVE MATRIX DISPLAY APPARATUS - An active matrix display apparatus including a transistor | 2010-04-15 |
20100090206 | POLYMER LIGHT-EMITTING DEVICE, POLYMER COMPOUND, COMPOSITION, LIQUID COMPOSITION, AND CONDUCTIVE THIN FILM - Disclosed is a polymer light-emitting device having a light-emitting layer arranged between an anode and a cathode, and a hole transport layer arranged between the light-emitting layer and the anode. This polymer light-emitting device is characterized in that the hole transport layer is a layer containing a polymer compound which contains a repeating unit represented by the general formula (I) below, a repeating unit represented by the general formula (II) below and a repeating unit represented by the general formula (III) below. | 2010-04-15 |
20100090207 | Electroluminescent Organic Semiconductor Element and a Method for Repair of an Electroluminescent Organic Semiconductor Element - An electroluminescent organic semiconductor element includes a substrate and a first electrode arranged on the substrate. The semiconductor element additionally contains a second electrode and at least one organic layer, which is arranged between the first electrode and the second electrode. The organic layer is a layer that generates light by recombination of charge carriers. At least one of the first and the second electrode contains a highly conductive organic sublayer. | 2010-04-15 |
20100090208 | THIN FILM TRANSISTOR SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND DISPLAY APPARATUS HAVING THE SAME - In a method of manufacturing a thin film transistor substrate, a semiconductor pattern is formed on a substrate, a first etch stop layer and a second etch stop layer are sequentially formed on the semiconductor pattern, and the second etch stop layer and the first etch stop layer are sequentially patterned to form a second etch stop pattern and a first etch stop pattern. Thus, when the second etch stop layer is patterned using an etchant, the first etch stop layer covers the semiconductor pattern, thereby preventing the semiconductor pattern from being etched by the etchant. | 2010-04-15 |
20100090209 | ORGANIC EL DISPLAY APPARATUS - Provided is an organic EL display apparatus which can be driven at a low voltage and in which a red-light-emitting device uses a phosphorescent material, a green-light-emitting device uses a delayed fluorescent material, and the same material is used in the hole transport layers of the respective devices. | 2010-04-15 |
20100090210 | COMPOUND HAVING THIOL ANCHORING GROUP, METHOD OF SYNTHESIZING THE SAME, AND MOLECULAR ELECTRONIC DEVICE HAVING MOLECULAR ACTIVE LAYER FORMED USING THE COMPOUND - Provided are an electron donor-azo-electron acceptor compound having a thiol-based anchoring group, a method of synthesizing the compound, and a molecular electronic device having a molecular active layer formed of the compound. The compound for forming a molecular electronic device includes an azo compound that has a dinitrothiophene group and an aminobenzene group having thiol derivatives. The compound forms a molecular active layer in the molecular electronic devices. The molecular active layer is self-assembled on an electrode using the thiol derivative in the azo compound as an anchoring group. The molecular active layer in the molecular electronic device forms a switching device switching between an on-state and an off-state in response to a voltage applied to electrodes or a memory device storing a predetermined electric signal in response to a voltage applied to the electrodes. | 2010-04-15 |
20100090211 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes steps of forming a gate electrode over a light-transmitting substrate, forming a gate insulating layer containing an inorganic material over the gate electrode and the substrate, forming an organic layer containing a photopolymerizable reactive group over the gate insulating layer, polymerizing selectively the organic layer by irradiating the organic layer with light from back side of the substrate, using the gate electrode as a mask, forming an organic polymer layer by removing a residue of the organic layer, being other than polymerized, forming an organosilane film including a hydrolytic group over the gate insulating layer in a region other than a region in which the organic polymer layer is formed, forming source and drain electrodes by applying a composition containing a conductive material over the organic polymer layer, and forming a semiconductor layer over the gate electrode, the source and drain electrodes. | 2010-04-15 |
20100090212 | MEMORY CELL - A memory cell comprising a metal-insulator-semiconductor (MIS) structure is disclosed using a homogeneous carrier trapping layer interposed between a semiconductor layer and the gate electrode of a transistor structure so that the operation voltage is reduced and the manufacturing is simplified with lowered cost. The MIS structure comprises: a gate electrode; a semiconductor layer; and a homogeneous carrier trapping layer interposed between the gate electrode and the semiconductor layer; wherein the homogeneous carrier trapping layer comprises novolac. | 2010-04-15 |
20100090213 | ONE-TIME PROGRAMMABLE DEVICES INCLUDING CHALCOGENIDE MATERIAL AND ELECTRONIC SYSTEMS INCLUDING THE SAME - A method of programming a one-time programmable device is provided. A switching device disposed in a substrate is turned on and a program current is applied to a fuse electrically connected to the switching device, thereby cutting the fuse. The fuse includes a first electrode electrically connected to the switching device, a second electrode spaced apart from the first electrode, and a chalcogenide pattern disposed between the first and second electrodes. Related one-time programmable devices, phase change memory devices and electronic systems are also disclosed. | 2010-04-15 |
20100090214 | OXIDE THIN FILM AND OXIDE THIN FILM DEVICE - Provided are an oxide thin film doped with an n-type impurity, and an oxide thin film device. In an oxide thin film ( | 2010-04-15 |
20100090215 | THIN FILM TRANSISTOR AND METHOD FOR PREPARING THE SAME - The present invention relates to a thin film transistor and a method of manufacturing the same. More particularly, the present invention relates to a thin film transistor that includes a zinc oxide material including Si as a channel material of a semiconductor layer, and a method of manufacturing the same. | 2010-04-15 |
20100090216 | ELECTRONIC SEMICONDUCTOR DEVICE BASED ON COPPER NICKEL AND GALLIUM-TIN-ZINC-COPPER-TITANIUM p AND n-TYPE OXIDES, THEIR APPLICATIONS AND CORRESPONDING MANUFACTURE PROCESS - The present invention corresponds to the use of p and n-type oxide semiconductors based on copper nickel (OCu | 2010-04-15 |
20100090217 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Electric characteristics and reliability of a thin film transistor are impaired by diffusion of an impurity element into a channel region. The present invention provides a thin film transistor in which aluminum atoms are unlikely to be diffused to an oxide semiconductor layer. A thin film transistor including an oxide semiconductor layer including indium, gallium, and zinc includes source or drain electrode layers in which first conductive layers including aluminum as a main component and second conductive layers including a high-melting-point metal material are stacked. An oxide semiconductor layer | 2010-04-15 |
20100090218 | SEALED DEVICE - A sealed device having a substrate, a device having a semiconductor or electroconductive layer comprising zinc and oxygen, and a gas-barrier laminate comprising an organic region and an inorganic region can protect the device from deterioration by water vapor. | 2010-04-15 |
20100090219 | METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE - A method of fabrication of a semiconductor device having low resistance in an interconnection line and the same coefficient of thermal expansion as a semiconductor substrate is disclosed. The method includes forming a nitride film over a semiconductor substrate including a bottom metal line and a top metal line connected to each other through a plurality of vias, forming a trench at a through-silicon via (TSV) region of the semiconductor substrate, filling the trench with a predetermined material to form a silicon film, exposing the silicon film using a photoresist pattern, ion-implanting a dopant into the exposed silicon film, and selectively performing laser annealing to the silicon film to diffuse only the dopant implanted into the silicon film. | 2010-04-15 |
20100090220 | THIN FILM TRANSISTOR AND SEMICONDUCTOR DEVICE USING THE SAME - The present invention aims at providing a high-performance semiconductor device such as display, IC tag, sensor or the like at a low cost by using an organic thin film transistor most members of which can be formed by printing, as a switching element. The present invention relates to a thin film transistor composed of members on a dielectric substrate, which are a gate electrode, a dielectric film, source/drain electrodes, and a semiconductor layer, wherein on said semiconductor layer there are formed at least two passivation films of a first passivation film capping said semiconductor layer to protect it and a second passivation film covering larger area than that of said first passivation film to protect all of said members. | 2010-04-15 |
20100090221 | DISTORTION TOLERANT PROCESSING - A method of manufacturing an integrated circuit (IC) for driving a flexible display includes depositing a pattern of spatially non-repetitive features in a first layer on a flexible substrate, said pattern of spatially non-repetitive features not substantially regularly repeating in both of two orthogonal directions (x,y) in the plane of the substrate; depositing a pattern of spatially repetitive features in a second layer on said first layer; aligning said second layer and said first layer so as to allow electrical coupling between said non-repetitive features and said repetitive features, wherein distortion compensation is applied during deposition of said repetitive features to enable said alignment. | 2010-04-15 |
20100090222 | THIN FILM TRANSISTOR; METHOD OF MANUFACTURING SAME; AND ORGANIC LIGHT EMITTING DEVICE INCLUDING THE THIN FILM TRANSISTOR - A thin film transistor according to one or more embodiments of the present invention includes: an insulation substrate; a gate electrode formed on the substrate; a gate insulating layer formed on the gate electrode; a semiconductor formed on the gate insulating layer and having a pair of openings facing each other; ohmic contact layers formed in the openings and including a conductive impurity; and a source electrode and a drain electrode in contact with their respective ohmic contact layers. An organic light emitting device in accordance with an embodiment includes: a first signal line and a second signal line intersecting each other on an insulation substrate; a switching thin film transistor connected to the first signal line and the second signal line; a driving thin film transistor connected to the switching thin film transistor; and a light emitting diode (LED) connected to the driving thin film transistor. | 2010-04-15 |
20100090223 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor device in which a bottom-gate TFT or an inverted stagger TFT arranged in each circuit is suitably constructed in conformity with the functionality of the respective circuits, thereby attaining an improvement in the operating efficiency and reliability of the semiconductor device. In the structure, LDD regions in a pixel TFT are arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in an N-channel TFT of a drive circuit is arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in a P-channel TFT of the drive circuit is arranged so as to overlap with a channel protection insulating film and to overlap with the gate electrode. | 2010-04-15 |
20100090224 | THIN FILM TRANSISTOR, METHOD OF FABRICATING THE SAME, AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE HAVING THE THIN FILM TRANSISTOR - A thin film transistor (TFT), a method of fabricating the same, and an organic light emitting diode (OLED) display device having the TFT, the TFT includes a substrate, a protection layer disposed on the substrate, a buffer layer disposed on the protection layer, a semiconductor layer disposed on the buffer layer, a gate electrode disposed on the semiconductor layer, a gate insulating layer to electrically insulate the semiconductor layer from the gate electrode, and source and drain electrodes electrically insulated from the gate electrode and connected to the semiconductor layer. The protection layer is formed of an amine-containing clay. The OLED includes the TFT, an insulating layer disposed on the TFT, a first electrode connected to the drain electrode of the TFT, an organic layer disposed on the first electrode, and a second electrode disposed on the organic layer. | 2010-04-15 |
20100090225 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes: a main semiconductor region comprising a first nitride semiconductor layer having a first band gap, and a second nitride semiconductor layer having a second band gap larger than the first band gap, a heterojunction being formed between the first nitride semiconductor layer and a the second nitride semiconductor layer such that two-dimensional electron gas layer can be caused inside the first nitride semiconductor layer based on the heterojunction; a source electrode formed on the main semiconductor region; a drain electrode formed on the main semiconductor region and separated from the source electrode; a third nitride semiconductor layer formed on the first nitride semiconductor layer and between the source electrode and the drain electrode; and a gate electrode formed on the third nitride semiconductor layer. The third nitride semiconductor layer has a third band gap smaller than the first band gap. | 2010-04-15 |
20100090226 | DIAMOND UV-RAY SENSOR - Au base electrode materials have fatal disadvantages, such as inferior adhesion to diamond, low mechanical strength, and low thermal stability. | 2010-04-15 |
20100090227 | METHOD FOR THE FORMATION OF A GATE OXIDE ON A SIC SUBSTRATE AND SIC SUBSTRATES AND DEVICES PREPARED THEREBY - Methods are provided for improving inversion layer mobility and providing low defect density in a semiconductor device based upon a silicon carbide (SiC) substrate. More specifically, embodiments of the present method provide for the formation of a gate oxide on a silicon carbide substrate comprising oxidizing the substrate with a gaseous mixture comprising oxygen at a temperature of at least about 1300° C. Semiconductor devices, such as MOSFETS, based upon a substrate treated according to the present method are expected to have inversion layer mobilities of at least about 12 cm | 2010-04-15 |
20100090228 | BORON ALUMINUM NITRIDE DIAMOND HETEROSTRUCTURE - A heterostructure having a heterojunction comprising: a diamond layer; and a boron aluminum nitride (B | 2010-04-15 |
20100090229 | SEMICONDUCTOR LIGHT EMITTING APPARATUS AND METHOD FOR PRODUCING THE SAME - A light emitting apparatus can have a front luminous intensity distribution having a sharp difference at the interface between the light emitting area and the surrounding non-light emitting area (outer environment) so as to suppress or prevent light color unevenness. The semiconductor light emitting apparatus can include a substrate, a plurality of light emitting elements each having a top surface as a light emitting surface and disposed on the substrate with a predetermined gap between the adjacent light emitting elements, bridge portions each disposed at the gap between the adjacent light emitting elements so as to connect the light emitting elements, and a wavelength conversion layer disposed over the top surfaces of the plurality of the light emitting elements and the bridge portions entirely. The wavelength conversion layer can have a decreased thickness at least around its peripheral area and gradually tapering to its end portion. | 2010-04-15 |
20100090230 | CRYSTAL SILICON ELEMENT AND METHOD FOR FABRICATING SAME - It is an object of the present invention to provide a crystal silicon element emitting a desired visible light at high efficiency, by markedly enhancing the crystallinity of the nano Si. A p-type single crystal silicon substrate | 2010-04-15 |
20100090231 | LED PACKAGE MODULE - An LED package module according to an aspect of the invention may include: a substrate having predetermined electrodes thereon; a plurality of LED chips mounted onto the substrate, separated from each other at predetermined intervals, and electrically connected to the electrodes; a first color resin portion molded around at least one of the plurality of LED chips; a second color resin portion molded around all of the LED chips except for the LED chip around which the first color resin portion is molded, and having a different color from the first color resin portion; and a third color resin portion encompassing both the first color resin portion and the second color resin portion and having a different color from the first color resin portion and the second color resin portion. Accordingly, a reduction in luminous efficiency of an LED caused by yellowing is prevented to thereby increase luminous efficiency and achieve a reduction in size. | 2010-04-15 |
20100090232 | POLYCHROMATIC LED AND METHOD FOR MANUFACTURING THE SAME - A wavelength conversion layer is formed on a surface of a light emitting device for transforming a portion of light emitted from the light emitting device into light of a different wavelength. The transformed light is mixed with the untransformed light, and thus the light emitting device can emit light having preferred CIE coordinates. | 2010-04-15 |
20100090233 | SIDE-VIEW SURFACE MOUNT WHITE LED - A light emitting diode is disclosed. The diode includes a package support and a semiconductor chip on the package support, with the chip including an active region that emits light in the visible portion of the spectrum. Metal contacts are in electrical communication with the chip on the package. A substantially transparent encapsulant covers the chip in the package. A phosphor in the encapsulant emits a frequency in the visible spectrum different from the frequency emitted by the chip and in response to the wavelength emitted by the chip. A display element is also disclosed that combines the light emitting diode and a planar display element. The combination includes a substantially planar display element with the light emitting diode positioned on the perimeter of the display element and with the package support directing the output of the diode substantially parallel to the plane of the display element. | 2010-04-15 |
20100090234 | LIGHT EMITTING DEVICE HAVING LIGHT EXTRACTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A nitride-based light emitting device capable of achieving an enhancement in emission efficiency and an enhancement in reliability is disclosed. The light emitting device includes a semiconductor layer, and a light extracting layer arranged on the semiconductor layer and made of a material having a refractive index equal to or higher than a reflective index of the semiconductor layer. | 2010-04-15 |
20100090235 | LIGHT-EMITTING DIODE DEVICE AND METHOD FOR FABRICATING THE SAME - A light-emitting diode (LED) device is disclosed. The LED device includes a semiconductor substrate with a light-emitting diode chip disposed thereon. At least two isolated outer wiring layers are disposed on the bottom surface of the semiconductor substrate and are electrically connected to the light-emitting diode chip, serving as input terminals. A lens module is adhered to the top surface of the semiconductor substrate to cap the light-emitting diode chip. In one embodiment, the lens module comprises a glass substrate having a first cavity formed at a first surface thereof, a fluorescent layer formed over a portion of a first surface exposed by the first cavity, facing the light-emitting diode chip, and a molded lens formed over a second surface of the glass carrier opposing to the first surface. | 2010-04-15 |
20100090236 | LIGHT EMITTING ELEMENT, METHOD FOR MANUFACTURING THE LIGHT EMITTING ELEMENT, OPTICAL ELEMENT AND METHOD FOR MANUFACTURING THE OPTICAL ELEMENT - Fine asperities are simply formed in the surface of a light emission surface to improve an luminous efficiency of a light emitting element. An LED element | 2010-04-15 |
20100090237 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device and corresponding method of manufacture, where the semiconductor light emitting device includes a light emitting structure, a second electrode layer, an insulating layer, and a protrusion. The light emitting structure comprises a second conductive semiconductor layer, an active layer under the second conductive semiconductor layer, and a first conductive semiconductor layer under the active layer. The second electrode layer is formed on the light emitting structure. The insulating layer is formed along the circumference of the top surface of the light emitting structure. The protrusion protrudes from the undersurface of the insulating layer to the upper part of the first conductive semiconductor layer. | 2010-04-15 |
20100090238 | WHITE ORGANIC ELECTROLUMINESCENT DEVICE - A high-efficiency, white organic electroluminescent device has such a structure that its emission layer is obtained by laminating sub-emission layers of red, green, and blue, respectively. The green sub-emission layer contacting a hole transport layer has a delayed fluorescent material, and the red sub-emission layer has a phosphorescent light emitting material. | 2010-04-15 |
20100090239 | CERAMIC PACKAGE STRUCTURE OF HIGH POWER LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A ceramic package structure of a high power light emitting diode comprises a light emitting diode die, a ceramic substrate, at least two conductive rods, and an electrical conductive film. The ceramic substrate comprises a first surface and a second surface opposite the first surface. A reflecting cup is disposed on the first surface. At least two through holes are disposed on the bottom of the reflecting cup. The electrical conductive film comprises a first electrode and a second electrode, and is fixed to the second surface. The at least two conductive rods are respectively filled in the at least two through holes, and are respectively connected to the first electrode and the second electrode. The LED diode is mounted on one or at least two of the conductive rods, and is electrically connected to the at least two conductive rods. | 2010-04-15 |
20100090240 | PHOTOELECTROCHEMICAL ETCHING FOR CHIP SHAPING OF LIGHT EMITTING DIODES - A photoelectrochemical (PEC) etch is performed for chip shaping of a device comprised of a III-V semiconductor material, in order to extract light emitted into guided modes trapped in the III-V semiconductor material. The chip shaping involves varying an angle of incident light during the PEC etch to control an angle of the resulting sidewalls of the III-V semiconductor material. The sidewalls may be sloped as well as vertical, in order to scatter the guided modes out of the III-V semiconductor material rather than reflecting the guided modes back into the III-V semiconductor material. In addition to shaping the chip in order to extract light emitted into guided modes, the chip may be shaped to act as a lens, to focus its output light, or to direct its output light in a particular way. | 2010-04-15 |
20100090241 | EMISSIVE LAYER PATTERNING FOR OLED - An organic light emitting device is provided. The device includes an anode, a cathode, and an organic emissive stack disposed between the anode and the cathode. The device may be a “pixel” in a display, capable of emitting a wide variety of colors through the use of independently addressable “sub-pixels,” each subpixel emitting a different spectrum of light. In the most general sense, the device includes a first subpixel and a second subpixel, and at least one of the anode and the cathode has independently addressable first and second regions corresponding to the first and second subpixels. The device includes an emissive stack disposed between the anode and the cathode. The emissive stack includes a first organic emissive layer and a second organic emissive layer. The first organic emissive layer is disposed between the anode and the cathode, and extends throughout the first and second regions. The second organic emissive layer is disposed between the anode and the cathode, and extends throughout the second region but not the first region. The second organic emissive layer is disposed closer to the cathode than the first organic emissive layer. The first organic emissive layer is emissive in the first region, and the second organic emissive layer is emissive in the second region. | 2010-04-15 |
20100090242 | LIGHT EMITTING DEVICE HAVING LIGHT EXTRACTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A nitride-based light emitting device capable of achieving an enhancement in emission efficiency and an enhancement in reliability is disclosed. The light emitting device includes a semiconductor layer, and a light extracting layer arranged on the semiconductor layer and made of a material having a refractive index equal to or higher than a reflective index of the semiconductor layer. | 2010-04-15 |
20100090243 | LIGHT EMITTING DEVICE HAVING LIGHT EXTRACTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A nitride-based light emitting device capable of achieving an enhancement in emission efficiency and an enhancement in reliability is disclosed. The light emitting device includes a semiconductor layer, and a light extracting layer arranged on the semiconductor layer and made of a material having a refractive index equal to or higher than a reflective index of the semiconductor layer. | 2010-04-15 |
20100090244 | LIGHT EMITTING DEVICE - A light emitting device includes a transparent substrate having first and second surfaces, a semiconductor layer provided on the first surface, a first light emission layer provided on the semiconductor layer and emitting first ultraviolet light including a wavelength corresponding to an energy larger than a forbidden bandwidth of a semiconductor of the semiconductor layer, a second light emission layer provided between the first light emission layer and the semiconductor layer, absorbing the first ultraviolet light emitted from the first light emission layer, and emitting second ultraviolet light including a wavelength corresponding to an energy smaller than the forbidden bandwidth of the semiconductor of the semiconductor layer, and first and second electrodes provided to apply electric power to the first light emission layer. | 2010-04-15 |
20100090245 | LIGHT EMITTING DIODE PACKAGE AND METHOD OF MAKING THE SAME - The light emitting diode package of the present invention uses photosensitive materials to form phosphor encapsulations or a phosphor layer, which can be fabricated by means of semiconductor processes in batch. Also, the concentration of phosphors in individual regions can be accurately and easily controlled by a laser printing process or by light-through holes. Accordingly, the optic effects of light emitting diode packages can be accurately adjusted. | 2010-04-15 |
20100090246 | VERTICAL NITRIDE-BASED LIGHT EMITTING DIODE AND METHOD OF MANUFACTURING THE SAME - Provided is a vertical nitride-based LED including a first electrode; a first nitride semiconductor layer that is disposed on the first electrode; an active layer that is disposed on the first nitride semiconductor layer; a second nitride semiconductor layer that is disposed on the active layer; an ohmic contact pattern that is disposed on the second nitride semiconductor layer; a second electrode that is disposed on the ohmic contact pattern; and a bonding pad that is electrically connected to the second electrode and disposed on the second nitride semiconductor layer. | 2010-04-15 |
20100090247 | SURFACE TREATMENT METHOD OF GROUP III NITRIDE SEMICONDUCTOR, GROUP III NITRIDE SEMICONDUCTOR, MANUFACTURING METHOD OF THE SAME AND GROUP III NITRIDE SEMICONDUCTOR STRUCTURE - There is provided a surface treatment method of a group III nitride semiconductor including: providing a group III nitride semiconductor including a first surface having a group III polarity and a second surface opposing the first surface and having a nitrogen polarity; and irradiating a laser beam onto the second surface to change the nitrogen polarity of the second surface to the group III polarity. | 2010-04-15 |
20100090248 | Semiconductor device having IGBT and FWD on same substrate - A semiconductor device includes: a semiconductor substrate; an IGBT element including a collector region; a FWD element including a cathode region adjacent to the collector region; a base layer on the substrate; multiple trench gate structures including a gate electrode. The base layer is divided by the trench gate structures into multiple first and second regions. Each first region includes an emitter region contacting the gate electrode. Each first region together with the emitter region is electrically coupled with an emitter electrode. The first regions include collector side and cathode side first regions, and the second regions include collector side and cathode side second regions. At least a part of the cathode side second region is electrically coupled with the emitter electrode, and at least a part of the collector side second region has a floating potential. | 2010-04-15 |
20100090249 | Compound Semiconductor Lamination, Method for Manufacturing the same, and Semiconductor Device - The present invention relates to a compound semiconductor lamination that enables an InSb film to be formed on an Si substrate and enables development of applications to magnetic sensors, such as Hall elements, magneto-resistance elements, etc., optical devices, such as infrared sensors, etc., and electronic devices, such as transistors, etc., to be provided industrially, and a method for manufacturing the compound semiconductor lamination. An active layer, which is a compound semiconductor that does not contain As, is directly formed on an Si substrate. As is present at an interface of the active layer and a single crystal layer of the Si substrate. The compound semiconductor contains at least nitrogen. The compound semiconductor is a single crystal thin film. The Si substrate is a bulk single crystal substrate or a thin film substrate with an uppermost layer being Si. | 2010-04-15 |
20100090250 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed of a plurality of sub-films. The passivation film includes a first sub-film made of aluminum nitride. | 2010-04-15 |
20100090251 | SURFACE TREATMENT AND PASSIVATION OF AIGaN/GaN HEMT - In the preferred embodiments, a method to reduce gate leakage and dispersion of group III-nitride field effect devices covered with a thin in-situ SiN layer is provided. This can be obtained by introducing a second passivation layer on top of the in-situ SiN-layer, in combination with cleaning of the in-situ SiN before gate deposition and before deposition of the second passivation layer. | 2010-04-15 |
20100090252 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD. | 2010-04-15 |
20100090253 | PROGRAMMABLE POWER MANAGEMENT USING A NANOTUBE STRUCTURE - Programmable power management using a nanotube structure is disclosed. In one embodiment, a method includes coupling a nanotube structure of an integrated circuit to a conductive surface when a command is processed, and enabling a group of transistors of the integrated circuit based on the coupling the nanotube structure to the conductive surface. A current may be applied to the nanotube structure to couple the nanotube structure to the conductive surface. The nanotube structure may be formed from a material chosen from one or more of a polymer, carbon, and a composite material. The group of transistors may be enabled during an activation sequence of the integrated circuit. In addition, one or more transistors of the group of transistors may be disengaged from the one or more power sources (e.g., to minimize leakage) when the nanotube structure is decoupled from the conductive surface. | 2010-04-15 |
20100090254 | BIOSENSOR AND MANUFACTURING METHOD THEREOF - Provided is a biosensor which can detect a specific biomaterial by an interaction between target molecules and probe molecules, and a manufacturing method thereof. The biosensor includes: a first conductive semiconductor substrate; a second conductive doping layer formed on the semiconductor substrate; an electrode formed on top of both opposite ends of the doping layer; and probe molecules immobilized on the doping layer. | 2010-04-15 |
20100090255 | Electronic component - An electronic component includes at least one electrode and at least one gas-sensitive region on a substrate. The gas-sensitive region is coated by at least one electrically conductive, gas-sensitive layer, and the electrode contacts the gas-sensitive layer. At least a part of the at least one electrode covers a part of the gas-sensitive region. | 2010-04-15 |
20100090256 | SEMICONDUCTOR STRUCTURE WITH STRESS REGIONS - A semiconductor structure with stress regions includes a substrate defining a first and a second device zone; a first and a second stress region formed in each of the first and second device zones to yield stress different in level; and a barrier plug separating the two device zones from each other. Due to the stress yielded at the stress regions, increased carrier mobility and accordingly, increased reading current can be obtained, and a relatively lower reading voltage is needed to obtain initially required reading current. As a result, the probability of stress-induced leakage current (SILC) is reduced and the semiconductor memory structure may have enhanced data retention ability. | 2010-04-15 |
20100090257 | SEMICONDUCTOR DEVICE, AND ITS MANUFACTURING METHOD - A channel is formed at a recessed portion or a projecting portion of a substrate, and a gate insulating film is formed so as to have first to third insulating regions along the channel. Each of the gate insulating films of the first and third insulating regions has a first gate insulating film containing no electric charge trap formed on a plane different from a principal surface of the substrate, an electric charge accumulating film containing an electric charge trap, and a second gate insulating film containing no electric charge trap. The gate insulating film of the second insulating region at the middle is formed on a plane parallel to the principal surface of the substrate and is composed of only a third gate insulating film containing no electric charge trap. | 2010-04-15 |
20100090258 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device which can reduce on-resistance by improving hole mobility of a channel region. A trench gate type MOSFET (semiconductor device) is provided with a p | 2010-04-15 |
20100090259 | LATERAL JUNCTION FIELD-EFFECT TRANSISTOR | 2010-04-15 |
20100090260 | Integrated circuit layout pattern for cross-coupled circuits | 2010-04-15 |
20100090261 | MAGNETIC STACK WITH LAMINATED LAYER - A magnetic stack with a multilayer free layer having a switchable magnetization orientation, the free layer comprising a first ferromagnetic portion and a second ferromagnetic portion with an electrically conducting non-magnetic intermediate layer between the first portion and the second portion. The magnetic stack also includes a first ferromagnetic reference layer having a pinned magnetization orientation, a first non-magnetic spacer layer between the free layer and the first reference layer, a second ferromagnetic reference layer having a pinned magnetization orientation, and a second non-magnetic spacer layer between the free layer and the second reference layer. | 2010-04-15 |
20100090262 | SPIN TRANSISTOR, PROGRAMMABLE LOGIC CIRCUIT, AND MAGNETIC MEMORY - A spin transistor includes a non-magnetic semiconductor substrate having a channel region, a first area, and a second area. The channel region is between the first and the second areas. The spin transistor also includes a first conductive layer located above the first area and made of a ferromagnetic material magnetized in a first direction; and a second conductive layer located above the second area and made of a ferromagnetic material magnetized in one of the first direction and a second direction that is antiparallel with respect to the first direction. The channel region introduces electron spin between the conductive layers. The spin transistor also includes a gate electrode located between the conductive layers and above the channel region; and a tunnel barrier film located between the non-magnetic semiconductor substrate and at least one of the conductive layers. | 2010-04-15 |
20100090263 | MEMORY DEVICES INCLUDING SEMICONDUCTOR PILLARS - One embodiment relates to an integrated circuit that includes a memory array of pillars arranged in rows and columns. The pillars are separated from one another by row trenches and column trenches. The column trenches include a pair of parallel column trenches. A first trench of the pair includes two parallel bit lines coupled to pillars adjacent to the first trench. A second trench of the pair is free of bit lines. Other methods, devices, and systems are also disclosed. | 2010-04-15 |
20100090264 | INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES - One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed. | 2010-04-15 |
20100090265 | High density nanodot nonvolatile memory - A nanodot nonvolatile memory element comprises a substrate having a source and a drain region formed therein, and an insulating layer formed on the substrate. The insulating layer contains a nanocrystalline floating gate of approximately three to six nanometers in diameter formed at a distance of approximately two to five nanometers from the substrate, and a carbon nanotube control gate having a diameter of approximately six nanometers or less is formed at a distance of approximately 10-15 nanometers from the substrate. | 2010-04-15 |
20100090266 | SEMICONDUCTOR DEVICE HAVING CONTROLLABLE TRANSISTOR THRESHOLD VOLTAGE - A semiconductor device of this invention is a single-layer gate nonvolatile semiconductor memory in which a floating gate having a predetermined shape is formed on a semiconductor substrate. This floating gate opposes a diffusion layer serving as a control gate via a gate oxide film and is capacitively coupled with the diffusion layer by using the gate oxide film as a dielectric film. The diffusion layer immediately below the dielectric film is insulated from the semiconductor substrate by an insulating film such as a silicon oxide film. A pair of diffusion layers are formed in surface regions of the semiconductor substrate on the two sides of the floating gate extending on a tunnel oxide film. This invention can realize a reliable semiconductor device which is a single-layer gate semiconductor device by which a low-cost process is possible, has a control gate which can well withstand a high voltage applied when data is erased or written, and can prevent an operation error by minimizing variations in the threshold value. | 2010-04-15 |
20100090267 | Nonvolatile memory devices and methods of forming the same - Nonvolatile memory devices and methods of forming the same are provided, the nonvolatile memory devices may include first regions and second regions which extend in a first direction and are alternately disposed in a semiconductor substrate along a second direction crossing the first direction. Buried doped lines are formed at the first regions respectively and extend in the first direction. The buried doped lines may be doped with a dopant of a first conductivity type. Bulk regions doped with a dopant of a second conductivity type and device isolation patterns are disposed along the second direction. The bulk regions and the device isolation patterns may be formed in the second regions. Word lines crossing the buried doped lines and the bulk regions are formed parallel to one another. Contact structures are connected to the buried doped lines and disposed between the device isolation patterns. Sidewalls of the device isolation patterns disposed in the first direction overlap with the word lines directly adjacent to the contact structures. | 2010-04-15 |
20100090268 | SEMICONDUCTOR DEVICE AND MEMORY - A memory applicable to an embedded memory is provided. The memory includes a substrate, a gate, a charge-trapping gate dielectric layer, a source, and a drain. The gate is disposed above the substrate. The charge-trapping gate dielectric layer is disposed between the gate and the substrate. The source and the drain are disposed in the substrate beside the gate respectively. | 2010-04-15 |
20100090269 | TRANSISTOR STRUCTURE HAVING A TRENCH DRAIN - A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength. | 2010-04-15 |
20100090270 | TRENCH MOSFET WITH SHORT CHANNEL FORMED BY PN DOUBLE EPITAXIAL LAYERS - A power MOS device includes double epitaxial (P/N) structure is disclosed for reduction of channel length and better avalanche capability. In some embodiments, the power MOS device further includes an arsenic Ion implantation area underneath each rounded trench bottom to further enhance breakdown voltage and further reduce Rds, and the concentration of said arsenic doped area is higher than that of N-type epitaxial layer. As the gate contact trench could be easily etched over to penetrate the gate oxide, which will lead to a shortage of tungsten plug filled in gate contact trench to epitaixial layer, a terrace poly gate is designed in a preferred embodiment of present invention. By using this method, the gate contact trench is lifted to avoid the shortage problem. | 2010-04-15 |
20100090271 | Power Switching Semiconductor Devices Including Rectifying Junction-Shunts - A semiconductor device includes a drift layer having a first conductivity type and a body region adjacent the drift layer. The body region has a second conductivity type opposite the first conductivity type and forms a p-n junction with the drift layer. The device further includes a contactor region in the body region and having the first conductivity type, and a shunt channel region extending through the body region from the contactor region to the drift layer. The shunt channel region has the first conductivity type. The device further includes a first terminal in electrical contact with the body region and the contactor region, and a second terminal in electrical contact with the drift layer. The shunt channel region has a length, thickness and doping concentration selected such that: 1) the shunt channel region is fully depleted when zero voltage is applied across the first and second terminals, 2) the shunt channel becomes conductive at a voltages less than the built-in potential of the drift layer to body region p-n junction, and/or 3) the shunt channel is not conductive for voltages that reverse biase the p-n junction between the drift region and the body region. | 2010-04-15 |
20100090272 | TRANSISTOR STRUCTURE HAVING A CONDUCTIVE LAYER FORMED CONTIGUOUS IN A SINGLE DEPOSITION - A semiconductor device is formed having a pedestal. The pedestal includes at least two dielectric layers. The pedestal has a sidewall and a major surface. A conductive layer is formed overlying the pedestal. A vertical portion of the conductive layer adjacent to the sidewall of the pedestal is a gate of the transistor. The portion of the conductive layer overlying the major surface can be used as interconnect. The gate and gate interconnect are contiguous and formed in a single process. A conductive shield layer may be integrated into the pedestal. The conductive shield layer functions as a faraday shield that reduces gate to drain capacitance of the device. | 2010-04-15 |
20100090273 | TRANSISTOR STRUCTURE HAVING DUAL SHIELD LAYERS - A semiconductor device is formed having lower gate to drain capacitance. A trench ( | 2010-04-15 |
20100090274 | TRENCH MOSFET WITH SHALLOW TRENCH CONTACT - A trench MOSFET element with shallow trench contact is disclosed. This shallow trench contact structure has some advantages: blocking the P+ underneath trench contact from lateral diffusion to not touch to channel region when a larger trench contact CD is applied; avoiding the trench gate contact etching through poly and gate oxide when trench gate becomes shallow; making lower cost to refill the trench contact using Al alloys with good metal step coverage as the trench contact is shallower. The disclosed trench MOSFET element further includes an n* region around the bottom of gate trenches to reduce Rds. In some embodiment, the disclosed trench MOSFET provides a terrace gate to further reduce Rg and make self-aligned source contact; In some embodiment, the disclosed trench MOSFET comprises a P* area underneath said P+ region for avalanche energy improvement with lighter dose than said P+ region. | 2010-04-15 |
20100090275 | TRANSISTOR STRUCTURE HAVING AN ACTIVE REGION AND A DIELECTRIC PLATFORM REGION - A semiconductor device is formed having lower gate-to-drain capacitance. The semiconductor device having an active region ( | 2010-04-15 |
20100090276 | Shielded gate trench (SGT) MOSFET devices and manufacturing processes - This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench. The semiconductor power device further includes an insulation protective layer disposed on top of the semiconductor power device having a plurality of source openings on top of the source region and the source connecting trench provided for electrically connecting to the source metal and at least a gate opening provided for electrically connecting the gate pad to the trenched gate. | 2010-04-15 |
20100090277 | LATERAL TRENCH FETS (FIELD EFFECT TRANSISTORS) - A semiconductor structure and associated method of formation. The semiconductor structure includes a semiconductor substrate, a first doped transistor region of a first transistor and a first doped Source/Drain portion of a second transistor on the semiconductor substrate, a second gate dielectric layer and a second gate electrode region of the second transistor on the semiconductor substrate, a first gate dielectric layer and a first gate electrode region of the first transistor on the semiconductor substrate, and a second doped transistor region of the first transistor and a second doped Source/Drain portion of the second transistor on the semiconductor substrate. The first and second gate dielectric layers are sandwiched between and electrically insulate the semiconductor substrate from the first and second gate electrode regions, respectively. The first and second gate electrode regions are totally above and totally below, respectively, the top substrate surface. | 2010-04-15 |
20100090278 | High-Voltage Transistor with High Current Load Capacity and Method for its Production - An isolation area ( | 2010-04-15 |
20100090279 | METHOD FOR FABRICATING A TRANSISTOR USING A SOI WAFER - Embodiments relate to a method for fabricating a transistor by using a SOI wafer. A gate insulation layer and a first gate conductive layer on a silicon-on-insulator substrate of a substrate to form a first gate conductive pattern, a gate insulation layer pattern, and a silicon layer pattern. A device isolation insulation layer exposing the top surface of the first gate conductive layer pattern may be formed. A second gate conductive layer may be formed. A mask pattern may be formed. Then, a gate may be formed by etching. After forming a source and drain conductive layer on the silicon layer pattern, the mask pattern may be removed. A salicide layer may be selectively contacting the gate and the source and drain conductive layer may be formed. | 2010-04-15 |
20100090280 | Transistors, semiconductor memory cells having a transistor and methods of forming the same - Transistors, semiconductor memory cells having a transistor and methods of forming the same are provided, the transistors may include a semiconductor substrate having a first semiconductor region. A gate pattern may be disposed on the first semiconductor region. Spacer patterns may each be disposed on a sidewall of the gate pattern. Second semiconductor regions and a third semiconductor regions may be disposed in the semiconductor substrate. The second semiconductor regions may be disposed under the spacer patterns. The third semiconductor regions may be disposed adjacent to the second semiconductor regions. The first semiconductor region may have a higher impurity ion concentration than the second semiconductor regions. | 2010-04-15 |
20100090281 | Field Effect Transistor with Metal-Semiconductor Junction - A MOSFET transistor comprising a substrate of semiconductor material having a source junction connected to a source electrode, a drain junction connected to a drain electrode, and a gate layer connected to a gate electrode, the source junction or the drain junction being a metal-semiconductor junction. | 2010-04-15 |
20100090282 | SEMICONDUCTOR INTEGRATED CIRCUIT - The semiconductor integrated circuit has so-called SOI type first MOS transistors (MNtk, MPtk) and second MOS transistors (MNtn, MPtn). The first MOS transistors have a gate isolation film thicker than that the second MOS transistors have. The first and second MOS transistors constitute a power-supply-interruptible circuit ( | 2010-04-15 |
20100090283 | Electro Static Discharge Protection Device - A semiconductor device for protecting against an electro static discharge is disclosed. In one embodiment, the semiconductor device includes a first low doped region disposed in a substrate, a first heavily doped region disposed within the first low doped region, the first heavily doped region comprising a first conductivity type, and the first low doped region comprising a second conductivity type, the first and the second conductivity types being opposite, the first heavily doped region being coupled to a node to be protected. The semiconductor device further includes a second heavily doped region coupled to a first power supply potential node, the second heavily doped region being separated from the first heavily doped region by a portion of the first low doped region, and a second low doped region disposed adjacent the first low doped region, the second low doped region comprising the first conductivity type. A third heavily doped region is disposed in the second low doped region, the third heavily doped region comprising the second conductivity type and being coupled to a second power supply potential node. | 2010-04-15 |
20100090284 | METAL-OXIDE-SEMICONDUCTOR DEVICE - A metal-oxide-semiconductor device includes a substrate, a gate on the substrate, a source in the substrate and adjacent to one side of the gate, a drain in the substrate and adjacent to another side of the gate, a gate channel in the substrate and under the gate, and a gate insulator between the source and the drain and the gate and the gate channel, wherein the gate insulator has a substantially uneven thickness for use in electrostatic discharge (ESD) protection. | 2010-04-15 |
20100090285 | Integrated Circuit with a Contact Structure Including a Portion Arranged in a Cavity of a Semiconductor Structure - An integrated circuit includes a contact structure with a buried first and a protruding second portion. The buried first portion is arranged in a cavity formed in a semiconductor structure and is in direct contact with the semiconductor structure. The protruding second portion is arranged above the main surface of the semiconductor structure and in direct contact with a conductive structure that is spaced apart from or separated from the main surface of the semiconductor structure. An insulator structure is arranged below and in direct contact with the contact structure. | 2010-04-15 |
20100090286 | Vertical-type semiconductor device and method of manufacturing the same - A vertical-type semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region, a wordline structure on the cell region of the semiconductor substrate, the wordline structure including a plurality of wordlines stacked on top of each other, a semiconductor structure through the wordline structure, a gate dielectric between the wordline structure and the semiconductor structure, and a dummy wordline structure on the peripheral circuit region, the dummy wordline structure having a vertical structure and including same components as the wordline structure. | 2010-04-15 |
20100090287 | ELECTRONIC DEVICE WITH A GATE ELECTRODE HAVING AT LEAST TWO PORTIONS - A transistor structure of an electronic device can include a gate dielectric layer and a gate electrode. The gate electrode can have a surface portion between the gate dielectric layer and the rest of the gate electrode. The surface portion can be formed such that another portion of the gate electrode primarily sets the effective work function in the finished transistor structure. | 2010-04-15 |
20100090288 | METHOD OF FORMING SOURCE AND DRAIN OF A FIELD-EFFECT-TRANSISTOR AND STRUCTURE THEREOF - A semiconductor fabrication method involving the use of eSiGe is disclosed. The eSiGe approach is useful for applying the desired stresses to the channel region of a field effect transistor, but also can introduce complications into the semiconductor fabrication process. Embodiments of the present invention disclose a two-step fabrication process in which a first layer of eSiGe is applied using a low hydrogen flow rate, and a second eSiGe layer is applied using a higher hydrogen flow rate. This method provides a way to balance the tradeoff of morphology, and fill consistency when using eSiGe. Embodiments of the present invention promote a pinned morphology, which reduces device sensitivity to epitaxial thickness, while also providing a more consistent fill volume, amongst various device widths, thereby providing a more consistent eSiGe semiconductor fabrication process. | 2010-04-15 |
20100090289 | SEMICONDUCTOR DEVICES HAVING FACETED SILICIDE CONTACTS, AND RELATED FABRICATION METHODS - The disclosed subject matter relates to semiconductor transistor devices and associated fabrication techniques that can be utilized to form silicide contacts having an increased effective size, relative to conventional silicide contacts. A semiconductor device fabricated in accordance with the processes disclosed herein includes a layer of semiconductor material and a gate structure overlying the layer of semiconductor material. A channel region is formed in the layer of semiconductor material, the channel region underlying the gate structure. The semiconductor device also includes source and drain regions in the layer of semiconductor material, wherein the channel region is located between the source and drain regions. Moreover, the semiconductor device includes facet-shaped silicide contact areas overlying the source and drain regions. | 2010-04-15 |
20100090290 | SEMICONDUCTOR DEVICE HAVING REDUCED STANDBY LEAKAGE CURRENT AND INCREASED DRIVING CURRENT AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate having an active region which includes a gate forming zone and an isolation region; an isolation layer formed in the isolation region of the semiconductor substrate to expose side surfaces of a portion of the active region including the gate forming zone, such that the portion of the active region including the gate forming zone constitutes a fin pattern; a silicon epitaxial layer formed on the active region including the fin pattern; and a gate formed to cover the fin pattern on which the silicon epitaxial layer is formed. | 2010-04-15 |
20100090291 | TRANSISTOR STRUCTURE HAVING REDUCED INPUT CAPACITANCE - A semiconductor device having reduced input capacitance is disclosed. The semiconductor device includes a pedestal region having a gate overlying a sidewall of the pedestal region and gate interconnect overlying a major surface of the pedestal region. The pedestal region includes a conductive shield layer ( | 2010-04-15 |
20100090292 | Semiconductor device and method of manufacturing same - A method of manufacturing a semiconductor device, comprises: forming a high dielectric gate insulating film in an nMIS formation region and a pMIS formation region of a semiconductor substrate; forming a first metal film on the high dielectric gate insulating film, the first metal film; removing the first metal film in the nMIS formation region; forming a second metal film on the high dielectric gate insulating film of the nMIS formation region and on the first metal film of the pMIS formation region; and processing the first metal film and the second metal film. The high dielectric gate insulating film has a dielectric constant higher than a dielectric constant of silicon oxide. The first metal film does not contain silicon and germanium. The second metal film contains at least one of silicon and germanium. | 2010-04-15 |
20100090293 | SELF-ALIGNED NANO FIELD-EFFECT TRANSISTOR AND ITS FABRICATION - Our invention discloses a self-aligned-gate structure for nano FET and its fabrication method. One dimension semiconductor material is used as conductive channel, whose two terminals are source and drain electrodes. Gate dielectric grown by ALD covers the area between source electrode and drain electrode, opposite sidewalls of source electrode and drain electrode, and part of upper source electrode and drain electrode. Gate electrode is deposited on gate dielectric by evaporation or sputtering. Total thickness of gate dielectric and electrode must less than source electrode or drain electrode. Gate electrode between source electrode and drain electrode is electrically separated from source and drain electrode by gate dielectric. The fabrication process of this self-aligned structure is simple, stable, and has high degree of freedom. Nearly the whole conductive channel between source electrode and drain electrode is covered by gate electrode, so the control efficiency of the gate over the conductive channel, described as transconductance, can be greatly enhanced. Additionally, there is no restriction on material of gate dielectric or electrode, so the devices' threshold voltage can be adjusted to satisfy the requirements of large scale integrated circuit. | 2010-04-15 |
20100090294 | TAILORING NITROGEN PROFILE IN SILICON OXYNITRIDE USING RAPID THERMAL ANNEALING WITH AMMONIA UNDER ULTRA-LOW PRESSURE - A method of forming a dielectric film that includes nitrogen. The method includes incorporating nitrogen into a dielectric film using a nitridation gas and a rapid thermal annealing process, wherein an ultra-low pressure of equal to or less than about 10 Torr is used for the rapid thermal annealing process. | 2010-04-15 |
20100090295 | Folded lead-frame packages for MEMS devices - The MEMS package comprises a first and a second pre-molded lead-frame substrate, at least one of them having a cavity formed by plastic sidewalls along its periphery. The first and second pre-molded lead-frame substrates are interconnected with metal leads. At least one MEMS device is attached to one of the substrates. The first pre-molded lead-frame substrate is folded over and joined to the second pre-molded lead-frame substrate to house the at least one MEMS device. In one embodiment, the first pre-molded lead-frame substrate has metal leads extending outside of sidewalls of the cavities. The extended metal leads are folded over the top of the second pre-molded lead-frame substrate to form surface mounting pads. In some embodiments, extended metal leads are folded along the sidewalls and connected to ground for electromagnetic interference (EMI) shielding. | 2010-04-15 |