15th week of 2021 patent applcation highlights part 53 |
Patent application number | Title | Published |
20210111142 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device and a method of manufacturing the same are provided. The display device includes a first electrode disposed on a substrate, an adhesive auxiliary layer disposed on the first electrode and including a self-assembled monolayer, a light emitting element disposed on the adhesive auxiliary layer, and a contact electrode disposed between the adhesive auxiliary layer and the light emitting element. The light emitting element includes a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, and an intermediate layer disposed between the first semiconductor layer and the second semiconductor layer. | 2021-04-15 |
20210111143 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor die with a metallization layer including a first metal with a comparatively high melting point, a die carrier including a second metal with a comparatively high melting point, a first intermetallic compound arranged between the semiconductor die and the die carrier and including the first metal and a third metal with a comparatively low melting point, a second intermetallic compound arranged between the first intermetallic compound and the die carrier and including the second metal and the third metal, and precipitates of a third intermetallic compound arranged between the first intermetallic compound and the second intermetallic compound and including the third metal and a fourth metal with a comparatively high melting point. | 2021-04-15 |
20210111144 | Systems and Processes for Increasing Semiconductor Device Reliability - A system configured to increase a reliability of electrical connections in a device. The system including a lead configured to electrically connect a pad of at least one support structure to a pad of at least one electrical component. The lead includes an upper portion that includes a lower surface arranged on a lower surface thereof. The lower surface of the upper portion is arranged vertically above a first upper surface of a first pad connection portion; and the lower surface of the upper portion is arranged vertically above a second upper surface of the second pad connection portion. A process configured to increase a reliability of electrical connections in a device is also disclosed. | 2021-04-15 |
20210111145 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a substrate and a semiconductor chip, a lower conductive layer and an upper conductive layer sequentially stacked on the substrate. The substrate includes first and second connection pads formed thereon. The semiconductor chip includes third and fourth connection pads formed thereon. The upper conductive layer is connected to the first and the third connection pads via a first and a second wiring, and the lower conductive layer is connected to the second and the fourth connection pads via a third and a fourth wiring. | 2021-04-15 |
20210111146 | CUPD WIRE BOND CAPILLARY DESIGN - A capillary for performing ball bonding includes a body defining a lumen, a first blade defined in a lower tip of the body, and a second blade defined in the lower tip of the body for increasing reliability of a ball bonding procedure performed using the capillary. | 2021-04-15 |
20210111147 | MICROELECTRONIC ASSEMBLIES - Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects. | 2021-04-15 |
20210111148 | METHOD OF USING OPTOELECTRONIC SEMICONDUCTOR STAMP TO MANUFACTURE OPTOELECTRONIC SEMICONDUCTOR DEVICE - A method of using an optoelectronic semiconductor stamp to manufacture an optoelectronic semiconductor device comprises the following steps: a preparation step: preparing at least one optoelectronic semiconductor stamp group and a target substrate, wherein each optoelectronic semiconductor stamp group comprises at least one optoelectronic semiconductor stamp, each optoelectronic semiconductor stamp comprises a plurality of optoelectronic semiconductor components disposed on a heat conductive substrate, each optoelectronic semiconductor component has at least one electrode, and the target substrate has a plurality of conductive portions; an align-press step: aligning and attaching at least one optoelectronic semiconductor stamp to the target substrate, so that the electrodes are pressed on the corresponding conductive portions; and a bonding step: electrically connecting the electrodes to the corresponding conductive portions. | 2021-04-15 |
20210111149 | METHOD FOR PRODUCING A STABLE SANDWICH ARRANGEMENT OF TWO COMPONENTS WITH SOLDER SITUATED THEREBETWEEN - A method for producing a stable sandwich arrangement of two components with solder situated therebetween, comprising the steps: | 2021-04-15 |
20210111150 | METHODS AND STRUCTURES FOR DIE-TO-DIE BONDING - Embodiments of die-to-die bonding schemes of three-dimensional (3D) memory devices are provided. In an example, a method for bonding includes dicing one or more device wafers to obtain a plurality of dies, placing at least one first die of the plurality of dies onto a first carrier wafer and at least one second die of the plurality of dies onto a second carrier wafer, and bonding the at least one first die each with a respective second die. The at least one first die and the at least one second die each are functional. In some embodiments, the method also includes removing, respectively, the first carrier wafer and the second carrier wafer to form a plurality of bonded semiconductor devices each having one of the first dies and the respective second die. | 2021-04-15 |
20210111151 | THIN BONDED INTERPOSER PACKAGE - Methods and systems for a thin bonded interposer package are disclosed and may, for example, include bonding a semiconductor die to a first surface of a substrate, forming contacts on the first surface of the substrate, encapsulating the semiconductor die, formed contacts, and first surface of the substrate using a mold material while leaving a top surface of the semiconductor die not encapsulated by mold material, forming vias through the mold material to expose the formed contacts. A bond line may be dispensed on the mold material and the semiconductor die for bonding the substrate to an interposer. A thickness of the bond line may be defined by standoffs formed on the top surface of the semiconductor die. | 2021-04-15 |
20210111152 | SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPS - A semiconductor package includes a base substrate; a printed circuit board disposed on the base substrate; a first chip stack disposed on the base substrate on one side of the printed circuit board, and including first semiconductor chips offset-stacked in a first offset direction facing the printed circuit board; a second chip stack disposed on the first chip stack, and including second semiconductor chips offset-stacked in a second offset direction facing away from the printed circuit board; a third chip stack disposed on the base substrate on the other side of the printed circuit board, and including third semiconductor chips offset-stacked in the second offset direction; and a fourth chip stack disposed on the third chip stack, and including fourth semiconductor chips offset-stacked in the first offset direction, wherein the second and fourth chip stacks are electrically connected with the base substrate through the printed circuit board. | 2021-04-15 |
20210111153 | MULTI-CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip. | 2021-04-15 |
20210111154 | MICROELECTRONIC ASSEMBLIES WITH COMMUNICATION NETWORKS - Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die. | 2021-04-15 |
20210111155 | MICROELECTRONIC ASSEMBLIES - Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects. | 2021-04-15 |
20210111156 | MICROELECTRONIC ASSEMBLIES - Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects. | 2021-04-15 |
20210111157 | LED IMAGE DISPLAY DEVICE - The invention concerns a display device including a transfer substrate ( | 2021-04-15 |
20210111158 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a first die, a second die, and a first conductive via. The first die includes a first dielectric layer and a first landing pad embedded in the first dielectric layer. The second die includes a second dielectric layer and a second landing pad embedded in the second dielectric layer. The first die is disposed on the second die. The second landing pad has a through-hole. The first conductive via extends from the first landing pad toward the second landing pad and penetrates through the through-hole of the second landing pad. | 2021-04-15 |
20210111159 | SEMICONDUCTOR PACKAGE INCLUDING A FILLET LAYER - A semiconductor package includes a base substrate having a first semiconductor substrate, and a first protective layer covering a top side thereof. A first semiconductor chip is on the first protective layer. A first fillet layer fills a space between the first protective layer and the first semiconductor chip. A first side surface of the base substrate extends in a first direction, and second and third side surfaces extend in a second direction. The base substrate includes two corner regions and a side region between the corner regions. A first protective layer in the side region includes a first side trench which overlaps the first semiconductor chip. A part of the first fillet layer fills the first side trench. | 2021-04-15 |
20210111160 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a base substrate, a first semiconductor chip on the base substrate, a dam structure on the base substrate and surrounding the first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a non-conductive film, and a molding member. The non-conductive film may be between the base substrate, the first semiconductor chip, and the second semiconductor chip. The molding member may cover the base substrate, the first semiconductor chip, and the second semiconductor chip. A level of an upper surface of the first semiconductor chip and a level of an upper surface of the dam structure may be at a same level. | 2021-04-15 |
20210111161 | DIFFUSED BITLINE REPLACEMENT IN STACKED WAFER MEMORY - Techniques are disclosed herein for creating metal BLs in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures. | 2021-04-15 |
20210111162 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A display device including light emitting modules having signal lines and common lines arranged thereon, each including light emitting diodes mounted on an upper surface thereof and electrically connected to the signal lines and the common lines, respectively, a motherboard coupled to the light emitting modules, and a bonding layer having electrical conductivity and coupling the light emitting modules to the motherboard, in which each of the light emitting modules includes signal line terminals and common line terminals disposed on a lower surface thereof and electrically connected to the signal lines and the multiple common lines, respectively, and the motherboard includes board signal line terminals and board common line terminals disposed on an upper surface thereof at locations corresponding to the signal line terminals and the common line terminals of the light emitting modules. | 2021-04-15 |
20210111163 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A semiconductor package includes a first redistribution layer. A plurality of posts is disposed on the first redistribution layer. A semiconductor chip is disposed on the first redistribution layer between the plurality of posts. A second redistribution layer is formed on the plurality of posts and the semiconductor chip. A first memory stack is disposed on the second redistribution layer. A height of each of the plurality of posts extends from an upper surface of the first redistribution layer to a lower surface of the second redistribution layer. | 2021-04-15 |
20210111164 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING ELECTRONIC DEVICE - The disclosure provides an electronic device and a method of manufacturing an electronic device. The electronic device includes a first substrate, a plurality of light-emitting dies, a transparent material layer, a sealing material, and a second substrate. The plurality of light-emitting dies are disposed on the first substrate. The transparent material layer is disposed on the first substrate. The sealing material is disposed on the first substrate and surrounds the transparent material layer. The second substrate is adhered to the first substrate through the transparent material layer and the sealing material. | 2021-04-15 |
20210111165 | DEVICE ASSEMBLY STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A device assembly structure includes a first device and at least one second device. The first device has a first active surface and a first backside surface opposite to the first active surface, and includes a plurality of first electrical contacts disposed adjacent to the first active surface. The second device has a second active surface and a second backside surface opposite to the second active surface, and includes a plurality of second electrical contacts disposed adjacent to the second active surface. The second active surface of the second device faces the first active surface of the first device, the second electrical contacts of the second device are electrically connected to the first electrical contacts of the first device, and a thickness of the second device is less than or equal to one fifth of a thickness of the first device. | 2021-04-15 |
20210111166 | MICROELECTRONIC ASSEMBLIES HAVING AN INTEGRATED CAPACITOR - Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar. | 2021-04-15 |
20210111167 | STRETCHABLE DISPLAY DEVICE - According to an aspect of the present disclosure, a stretchable display device includes a lower substrate. A plurality of first substrates is disposed on the lower substrate and includes a plurality of pixels, and a plurality of connection lines electrically connects the plurality of pixels. A plurality of heat transfer lines overlap the plurality of connection lines, and a heat radiator is exposed to the outside and overlaps the plurality of connection lines and the plurality of heat transfer lines. By doing this, a heat radiation efficiency of the stretchable display device may be improved. | 2021-04-15 |
20210111168 | LIGHT EMITTING DIODE MODULE AND DISPLAY DEVICE HAVING THE SAME - Provided are a light emitting diode (LED) module that enables a freedom in structure design thereof using a fan-out interconnection and an insulating layer, and a display device having the same. The LED module having a multi-layer structure includes substrate; a LED located on the substrate and emitting light toward the substrate; a plurality of upper electrodes located on the LED and connected to the LED; an upper insulating layer provided to surround the plurality of upper electrodes; a film on glass (FOG) electrode located on the upper insulating layer; and a fan out interconnection structure configured to connect the plurality of upper electrodes to the FOG electrode through the upper insulating layer. | 2021-04-15 |
20210111169 | BEZEL-FREE DISPLAYS - A bezel-free display comprises a display substrate and an array of pixels. Pixel rows and pixel columns are separated by row and column distances and connected by row and column lines, respectively. A column driver is electrically connected to each of the column lines and a row driver is electrically connected to each of the row lines. Row-connection lines are electrically connected to each of the row lines or row drivers. In certain embodiments, each pixel in the column of pixels closest to a display substrate edge is spatially separated from the edge by a distance less than or equal to the column distance. At least one row driver is spatially separated from the corresponding row by a distance less than the column or row distance, at least one column driver is spatially separated from the corresponding column by a distance less than the column or row distance, or both. | 2021-04-15 |
20210111170 | MICROELECTRONIC ASSEMBLIES - Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects. | 2021-04-15 |
20210111171 | ELECTROSTATIC DISCHARGE HANDLING FOR SENSE IGBT USING ZENER DIODE - A main Insulated Gate Bipolar Transistor (IGBT) and a sense IGBT may have a sense resistor connected between a sense emitter of the sense IGBT and a main emitter of the main IGBT. Back-to-back Zener diodes may be connected between a sense gate of the sense IGBT and the sense emitter, and configured to clamp a voltage between the sense gate and the sense emitter during an electrostatic discharge (ESD) event. | 2021-04-15 |
20210111172 | ELECTROSTATIC PROTECTIVE ELEMENT AND ELECTRONIC DEVICE - The present technique relates to an electrostatic protective element that enables protective performance with respect to static electricity to be improved and to an electronic device. An electrostatic protective element includes: a first impurity region of a first conductivity type which is formed on the predetermined surface side of a semiconductor substrate; a second impurity region of a second conductivity type which is formed on the predetermined surface side of the semiconductor substrate so as to form a clearance in a horizontal direction with respect to the first impurity region; a collector contact which is formed on the predetermined surface side in the first impurity region, which has a higher concentration than the first impurity region, and which is an impurity region of the first conductivity type; a base contact which is formed on the predetermined surface side in the second impurity region, which has a higher concentration than the second impurity region, and which is an impurity region of the second conductivity type; and an emitter contact which is formed on the predetermined surface side in the second impurity region at a position that is closer to the collector contact than the base contact, which has a higher concentration than the second impurity region, and which is an impurity region of the first conductivity type. The present technique can be applied to, for example, an electronic device. | 2021-04-15 |
20210111173 | OFF CHIP DRIVER STRUCTURE - An off chip driver structure includes a plurality of pull-up transistors, a plurality of pull-down transistors, a plurality of first regions of a first type, a plurality of second regions of a second type and a plurality of resistor components. The first regions and the second regions are staggered to form an electrostatic discharge (ESD) component. One of the resistor components is coupled to one of the pull-up transistors or one of the pull-down transistors, the resistor components are arranged between the first regions and the second regions. | 2021-04-15 |
20210111174 | CIRCUIT-PROTECTION DEVICES - Circuit-protection devices might include first and second circuit-protection units each comprising a first node and a second node, a first field-effect transistor having a first source/drain connected to the first node of the first circuit-protection unit, and a second field-effect transistor having a first source/drain connected to the first node of the second circuit-protection unit, wherein a second source/drain of the first field-effect transistor merges with a second source/drain of the second field-effect transistor. | 2021-04-15 |
20210111175 | SEMICONDUCTOR DEVICE INCLUDING VERTICAL ROUTING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer. | 2021-04-15 |
20210111176 | Semiconductor Device and Method - A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess. | 2021-04-15 |
20210111177 | MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A method of fabricating a memory device includes forming an oxide layer on a semiconductor substrate, and forming an isolation structure in the semiconductor substrate and the oxide layer to define an active area. The method also includes forming a word line and a bit line in the semiconductor substrate, wherein the bit line is above the word line. The method further includes removing the oxide layer to form a recess between the isolation structure and the bit line, and forming a storage node contact in the recess. In addition, from a top view, the storage node contact of the memory device overlaps a corresponding portion of the active area. | 2021-04-15 |
20210111178 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having an active pattern, a cell region on the substrate and having a cell circuit, and a core region on the substrate having a peripheral circuit. In plan view, the active pattern on the core region includes a plurality of corners. Each of the corners has a rounding index that is equal to or less than about 15 nm. The rounding index is a distance between a respective tip of each of the corners and a right-angled corner. | 2021-04-15 |
20210111179 | 3D-FERROELECTRIC RANDOM ACCESS MEMORY (3D-FRAM) - A memory device comprises a bitline along a first direction. A wordline is along a second direction orthogonal to the first direction. An access transistor is coupled to the bitline and the wordline. A first ferroelectric capacitor is vertically aligned with and coupled to the access transistor. A second ferroelectric capacitor is vertically aligned with the first ferroelectric capacitor and coupled to the access transistor, wherein both the first ferroelectric capacitor and the second ferroelectric capacitor are controlled by the access transistor. | 2021-04-15 |
20210111180 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE AND CAPABLE OF CONTROLLING THICKNESSES OF DIELECTRIC LAYERS - A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a substrate; forming a second dielectric layer on the first dielectric layer; using a photomask to apply a photoresist to cover a first part of the second dielectric layer; removing a second part of the second dielectric layer while retaining the first part of the second dielectric layer; and removing the photoresist. The first part of the second dielectric layer covers a first part of the first dielectric layer in a first area. The second part of the second dielectric layer covers a second part of the first dielectric layer in a second area. The first area is corresponding to a memory device. The second area is corresponding to a logic device. | 2021-04-15 |
20210111181 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The present technology includes a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a first semiconductor layer, a cell stack and a peripheral stack each disposed on the first semiconductor layer, a first slit structure extending in a first direction and penetrating the cell stack and the peripheral stack, a penetration structure penetrating the peripheral stack and being spaced apart from the first slit structure, and a support structure penetrating the peripheral stack. The support structure includes first sidewall portions spaced apart from each other and a second sidewall portion connecting the first sidewall portions to each other, and the penetration structure is disposed between the first sidewall portions. | 2021-04-15 |
20210111182 | METHOD TO FABRICATE UNIFORM TUNNELING DIELECTRIC OF EMBEDDED FLASH MEMORY CELL - Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width. | 2021-04-15 |
20210111183 | DEVICE AND METHOD OF FORMING WITH THREE-DIMENSIONAL MEMORY AND THREE-DIMENSIONAL LOGIC - A method for forming a semiconductor device is provided. In the disclosed method, a stack is formed on a working surface of a substrate. The stack has alternating first layers and second layers positioned over the substrate. A separation structure is formed in the stack that separates the stack into a first region and a second region, where the separation structure extends in a first direction of the substrate. The second layers in the second region are further replaced with insulating layers, and the first layers in the second region are doped with a dopant. | 2021-04-15 |
20210111184 | Memory Arrays and Methods Used in Forming a Memory Array Comprising Strings of Memory Cells - A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. A wall is formed in individual of the trenches laterally-between immediately-laterally-adjacent of the memory-block regions. The forming of the wall comprises lining sides of the trenches with insulative material comprising at least one of an insulative nitride and elemental-form boron. A core material is formed in the trenches to span laterally-between the at least one of the insulative nitride and the elemental-form boron. Structure independent of method is disclosed. | 2021-04-15 |
20210111185 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION THEREOF - Aspects of the disclosure provide a semiconductor device and a method to manufacture the semiconductor device. A trench is formed in a stack over a substrate of the semiconductor device where the stack includes alternating first layers and second layers. The trench has a first sidewall and a second sidewall opposite to the first sidewall. Channel materials are formed along the first and second sidewalls of the trench, respectively. The trench is further divided into multiple units by replacing portions of the channel materials with first dielectric structures. Remaining portions of the channel materials along the first and second sidewalls form first and second channel structures of first and second strings of transistors, respectively. The second layers are replaced with first and second gate structures of the first and second strings of transistors, respectively. Each of the first and second strings of transistors is vertically stacked over the substrate. | 2021-04-15 |
20210111186 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device with improved product reliability and a method of fabricating the same is provided. The nonvolatile memory device comprises a substrate, a first mold structure disposed on the substrate and including a plurality of first gate electrodes, a second mold structure disposed on the first mold structure and including a plurality of second gate electrodes and a plurality of channel structures intersecting the first gate electrodes and the second gate electrodes by penetrating the first and second mold structures, wherein the first mold structure includes first and second stacks, which are spaced apart from each other, and the second mold structure includes a third stack, which is stacked on the first stack, a fourth stack, which is stacked on the second stack, and first connecting parts, which connect the third and fourth stacks. | 2021-04-15 |
20210111187 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device including a mold structure including a plurality of gate electrodes on a substrate, the plurality of gate electrodes including first, second, and third string selection lines sequentially stacked on the substrate; a channel structure that penetrates the mold structure and intersects each of the gate electrodes; a first cutting region that cuts each of the gate electrodes; a second cutting region that is spaced apart from the first cutting region in a first direction and cuts each of the gate electrodes; a first cutting line that cuts the first string selection line between the first cutting region and the second cutting region; a second cutting line that cuts the second string selection line between the first cutting region and the second cutting region; and a third cutting line that cuts the third string selection line between the first cutting region and the second cutting region. | 2021-04-15 |
20210111188 | MEMORY DEVICE - A memory device includes a substrate; a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers that are alternately stacked on the substrate in a vertical direction, the stacked structure including a row of cutouts, each of the cutouts extending in a first horizontal direction and being configured to cut the plurality of gate layers, the cutouts being apart from each other and arranged in a cell region of the stacked structure in the first horizontal direction; and a row of channel structures, the channel structures being arranged in the cell region in the first horizontal direction, each of the channel structures extending in the vertical direction to penetrate the plurality of gate layers. | 2021-04-15 |
20210111189 | NON-VOLATILE MEMORY DEVICE - According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction. | 2021-04-15 |
20210111190 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE - The present technology includes a semiconductor memory device. The semiconductor memory device includes a stack including a conductive pattern and an insulating pattern, a channel structure penetrating the stack, and a memory pattern between the conductive pattern and the channel structure. The memory pattern includes a blocking pattern, a tunnel pattern, a storage pattern, and a ferroelectric pattern. | 2021-04-15 |
20210111191 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - An array substrate includes: a base substrate; and a display region in which a signal line is provided and a fanout region provided on the base substrate, the fanout region including a first fanout line layer in which a first fanout line is provided, a second fanout line layer in which a second fanout line is provided, and one or more spacer layers between the first fanout line layer and the second fanout line layer; the signal line is connected to the first fanout line or the second fanout line; and the spacer layers are made of an insulating material; wherein an orthographic projection of the first fanout line on the base substrate and an orthographic projection of the second fanout line on the base substrate are at least partially overlapped with each other. A method of manufacturing an array substrate and a display device are also provided. | 2021-04-15 |
20210111192 | INTEGRATED POWER AMPLIFIER - The semiconductor structure includes a semiconductor-on-insulator (SOI) substrate. A group III nitride transistor is formed in a trench in the SOI substrate. The activation of the group III nitride transistor is controlled by a silicon-based transistor. The silicon-based transistor that includes a portion of a silicon layer of the SOI substrate. A group III nitride transistor device is adjacent to the silicon-based transistor. | 2021-04-15 |
20210111193 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The first gate insulating film is an insulating film made of silicon oxide, and to which hafnium (Hf) is added without addition of aluminum (Al). Also, the second gate insulating film is an insulating film made of silicon oxide, and to which aluminum is added without addition of hafnium. The third gate insulating film is an insulating film made of silicon oxide, and to which aluminum is added. Further, the fourth gate insulating film is an insulating film made of silicon oxide, and to which hafnium is added. Accordingly, it is possible to reduce the power consumption of the semiconductor device. | 2021-04-15 |
20210111194 | SEMICONDUCTOR DEVICE - Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor. | 2021-04-15 |
20210111195 | HIGH MOBILITY COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) DEVICES WITH FINS ON INSULATOR - The subject disclosure relates to high mobility complementary metal-oxide-semiconductor (CMOS) devices and techniques for forming the CMOS devices with fins formed directly on the insulator. According to an embodiment, a method for forming such a high mobility CMOS device can comprise forming, via a first epitaxial growth of a first material, first pillars within first trenches formed within a dielectric layer, wherein the dielectric layer is formed on a silicon substrate, and wherein the first pillars comprise first portions with defects and second portions without the defects. The method can further comprise forming second trenches within a first region of the dielectric layer, and further forming second pillars within the second trenches via a second epitaxial growth of one or more second materials using the second portions of the first pillars as seeds for the second epitaxial growth. | 2021-04-15 |
20210111196 | DISPLAY DEVICE - A high-definition display device is provided. A display device with low power consumption is provided. A highly reliable display device is provided. The display device includes a first transistor and a display element electrically connected to the first transistor. The first transistor includes a first oxide, a second oxide, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor and the second conductor are positioned over the first oxide to be apart from each other. The first insulator is positioned over the first conductor and the second conductor and includes an opening. The opening overlaps with a portion between the first conductor and the second conductor. The third conductor is positioned in the opening. The second insulator is positioned between the third conductor, and the first oxide, the first conductor, the second conductor, and the first insulator. The second oxide is positioned between the second insulator, and the first oxide, the first conductor, the second conductor, and the first insulator. | 2021-04-15 |
20210111197 | DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A display device includes: a substrate; a first active layer of a first transistor and a second active layer of a second transistor on the substrate; a first gate insulating layer on the first active layer; a first gate electrode on the first gate insulating layer; a second gate insulating layer on the second active layer; and a second gate electrode on the second gate insulating layer, wherein a hydrogen concentration of the first gate insulating layer is lower than a hydrogen concentration of the second gate insulating layer. | 2021-04-15 |
20210111198 | DISPLAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE INCLUDING THE SAME - A display substrate includes a substrate, a first gate electrode on the substrate, a first gate insulating layer on the first gate electrode, an active layer on the first gate insulating layer, a second gate insulating layer on the active layer, a second gate electrode on the second gate insulating layer, an interlayer insulating layer on the second gate electrode, a first electrode on the interlayer insulating layer to contact a top surface, a side wall, and a bottom surface of the active layer via a first contact hole through the interlayer insulating layer, the second gate insulating layer, the active layer, and a portion of the first gate insulating layer, and a second electrode on the interlayer insulating layer to contact the first gate electrode via a second contact hole through the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer. | 2021-04-15 |
20210111199 | MANUFACTURING METHOD OF DISPLAY SUBSTRATE, DISPLAY SUBSTRATE AND DISPLAY DEVICE - The present disclosure provides a manufacturing method of a display substrate, a display substrate and a display device, belongs to the field of display technology, and can at least partially solve a problem of residual sand in the display substrate. The manufacturing method of the display substrate includes: providing a base; forming a passivation layer on a surface of the base; forming an amorphous oxide conductive material layer on a surface of the passivation layer facing away from the base; forming a photoresist pattern on the oxide conductive material layer, the photoresist pattern having an exposure region; etching a portion of the oxide conductive material layer in the exposure region of the photoresist pattern to form a hollow position exposing a portion of the passivation layer; and removing a certain thickness material of the portion of the passivation layer exposed through the hollow position. | 2021-04-15 |
20210111200 | METHOD FOR PREPARING ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY PANEL - The present disclosure discloses a method for preparing an array substrate, an array substrate and a display panel, wherein the method comprises: forming a buffer layer on a substrate in a first region and a second region, wherein the buffer layer has a groove located in the second region; forming a first indium oxide thin film on the buffer layer in the first region; forming a second indium oxide thin film in the groove; performing a reduction process on the second indium oxide thin film to obtain indium particles; forming an amorphous silicon thin film in the groove, and inducing the amorphous silicon of the amorphous silicon thin film to form microcrystalline silicon at a preset temperature by using the indium particles; and removing the indium particles in the microcrystalline silicon to form a microcrystalline silicon semiconductor layer of the microcrystalline silicon thin film transistor. | 2021-04-15 |
20210111201 | Image Sensor Structure and Method of Forming the Same - An image sensor structure including: a substrate, having a first conductive type; a first well region and a second well region disposed in the substrate and spaced apart; an isolation region disposed in the first well region; a gate disposed on the substrate and between the first well region and the second well region; and a pinned photodiode disposed in the substrate and between the first well region and the second well region is provided. The pinned photodiode includes: a first doping region disposed in the substrate and having a first doping concentration and the first conductive type; and a second doping region disposed on the first doping region and having a second doping concentration opposite to the first conductive type. One or both of the first doping region and the second doping region is non-uniform and the first doping concentration is greater than the second doping concentration. | 2021-04-15 |
20210111202 | SEMICONDUCTOR DEVICE - An image sensor is provided. The image sensor includes a substrate and a conductive line pattern. The substrate includes an isolation pattern that extends from a bottom surface of the substrate into the substrate and defines pixel regions, and a photoelectric conversion region and a transistor for each of the pixel regions. The conductive line pattern is disposed on a top surface of the substrate, and vertically overlaps the isolation pattern in plan view and electrically connects to transistors of two or more of the pixel regions. | 2021-04-15 |
20210111203 | BACK-LIT IMAGE SENSOR AND PREPARATION THEREOF - A back-lit image sensor and a method for manufacturing the back-lit image sensor; the back-lit image sensor comprises a photoreceptor portion and a circuit portion, wherein the photoreceptor portion comprises: a microlens and a light filter incident photons entering the back-lit image sensor first by means of the microlens and then passing through the light filter; a transparent conductive film, which is located below the microlens and the light filter, the incident photons continuing to enter by means of the transparent conductive film; and a first substrate, which is located below the transparent conductive film and which is used for capturing and detecting received photons; a heterojunction is formed between the transparent conductive film and the first substrate. | 2021-04-15 |
20210111204 | SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE, AND ELECTRONIC EQUIPMENT - The present technology relates to a semiconductor device, a solid-state imaging device, and electronic equipment, which are able to suppress increase of resistivity to a high level at a connection portion between an ESV and a wiring layer and to improve reliability of an electric connection using an ESV. The semiconductor device according to a first aspect of the present technology has a plurality of semiconductor substrates layered, and includes: a through electrode penetrating a silicon layer of the semiconductor substrates; a wiring layer formed inside the semiconductor substrates; and a through electrode reception part connected to the wiring layer, in which the through electrode has a width smaller than the through electrode reception part, and the through electrode is electrically connected to the wiring layer via the through electrode reception part. The present technology is applicable, for example, to a CMOS image sensor. | 2021-04-15 |
20210111205 | OPTOELECTRONIC DEVICE HAVING A DIODE PUT UNDER TENSILE STRESS BY AN INVERSE PIEZOELECTRIC EFFECT - The invention relates to an optoelectronic device ( | 2021-04-15 |
20210111206 | MOIRE PATTERN IMAGING DEVICE - A moiré pattern imaging device includes a light-transmitting film and an optical sensor. The light-transmitting film includes a plurality of microlenses, and a light-incident surface and a light-exit surface opposite to each other. The plurality of microlenses are disposed on the light-incident surface, the light-exit surface or a combination thereof, and the plurality of microlenses are arranged in two dimensions to form a microlens array. The optical sensor includes a photosurface. The photosurface faces the light-exit surface of the light-transmitting film, the photosurface is provided with a plurality of pixels, and the plurality of pixels are arranged in two dimensions to form a pixel array. The microlens array and the pixel array correspondingly form a moiré pattern effect to produce an imaging magnification effect, and the photosurface of the optical sensor senses light and forms a moiré pattern magnification image. | 2021-04-15 |
20210111207 | IMAGE SENSOR WITH IMAGE RECEIVER AND AUTOMATIC IMAGE SWITCHING - Provided are an image sensor with one or more image receivers for image switching, and an imaging system and method therefor. The image sensor includes an image sensor array to generate first image data for a first image; a receiver to receive, into the image sensor, second image data for a second image; an image selection circuit coupled to the image sensor array and the receiver to receive the first image data and the second image data and select one of the first image data and the second image data according to one or more image selection criteria and at least one of the first image data and the second image data; and a transmitter coupled to the image selection circuit to transmit the selected one of the first image data and the second image data from the image sensor. | 2021-04-15 |
20210111208 | IMAGING APPARATUS AND CAMERA - In an apparatus, effective pixels of C×A-number composed of pixel rows of A-number and pixel columns of C-number or composed of the pixel rows of the C-number and the pixel columns of the A-number are arrayed in an effective pixel area of a chip, and images of a number not more than B-number are output from the chip for one second, wherein A, B and C are positive integers. The adhesive includes first, second, third, and fourth portions placed between a base body and the chip. The first and second portions are positioned between the third and fourth portions in the array direction of the pixel rows or columns. A gap is provided between the first and second portions, between the second and third portions, and between the first and fourth portions. The first and second portions are positioned between the effective pixel area and the base body. | 2021-04-15 |
20210111209 | OPTICAL FILTER ARRAY - A device may include a filter array disposed on a substrate. The filter array may include a first mirror disposed on the substrate. The filter array may include a plurality of spacers disposed on the first mirror. A first spacer, of the plurality of spacers, may be associated with a first thickness. A second spacer, of the plurality of spacers, may be associated with a second thickness that is different from the first thickness. A first channel corresponding to the first spacer and a second channel corresponding to the second spacer may be associated with a separation width of less than approximately 10 micrometers (μm). The filter array may include a second mirror disposed on the plurality of spacers. | 2021-04-15 |
20210111210 | IMAGE CAPTURE DEVICE - An image capture device includes a first housing, a second housing, a first integrated sensor-lens assembly (ISLA), and a second ISLA. The second housing is coupled to the first housing to form an internal compartment. The first ISLA includes a first image sensor coupled to a first lens in fixed alignment. The second ISLA includes a second image sensor coupled to a second lens in fixed alignment. The first ISLA is positively statically connected to the first housing, and the second ISLA is coupled to the first housing indirectly via the first ISLA. | 2021-04-15 |
20210111211 | IMAGE SENSOR - The present disclosure relates to an image sensor including a plurality of pixels formed in and on a semiconductor substrate and arranged in a matrix with N rows and M columns, with N being an integer greater than or equal to 1 and M an integer greater than or equal to 2. A plurality of microlenses face the substrate, and each of the microlenses is associated with a respective pixel. The microlenses are arranged in a matrix in N rows and M columns, and the pitch of the microlens matrix is greater than the pitch of the pixel matrix in a direction of the rows of the pixel matrix. | 2021-04-15 |
20210111212 | STACK CHIP AIR GAP HEAT INSULATOR - Image sensors include a pixel die that is stacked on a logic die. The logic die includes at least one function logic element disposed on a bond side thereof, and a logic oxide array of raised logic oxide features also disposed on the bond side. The pixel die includes a pixel array disposed on a light receiving side thereof, and a pixel oxide array of raised pixel oxide features disposed on a bond side of the pixel die. A plurality of outer bonds is disposed between an outer region of the logic die and an outer region of the pixel die. A plurality of inner bonds is formed at an inner region of the image sensor between the pixel oxide array and the logic oxide array, the inner bonds being spaced apart by a plurality of fluidly connected air gaps that extend between the logic die and the pixel die. | 2021-04-15 |
20210111213 | IMAGING DEVICE - An imaging device including: pixel area and a peripheral area that lies outside the pixel area; light receiving element provided in the pixel area; circuit board provided in the pixel area and the peripheral area, the circuit board including a semiconductor substrate and a multilayer wiring layer, the multilayer wiring layer being provided between the semiconductor substrate and the light receiving element; first wiring line provided in the multilayer wiring layer, the first wiring line being electrically coupled to the light receiving element; a protective member that is opposed to the circuit board, the protective member and the circuit board sandwiching the light receiving element; and an extended wiring section provided between the semiconductor substrate and the protective member in the peripheral area, one end of the extended wiring section being open and another end of the extended wiring section being electrically coupled to the first wiring line. | 2021-04-15 |
20210111214 | ELECTRONIC DEVICE IMAGE SENSOR - An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers. | 2021-04-15 |
20210111215 | ELECTRONIC DEVICE IMAGE SENSOR - An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers. | 2021-04-15 |
20210111216 | BIOSENSOR AND METHOD OF DISTINGUISHING A LIGHT - A biosensor is provided. The biosensor includes a substrate, a first photodiode, a second photodiode, an angle-sensitive filter, and an immobilization layer. The first photodiode and the second photodiode are disposed in the substrate and define a first pixel and a second pixel, respectively. The first pixel and the second pixel receive a light. The angle-sensitive filter is disposed on the substrate. The immobilization layer is disposed on the angle-sensitive filter. | 2021-04-15 |
20210111217 | IMAGE SENSORS WITH SILVER-NANOPARTICLE ELECTRODES - Disclosed herein is an apparatus comprising: an array of avalanche photodiodes (APDs) or an absorption region comprising a semiconductor single crystal such as a CdZnTe single crystal or a CdTe single crystal. The apparatus may be configured to absorb radiation particles incident on an absorption region of the APDs or the semiconductor single crystal and to generate charge carriers. The apparatus may comprise an electrode comprising silver nanoparticles and being electrically connected to the absorption region of the APDs or the semiconductor single crystal. For the APDs, each of the APDs may comprise an amplification region, which may comprise a junction with an electric field in the junction. The electric field may be at a value sufficient to cause an avalanche of charge carriers entering the amplification region, but not sufficient to make the avalanche self-sustaining. The junctions of the APDs may be discrete. | 2021-04-15 |
20210111218 | IMAGING PANEL AND METHOD FOR MANUFACTURING SAME - Provided are an X-ray imaging panel capable of suppressing a leak current of a photoelectric conversion layer while reducing the number of steps for manufacturing the imaging panel, and a method for manufacturing the same. An imaging panel | 2021-04-15 |
20210111219 | Use of Surface Patterning for Fabricating a Single Die Direct Capture Dental X-ray Imaging Sensor - A device and process in which a single continuous depositional layer of a polycrystalline photoactive material is deposited on an integrated charge storage, amplification, and readout circuit with an irregular surface wherein the polycrystalline photoactive material is comprised of a II-VI semiconductor compound or alloys of II-VI compounds. | 2021-04-15 |
20210111220 | LIGHT-SHIELDED CAMERAS AND METHODS OF MANUFACTURE - A method for manufacturing light-shielded cameras includes forming a plurality of camera dies by dicing a camera wafer stack including (a) an image sensor wafer having a plurality of image sensors, (b) a cover glass bonded to the image sensor wafer, and (c) a lens wafer bonded to the cover glass and having a plurality of lenses, to form a plurality of camera dies. The method further includes, prior to the step of dicing, (i) from a first side of the image sensor wafer facing away from the cover glass and at least partly covered by an opaque layer, pre-cutting a sensor-cover wafer stack that includes the image sensor wafer and the cover glass, and (ii) depositing an opaque material in the pre-cuts. The method also includes, after the step of dicing, applying an opaque coating to second-side surfaces, of the camera dies, formed by the step of dicing. | 2021-04-15 |
20210111221 | IMAGE-SENSOR CHIP-SCALE PACKAGE AND METHOD FOR MANUFACTURE - A method for fabricating an image-sensor chip-scale package includes bonding, with temporary adhesive, a glass wafer to a device wafer including an array of image sensors. The method also includes forming an isolated-die wafer by removing, from the device wafer, each of a plurality of inter-sensor regions each located between a respective pair of image sensors of the array of image sensors. The isolated-die wafer includes a plurality of image-sensor dies each including a respective image sensor, of the array of image sensors, bonded to the glass wafer. The method also includes encapsulating the isolated-die wafer to form an encapsulated-die wafer; removing, from each of the plurality of image-sensor dies, a respective region of the glass wafer covering the respective image sensor; and singulating the encapsulated-die wafer. | 2021-04-15 |
20210111222 | PROCESS TO IMPROVE INTERFACE STATE DENSITY Dit ON DEEP TRENCH ISOLATION (DTI) FOR CMOS IMAGE SENSOR - Embodiments disclosed herein include CMOS image sensors and methods of forming such devices. In an embodiment, a method of forming a CMOS image sensor comprises pressurizing a chamber with a gas comprising hydrogen, and annealing a substrate in the pressurized chamber. In an embodiment the substrate comprises the CMOS image sensor. In an embodiment, the CMOS image sensor comprises a semiconductor body and a trench around a perimeter the semiconductor body, wherein the trench is filled with a high-k oxide that directly contacts the semiconductor body. In an embodiment, the method further comprises, depressurizing the chamber. | 2021-04-15 |
20210111223 | MAGNETORESISTIVE STACK WITH SEED REGION AND METHOD OF MANUFACTURING THE SAME - A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/−10%) and less than or equal to 60 Angstroms (+/−10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/−10%) or 30-50 atomic percent (+/−10%). | 2021-04-15 |
20210111224 | SEMICONDUCTOR DEVICE AND MEMORY CELL - A semiconductor device includes a first electrode, a second electrode, and an In-doped chalcogenide-based selector layer disposed between the first electrode and the second electrode, in which the In-doped chalcogenide-based selector layer has an In compound content of about 2 at. % to about 10 at. %. A memory cell including the In-doped chalcogenide-based selector layer is also provided. | 2021-04-15 |
20210111225 | STEEP-SWITCH FIELD EFFECT TRANSISTOR WITH INTEGRATED BI-STABLE RESISTIVE SYSTEM - Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, and a trench extending to the source/drain. A trench contact is formed in the trench in contact with the source/drain. A recess is formed in a portion of the trench contact below a top surface of the cap using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the trench contact. A source/drain contact is formed upon the BRS material, a portion of the trench contact, the BRS material, and a portion of the source/drain contact forming a reversible switch. | 2021-04-15 |
20210111226 | MEMORY ARRAY WITH GRADED MEMORY STACK RESISTANCES - Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component. | 2021-04-15 |
20210111227 | LIGHT EMITTING DEVICE, DISPLAY DEVICE, PHOTOELECTRIC CONVERSION DEVICE, ELECTRONIC DEVICE, ILLUMINATION DEVICE, AND MOBILE DEVICE - A light emitting device comprising a plurality of pixels is provided. Each of the plurality of pixels includes a light emitting element, a first transistor having a drain region connected to the light emitting element, and a second transistor having a drain region connected to a gate electrode of the first transistor. The plurality of pixels include a first pixel and a second pixel, which are adjacent to each other in a first direction. A source region of the second transistor of the first pixel and a source region of the second transistor of the second pixel share one diffusion region, and a source region, a gate electrode, and the drain region of the first transistor of the first and second pixels are sequentially arranged in one of a positive direction and a negative direction in the first direction. | 2021-04-15 |
20210111228 | DISPLAY DEVICE, METHOD FOR MANUFACTURING DISPLAY DEVICE, AND ELECTRONIC APPARATUS - In a display device, a reflection film and a semi-transmissive reflection film are disposed at a distance from each other, the distance differing depending on an emission color of a pixel, an organic layer and a cathode electrode being transparent are stacked between the reflection film and the semi-transmissive reflection film, the organic layer including a light emission layer, the semi-transmissive reflection film is formed on the cathode electrode, and the cathode electrode is formed to have a film thickness that differs depending on the emission color. | 2021-04-15 |
20210111229 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes a plurality of pixels including a first pixel and a second pixel. Each of the first pixel and the second pixel includes at least one red sub pixel, a plurality of green sub pixels, and at least one blue sub pixel. The red sub pixels and the blue sub pixels are aligned in a first direction, and the plurality of green sub pixels is disposed between the at least one red sub pixel and at least one blue sub pixel of each pixel. The red sub pixel, the plurality of green sub pixels, and the blue sub pixel of the first pixel form a first group, and the red sub pixel, the plurality of green sub pixels, and the blue sub pixel of the second pixel form a second group. | 2021-04-15 |
20210111230 | FOLDABLE DISPLAY DEVICE - A display device including: a sensor device; a display module to display an image and having a first through-hole in which the sensor device is positioned; and a bottom panel cover on one surface of the display module and having a second through-hole in which the sensor device is positioned. The first through-hole has breadth that increases from the one surface of the display module toward another surface of the display module opposite to the one surface of the display module. | 2021-04-15 |
20210111231 | DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF - A display apparatus includes a display area and a transmission area on a substrate, and an intermediate area arranged between the display area and the transmission area and including a first sub-intermediate area and a second sub-intermediate area between the first sub-intermediate area and the transmission area, and a number of layers of thin films stacked on the substrate in the first sub-intermediate area is different from a number of layers of thin films stacked on the substrate in the second sub-intermediate area. | 2021-04-15 |
20210111232 | LIGHT-EMITTING DISPLAY APPARATUS - A method of manufacturing a light-emitting display apparatus and a light-emitting display apparatus are provided. The method includes forming a first photosensitive layer on a conductive material layer, forming a pixel electrode by etching the conductive material layer by using the first photosensitive layer as a mask, ashing the first photosensitive layer disposed on the pixel electrode, forming a pixel defining layer that covers an edge portion of the pixel electrode and includes a first opening overlapping the ashed first photosensitive layer, removing the ashed first photosensitive layer disposed in the first opening, forming an intermediate layer including a functional layer and an emission layer on the pixel defining layer, and forming an opposite electrode on the intermediate layer. | 2021-04-15 |
20210111233 | METHOD OF MANUFACTURING TRANSPARENT DISPLAY DEVICE - A transparent display device including a base substrate, a plurality of pixels disposed on the base substrate, each pixel having an emission area and a transmission area transparent to external light, a circuit element layer disposed on the base substrate, a first electrode disposed on the circuit element layer and corresponding to the emission area, a pixel define layer disposed on the circuit element layer, the pixel define layer including a first sidewall defining the emission area and a second sidewall defining the transmission area, an emission layer disposed on the first electrode and corresponding to the emission area, and a second electrode disposed on the emission layer and including an opening that corresponds to the transmission area, in which the first sidewall is inclined at a first angle, and the second sidewall is inclined at a second angle greater than the first angle. | 2021-04-15 |
20210111234 | DISPLAY DEVICE HAVING A BENDING REGION - A display device includes a substrate having a first region in which an image is displayed, a second region in which an image is not displayed, and a bending region connecting the first region and the second region. The bending region is configured to bend along a bending axis which extends in a first direction. A plurality of pad terminals is disposed within the second region. A first width of the bending region, measured along the first direction, is narrower than a second width of the second region, measured along the first direction. | 2021-04-15 |
20210111235 | DISPLAY DEVICE, METHOD FOR MANUFACTURING DISPLAY DEVICE, AND ELECTRONIC APPARATUS - Provided is a display device in which more than one pixel is arranged in a two-dimensional matrix on a circuit board, the pixel including a light emission unit including a first electrode, an organic layer, and a second electrode that are stacked, in which the first electrode is disposed for each light emission unit, and a partition is formed between the first electrode and an adjacent first electrode, the organic layer and the second electrode are stacked on an entire surface including the first electrode and the partition, the first electrode is formed on an interlayer insulation film, and a reflection film is formed below the first electrode, the reflection film including a light reflecting surface disposed to be flush with a boundary plane on which different insulation materials are in contact with each other in the interlayer insulation film. | 2021-04-15 |
20210111236 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - The present disclosure discloses an organic light emitting display device. The organic light emitting display device includes a substrate, a driving transistor, a reflection electrode, a dielectric layer, a first and second electrode, and an organic light emitting layer. The driving transistor is in each of a plurality of pixel regions which are defined on the substrate. The reflection electrode is on the driving transistor, and is electrically connected to a gate electrode of the driving transistor. The dielectric layer is on the reflection electrode. The first electrode is on the dielectric layer, and is electrically connected to a source electrode of the driving transistor, and faces the reflection electrode. The organic light emitting layer is on the first electrode. The second electrode is on the organic light emitting layer. | 2021-04-15 |
20210111237 | DISPLAY APPARATUS, MANUFACTURING METHOD OF DISPLAY APPARATUS, AND ELECTRONIC DEVICE - A display apparatus including: a display region provided with a plurality of pixel portions; wires installed to the respective pixel portions within the display region from an outside of the display region for transmitting a signal to drive the respective pixel portions; connection pads provided on the outside of the display region and serving as input portions to provide the wires with a signal while electrically conducting with the wires; switch elements provided on the outside of the display region in a middle of the wires; and a light shielding covering portion shielding the switch elements from light and formed to cover the connection pads while electrically conducting with the connection pads. | 2021-04-15 |
20210111238 | DISPLAY DEVICE INCLUDING A SEALING AREA OVERLAPPING TRANSFER WIRINGS - A display device includes: an array substrate including a pixel array disposed on a display area, a first transfer wiring disposed on a peripheral area adjacent to the display area and electrically connected to the pixel array, a second transfer wiring disposed on the peripheral area adjacent to the display area and electrically connected to the pixel array, and a barrier member disposed between the first transfer wiring and the second transfer wiring, the barrier member including an inorganic insulation material; and a sealing member disposed between the array substrate and an encapsulation substrate to combine the array substrate with the encapsulation substrate, the sealing member contacting at least a portion of the first transfer wiring and the second transfer wiring. | 2021-04-15 |
20210111239 | DISPLAY DEVICE - A display device includes a signal line extending in a first direction, a first transistor configured to control a driving current, a light-emitting element electrically coupled to a second electrode of the first transistor, a second transistor electrically coupled to a first electrode of the first transistor and configured to transfer a data voltage, a first scan line electrically coupled to a gate electrode of the second transistor and extending in the first direction, a third transistor including a first electrode electrically coupled to the second electrode of the first transistor and a second electrode electrically coupled to a gate electrode of the first transistor and a second scan line electrically coupled to a gate electrode of the third transistor and extending in the first direction, wherein the second scan line overlaps one selected from among the signal line and the first scan line. | 2021-04-15 |
20210111240 | DISPLAY DEVICE INCLUDING A FLEXIBLE SUBSTRATE - A display device includes a substrate including a display area and a peripheral area disposed around the display area. The peripheral area includes a bending region and a contact region adjacent to the bending region. A first connection line includes a first portion disposed in the contact region, and a second portion disposed in both the bending region and the contact region, and including a first layer and a second layer. At least part of the second layer of the second portion overlaps the first layer of the second portion. In the contact region, the first layer of the second portion is electrically connected to the first portion, and the second layer of the second portion is electrically connected to the first layer of the second portion. | 2021-04-15 |
20210111241 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME - An electronic device including a base structure, a first pattern having at least one projection disposed on the base structure, a first conductive layer including a first portion disposed on the base structure and a second portion disposed on the first pattern and connected to the first portion, an insulating layer disposed on the first conductive layer covering the first portion and exposing the second portion, and a second conductive layer provided on the insulating layer and overlapping the first conductive layer. The second conductive layer is spaced apart from the first portion and is in contact with the second portion. Methods of manufacturing an electronic device capable of reducing the number of process steps in the manufacturing process are also disclosed. | 2021-04-15 |