16th week of 2009 patent applcation highlights part 13 |
Patent application number | Title | Published |
20090095921 | Device for Irradiating Tumour Tissue in a Patient With a Particle Beam - There is proposed a device for the slice-by-slice irradiation of tumour tissue ( | 2009-04-16 |
20090095922 | METHOD OF REPAIRING A POLYMER MASK - A method of repairing defects to a patterned polymer mask for a photolithography process is described, illustrated, and claimed. Generally, there are two types of defects to a polymer mask, which are an ink spot on a transparent polymer substrate and an ink void in a patterned area. The ink spot is repaired by an effective ablation by a laser that does not substantially affect a transparency of the polymer substrate. The ink void is repaired by various embodiments using laser-assisted touch-up processes, wherein the laser-assisted touch-up restores the void to block UV light during a photolithography exposure. | 2009-04-16 |
20090095923 | INSTALLATION AND METHOD OF NANOFABRICATION - Nanofabrication installation comprising: a specimen holder, for holding a specimen; a mask, having a through-opening between the upper and lower faces of the mask, for letting charged particles through onto the specimen holder; a near-field detection device for detecting a relative position between the mask ( | 2009-04-16 |
20090095924 | ELECTRODE DESIGN FOR EUV DISCHARGE PLASMA SOURCE - An apparatus for producing an extreme ultraviolet (EUV) discharge includes a metal source, a laser that produces a focused laser beam, and electrode operatively coupled to the metal source. The electrode includes a plurality of discrete metal retaining zones that deliver a controlled volume of metal into the focused laser beam to produce an EUV discharge plasma. | 2009-04-16 |
20090095925 | LPP EUV light source drive laser system - An apparatus and method is disclosed which may comprise a laser produced plasma EUV system which may comprise a drive laser producing a drive laser beam; a drive laser beam first path having a first axis; a drive laser redirecting mechanism transferring the drive laser beam from the first path to a second path, the second path having a second axis; an EUV collector optical element having a centrally located aperture; and a focusing mirror in the second path and positioned within the aperture and focusing the drive laser beam onto a plasma initiation site located along the second axis. The apparatus and method may comprise the drive laser beam is produced by a drive laser having a wavelength such that focusing on an EUV target droplet of less than about 100 μm at an effective plasma producing energy is not practical in the constraints of the geometries involved utilizing a focusing lens. The drive laser may comprise a CO | 2009-04-16 |
20090095926 | PHYSIOLOGICAL PARAMETER DETECTOR - A pulse oximetry sensor has an emitter adapted to transmit optical radiation into a tissue site and a ceramic detector adapted to receive optical radiation from the emitter after tissue site absorption. The detector is surrounded by shielding material to reduce undesirable electromagnetic interference. | 2009-04-16 |
20090095927 | THERMALLY ACTUATED VALVES, PHOTOVOLTAIC CELLS AND ARRAYS COMPRISING SAME, AND METHODS FOR PRODUCING SAME - Thermally actuated valves, photovoltaic cells and arrays comprising same, and methods for producing same are disclosed. In some embodiments, thermally actuated valves are provided, comprising: a first material defining at least one opening; and a beam attached to the first material so as to at least partially cover the at least one opening, wherein the first material and the beam comprise different thermal expansion properties, such that, when a temperature is applied to at least one of the first material and the beam, the beam buckles so as to at least partially uncover the at least one opening. In some embodiments, photovoltaic cells and arrays comprising thermally actuated valves, and methods for producing thermally actuated valves are provided. | 2009-04-16 |
20090095928 | SOLENOID VALVE FOR BRAKE SYSTEM - A solenoid valve for a brake system, which has a simplified configuration and can be easily manufactured with reduced manufacturing costs. The solenoid valve includes valve seat member integrally formed with a seat portion having a first orifice, an opening/closing member slidably installed in the valve seat member, the opening/closing member having an inner passage formed through the opening/closing member, an outer passage formed at an outer surface of the opening/closing member, a second orifice formed at one end of the opening/closing member, the second orifice having a smaller diameter than that of the first orifice, and a first opening/closing portion formed at the other end of the opening/closing member to open or close the first orifice, an opening spring to move the opening/closing member, for opening of the first orifice, a sleeve having a first end coupled to an outer surface of the valve seat member and a flange formed at the first end so as to be fixed to a modulator block, a valve core coupled to a second end of the sleeve, opposite to the first end of the sleeve, an armature slidably mounted in the sleeve, the armature having a second opening/closing portion to open or close the second orifice, and a restoring spring to press the armature toward the second orifice. | 2009-04-16 |
20090095929 | SOLENOID VALVE FOR BRAKE SYSTEM - A solenoid valve for a brake system enabling miniaturization of the valve and having an improved configuration to facilitate assembly and production of the valve. The solenoid valve includes an armature provided at one end thereof with an opening/closing member, a valve housing including a hollow first valve block fixed in a modulator block and a second valve block disposed below the first valve block and having an inlet for introduction of fluid, a valve seat installed in the first valve block and having a flow-hole to be opened or closed by the opening/closing member and a hollow extending longitudinally from the flow-hole, and an orifice sleeve located in the second valve block to define a fluid discharge passage and having an orifice formed in one end thereof to communicate with the hollow of the valve seat. | 2009-04-16 |
20090095930 | PNEUMATIC DEVICE CONTROL SYSTEM - A plurality of valve assemblies having a plurality of manifold valves assembled are electrically coupled in a row via lead wire assemblies to transmit a power signal for driving solenoids of the manifold valves in parallel from the valve assembly at a proximal side of the row to the valve assembly at a leading end side via the manifold valves of the valve assemblies and the lead wire assemblies. | 2009-04-16 |
20090095931 | Ball valve having self-centering seats - A trunnion type ball valve having valve seats that are laterally moveable within seat recesses of the valve and establish sealing engagement with a valve ball member that is trunnion supported for rotational movement between open and closed positions. The valve seat members are self-centering for optimum sealing engagement with the spherical sealing surface of the ball member. The internal geometry of the seat assemblies are designed to permit optimum flow through the valve mechanism even under circumstances where the seat members are located in laterally off-center relation with respect to the centerline of the flow passages due to self-centering seat movement. The ball valve is readily adapted for fire-safe application via the use of heat resistant seals and metal-to-metal sealing of components to prevent or minimize leakage in the event of seal destruction or degradation by excess heat. | 2009-04-16 |
20090095932 | Knife Gate Valve - A gate valve apparatus includes an inlet side panel, and outlet side panel defining a ring recess on its inner face. The panels are fastened together and the valve gate moves between the panels. A seat ring defines a seat ring aperture and is positioned in the ring recess and oriented such that fluid pushing on the front face of the gate seals the gate against the seat ring. Removable ring fasteners countersunk below the inner surface of the seat ring extend into the outlet side panel. Removable inlet and outlet wear rings are positioned in the corresponding inlet and outlet passages, and the inner end of the outlet wear ring extends into the seat ring aperture to cover the fastener heads. The inlet and outlet wear rings have an inside diameter equal to an inside diameter of the inlet and outlet conduits. | 2009-04-16 |
20090095933 | GATE VALVE WITH REPLACEABLE INSERTS AND METHOD OF REFURBISHING SAME - A gate valve includes a valve body having a cylindrical passage defining a flow path through the valve, a gate for controlling fluid flow through the valve and a replaceable wear-resistant flow-path liner for in the flow path. The flow-path liner includes a plurality of replaceable wear-resistant inserts, including wear sleeves lining ports of the valve body, valve seats and a gate insert for a flow path bore through the gate. Each replaceable valve seat has a wiper ring for cleaning the gate when it opens and closes. By regularly inspecting and replacing worn-out inserts, the service life of the gate valve can be prolonged and the expense associated with replacing or rebuilding the valve body is avoided. | 2009-04-16 |
20090095934 | PRESSURE RATED OIL FIELD GATE VALVE - The disclosure provides an efficient design for a pressure rated oil field gate valve that meets the challenges of providing a quality product with minimal increase in price due to the design. It minimizes weight increase in the valve body over valves not meeting strict pressure specifications, due to strengthening ribs at strategic places without having to increase the overall body size as in commonplace in the industry. It provides redundancy of seals with minimal costs and no change in seat pockets over valves not capable of meeting the higher standards. It provides multiple shear points along a valve stem that can still allow a user to operate the valve from external to the valve bonnet. It further provides for additional sealing of the valve bonnet to the valve body by using elasticity in metal over long lengths to maintain a compression seal between the bonnet and the body. | 2009-04-16 |
20090095935 | Irrigation valve - The present invention relates to a diaphragm valve, comprising: a valve body with an internal cavity and an inlet passage forming a continuous path of constant cross-section and minimal direction changes, allowing for less turbulent flow within the valve. The invention further comprises a valve cap mounted to a top of the valve body to cover the internal cavity, the valve cap comprising a solenoid port and a plurality of supporting ribs forming a continuous, channeled path allowing for reliable communication between the metering pin, the top of the diaphragm, and the solenoid port. | 2009-04-16 |
20090095936 | Fluoroalkenyl Poly[1,6]glycosides - Fire extinguishing compositions and methods of extinguishing a fire comprising compounds of formula (I) where R | 2009-04-16 |
20090095937 | Magnetic rubber composition for encoder - A magnetic rubber composition for encoder having a magnetic characteristic in sufficient application range, used as encoder after magnetization as well as heat resistance, water resistance and oil resistance required for use as encoder, and excellent processing property, and capable of being bonded by vulcanization with a metal, is provided. Furthermore, a magnetic rubber composition for encoder capable of obtaining sufficient magnetic force required for encoder on a circumference of the molded encoder as well as capable of effectively restraining variation of the level of magnetic force, is provided. It is provided by comprising 300 to 1,800 parts of strontium-ferrite, or 300 to 1,800 parts of barium-ferrite, or 300 to 1,800 parts of a mixture of strontium-ferrite and barium-ferrite, 0.5 to 2 parts of silane coupling agent, and 1 to 10 parts of lubricating agent, per 100 parts of a hydrogenated nitrile butadiene rubber with 15 to 50% of acrylonitrile amount and 80 to 99% of hydrogenation ratio. | 2009-04-16 |
20090095938 | APPARATUS FOR PRODUCING ALLOY AND RARE EARTH ELEMENT ALLOY - The object of the present invention is to provide an apparatus for producing an alloy, including: a casting device which casts a molten alloy using the strip cast method; a crushing device which crushes the cast alloy after casting; and a heating device which keeps the thin laminas of the cast alloy after crushing at a predetermined temperature or which heats the thin laminas of the cast alloy after crushing, wherein the heating device is equipped with a container and a heater. | 2009-04-16 |
20090095939 | Slurry Composition for Chemical Mechanical Polishing of Metal and Polishing Method Using the Same - Provided is a slurry composition for chemical mechanical polishing (CMP) of a metal. The slurry composition comprises a copolymer whose average molecular weight is from about 600,000 to about 1,300,000 and whose monomers are acrylic acid and acrylamide in a molar ratio of about 1:30 to about 30:1. The slurry composition exhibits a non-Prestonian behavior to achieve minimized dishing and attain a high degree of planarization. | 2009-04-16 |
20090095940 | High quantum yield infranred phosphors and methods of making phosphors - Embodiments of the present disclosure include Gd | 2009-04-16 |
20090095941 | MOISTURE-RESISTANT DEOXIDANT - A deoxidant composition comprising 100 parts by weight of iron powder, 0.01 to 20 parts by weight of metal halide and 0.01 to 5 parts by weight of water repellent agent. The deoxidant composition even when used in a high-humidity atmosphere can maintain oxygen absorption potency. A deoxidant pack for high humidity obtained by wrapping the deoxidant composition without mixing of any inorganic filler by means of an air-permeable packaging material can reduce the apparent volume of deoxidant composition, so that the amount of packaging material used in the production of the deoxidant pack can be reduced. | 2009-04-16 |
20090095942 | Positive Electrode Material for Lithium Secondary Battery - It is a first object of the present invention to provide a lithium secondary battery using a conductive polymer such as polyaniline, which exhibits a stable electrical conductivity over a long time. To achieve the first object, there is provided a positive electrode material for a lithium secondary battery, comprising an electrically conductive polymer having an amino group, a hydrogen bonding compound, and a protonic acid. Further, it is a second object of the present invention to provide a lithium secondary battery exhibiting a high charge-discharge capacity while using a conductive polymer such as polyaniline. To achieve the second object, there is provided a positive electrode material for a lithium secondary battery, comprising an electrically conductive polymer, and LiNiO | 2009-04-16 |
20090095943 | Carpet seam lock - A carpet seam clamping device for maintaining pre-positioned carpet sections abutted at a seam subsequent to removal of a carpet stretcher which prevents overlapping. The device employs a pair of planar surfaces which translate toward each other and lock in position once totally translated. The length of translation is equal to or less than the length of pins which engage into the carpet body thereby preventing overstretch. | 2009-04-16 |
20090095944 | LIFTING APPARATUS - A lifting apparatus for extending upwardly out of a commercial building roof hatch, including a ladder docking device surrounding the roof hatch and optionally including roof hatch grab bars for ease of emergence through the roof hatch. The roof hatch ladder docking device is rapidly and removably attached to a permanent vertical ladder attached to the interior of the building. The lifting apparatus includes a winch post, a pulley mounted on the winch post and the ladder attachment device includes a fixed lower ladder attachment bracket along with a sliding upper ladder attachment sleeved over the winch post. | 2009-04-16 |
20090095945 | Method and Use of High Tension Cable Barrier Clamp - The present invention is a portable clamp to facilitate the construction and post-impact repair of high tension cable median barrier systems. Such a clamp allows a single operator to manipulate a high tension cable in order to install the hook bolts necessary to maintain proper function of the barrier system, thereby reducing the number of required employees and costs associated with the installation and repair processes. | 2009-04-16 |
20090095946 | Silt Fence System And Method Of Manufacture - A silt fence with configurable barrier sections. The silt fence comprises a plurality of posts mounted on or in the ground, a fence panel, an apron panel, and a plurality of configurable barrier sections. The fence panel is secured in a vertical position to the posts and has a fence toe adapted to be buried in the ground. The apron panel is attached to the fence panel and extends from the fence panel to rest on the ground. An apron toe is also adapted to be buried in the ground to prevent erosion. Each of the plurality of configurable barrier sections has a panel edge and an apron edge, with the panel edge attachable to the fence panel perpendicular to the length of the fence panel and the apron edge attachable to the apron panel perpendicular to the length of the apron panel. The configurable barrier sections may be flexible or removable, and may be positioned in a barrier position or a cleaning position. In the cleaning position, accumulated silt or runoff is easily cleaned from the apron panel of the fence. | 2009-04-16 |
20090095947 | Fall protection assembly - A fall protection assembly is provided. The fall protection assembly may include a base member that is configured for attachment to a structure. The base member can have first and second upright pieces arranged with respect to one another so as to be capable of receiving at least a portion of a kick member therebetween. An upright support member can also be present and can be supported by the base member. The upright support member can be capable of supporting at least one cross member for use in fall prevention. | 2009-04-16 |
20090095948 | Programmable Resistive Memory with Diode Structure - Programmable resistive memory cells are accessed by semiconductor diode structures. Manufacturing methods and integrated circuits for programmable resistive elements with such diode structures are also disclosed. | 2009-04-16 |
20090095949 | Low Area Contact Phase-Change Memory - A memory device includes a first electrode and a second electrode. A phase-change material is disposed between the first and second electrodes. The phase-change material is in electrical communication with the first and second electrodes at a first contact region and a second contact region respectively. The first and second contact regions are similar in contact area. The device enables scaling of reset current to smaller dimensions without encountering a limitation imposed by an offset current. | 2009-04-16 |
20090095950 | Nanoscale Wire-Based Data Storage - The present invention generally relates to nanotechnology and submicroelectronic devices that can be used in circuitry and, in some cases, to nanoscale wires and other nanostructures able to encode data. One aspect of the invention provides a nanoscale wire or other nanostructure having a region that is electrically-polarizable, for example, a nanoscale wire may comprise a core and an electrically-polarizable shell. In some cases, the electrically-polarizable region is able to retain its polarization state in the absence of an external electric field. All, or only a portion, of the electricallypolarizable region may be polarized, for example, to encode one or more bits of data. In one set of embodiments, the electrically-polarizable region comprises a functional oxide or a ferroelectric oxide material, for example, BaTiO | 2009-04-16 |
20090095951 | Memory Device With Low Reset Current - An electronic device includes a first electrode and a second electrode. The device also includes a resistive material between the first and second electrodes. An active material is between the first electrode and the resistive material. The active material is in electrical communication with the first electrode and the active material is in electrical communication with the second electrode through the resistive layer. | 2009-04-16 |
20090095952 | Storage node, phase change memory device and methods of operating and fabricating the same - A storage node, a phase change memory device, and methods of operating and fabricating the same are provided. The storage node may include a lower electrode, a phase change layer on the lower electrode and an upper electrode on the phase change layer, and the lower electrode and the upper electrode may be composed of thermoelectric materials having a melting point higher than that of the phase change layer, and having different conductivity types. An upper surface of the lower electrode may have a recessed shape, and a lower electrode contact layer may be provided between the lower electrode and the phase change layer. A thickness of the phase change layer may be about 100 nm or less, and the lower electrode may be composed of an n-type thermoelectric material, and the upper electrode may be composed of a p-type thermoelectric material, or they may be composed on the contrary to the above. Seeback coefficients of the lower electrode, the phase change layer, and the upper electrode may be different from each other. | 2009-04-16 |
20090095953 | PHASE CHANGE MATERIALS AND ASSOCIATED MEMORY DEVICES - A memory device utilizes a phase change material as the storage medium. The phase change material includes at least one of Ge, Sb, Te, Se, As, and S, as well as a nitride compound as a dopant. The memory device can be a solid-state memory cell with electrodes in electrical communication with the phase change medium, an optical phase change storage device in which data is read and written optically, or a storage device based on the principle of scanning probe microscopy. | 2009-04-16 |
20090095954 | FIELD-EFFECT TRANSISTOR - A field-effect transistor is provided, which includes an organic thin film and which can realize a low threshold voltage while a stable, high field-effect mobility is ensured at the same time. In a field-effect transistor provided with a gate electrode, a source electrode, a drain electrode, a semiconductor film, a gate insulating film, and a substrate, the gate insulating film is formed from a plurality of insulating layers. Here, a first insulating layer in contact with the semiconductor film is formed from poly-p-xylylene formed into a film by a CVD method. A second insulating layer is formed from, for example, cyanoethylpullulan, and the dielectric constant is specified to be higher than that of the first insulating layer. | 2009-04-16 |
20090095955 | SEMICONDUCTOR INTEGRATED CIRCUIT AND TESTING METHOD THEREOF - A semiconductor integrated circuit including a detector and a secure checker. The detector generates a detection signal upon sensing an abnormal state in an operating environment of the semiconductor integrated circuit. The secure checker generates a check signal to find an operating condition of the detector and receives the detection signal. The detector activates the detection signal in response to the check signal. | 2009-04-16 |
20090095956 | SINGLE-CRYSTAL SILICON SUBSTRATE, SOI SUBSTRATE, SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device of the present invention is arranged in such a manner that a MOS non-single-crystal silicon thin-film transistor including a non-single-crystal silicon thin film made of polycrystalline silicon, a MOS single-crystal silicon thin-film transistor including a single-crystal silicon thin film, and a metal wiring are provided on an insulating substrate. With this arrangement, (i) a semiconductor device in which a non-single-crystal silicon thin film and a single-crystal silicon thin-film device are formed and high-performance systems are integrated, (ii) a method of manufacturing the semiconductor device, and (iii) a single-crystal silicon substrate for forming the single-crystal silicon thin-film device of the semiconductor device are obtained. | 2009-04-16 |
20090095957 | Display device and method of manufacturing display device - To provide a display device, including a polysilicon thin film transistor, which achieves a reduction of an off current with a simple configuration and with only a slight increase in a number of processes. A display device includes: an insulating substrate, and a thin film transistor formed on the insulating substrate, wherein a semiconductor layer of the thin film transistor has a polysilicon layer, a first amorphous silicon layer formed above the polysilicon layer, and a second amorphous silicon layer formed above the first amorphous silicon layer. | 2009-04-16 |
20090095958 | THIN FILM TRANSISTOR ARRAY AND DISPLAYING APPARATUS - A thin film transistor array is disclosed. The thin film transistor array includes plural gate electrodes formed on an insulation substrate, plural source electrodes formed above or under the gate electrodes via a gate insulation film so that the source electrodes cross the gate electrodes in a planar view, plural drain electrodes formed at corresponding positions surrounded by the gate electrodes and the source electrodes in a planar view in the same layer as that of the source electrodes, semiconductor layers formed via the gate insulation film to face the gate electrodes for forming corresponding channel regions between the source electrodes and the drain electrodes. The plural gate electrodes are linearly formed, and the channel regions are disposed to face the gate electrodes. | 2009-04-16 |
20090095959 | HEAT DISSIPATION DEVICE FOR LED CHIPS - A heat dissipation device for removing heat from LED chips includes a heat sink and a plurality of substrates. The heat sink comprises a base plate. A plurality of fins extends upwardly from the base plate. The substrates each have a unidirectional heat transfer and are attached to a bottom face of the heat sink. Each of the substrates defines a first wall on which The LED chips are mounted and a second wall coupled to the heat sink. The substrates only transfer heat from the first wall to the second wall and restrict the heat transfer in a reverse direction. When the LED chips generate heat, the heat is transferred to the fins of the heat sink via the unidirectional substrates to lower temperature of the LED chips. | 2009-04-16 |
20090095960 | HEAT DISSIPATION MEMBER, SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR LIGHT EMITTING APPARATUS - A heat dissipation member includes a first plate-shaped member and a second plate-shaped member. The first plate-shaped member has a first surface thermally connectable with a heat generating element and a second surface. The second plate-shaped member is thermally connected with the second surface of the first plate-shaped member. The first plate-shaped member and the second plate-shaped member form a laminated-plate-shaped member. The laminated-plate-shaped member defines an inlet for admission of a fluid and an outlet communicating with the inlet for ejection of the fluid. The second surface of the first plate-shaped member forms asperities thereon. | 2009-04-16 |
20090095961 | Combination of LED and heat dissipation device - A combination of LED and heat dissipating device includes a heat dissipating device, an electrically insulative thermal conductivity layer covered on a part of the surface of the heat dissipating device, thermal and electric conducting layers disposed at the electrically insulative thermal conductivity layer and electrically isolated from one another, LED units each having an LED unit installed in one thermal and electric conducting layer and a lead wire that connects the LED chip of the respective LED unit to the LED chip of another LED unit, and a packaging device covering the LED units. | 2009-04-16 |
20090095962 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING DISPLAY APPARATUS, APPARATUS OF MANUFACTURING SEMICONDUCTOR DEVICE, AND DISPLAY APPARATUS - A method of manufacturing a semiconductor device includes the steps of: modifying a semiconductor film by applying a laser beam; and forming a semiconductor device on the modified semiconductor film. In the step of modifying the semiconductor film, the laser beam and the substrate are moved relative to each other in a first direction and a second direction which is opposite to the first direction, a change in an optical characteristic between an area irradiated with the laser beam and an area which is not irradiated with the laser beam in the substrate or an optical characteristic of the irradiated area is measured in each of the first and second directions, and irradiation power of the laser beam is modulated so that the difference between a measurement result in the first direction and a measurement result in the second direction lies in a predetermined range. | 2009-04-16 |
20090095963 | BARE DIE SEMICONDUCTOR DEVICE CONFIGURED FOR LAMINATION - A bare die semiconductor device, e.g., a bare die LED, includes a substrate having a bottom face and a bottom die electrode. There is also a top face having a top face edge, a top face area, a top face periphery and a top die electrode. A semiconductor material provides a p-n semiconductor junction between the top and bottom faces. The top die electrode inhibits an external top planar electrode from contact with the top face edges. Such bare die LEDs can be incorporated into a light sheet that has a transparent first substrate having a planar top electrode and a second substrate having a bottom substrate electrode. An adhesive secures the second substrate to the first substrate. Bare die LEDs are disposed in the adhesive with their top die electrodes contacting the top planar electrode and their bottom die electrodes contacting the bottom substrate electrode. | 2009-04-16 |
20090095964 | Nitride Semiconductor Laser Device and Nitride Semiconductor Laser Apparatus - In one embodiment of the present invention, a long-life nitride semiconductor laser element is disclosed wherein voltage characteristics do not deteriorate even when the element is driven at high current density. Specifically disclosed is a nitride semiconductor laser element which includes a p-type nitride semiconductor and a p-side electrode formed on the p-type nitride semiconductor. In at least one embodiment, the p-side electrode has a first layer which is in direct contact with the p-type nitride semiconductor and a conductive second layer formed on the first layer, and the second layer contains a metal element selected from the group consisting of Ti, Zr, Hf, W, Mo and Nb, and an oxygen element. | 2009-04-16 |
20090095965 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DIODE - A nitride semiconductor light emitting diode (LED) comprises an n-type nitride semiconductor layer; an electron emitting layer formed on the n-type nitride semiconductor layer, the electron emitting layer being composed of a nitride semiconductor layer including a transition element of group III; an active layer formed on the electron emitting layer; and a p-type nitride semiconductor layer formed on the active layer. | 2009-04-16 |
20090095966 | Multiple conversion material light emitting diode package and method of fabricating same - An emitter package comprising a light emitting diode (LED) emitting light at a wavelength within a wavelength range and a plurality of phosphors. Each of the phosphors absorbs at least some light from the LED and re-emits a different wavelength of light. The package emits a combination of light from the LED and the plurality of phosphors, with the phosphors having excitation characteristics such that the emitter package emits light within a standard deviation of a target color for LEDs emitting at the wavelengths with the wavelength range. A method for fabricating emitter packages comprising fabricating a plurality of LEDs, each of which emits at a wavelength within a range of wavelengths. Each of the LEDs are arranged in a respective package with a plurality of conversion materials so that at least some light from each of the LEDs is absorbed and re-emitted by its corresponding conversion materials. The plurality of conversion materials have excitation characteristics that compensate for different LED emission wavelengths within the LED range of wavelengths such that each of the LED packages emits light within a standard deviation from a target color. | 2009-04-16 |
20090095967 | LIGHT EMITTING DEVICE - The lighting device ( | 2009-04-16 |
20090095968 | Image Sensor and Method for Manufacturing the Same - Provided are an image sensor and a method for manufacturing the same. A trench can be formed through metal interconnection layers of the image sensor in a region corresponding to a light receiving device for each unit pixel. A passivation layer pattern can be provided at sidewalls of the trench to inhibit light incident into the metal interconnection layers and reduce cross-talk and noise. A filler material can be provided to fill the trench. A color filter layer and microlens can be formed on the filler material. The filler material can be, for example, a polymer, an oxide layer, or a photoresist. | 2009-04-16 |
20090095969 | Substrate for mounting an optical semiconductor element, manufacturing method thereof, an optical semiconductor device, and manufacturing method thereof - A substrate for mounting optical semiconductor elements is provided, including a base substrate having an insulating layer and a plurality of wiring circuits formed on the upper face of the insulating layer, and having at least one external connection terminal formation opening portion which penetrates the insulating layer and reaches the wiring circuits; and an optical reflection member, which is provided on the upper face of the base substrate, and which forms at least one depressed portion serving as an area for mounting an optical semiconductor element. | 2009-04-16 |
20090095970 | WHITE PHOSPHORS, METHODS OF MAKING WHITE PHOSPHORS, WHITE LIGHT EMITTING LEDS, METHODS OF MAKING WHITE LIGHT EMITTING LEDS, AND LIGHT BULB STRUCTURES - Phosphor compositions, white phosphor compositions, methods of making white phosphor compositions, tinted white phosphor compositions, methods of making tinted white phosphor compositions, LEDs, methods of making LEDs, light bulb structures, paints including phosphor compositions, polymer compositions including phosphor compositions, ceramics including phosphor compositions, and the like are provided. | 2009-04-16 |
20090095971 | WIRE BOND LED LIGHTING UNIT - A wire bond LED lighting unit and method for maximizing heat transfer in an LED lighting unit are disclosed, wherein the LED lighting unit includes an LED package disposed on a first carrier plate and is in thermal communication therewith. A PWB is disposed on the first carrier plate spaced from the LED package. The LED package is in electrical communication with the PWB. The first carrier plate is also in thermal communication with the PWB. | 2009-04-16 |
20090095972 | LIGHT-EMITTING DEVICE - A light-emitting device is provided in a light-emitting element with a bonding wire that is a fine metallic wire formed mainly of gold or copper and coated at least partly with a substance capable of heightening a reflection coefficient of a wavelength of light emitted from the light-emitting element. | 2009-04-16 |
20090095973 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device has a device body made of a group III nitride semiconductor having a major surface defined by a nonpolar plane. In the device body, a contact portion with an n-type electrode includes a crystal plane different from the major surface. For example, the contact portion may include a corrugated surface. More specifically, the contact portion may include a region having a plurality of protrusions parallel to a polar plane formed in a striped manner. | 2009-04-16 |
20090095974 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package including a base body having a recessed portion for installing an electronic component on one surface, the recessed portion including an inner bottom surface, inclined surface and a shoulder part and a wiring pattern having one end positioned in the inner bottom surface of the recessed portion and the other end extending to an outside region of the recessed portion beyond the shoulder part of the recessed portion. The shoulder part of the recessed portion is a smoothly curved surface. | 2009-04-16 |
20090095975 | LIGHT EMITTING DIODE PACKAGE - A light emitting diode package for preventing an electric short circuit among semiconductor layers and with excellent bonding strength. The light emitting diode package includes a package substrate, a light emitting diode chip bonded to an upper surface of the package substrate, and a bonding material for bonding the light emitting diode chip to the package substrate. The package substrate has a recess formed in a bonding surface thereof to accommodate the bonding material. | 2009-04-16 |
20090095976 | NITRIDE-BASED LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a nitride-based light-emitting device including a transparent electrode made of a transparent conductive oxide having a higher work function than indium tin oxide and a method of manufacturing the same. The nitride-based light-emitting device has a sequentially stacked structure of a substrate, an n-type clad layer, an active layer, a p-type clad layer, and an ohmic contact layer. The ohmic contact layer is formed as a film made of a transparent conductive oxide having a higher work function than indium tin oxide or as a film made of the transparent conductive oxide doped with a metal dopant. Therefore, ohmic contact characteristics with the p-type clad layer are enhanced, thereby ensuring excellent current-voltage characteristics. Furthermore, the high light transmittance of the transparent electrode can increase the emission efficiency of the device. | 2009-04-16 |
20090095977 | VERTICAL SEMICONDUCTOR DEVICE - In a vertical semiconductor device including a first base layer of a first conductivity type, second base layers of a second conductivity type, emitter layer of the first conductive type and gate electrodes which are formed at one main surface of the first base layer and including a buffer layer of the first conductivity type, a collector layer of the second conductivity type and a collector electrode which are formed at the other main surface of the first base layer, an electric field relaxing structure selectively formed outside from the second base layers and the collector layer is formed expect the region below the electric field relaxing structure. | 2009-04-16 |
20090095978 | Low capacitance over-voltage tage protection thyristor device - An over-voltage protection thyristor has reduced junction capacitance making it suitable for use in high bandwidth applications. The reduced capacitance is achieved through the introduction of a deep base region. The deep base region has a graded doping ,concentration which reduces with depth into the substrate. The thyristor is useful for protecting sensitive electrical equipment from transient surges. | 2009-04-16 |
20090095979 | Power Module - A power module includes a substrate having first and second main substrate surfaces; a semiconductor device disposed on the first main substrate surface, and having a first main surface on which a first main electrode is formed, and a second main surface on which a second main electrode in contact with the first main substrate surface is formed; a heat conduction portion disposed on the first main substrate surface in a residual region of a region on which the semiconductor device is disposed; and an upper cooling portion disposed on the heat conduction portion. | 2009-04-16 |
20090095980 | Reducing Resistance in Source and Drain Regions of FinFETs - A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer. | 2009-04-16 |
20090095981 | Complementary metal oxide semiconductor device and method of manufacturing the same - Provided are a complementary metal oxide semiconductor (CMOS) device and a method of manufacturing the same. The CMOS device comprises an epi-layer that may be formed on a substrate; a first semiconductor layer and a second semiconductor layer that may be formed on different regions of the epi-layer, respectively; and a PMOS transistor and a NMOS transistor that may be formed on the first and second semiconductor layers, respectively. | 2009-04-16 |
20090095982 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device to which a stress technique is applied and in which a leakage current caused by silicidation can be suppressed. A gate electrode is formed over an element region defined by an isolation region formed in a semiconductor substrate with a gate insulating film between. Extension regions and source/drain regions are formed in the element region on both sides of the gate electrode. In addition, a semiconductor layer which differs from the semiconductor substrate in lattice constant is formed apart from at least part of the isolation region. By doing so, the formation of a spike near the isolation region is suppressed even if a silicide layer is formed. Accordingly, a leakage current caused by such a spike can be suppressed. | 2009-04-16 |
20090095983 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING SAME - In one example embodiment, an integrated semiconductor circuit ( | 2009-04-16 |
20090095984 | DIELECTRIC INTERFACE FOR GROUP III-V SEMICONDUCTOR DEVICE - A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region. | 2009-04-16 |
20090095985 | Multi-layer electrode, cross point memory array and method of manufacturing the same - Provided may be a multi-layer electrode, a cross point resistive memory array and method of manufacturing the same. The array may include a plurality of first electrode lines arranged parallel to each other; a plurality of second electrode lines crossing the first electrode lines and arranged parallel to each other; and a first memory resistor at intersections between the first electrode lines and the second electrode lines, wherein at least one of the first electrode lines and the second electrode lines have a multi-layer structure including a first conductive layer and a second conductive layer formed of a noble metal. | 2009-04-16 |
20090095986 | PHOTO SENSOR WITH A LOW-NOISE PHOTO ELEMENT, SUB-LINEAR RESPONSE AND GLOBAL SHUTTER - A photo sensor exhibiting low noise, low smear, low dark current, high dynamic range and global shutter functionality consists either of a pinned (or buried) photodiode or a photo-sensitive charge-coupled device, each with associated transfer gate, a sub-linear element, a shutter transistor, a reset circuit and a read-out circuit. Using two output paths global shutter and high speed operation are possible for the linear and the sub-linear output of the sensor. Because of its compact size, the photo sensor can be employed in one- and two-dimensional image sensors, fabricated with industry-standard CMOS and CCD technologies. | 2009-04-16 |
20090095987 | Transistor Design and Layout for Performance Improvement with Strain - The present invention facilitates semiconductor device fabrication and performance by providing a semiconductor device that can improve channel mobility for both N type and P type transistor devices. The semiconductor device of the present invention is fabricated on a semiconductor substrate | 2009-04-16 |
20090095988 | Transistor Design and Layout for Performance Improvement with Strain - The present invention facilitates semiconductor device fabrication and performance by providing a semiconductor device that can improve channel mobility for both N type and P type transistor devices. The semiconductor device of the present invention is fabricated on a semiconductor substrate | 2009-04-16 |
20090095989 | MULTI-FINGER TRANSISTORS INCLUDING PARTIALLY ENCLOSING CONDUCTIVE LINES - A multi-finger transistor includes gate fingers disposed on a substrate, at least one gate wiring connected to end portions of the gate fingers, source regions and drain regions disposed between the gate fingers, a conductive line partially enclosing the gate fingers and the gate wiring, and substrate plugs electrically connecting the conductive line to the substrate. The conductive line is separated from the gate fingers and the gate wiring. Since the conductive line and the substrate plugs may partially, but not fully, enclose a portion of the substrate where the gate fingers and the gate wiring are positioned, parasitic capacitances caused by the conductive line and the substrate plugs may be considerably reduced to thereby allow high RF frequency characteristics of the multi-finger transistor. | 2009-04-16 |
20090095990 | METAL-OXIDE-SEMICONDUCTOR TRANSISTOR AND METHOD OF FORMING THE SAME - A method of forming a metal-oxide-semiconductor (MOS) transistor device is provided. First, a semiconductor substrate is prepared. Subsequently, a gate structure is formed on the semiconductor substrate. The gate structure includes a first strip portion and a second strip portion that is not parallel to the first strip portion. The gate structure further includes a junction between the first strip portion and the second strip portion. Thereafter, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure. Next, a portion of the stressed cap layer is removed to expose the junction between the first strip portion and the second strip portion. | 2009-04-16 |
20090095991 | METHOD OF FORMING STRAINED MOSFET DEVICES USING PHASE TRANSFORMABLE MATERIALS - A method of forming a strained metal oxide semiconductor field effect transistor (MOSFET) device includes forming a gate conductor and gate insulator layer over a semiconductor substrate; forming source and drain regions in the semiconductor substrate, thereby defining the MOSFET device; forming a phase transformable material layer over the MOSFET device, wherein the phase transformable layer is in a first phase upon initial formation thereof, and following the initial formation of the phase transformable material layer, converting the phase transformable layer from the first phase to a second phase, wherein the second phase results in the phase transformable layer applying a longitudinal stress on a channel of the MOSFET device. | 2009-04-16 |
20090095992 | SEMICONDUCTOR DEVICE INCLUDING MOS FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - Element isolation regions are formed in a semiconductor substrate of a first conductivity type. A gate insulator is formed on the semiconductor substrate between the element isolation regions. A gate electrode is formed on the gate insulator. Sidewall insulating films are formed on side surfaces of the gate electrode. Trenches are formed on the semiconductor substrate between the element isolation regions and the gate electrode. A first epitaxial semiconductor layer of a second conductivity type is formed by the epitaxial growth method in each of the trenches. The first epitaxial semiconductor layer has a facet. A silicide film is formed on the first epitaxial semiconductor layer. A semiconductor region of the second conductivity type is formed in the semiconductor substrate under the first epitaxial semiconductor layer. | 2009-04-16 |
20090095993 | SEMICONDUCTOR MEMORY DEVICE AND FABRICATING METHOD FOR SEMICONDUCTOR MEMORY DEVICE - According to an aspect of the present invention, there is provided a semiconductor memory device including a ferroelectric capacitor, including a semiconductor substrate, a transistor having diffusion layers being a source and a drain, the transistor being formed on a surface of the semiconductor substrate, a ferroelectric capacitor being formed over the transistor, the ferroelectric capacitor including a lower electrode, a ferroelectric film and an upper electrode stacked in order, an interlayer insulator separating between the transistor and the ferroelectric capacitor, a first contact plug being embedded in the interlayer insulator formed beneath the ferroelectric capacitor, the first contact plug directly connecting between one of the diffusion layers and the lower electrode, a first hydrogen barrier film covering the transistor a second hydrogen barrier film, a portion of the second hydrogen barrier film being formed on the first hydrogen barrier film, another portion of the second hydrogen barrier film covering at least the ferroelectric capacitor, and a second contact plug being embedded in the interlayer insulator, the second hydrogen barrier film and the first hydrogen barrier film, one end of the second contact plug connecting to the other of the diffusion layers. | 2009-04-16 |
20090095994 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprises a substrate; an insulating layer formed over the substrate; a contact hole formed through the insulating layer; a plurality of first plug electrodes each formed inside the contact hole to the surface of the insulating layer; a capacitor layer formed on the first plug electrode in a first region; and a second plug electrode formed on the first plug electrode in a second region different from the first region. The capacitor layer includes a lower electrode, a ferroelectric film, and an upper electrode stacked in turn. The first plug electrode includes a plug conduction layer formed from the surface of the substrate, and a plug barrier layer formed from above the plug conduction layer up to an upper surface of the insulating layer, the plug barrier layer having a higher etching selection ratio than the lower electrode. | 2009-04-16 |
20090095995 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode. | 2009-04-16 |
20090095996 | Semiconductor device - A semiconductor device includes a substrate including an active region, a first impurity region, second impurity regions, a word line and a bit line. The active region has end portions extending in a first direction and a central portion extending in a second direction inclined relative to the first direction. The first impurity region is disposed at the central portion, and the second impurity regions are disposed at the end portions. The word line extends in a third direction substantially perpendicular to the first direction. The bit line extends in the first direction. The bit line is electrically connected to the first impurity region. The second impurity regions may be symmetrical to each other centering adjacent two word lines and adjacent one bit line. The semiconductor device may have improved sensing margin by reducing the capacitance of the bit line. | 2009-04-16 |
20090095997 | EPITAXIAL SILICON GROWTH - Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon growth. The method includes providing a silicon layer on a substrate. A dielectric layer is provided on the silicon layer. A trench is formed in the dielectric layer to expose the silicon layer, the trench having trench walls in the <100> direction. The method includes epitaxially growing silicon between trench walls formed in the dielectric layer. | 2009-04-16 |
20090095998 | DEEP TRENCH CAPACITOR AND METHOD - Disclosed herein are embodiments of a deep trench capacitor structure and a method of forming the structure that incorporates a buried capacitor plate contact that is simultaneously formed using an adjacent deep trench. This configuration eliminates the need for additional photolithographic processing, thereby, optimizing process windows. This configuration further eliminates the need to form the deep trench capacitor through an N-doped diffusion region connector and, thereby, allows for greater design flexibility when connecting the deep trench capacitor to another integrated circuit structure (e.g., a memory cell or decoupling capacitor array). Also, disclosed herein are embodiments of another integrated circuit structure and method, and more specifically, a memory cell (e.g., a static random access memory (SRAM) cell)) and method of forming the memory cell that incorporates one or more of these deep trench capacitors in order to minimize or eliminate soft errors. | 2009-04-16 |
20090095999 | Semiconductor device and method of fabricating the same - Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device includes a first conductive well region in a semiconductor substrate and a second conductive well region on or in the first conductive well region. A gate electrode is in a trench on a gate insulation layer, and the trench is in the second conductive region and the first conductive well region. A drain includes a drain insulation layer, a (polysilicon) shield layer, and drain plug. The drain insulation layer is in a trench in the second conductive region and the first conductive well region. The shield layer encloses the drain plug. A lower portion of the drain plug contacts the second conductive well region. A first conductive source region is at a side of the gate electrode. | 2009-04-16 |
20090096000 | DRAM CELLS WITH VERTICAL TRANSISTORS - The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The invention also includes methods of forming semiconductor structures. | 2009-04-16 |
20090096001 | Integrated Circuit and Method of Manufacturing the Same - A method of manufacturing an integrated circuit includes: forming a trench in a substrate, forming a high-k dielectric layer lining the trench, and removing a section of the high-k dielectric layer from the trench via an isotropic dry etch process. | 2009-04-16 |
20090096002 | System and Method for Source/Drain Contact Processing - System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin. | 2009-04-16 |
20090096003 | SEMICONDUCTOR CELL STRUCTURE INCLUDING BURIED CAPACITOR AND METHOD FOR FABRICATION THEREOF - A semiconductor structure and a method for fabricating the semiconductor structure include at least one field effect transistor, and also a capacitor, located over a substrate. In particular, the capacitor is located interposed between the field effect transistor and the substrate. The field effect transistor may include a planar field effect transistor as well as a fin-FET. The capacitor may be connected with a conductor plug layer to a source/drain region of the field effect transistor to form a dynamic random access memory cell structure. | 2009-04-16 |
20090096004 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor storage device includes: a substrate having a semiconductor layer at least on a surface thereof; and a plurality of quantum dot elements forming a charge storage layer formed above the semiconductor layer via a first insulating film that becomes a tunnel insulating film in such a manner that the quantum dot elements are connected with a bit line in series, wherein each quantum dot element forms a single electron memory. | 2009-04-16 |
20090096005 | SEMICONDUCTOR MEMORY DEVICE INCLUDING DOUBLE SPACERS ON SIDEWALL OF FLATING GATE, ELECTRONIC DEVICE INCLUDING THE SAME - A semiconductor memory device includes a device isolation layer formed in a semiconductor substrate to define a plurality of active regions. Floating gates are disposed on the active regions. A control gate line overlaps top surfaces of the floating gates and crosses over the active regions. The control gate line has an extending portion disposed in a gap between adjacent floating gates and overlapping sidewalls of the adjacent floating gates. First spacers are disposed on the sidewalls of the adjacent floating gates. Each of the first spacers extends along a sidewall of the active region and along a sidewall of the device isolation layer. Second spacers are disposed between outer sidewalls of the first spacers and the extending portion and are disposed above the device isolation layer. An electronic device including a semiconductor memory device and a method of fabricating a semiconductor memory device are also disclosed. | 2009-04-16 |
20090096006 | NONVOLATILE SEMICONDUCTOR STORAGE APPARATUS AND METHOD FOR MANUFACTURING THE SAME - According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage apparatus including: a semiconductor substrate on which element isolation trenches are formed to define element formation regions on the semiconductor substrate; gate insulating films that are formed on the element formation regions of the semiconductor substrate; floating gate electrodes that are formed on the gate insulating films; element isolation insulating films that each includes: a coating type insulating film that is formed in a corresponding one of the element isolation trenches; and a non-coating type insulating film that is formed to cover a top surface of the coating type insulating film; a interelectrode insulating film that is formed on the element isolation insulating films and floating gate electrodes; and a control gate electrode that is formed on the interelectrode insulating film. | 2009-04-16 |
20090096007 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture. | 2009-04-16 |
20090096008 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device having a blocking insulating layer with an excellent data retention property and a method of fabricating the same are provided. The nonvolatile memory device may include a semiconductor substrate having a channel region formed therein; and a gate stack including a tunneling insulating layer, a charge storing layer, a blocking insulating layer and a control gate electrode sequentially stacked on the channel region of the semiconductor substrate. The blocking insulating layer may comprise a lanthanum aluminum oxide having a formula of La | 2009-04-16 |
20090096009 | NONVOLATILE MEMORIES WHICH COMBINE A DIELECTRIC, CHARGE-TRAPPING LAYER WITH A FLOATING GATE - A nonvolatile memory cell stores at least 50% of the charge in a dielectric, charge-trapping layer ( | 2009-04-16 |
20090096010 | NONVOLATILE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A nonvolatile memory device and a fabrication method thereof are disclosed. The nonvolatile memory device comprises a tunnel insulating film formed on an active region of a semiconductor substrate, a first conductive layer for a floating gate formed on the tunnel insulating film, a dielectric layer formed on the first conductive layer, a second conductive layer for a control gate formed on the dielectric layer, an etch-stop layer formed on the second conductive layer, and a gate electrode layer formed on the etch-stop layer. Accordingly, there is no difference in the degree to which the conductive layer under the gate electrode layer is etched when etching the gate electrode layer of the memory cell region and the peri region. | 2009-04-16 |
20090096011 | Non-Volatile Memory Device Having Asymmetric Source/Drain Junction and Method for Fabricating the Same - Disclosed herein are non-volatile memory devices with asymmetric source/drain junctions and a method for fabricating the same. According to the method, a gate stack is formed on a semiconductor substrate, and impurity ions are implanted at a predetermined angle to form a source/drain junction in the semiconductor substrate. Thermal treatment of the semiconductor substrate forms an asymmetrically disposed source/drain junction between adjacent gate stacks. | 2009-04-16 |
20090096012 | FLASH MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A flash memory secures a desired coupling ratio in a target thickness by lowering the leakage current through a high-dielectric (k) layer employing a combination of energy band gaps. The flash memory device includes a tunnel insulating layer formed on a semiconductor substrate, a first conductive layer formed on the tunnel insulating layer, a high-dielectric (k) layer having a stacked structure of first, second and third high-k insulating layers formed on the first conductive layer, and a second conductive layer formed on the high-k layer. The first high-k insulating layer has a first energy bandgap, the second high-k insulating layer has a second energy bandgap greater than the first energy bandgap, and the third high-k insulating layer has a third energy bandgap smaller than the second energy bandgap. | 2009-04-16 |
20090096013 | NON-VOLATILE MEMORY DEVICES WITH CHARGE STORAGE REGIONS - A memory device includes a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, and a control gate. Applying a positive bias to the control gate, the select gate and the source of the device injects negative charges from a channel region of a substrate by hot electron injection through the tunneling dielectric layer at a location near a gap between the select gate and the control gate into the charge storage layer to store negative charges in the charge storage layer. Applying a negative bias is to the control gates directly tunnels positive charges from the channel region of the substrate through the tunneling dielectric layer and into the charge storage layer to store positive charges in the charge storage layer. | 2009-04-16 |
20090096014 | NONVOLATILE MEMORY DEVICES THAT INCLUDE AN INSULATING FILM WITH NANOCRYSTALS EMBEDDED THEREIN AND METHODS OF MANUFACTURING THE SAME - A nonvolatile memory device includes a semiconductor substrate, a charge-trap structure disposed on the semiconductor substrate, which includes an insulating film and a plurality of carbon nanocrystals embedded in the insulating film, and a gate disposed on the charge-trap structure. The nonvolatile memory device may exhibit memory hysteresis characteristics with improved reliability. | 2009-04-16 |
20090096015 | Nonvolatile semiconductor memory device and manufacturing method therefor - In a nonvolatile semiconductor memory device, a floating gate is formed on a semiconductor substrate through a gate insulating film, and has a first portion contacting the gate insulating film and a second portion extending upwardly from a part of a surface of the first portion. A first diffusion layer is formed in the semiconductor substrate to have a plane parallel to a surface of the semiconductor substrate. A second diffusion layer is formed in the semiconductor substrate, to have the plane. A control gate is provided near the floating gate above a channel region in the semiconductor substrate and is formed on a first side of the first portion. A conductive film is connected with the first diffusion layer and is formed on a second side of the first portion and a first side of the second portion through the first insulating film. | 2009-04-16 |
20090096016 | Method of manufacturing a sonos device - A SONOS device and a method of manufacturing the same is provided. A tunnel dielectric layer, a charge trap layer, and a charge blocking layer are formed on a semiconductor substrate, and the charge blocking layer is formed on the charge trap layer such that the charge blocking layer is relatively thicker at regions adjacent to or overlapping the source and the drain and relatively thinner at a region overlapping the channel region. A gate is then formed on the blocking layer. | 2009-04-16 |
20090096017 | STACKED THIN FILM TRANSISTOR, NON-VOLATILE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - A manufacturing method for stacked, non-volatile memory devices provides a plurality of bitline layers and wordline layers with charge trapping structures. The bitline layers have a plurality of bitlines formed on an insulating layer, such as silicon on insulator technologies. The wordline layers are patterned with respective pluralities of wordlines and charge trapping structures orthogonal to the bitlines. | 2009-04-16 |
20090096018 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes: a body region of a first conductive type; trenches formed by digging in from a top surface of the body region; gate electrodes embedded in the trenches; source regions of a second conductive type formed at sides of the trenches in a top layer portion of the body region; and body contact regions of the first conductive type, penetrating through the source regions in a thickness direction and contacting the body region. The body contact regions are formed in a zigzag alignment in a plan view. With respect to a column formed by the body contact regions aligned in a predetermined column direction, the trenches are disposed at both sides in a row direction orthogonal to the column direction in a plan view, extend in the column direction, and form meandering lines each connecting a plurality of curved portions so that a predetermined gap in the row direction is formed respectively between adjacent trenches extending in the column direction and between the trenches and the body contact regions. | 2009-04-16 |
20090096019 | MOSGATED POWER SEMICONDUCTOR DEVICE WITH SOURCE FIELD ELECTRODE - A power semiconductor device which includes a source field electrode, and at least one insulated gate electrode adjacent a respective side of the source field electrode, the source field electrode and the gate electrode being disposed in a common trench. | 2009-04-16 |
20090096020 | Semiconductror device and manufacturing method thereof - A semiconductor device includes field effect transistors, each having a semiconductor layer formed on a major surface of a semiconductor substrate, a base region formed in a surface layer portion of a semiconductor layer, a source region formed in a surface layer portion of the base region, a source electrode formed on the base region and the source region, a gate electrode formed on the semiconductor layer and the base region via a gate insulating film interposed therebetween, and a drain electrode formed on a back surface of the semiconductor substrate, and which are placed side by side. A columnar intermediate region is formed in its corresponding predetermined region of the surface layer portion of the semiconductor layer placed below each gate electrode. Connection regions are formed in the surface layer portion of the semiconductor layer to contact the intermediate region and the base regions. | 2009-04-16 |