16th week of 2013 patent applcation highlights part 17 |
Patent application number | Title | Published |
20130093446 | SUPPORT BODY FOR CONTACT TERMINALS AND PROBE CARD - A support body for a plurality of contact terminals included in a probe card for inspecting semiconductor devices formed in a semiconductor substrate is provided. | 2013-04-18 |
20130093447 | Methods for Reducing Path Loss While Testing Wireless Electronic Devices with Multiple Antennas - A test station may include a test host, a test unit, and a test enclosure. A device under test (DUT) having at least first and second antennas may be placed in the test enclosure during production testing. Radio-frequency test signals may be conveyed from the test unit to the DUT using a test antenna in the test enclosure. In a first time period during which the performance of the first antenna is being tested, the DUT may be oriented in a first position such that path loss between the first antenna and the test antenna is minimized. In a second time period during which the performance of the second antenna is being tested, the DUT may be oriented in a second position such that path loss between the second antenna and the test antenna is minimized. The DUT is marked as a passing DUT if gathered test data is satisfactory. | 2013-04-18 |
20130093448 | VOLTAGE TESTER HAVING ALTERNATIVELY ATTACHABLE OR SEPARABLE PROBES - A tester includes a main body and a removable probe. The main body includes a main body probe and a front panel including selectable options for selecting a tester function. The removable probe may be coupled to the main body via a cord. The removable probe is fixable to the main body via a latch assembly. The latch assembly including a socket disposed on one of the removable probe or the main body and a mating protrusion disposed at the other of the removable probe or the main body, the main body having a probe support ridge associated therewith and the removable probe having an alignment ridge associated therewith, the alignment ridge and the probe support ridge lying in a same plane when the mating protrusion is inserted into the socket. | 2013-04-18 |
20130093449 | VOLTAGE TESTER HAVING ALTERNATIVELY ATTACHABLE OR SEPARABLE PROBES - A tester includes a main body and a removable probe. The main body includes a main body probe and a front panel including selectable options for selecting a tester function. The removable probe may be coupled to the main body via a cord. The removable probe is fixable to the main body via a latch assembly. The latch assembly includes a socket disposed on one of the removable probe or the main body and a mating protrusion disposed at the other of the removable probe or the main body. | 2013-04-18 |
20130093450 | VERTICAL PROBE ARRAY ARRANGED TO PROVIDE SPACE TRANSFORMATION - Improved probing of closely spaced contact pads is provided by an array of vertical probes having all of the probe tips aligned along a single contact line, while the probe bases are arranged in an array having two or more rows parallel to the contact line. With this arrangement of probes, the probe base thickness can be made greater than the contact pad spacing along the contact line, thereby advantageously increasing the lateral stiffness of the probes. The probe tip thickness is less than the contact pad spacing, so probes suitable for practicing the invention have a wide base section and a narrow tip section. | 2013-04-18 |
20130093451 | METHOD AND APPARATUS FOR DE-EMBEDDING - De-embedding apparatus and methods of de-embedding are disclosed. A de-embedding apparatus includes a test structure including a device-under-test (DUT) embedded in the test structure, and a plurality of dummy test structures including an open dummy structure, a distributed open dummy structure, and a short dummy structure. The distributed open dummy structure may include a first signal transmission line coupled to a left signal test pad and a second signal transmission line coupled to a right signal test pad, the first and second signal transmission lines having a smaller total length than a total length of signal transmission lines of the open dummy structure, and intrinsic transmission characteristics of the DUT can be derived from transmission parameters of the dummy test structures and the test structure | 2013-04-18 |
20130093452 | PROBE CARD PARTITION SCHEME - A method of probe card partitioning for testing an integrated circuit die includes providing a first probe card partition layout having a first number of distinct sections. Each distinct section uses a distinct probe card for testing. The first probe card partition layout is repartitioned into a second probe card partition layout having a second number of distinct sections. The second number is less than the first number. | 2013-04-18 |
20130093453 | CONNECTING DEVICE, SEMICONDUCTOR WAFER TEST APPARATUS COMPRISING SAME, AND CONNECTING METHOD - A connecting device electrically connects a performance board which has PB terminals and a test head, and includes a sub board which is electrically connected to the test head and has sub terminals which face the PB terminals, a sealing mechanism which forms a sealed space between the sub board and the performance board, and a pressure reducing device which reduces the pressure of the sealed space. The pressure reducing device reduces the pressure of the sealed space so that the performance board and the sub board approach each other and the PB terminals and the sub terminals contact. | 2013-04-18 |
20130093454 | TESTING AND REPAIRING APPARATUS OF THROUGH SILICON VIA IN STACKED-CHIP - A testing and repairing apparatus of through silicon via (TSV) disposed between a first and a second chips is provided. First terminals of a first and a second switches are coupled to a first terminal of the TSV. First terminals of a third and a fourth switches are coupled to a second terminal of the TSV. A first terminal of a first resister is coupled to a first voltage. A first selector is coupled between second terminals of the second switch and the first resister. A second selector is coupled between a second terminal of the fourth switch and a second voltage. A first control circuit detects the second terminal of the second switch, and controls the first switch, the second switch and the first selector. A second control circuit controls the third switch, the fourth switch and the second selector. | 2013-04-18 |
20130093455 | TSV TESTING METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for testing TSVs in a single die or TSV connections in a stack of die. | 2013-04-18 |
20130093456 | TESTING DEVICE FOR SOLID OXIDE FUEL CELL - A testing device for solid oxide fuel cell (SOFC) is disclosed. The testing device which combines the original cell housing with a four-point probe equipment is set for measuring SOFC MEA. The current collectors on anode and cathode in the original cell housing are respectively replaced by four independent probe units. They are not only to collect current but also to become measuring probes. Therefore, the lateral impedance of anode and cathode can be measured. Furthermore, the local characteristics are examined by open circuit voltage (OCV), I-V curve, and electrochemical impedance spectroscopy (EIS) measurements. The results show that the lateral impedance is substantially varied with temperatures. The distributions of OCV, current density, EIS and cell voltage in long-term test at the center of the cell are different from the edge. | 2013-04-18 |
20130093457 | METHOD FOR TESTING AN INVERTER DRIVE ROTATING ELECTRIC MACHINE - With a rotating electric machine testing method for applying a test voltage to an armature winding of the rotating electric machine to thereby test insulation performance of the armature winding, in the case where a rated voltage of the armature winding of the rotating electric machine is E, and an insulation test voltage of an armature winding of a sine wave voltage drive rotating electric machine at the rated voltage E is E/√{square root over (3)} or E, a test voltage V | 2013-04-18 |
20130093458 | BINARY HALF-ADDER USING OSCILLATORS - A binary half-adder comprising first and second oscillators, each oscillator being connected to a first input and to a second input, the second oscillator being connected to the first oscillator, wherein the first oscillator is configured to oscillate if the first input is high or the second input is high, the second oscillator is configured to oscillate if the first and the second inputs are high, and wherein the connection between the second oscillator and the first oscillator is configured to suppress oscillation of the first oscillator if the second oscillator is oscillating. | 2013-04-18 |
20130093459 | TERMINATION DEVICE SYSTEM - A termination device system is provided that includes a device required to be terminated with a resistor and a termination circuit. The termination circuit includes a termination resistor circuit and a judgment circuit connected to the termination resistor circuit. The termination resistor circuit includes at least one controlled termination unit. Each controlled termination unit includes a termination connecting end for connecting the device required to be terminated with a resistor, a controlled switch and a resistor, and provides, based on on/off of the controlled switch, a termination resistor for the device connected to the termination connecting end. The judgment circuit judges whether the device is required to be connected to the termination resistor based on a control instruction of a control device controlling the device connected to the termination connecting end, to output an on/off control signal to the controlled switch of the termination resistor circuit to control on/off. | 2013-04-18 |
20130093460 | CONFIGURABLE STORAGE ELEMENTS - An integrated circuit (“IC”) having configurable logic circuits for configurably performing multiple different logic operations based on configuration data is provided. The IC includes a row of the configurable logic circuits and multiple configuration retrieval circuits for providing configuration bits to the row of configurable logic circuits. The IC also includes a row configuration controller for forcing the multiple configuration retrieval circuits to output a particular configuration value based on a user signal that is received at runtime. | 2013-04-18 |
20130093461 | CONFIGURABLE STORAGE ELEMENTS - An integrated circuit (“IC”) having configurable logic circuits for configurably performing multiple different logic operations based on configuration data is provided. The IC includes a configurable routing fabric for configurably routing signals among configurable logic circuits. The configurable routing fabric includes a particular wiring path that connects an output of a source circuit to inputs of a destination circuit. The particular wiring path includes a first path and a second path that is parallel to the first path. The first and second paths are for configurably storing output signals of the source circuit. The first path connects to a first input of the destination circuit and the second path connects to a second input of the destination path. | 2013-04-18 |
20130093462 | CONFIGURABLE STORAGE ELEMENTS - A low power sub-cycle reconfigurable conduit is provided. The low power reconfigurable conduit is a clocked storage element that consumes less power when performing low-throughput operations that do not require sub-cycle rate. The low power conduit includes a first configurable routing multiplexer that is reconfigurable to select one of several inputs at a first clock rate. The low power conduit also includes an array of storage elements for storing output data from the configurable routing multiplexer at the first clock rate. Each storage element in the array of storage elements operate at a second clock rate that is slower than the first clock rate. Each storage element receives a different phase of a clock that operates at the second clock rate. The low power conduit also includes a second configurable routing multiplexer that is reconfigurable to select from the array of storage elements at the first clock rate. | 2013-04-18 |
20130093463 | HIGH FREQUENCY CMOS PROGRAMMABLE DIVIDER WITH LARGE DIVIDE RATIO - A dynamic latch has a pair of parallel pass gates (a first parallel pass gate that receives a seed signal, and a second parallel pass gate that receives a data signal). A first latch logic circuit performs logic operations using signals output by the parallel pass gates to produce an updated data signal. An additional pass gate is operatively connected to the first latch logic circuit. An additional pass gate controls passage of the updated data signal. An inverter receives the updated data signal from the pass gate, and inverts and outputs the updated data signal as an output data signal. Thus, the dynamic latch comprises two inputs into the pair of parallel pass gates and performs only one of four logical operations on a received data signal. The four logical operations are performed using the signals applied to the two inputs. | 2013-04-18 |
20130093464 | SIGNAL TRANSFER CIRCUIT - A signal transfer circuit includes a signal transfer unit configured to transfer an input signal applied to an input node to an output node in response to a control signal and a driving unit configured to drive an output signal of the output node to a level of the input signal in response to the control signal. | 2013-04-18 |
20130093465 | ASYMMETRICAL BUS KEEPER - Various embodiments are described herein for an asymmetrical bus keeper circuit that provides asymmetrical drive towards one logic level. The asymmetrical bus keeper circuit comprises a first inverter stage having an input node and an output node, an asymmetrical inverter stage having an input node and an output node and a feedback stage with an input node and an output node. The input node of the asymmetrical inverter stage is connected to the output node of the first inverter stage. The input node of the feedback stage connected to the output node of the asymmetrical inverter stage and the output node of the feedback stage connected to the input node of the first inverter stage. The asymmetrical stage provides asymmetrical drive towards one logic level. | 2013-04-18 |
20130093466 | ON DIE LOW POWER HIGH ACCURACY REFERENCE CLOCK GENERATION - A system and method are disclosed for generating a high accuracy and low power on die reference clock. An LC clock is generated on die and a frequency divider lowers the LC clock frequency to a target reference frequency. An RCO clock is generated on die with an unknown initial frequency. The RCO clock and target reference clock are compared to determine in which direction the frequency of the RCO clock should be adjusted to move closer to the target reference frequency. A signal is sent causing a current source or capacitor in the RCO circuit to be modified. Therefore, the RCO clock frequency is adjusted. The RCO circuit is repeatedly adjusted until the RCO clock frequency is sufficiently accurate. The LC clock is disabled to conserve the power that would have been consumed in generating the LC clock. | 2013-04-18 |
20130093467 | FOREGROUND TECHNIQUES FOR COMPARATOR CALIBRATION - A method and a device for canceling an offset voltage in an output of a comparator circuit include applying a signal to a first input of the comparator as a function of an initial tap point in a resistor ladder. While the signal is applied to the first input, a nominal voltage is applied to a second input of the comparator, and then an output of the comparator is analyzed. The signal to the first input is changed in response to the analyzing, by accessing a different tap point in the resistor ladder. | 2013-04-18 |
20130093468 | METHOD AND APPARATUS FOR MANAGING ARBITRARY FREQUENCIES - Frequency synthesizers for use with oscillators that generate an arbitrary frequency are described, as well as related devices and methods. Divider information can be generated or otherwise accessed for use in configuring a phase lock loop device that is adapted for coupling with the oscillator, where the phase lock loop device can include a plurality of integer dividers without utilizing a fractional divider, where the divider information can include frequency deviations corresponding to groups of integer divider settings for the phase lock loop device, and where each deviation of the frequency deviations can be based on a frequency differential between a standard operating frequency and an output frequency for the phase lock loop utilizing one group of integer divider settings from the groups of integer divider settings. | 2013-04-18 |
20130093469 | FREQUENCY SYNTHESIZER AND ASSOCIATED METHOD - A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter coupled to said oscillator for providing a shifted RF clock by changing phase of said RF clock, and a time-to-digital converter (TDC) coupled to said phase shifter for quantizing a time difference between a frequency reference clock and said shifted RF clock, wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided. | 2013-04-18 |
20130093470 | FREQUENCY SYNTHESIZER AND ASSOCIATED METHOD - A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter arranged to provide a shifted reference clock by changing phase of a frequency reference clock, and a time-to-digital converter (TDC) for producing a digital TDC output by quantizing a time difference between said RF clock and said shifted reference clock; wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided. | 2013-04-18 |
20130093471 | TIME-TO-DIGITAL SYSTEM AND ASSOCIATED FREQUENCY SYNTHESIZER - A time-to-digital system, such as a frequency synthesizer, includes a power management circuit and a time-to-digital converter (TDC). Said power management circuit is coupled to a frequency reference clock and a variable clock, and arranged to output a delayed frequency reference clock and a single pulse of said variable clock ahead of a transition of said delayed frequency reference clock. Said TDC is coupled to said power management circuit and arranged to produce a digital TDC output. | 2013-04-18 |
20130093472 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a driving unit, a first current path and a second current path. The driving unit applies a power supply voltage to a drive node in response to a control signal. The first current path couples the drive node and an output node. The second current path couples the drive node and the output node. The first current path and the second current path are coupled in parallel between the drive node and the output node. | 2013-04-18 |
20130093473 | DATA OUTPUT APPARATUS AND METHOD FOR OUTPUTTING DATA THEREOF - A data output apparatus includes a driver driving unit configured to generate driving signals by using input data when a data output enable signal is enabled, a data driver unit configured to drive an output terminal to a level corresponding to the input data in response to the driving signals to generate output data, and an output data level control unit configured to open a current path to control a level of the output data, wherein the current path is different from a current path for driving the output terminal to a level corresponding to the input data. | 2013-04-18 |
20130093474 | SYSTEMS AND METHODS FOR DRIVING TRANSISTORS WITH HIGH THRESHOLD VOLTAGES - System and method are provided for driving a transistor. The system includes a floating-voltage generator, a first driving circuit, and a second driving circuit. The floating-voltage generator is configured to receive a first bias voltage and generate a floating voltage, the floating-voltage generator being further configured to change the floating voltage if the first bias voltage changes and to maintain the floating voltage to be lower than the first bias voltage by a first predetermined value in magnitude. The first driving circuit is configured to receive an input signal, the first bias voltage and the floating voltage. The second driving circuit is configured to receive the input signal, a second bias voltage and a third bias voltage, the first driving circuit and the second driving circuit being configured to generate an output signal to drive a transistor. | 2013-04-18 |
20130093475 | INJECTION-LOCKED FREQUENCY DIVIDER - An injection-locked frequency divider (ILFD) including a signal injector, an oscillator (OSC), and a buffer stage is provided. The signal injector is configured for receiving an injection signal. The OSC is configured for dividing the frequency of the injection signal, so as to generate a first divided frequency signal, where there is an integral-multiple relation between the frequency of the first divided frequency signal and that of the injection signal. The buffer stage is configured for receiving and boosting the first divided frequency signal, and performing a push-push process on the first divided frequency signal, so as to output a second divided frequency signal, where there is a fractional-multiple relation between the frequency of the second divided frequency signal and that of the injection signal. | 2013-04-18 |
20130093476 | CLOCK DISTRIBUTION CIRCUIT - A clock distribution circuit is provided with a clock generation circuit configured to generate a clock signal, a clock distribution network in which the clock signal is distributed, and a sequential circuit configured to operate on the clock signal distributed through a branch point of the clock distribution network. The clock distribution circuit is further provided with a clock generation circuit configured to input as a feedback signal the clock signal that has branched from the branch point and to output the clock signal to the clock distribution network based on the inputted feedback signal and a reference clock signal. The branch point is provided at a clock driver near the clock generation circuit, among preceding stage clock drivers of the sequential circuit of the clock distribution network. | 2013-04-18 |
20130093477 | SYSTEMS AND METHODS FOR GENERATING A HIGH FREQUENCY LOCAL OSCILLATOR SIGNAL - One embodiment of the present invention relates to a system that provides a high frequency local oscillator (LO) signal. The system comprises a first LO that generates a first frequency LO signal component, a mixer that generates a difference signal from the first frequency LO signal component and a second frequency LO signal component, and a second LO that generates the second frequency LO signal component that is a harmonic of the difference signal. | 2013-04-18 |
20130093478 | DIFFERENTIATOR BASED SPREAD SPECTRUM MODULATOR - A spread spectrum clock generator which includes a pulse train generator circuit and a modulating circuit configured to produce a modulating signal relating to a time derivative of an output of the pulse train generator circuit. In one embodiment the modulating circuit includes a active differentiator circuit and in another embodiment the modulating circuit includes a passive differentiator circuit. A modulator is included which is configured to produce a spread spectrum clock output which is frequency modulated by the modulating signal. | 2013-04-18 |
20130093479 | SEMICONDUCTOR DEVICE AND RADIO COMMUNICATION TERMINAL MOUNTING THE SAME - A phase detector, which forms a semiconductor device, detects a phase difference between a reference signal and a feedback signal obtained by feeding back an output signal of an oscillator, and generates a phase difference value indicating a value in accordance with the phase difference. An amplifier amplifies the phase difference value at a gain determined in accordance with a control signal from outside the device. A filter smoothes an output value of the amplifier. The oscillator controls a frequency of the output signal in accordance with an output value of the filter. | 2013-04-18 |
20130093480 | DIGITAL PHASE LOCKED LOOP - A phase locked loop circuit ( | 2013-04-18 |
20130093481 | HIGH FREQUENCY CMOS PROGRAMMABLE DIVIDER WITH LARGE DIVIDE RATIO - A phase lock loop (PLL) includes a PLL feedback circuit having a feedback divider. The feedback divider has a first dynamic latch, a first logic circuit, and a plurality of serially connected dynamic latches. Each of the serially connected dynamic latches receives and forwards additional data signals to subsequent ones of the serially connected dynamic latches in series. The second-to-last dynamic latch in the series outputs a fourth data signal to a last dynamic latch in the series. The last dynamic latch receives the fourth data signal and outputs a fifth data signal. A first feedback loop receives the fourth data signal from the second-to-last dynamic latch and the fifth data signal from the last dynamic latch. The first feedback loop comprises a NAND circuit that combines the fourth and fifth data signals and the first feedback loop outputs the first feedback signal. | 2013-04-18 |
20130093482 | CLOCK AND DATA RECOVERY CIRCUITRY WITH AUTO-SPEED NEGOTIATION AND OTHER POSSIBLE FEATURES - An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation. | 2013-04-18 |
20130093483 | Dual Phase Detector Phase-Locked Loop - A phase-locked loop for generating an output signal that has a predetermined frequency relationship with a reference signal, the phase-locked loop comprising a signal generator arranged to generate the output signal, a charge pump arranged to generate current pulses for controlling the signal generator, two control units for controlling a duration of the current pulses generated by the charge pump and a selection unit arranged to select either the first control unit or the second control unit to control the charge pump, wherein a first one of the control units is arranged to continuously monitor a phase-difference between the reference signal and a feedback signal formed from the output signal and to, when selected by the selection unit, control the charge pump to output a current pulse having a duration that is dependent on that phase-difference and a second one of the control units is arranged to, when selected by the selection unit, control the charge pump to output a current pulse of predetermined duration that compensates for a phase error in the feedback signal. | 2013-04-18 |
20130093484 | DELAY CIRCUIT AND METHOD FOR DRIVING THE SAME - A delay circuit includes a pulse generation unit configured to generate a pulse signal, which is activated in response to an input signal and has a pulse width corresponding to delay information, and an output unit configured to activate a final output signal in response to a deactivation of the pulse signal. | 2013-04-18 |
20130093485 | REDUCED VOLTAGE SWING CLOCK DISTRIBUTION - A system and method for reducing power consumption within clock distribution on a semiconductor chip. A 4-phase clock generator within a clock distribution network provides 4 non-overlapping clock signals dependent upon a received input clock. A reduced voltage swing clock generator receives the non-overlapping clock signals and charges and discharges a second set of clock lines in a manner sequenced by the non-overlapping clock signals. The sequencing prevents a voltage range from reaching a magnitude equal to a power supply voltage for each of the second set of clock lines. In one embodiment, the magnitude reaches half of the power supply voltage. The reduced voltage swing latch receives the second set of clock lines. The reduced voltage swing latch updates and maintains logical state based at least upon the received second set of clock lines. | 2013-04-18 |
20130093486 | INTEGRATED CIRCUIT HAVING LATCH-UP RECOVERY CIRCUIT - An integrated circuit includes first and second transistors, a switch, and a power-on reset (POR) circuit. The first transistor has a first current electrode, a second current electrode, and a control electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode, and a control electrode. The switch is for coupling the first and second transistors to receive a power supply voltage in response to an asserted bias control signal. The POR circuit has a latch-up detection circuit coupled to receive the power supply voltage and to a control terminal of the switch. The latch-up detection circuit is for detecting a low voltage condition of the power supply voltage, and in response, deasserting the bias control signal to decouple the first and second transistors from the power supply voltage. | 2013-04-18 |
20130093487 | ELECTRONIC DEVICE AND METHOD FOR LOW POWER RESET - An electronic device and a method for operating an electronic device, wherein the electronic device comprises a reset stage which is configured to have a power down threshold and a power cycle threshold. The voltage level of the power cycle threshold is lower than the voltage level of the power down threshold. The two threshold levels define a first and second interval for a supply voltage of the electronic device. A first interval is between the power cycle threshold and the power down threshold. A second interval is above the power down threshold. The reset stage is further configured to provide the control signal having a defined first state in the first interval and a defined second state in the second interval. The electronic device is set to a low power reset mode if the control signal is in the first state and the electronic device is enabled to enter an active mode if the control signal is in the second state. | 2013-04-18 |
20130093488 | TEST CIRCUIT AND METHODS FOR SPEED CHARACTERIZATION - A system and method for efficiently performing timing characterization of regions of an integrated circuit. An integrated circuit has monitors distributed in different physical regions across its die. Each monitor includes timing characterization and self-test circuitry. This circuitry includes one or more tunable delay lines used during timing measurements. The circuitry verifies the tunable delay lines are defect free prior to the timing measurements. If defects are detected, but tunable delay lines may still be used, a scaling factor may be generated for a failing tunable delay line. The scaling factor may be used during subsequent timing measurements to maintain a high accuracy for the measurements. The timing measurements may determine a particular physical region of the die provides fast or slow timing values. The resulting statistics of the timing measurements may be used to change an operational mode of the IC in at least the particular region. | 2013-04-18 |
20130093489 | SIGNAL CONVERTER EQUIPPED WITH OVERVOLTAGE PROTECTION MECHANISM - A signal converter equipped with an overvoltage protection mechanism includes a pulse width modulation unit, a timing processing unit, an overvoltage detection unit, a pulse width control unit and a multi-level conversion unit. The pulse width modulation unit converts an analog signal into a pulse signal. The timing processing unit converts the pulse signal into a digital signal and outputs the digital signal to the overvoltage detection unit. When the digital signal is higher than the maximum limitation or less than the minimum limitation, the overvoltage detection unit outputs an over-threshold signal to the pulse width control unit to allow the pulse width modulation unit to perform feedback adjustment and prevent the multilevel conversion unit connected to the timing processing unit from causing burnout of downstream circuits because the multilevel conversion unit outputs maximum power intensity of signal over a long time. | 2013-04-18 |
20130093490 | INTERNAL VOLTAGE GENERATION CIRCUIT AND METHOD - An internal voltage generation method includes the steps of: setting first to third sections by using a reference voltage; determining to which section an internal voltage level corresponds, among the first to third sections; and generating the internal voltage by controlling a voltage pumping amount according to a section corresponding to the internal voltage level. | 2013-04-18 |
20130093491 | SEMICONDUCTOR DEVICE AND LEVEL SHIFTING CIRCUIT FOR THE SAME - A level shifting circuit includes an inverter inverting an input voltage of an input node and driving a first voltage of a first node, a first output driving unit driving an output voltage of an output node to a first level in response to the first voltage of the first node, a first connection unit electrically coupling the first node to a second node or electrically isolating the first node from the second node in response to the first voltage of the first node, an internal driving unit driving a second voltage of the second node to a second level in response to the input voltage of the input node and the output voltage of the output node, and a second output driving unit driving the output voltage of the output node to the second level in response to the second voltage of the second node. | 2013-04-18 |
20130093492 | DEVICE - A semiconductor device has a first controlled chip, including a first replica output circuit having the same configuration as a first output circuit, a first ZQ terminal connected to the first replica output circuit, a first through electrode connected to the first ZQ terminal, and a first control circuit which sets the impedance of the first replica output circuit. A control chip includes a second ZQ terminal connected to the first through electrode, a comparator circuit which compares a voltage of the second ZQ terminal with a reference voltage, and a second control circuit | 2013-04-18 |
20130093493 | ARBITRARY MULTIBAND OVERLAY MIXER APPARATUS ANDMETHOD FOR BANDWIDTH MULTIPLICATION - An apparatus and method for splitting a wide band input signal and overlaying multiple frequency bands on each path associated with one or more digitizers. All frequencies from the split signal on each path can be fed to a mixer. The local oscillator of each mixer receives a sum of signals, which can each be set to any arbitrary frequency, as long as an associated matrix determinant of coefficients is non-zero. Each oscillator signal is multiplied by a coefficient, which can represent phase and magnitude, prior to summing the oscillator signals together. Each mixer mixes a combined signal with the input, thereby generating a set of multiple overlaid frequency bands. The digitized signals are processed to substantially reconstruct the original input signal. Thus, the wide band input signal is digitized using multiple individual digitizers. In particular, a system can support two wide band signals using four digitizers of narrower bandwidth. | 2013-04-18 |
20130093494 | DIFFERENTIAL CURRENT BUFFER - Apparatus and methods provide a differential current buffer. The current buffer has cross-coupled feedback and offers relatively good common-mode rejection and a relatively low and linear input impedance, which can reduce intermodulation distortion. The current buffer can be used in, for example, an RF modulator, such as a quadrature modulator. | 2013-04-18 |
20130093495 | TRANSMITTER - There is provided a transmitter with a small area and low noise. A direct RF modulation transmitter is constituted by an N-number of input signal delay-attached direct RF converters to which an I digital baseband signal is input, an M-number of input signal delay circuit-attached direct RF converters (DDRCs) to which a Q digital baseband signal is input, a Divide-by-2 divider for generating a differential local signal differing in phase by 90 degrees, an output matching circuit, and a delay control circuit for controlling an input data delay amount for the DDRCs. This transmitter sets delay amounts for the DDRCs using the delay control circuit independently. Particularly when N is set to equal M and the same amount of delay is set for N-number of converters corresponding to the I digital baseband signal and the Q digital baseband signal, noise reduction effect in a predetermined frequency band is heightened. | 2013-04-18 |
20130093496 | POWER-SAVING RECEIVER CIRCUITS, SYSTEMS AND PROCESSES - An electronic circuit includes a receiver circuit (BSP) operable to perform coherent summations having a coherent summations time interval, and a power control circuit ( | 2013-04-18 |
20130093497 | TUNNEL FIELD EFFECT TRANSISTOR (TFET) WITH LATERAL OXIDATION - A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling effect in a tunnel region underlying a drain region, during an OFF-state of the TFET. The reduction in tunneling effect results in a reduction or elimination of a flow of OFF-state leakage current between the source region and the drain region. The TFET may have components made from group III-V compound materials. | 2013-04-18 |
20130093498 | MATRIX-STAGES SOLID STATE ULTRAFAST SWITCH - A semiconductor switching device for switching high voltage and high current. The semiconductor switching device includes a control-triggered stage and one or more auto-triggered stages. The control-triggered stage includes a plurality of semiconductor switches, a breakover switch, a control switch, a turn-off circuit, and a capacitor. The control-triggered stage is connected in series to the one or more auto-triggered stages. Each auto-triggered stage includes a plurality of semiconductor switches connected in parallel, a breakover switch, and a capacitor. The control switch provides for selective turn-on of the control-triggered stage. When the control-triggered stage turns on, the capacitor of the control-triggered stage discharges into the gates of the plurality of semiconductor switches of the next highest stage to turn it on. Each auto-triggered stage turns on in a cascade fashion as the capacitor of the adjacent lower stage discharges or as the breakover switches of the auto-triggered stages turn on. | 2013-04-18 |
20130093499 | POWER SWITCH AND OPERATION METHOD THEREOF - A power switch includes a control circuit, a cross-coupled amplifier, a first switching circuit coupled between a first output terminal and the first controlled ground terminal, and a second switching circuit coupled between a second output terminal and the second controlled ground terminal. The control circuit is configured to connect the second controlled ground terminal to a ground during a first period that a voltage level at the first output terminal is switched from the ground to a first voltage level and to set the second controlled ground terminal at an elevated ground level during a second period that the voltage level at the first output terminal remains at the first voltage level. | 2013-04-18 |
20130093500 | PRESSURE DEPENDENT CAPACITIVE SENSING CIRCUIT SWITCH CONSTRUCTION - A user interface which includes a capacitive measurement circuit with a sense plate covered by an electrically conductive cover member, and wherein said circuit may sense two types of events, said types distinguished by an inverse change in measured capacitance, and wherein user proximity and touches with less than a minimum required force constitute one event type, and touches with more than said minimum force constitute the other event type. | 2013-04-18 |
20130093501 | ELECTRICAL STIMULATION DEVICE AND ELECTRICAL STIMULATION METHOD - In an electrical stimulation device and an electrical stimulation method thereof, electrical stimulation can be adjusted more in real time, and stability and safety of the electrical stimulation can be more improved. An electrical stimulation device includes an electrode an electrical signal supply section, a skin impedance detection section, and an electrical signal controller. The electrical signal supply section supplies an electrical signal for generating the electrical stimulation to the electrode. During the supply of the electrical signal, the electrical signal controller acquires information associated with skin impedance through the skin impedance detection section in a cycle shorter than a supply period of the electrical signal, and adjusts the electrical signal to be supplied to the electrode in the next cycle based on the acquired information associated with skin impedance. | 2013-04-18 |
20130093502 | APPARATUS AND METHOD FOR GENERATING DIGITAL VALUE - Provided is an apparatus for generating a digital value that may generate a random digital value, and guarantee time invariance of the generated digital value. The apparatus may include a digital value generator to generate a random digital value using semiconductor process variation, and a digital value freezing unit that may be connected to the digital value generator and fixed to one of a first state and a second state based on the generated digital value, to freeze the digital value. | 2013-04-18 |
20130093503 | HIGH CURRENT DRIVE SWITCHED CAPACITOR CHARGE PUMP - Systems, methods, and devices that employ a dynamic gate boost component (DGBC) to generate a desired boosted gate voltage to facilitate controlling an enhanced charge pump are presented. An enhanced charge pump can comprise a desired number of charge transfer switches (CTSs) and a desired number of DGBCs, wherein a DGBC can apply a desired boosted gate voltage to the gate of an associated CTS to control switching of the CTS. An auxiliary gate boost component (AGBC) of one circuit path can apply a desired boosted gate voltage to a CTS of another circuit path to control switching of that CTS. The AGBC and DGBC can operate to facilitate maintaining the overdrive voltages of all of the CTSs in the enhanced charge pump so that the overdrive voltages are essentially unchanged under various loading current conditions. Multiple enhanced charge pumps can be cascaded to produce a higher output voltage. | 2013-04-18 |
20130093504 | REFERENCE VOLTAGE GENERATORS, INTEGRATED CIRCUITS, AND METHODS FOR OPERATING THE REFERENCE VOLTAGE GENERATORS - A reference voltage generator is described. The reference voltage generator includes a proportional to absolute temperature (PTAT) current source, the PTAT current source being capable of providing a first current that is proportional to a temperature. The reference voltage generator further includes a current mirror comprising a first transistor and a second transistor, the current mirror configured to generate a second current proportional to the first current, wherein a ratio of the first current to the second current is equal to a ratio of a gate width of the first transistor to a gate width of the second transistor. The reference voltage generator further includes a voltage divider, the voltage divider being capable of receiving the second current, the voltage divider capable of outputting a reference voltage, the reference voltage being substantially independent from a change of the temperature. | 2013-04-18 |
20130093505 | ON-CHIP VOLTAGE REGULATOR - A digital logic controller for regulating a voltage of a SoC includes a first input for receiving a reference signal having a first property that is constant over a range of operating conditions of the SoC, and a second input for receiving a second signal that has a second property that is indicative of an operating condition of the SoC. The second property may vary over a range of operating conditions of the SoC. A comparator compares the first and second properties and the digital logic controller, based on the comparison, outputs to a regulation signal to a voltage regulator to regulate the voltage of the SoC at or near a target voltage that is higher than a minimum operating voltage of the SoC. | 2013-04-18 |
20130093506 | SOLID STATE DISK POWER SUPPLY SYSTEM - A solid state disk (SSD) power supply system includes power supply switching circuit. The power supply switching circuit comprises a first power input to receive a first direct current (DC) voltage signal, a second power input connected to a super capacitor to receive a second DC voltage signal provided by the super capacitor, a switching chip connected to the first and second power inputs and configured to select the second DC voltage signals to output in a situation that the first power input is disabled to receive the first DC voltage signal, a voltage converting chip to receive the voltage signal output from the switching chip, and a voltage output to output an operation voltage to an SSD according to the voltage signal. The switching chip and the voltage converting chip respectively output a first and second test signals for testing a discharging time of the super capacitor. | 2013-04-18 |
20130093507 | Op-R, A Solid State Filter - The device described herein proposes an electronic active filter void of capacitors and inductors. The circuit utilizes only operational amplifiers (OP-Amp) and resistors, hence the name Op-R. Although capable of being constructed of lumped circuit elements this filter is intended for integrated circuit (IC) applications. Filtering of signals can be accommodated from dc through the UHF frequency range depending on the selected op-amp ICs. Low pass, band pass, high pass, as well as band reject frequency responses are achievable. Although the circuits described herein are single input-single output, multiple inputs and outputs present no difficulty, being limited only chip space. Temperature and production spread variations are also considered within the realm of tenability. | 2013-04-18 |
20130093508 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region. | 2013-04-18 |
20130093509 | HYBRID COUPLER - A circuit for amplifying an input signal can comprise a plurality of couplers. A splitting coupler of the plurality of couplers can receive the input signal and a combining coupler of the plurality of couplers can provides an output signal. N number of amplifiers can be included in the circuit to amplify the input signal, wherein N is a non-binary integer greater than one. At least one of the plurality of couplers can comprise a hybrid coupler that has two ports terminated into substantially equal reactances. | 2013-04-18 |
20130093510 | HIGH-FREQUENCY SIGNAL AMPLIFIER - A high-frequency signal amplifier includes an amplifier having an input terminal and an output terminal, and amplifying a high-frequency signal; a signal line connected between the output terminal of the amplifier and an antenna; coupled lines arranged in parallel and coupled to the signal line and having different line lengths or differently terminated ends; and phase shifters shifting phase of high-frequency signals applied via the signal line and the coupled lines, supplying the high-frequency signals to the input terminal of the amplifier, and having different amounts of phase change. | 2013-04-18 |
20130093511 | APPARATUS AND METHOD FOR IMPROVING EFFICIENCY IN POWER AMPLIFIER - An apparatus and method for enhancing the whole efficiency of power amplification in a supply modulated amplifier are provided. The power amplification apparatus includes a controller, a Doherty power amplifier, and a supply modulated amplifier. The controller selects a power amplifier among the Doherty power amplifier and the supply modulated amplifier. The Doherty power amplifier amplifies a power of a transmission signal when the Doherty power amplifier is selected by the controller. The supply modulated amplifier amplifies the power of the transmission signal using a supply voltage determined considering the amplitude of the transmission signal, when the supply modulated amplifier is selected by the controller. | 2013-04-18 |
20130093512 | POWER AMPLIFIER AND OPERATION CONTROLLING CIRCUIT THEREOF - There are provided a power amplifier and an operation controlling circuit thereof. The power amplifier includes: a signal generating unit generating a current input signal; an amplifying unit amplifying the current input signal; and a driving circuit unit supplying a driving signal to the amplifying unit, wherein the signal generating unit includes a control circuit unit generating a predetermined voltage signal from input power and a current mirror circuit unit generating the current input signal from the voltage signal. | 2013-04-18 |
20130093513 | APPARATUS AND METHOD FOR EXPANDING OPERATION REGION OF POWER AMPLIFIER - An apparatus and a method for expanding an operation region in an envelope tracking power amplifier are provided. The apparatus for amplifying power of a transmission signal includes an amplitude component determination unit, a supply modulator, and a power amplify module. The amplitude component determination unit determines an amplitude component of a transmission signal. The supply modulator generates a supply voltage to be provided to the power amplify module depending on the amplitude component of the transmission signal determined by the amplitude component determination unit. The power amplify module amplifies power of the transmission signal depending on the supply voltage generated by the supply modulator. | 2013-04-18 |
20130093514 | POWER CONVERTER SYSTEM FOR MOBILE DEVICES - A power converter system for managing power between a power supply and a load, the system including: a first buck-boost circuit connected to the power supply; and a capacitor provided between the buck-boost circuit and the load to buffer power supply for the load. The system may include a second buck-boost circuit between the capacitor and the load. In another embodiment, a power converter system includes: a boost circuit connected to the power supply; a buck circuit connected to the load; and a capacitor provided between the boost circuit and the buck circuit to manage the supply of power to the load. | 2013-04-18 |
20130093515 | PWM COMPARATOR AND CLASS D AMPLIFIER - The present disclosure generally relates to a PWM comparator and a class D. The PWM comparator described above introduces current feedback mechanism, basing the waveform state of received high frequency triangle signal and the level state of output signal of the PWM comparator, the hysteresis is changing dynamically. In the same resolution, the noise resistance ability of the PWM comparator described above is much better than that of the conventional PWM comparators which has a fixed hysteresis, thus the PWM comparator can work stably even if the duty cycle of output signal is nearly 100%. | 2013-04-18 |
20130093516 | LOW OUTPUT IMPEDANCE RF AMPLIFIER - A radio frequency (RF) power amplifier includes a low impedance pre-driver driving the input of a common-source output amplifier stage. The preamplifier includes a first transistor that has a first terminal coupled to a preamplifier RF input node, a second terminal coupled to a preamplifier RF output node, and a third terminal coupled to a supply voltage node. A first inductor is coupled between the RF output node and a bias voltage node. A voltage difference between respective first and second voltages on the RF input node and the RF output node that are substantially in phase, determines current through the first transistor. | 2013-04-18 |
20130093517 | Buffer Amplifier - A buffer amplifier with unity voltage gain, high input impedance, high speed, high current gain, high output power and low offset includes three stages and a DC servo circuit. The first stage of the buffer amplifier contains complementary N-channel and P-channel MOSFET source followers that provide high input impedance to buffer the input signal source. A feedback DC servo signal is provided to correct the subsequent stages so as to maintain the output at virtual DC ground level. The second stage is a driver stage that also contains complementary N-channel and P-channel MOSFET source followers to provide sufficient current to drive the output stage. The last stage is an output stage that contains at least one pair of complementary power MOSFETs or BJTs to deliver high currents to a load. | 2013-04-18 |
20130093518 | BALANCED-INPUT CURRENT-SENSING DIFFERENTIAL AMPLIFIER - The invention relates to a current-sensing differential amplifier having a balanced input. | 2013-04-18 |
20130093519 | POSITIVE AND NEGATIVE VOLTAGE INPUT OPERATIONAL AMPLIFIER SET - A positive and negative voltage input operational amplifier includes a positive operational amplifier and a negative operational amplifier. Each of the positive operational amplifier and the negative operational amplifier has a reduced layout area and a lowered static current, so that the power consumption is effectively reduced. | 2013-04-18 |
20130093520 | POWER AMPLIFIER WITH LOW NOISE FIGURE AND VOLTAGE VARIABLE GAIN - The object of the present invention is a low noise figure amplifier with a variable gain which comprises a cascode amplification stage comprising, serially mounted, a low-voltage MOSFET transistor installed as a common source followed by a bipolar transistor with high breakdown voltage installed as a common base. A resistor is placed between the bipolar transistor's collector and the grid of the cascode stage's MOSFET transistor, and the cascode stage is electrically powered through a choke. | 2013-04-18 |
20130093521 | APPARATUS AND METHOD FOR INTERLEAVING SWITCHING IN POWER AMPLIFIER - An apparatus of a hybrid power modulator using interleaving switching is provided. The apparatus includes a linear switching unit for generating an output signal by comparing an envelope input signal and a feedback signal, an interleaving signal generator for generating an interleaving switching signal arranged not to supply the signal to input stages of P-type Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (FETs) and N-type MOS FETs of power cells at the same time by comparing the output signal and a reference signal, and a switching amplifying unit for determining a level of the switching signal using the interleaving switching signal. Hence, the hybrid power modulator using the interleaving switching method in the envelope signal of the wide bandwidth maintains high efficiency and high linearity. In addition, the buck converter can use the single inductor by preventing the simultaneous on/off of the power cells. | 2013-04-18 |
20130093522 | HIGH ACCURACY RC OSCILLATOR - A device includes an RC oscillator circuit and incorporates various features that individually and in combination can help improve the stability or accuracy of the oscillator output frequency. The oscillator circuit is operable to provide a tunable output frequency and includes a bias circuit switchable between first and second modes of operation. One of the modes has less drift in oscillator bias current relative to the other mode. The device also includes drift compensation circuitry that is operable to compensate for drift in the oscillator output frequency in a closed-loop mode of operation based on a comparison of the oscillator output frequency with a reference frequency. The device further includes a processor operable to compensate for temperature-based drift in the oscillator frequency in an open-loop mode of operation based on a measured temperature value in the vicinity of the oscillator circuit. | 2013-04-18 |
20130093523 | DIGITALLY CONTROLLED OSCILLATOR DEVICE AND HIGH FREQUENCY SIGNAL PROCESSING DEVICE - The present invention provides a digitally controlled oscillator device capable of realizing a reduction in DNL. The digitally controlled oscillator device includes, for example, an amplifier circuit block, coil elements and a plurality of unitary capacitor units coupled in parallel between oscillation output nodes. Each of the unitary capacitor units is provided with capacitive elements, and a switch which selects whether the capacitive elements should be allowed to contribute as set parameters for an oscillation frequency. The switch is driven by an on/off control line extending from a decoder circuit. The on/off control line is shielded between the oscillation output nodes by a shield section. | 2013-04-18 |
20130093524 | DIGITALLY CONTROLLED OSCILLATOR DEVICE AND HIGH FREQUENCY SIGNAL PROCESSING DEVICE - The present invention provides a digitally controlled oscillator device capable of reducing noise away from an oscillation frequency, and a high frequency signal processing device. Fractional capacitances are realized using a plurality of unitary capacitor units, for example. In one unitary capacitor unit, one ends of two types of capacitive elements are respectively coupled to oscillation output nodes. On the other hand, in the unitary capacitor units other than the one unitary capacitor unit, one ends of two types of capacitive elements are respectively coupled to a fixed voltage. The other ends of one capacitive elements in all the unitary capacitor units are coupled in common, and the other ends of other capacitive elements are also coupled in common. Turning on and off of respective switches in all the unitary capacitor units are controlled in common. | 2013-04-18 |
20130093525 | CIRCUIT AND METHOD FOR CORRECTING TEMPERATURE DEPENDENCE OF FREQUENCY FOR PIEZORESISTIVE OSCILLATORS - MEMS oscillators, which include a silicon-type, in particular piezoresistive resonators, can be used to provide a fixed, stable output frequency. Silicon has a natural temperature dependence of Young's modulus, therefore, as ambient temperature changes and/or the piezoresistive resonator is powered, the resonator temperature changes, and the resonance frequency of the resonator drifts. In order to account for the temperature drift of the piezoresistive resonator, the piezoresistive resonator itself is used as a temperature sensor. The relative resistance change of the piezoresistive resonator depends only on the relative temperature change and material property of the resonator. Therefore, an accurate temperature can be sensed directly on the piezoresistive resonator. The temperature drift information is provided to a frequency adjuster, which corrects the output frequency of the circuit. | 2013-04-18 |
20130093526 | "REPLICA BASED" VCO GAIN AND LOOP FILTER'S JITTER REDUCTION TECHNIQUE FOR RING OSCILLATOR PLLS - Reducing a gain of a VCO, which may be used in a serdes system, includes using an oscillator replicating the VCO. The oscillator frequency varies according to PVT conditions of circuit elements of the oscillator, which affect a speed of the circuit elements. A first circuit receives an output of the oscillator to produce a current that varies inversely proportionally to the oscillator frequency. A second circuit injects the current into a power supply line of the VCO. Thus, high VCO frequencies can be attained. By reducing the gain of the VCO, thermal noise contribution of the loop resistor and the loop capacitor required for desired loop bandwidth are reduced. During fast corner conditions, minimal current is injected into the VCO. During slow corner conditions, high current is injected into the VCO. These help keep VCTRL of the PLL loop close to a mid-rail operating region. | 2013-04-18 |
20130093527 | TRANSVERSE ACOUSTIC WAVE RESONATOR, OSCILLATOR HAVING THE RESONATOR AND METHOD FOR MAKING THE RESONATOR - A transverse acoustic wave resonator includes a base, a resonator component, a number of driving electrodes fixed to the base and a number of fixing portions connecting the base and the resonator component. The resonator component is suspended above a top surface of the base and is perpendicular to the base. The driving electrodes are coupling to side surfaces of the resonator component. The resonator component is formed in a shape of an essential regular polygon. The driving electrodes and the resonator component jointly form an electromechanical coupling system for converting capacitance into electrostatic force. Besides, a capacitive-type transverse extension acoustic wave silicon oscillator includes the transverse acoustic wave resonator and a method of fabricating the transverse acoustic wave resonator are also disclosed. | 2013-04-18 |
20130093528 | METHOD FOR OPERATING CONTROL EQUIPMENT OF A RESONANCE CIRCUIT AND CONTROL EQUIPMENT - The invention relates to a method for operating control equipment ( | 2013-04-18 |
20130093529 | OSCILLATOR ELEMENT AND METHOD FOR PRODUCING THE OSCILLATOR ELEMENT - An oscillator element according to one embodiment of the present invention includes a magnetoresistive element having a magnetization free layer, magnetization fixed layer, and a tunnel barrier layer. Provided on the magnetization free layer are a protection layer and an electrode having a point contact section where the electrode is partially in electrical contact with the protection layers. An interlayer insulating film is provided between the electrode and the protection layer. The area of the interface between the magnetization free layer and the tunnel barrier layer is larger than the surface area of the point contact section. Moreover, a portion of the protection layer in contact with the interlayer insulating film has a smaller thickness in a surface normal direction than the portion of the protection layer in contact with the electrode. | 2013-04-18 |
20130093530 | MARCHAND BALUN CIRCUIT - A Marchand balun circuit includes a Marchand balun, an unbalanced matching circuit, and a balanced matching circuit. The Marchand balun includes an unbalanced terminal, and two balanced terminals. The unbalanced matching circuit includes a first and the second impedances which are connected between the unbalanced terminal and ground in series, and a first resistor which is connected between ground and a connection node of the first and the second impedances. The balanced matching circuit includes a third and a fourth impedances which are connected between one balanced terminal and ground in series, a fifth and a sixth impedance which are connected between the other balanced terminal and ground in series, a second resistor which is connected between ground and a connection node of the third and the fourth impedances, and a third resistor which is connected between ground and a connection node of the fifth and the sixth impedances. | 2013-04-18 |
20130093531 | BALANCED-UNBALANCED TRANSFORMER - A balanced-unbalanced transformer includes: a balanced transmission line including paired transmission lines; an unbalanced transmission line; and two lead transmission lines connected to two neighboring end portions of four end portions of the paired transmission lines at a right angle to the paired transmission lines, wherein one of the two lead transmission lines has a first electrode face which faces the other of the two lead transmission lines, the other of the two lead transmission lines has a second electrode face which faces the one of the two lead transmission lines, and the first electrode face and the second electrode face are electrode faces of a capacitor. | 2013-04-18 |
20130093532 | FLEXIBLE PRINTED CIRCUIT BOARD - A flexible printed circuit board including: a base substrate; a pad formed on one surface side of the base substrate; and a ground plane layer formed on the other surface side of the base substrate, the ground plane layer including a ground-removed portion, the ground-removed portion being formed at a position facing the pad via the base substrate so as to be of similar shape to the pad and have an outer shape extended 100±50 μm outwardly from an outer shape of the pad. | 2013-04-18 |
20130093533 | M-WAY COUPLER - An M-way coupler having a first port, M second ports, M transmission line sections, M isolation resistors and a phase shifting network is disclosed, where M is an integer number greater than 1. The M transmission line sections couple the first port to the M second ports, respectively. Each of the M isolation resistors has a first terminal and a second terminal. The first terminals of the M isolation resistors are coupled to the M second ports, respectively. The phase shifting network has M I/O terminals coupled to the second terminals of the M isolation resistors, respectively. The phase shifting network is arranged to provide a phase shift within a predetermined tolerance margin between arbitrary two I/O terminals of the M I/O terminals of the phase shifting network. | 2013-04-18 |
20130093534 | Doherty Power Amplifier Network - The present invention is directed to a network that includes an output matching network coupled to an amplifier. The output matching network is configured to transform the at least one amplifier transistor output impedance to an output matching network impedance. A combiner network is coupled to the output matching network. The combiner network includes a first quarter wavelength transmission line coupled between the in-phase signal path and a combiner node. The combiner network further includes a bandwidth enhancement element coupled to the quadrature signal path at the combiner node and an impedance transformation element coupled between the combiner node and a load. The impedance transformation element is configured to substantially transform a combined output matching network impedance at the combiner node to the load impedance. | 2013-04-18 |
20130093535 | POWER COMBINER/DISTRIBUTOR, POWER AMPLIFYING CIRCUIT, AND WIRELESS APPARATUS - A power combiner/distributor including first, second, and third waveguides connected with each other in a planar shape, and for either one of distributing power inputted from the first waveguide to the second and third waveguides and combining powers inputted from the second and third waveguides to input the combined power to the first waveguide is provided. The power combiner/distributor includes a branch circuit connected with the first waveguide and for branching a transmission path formed in the first waveguide into first and second transmission paths, and decoupling circuits connected with the branch circuit and also to the second and third waveguides, respectively, the decoupling circuits having a power losing resonator coupled to the second and third waveguides, resonating within an operation frequency band, and causing a power loss. | 2013-04-18 |
20130093536 | MULTILAYER ELECTRONIC COMPONENT AND MULTILAYER ELECTRONIC COMPONENT MANUFACTURING METHOD - A multilayer electronic component and a multilayer electronic component manufacturing method are capable of easily controlling the degree of magnetic field coupling between inductors. Via-hole conductors are arranged so that they extend in a lamination direction in a laminate, and function as a first inductor. Via-hole conductors are arranged so that they extend in the lamination direction in the laminate, and function as a second inductor. A first capacitor and the first inductor define a first resonance circuit. A second capacitor and the second inductor define a second resonance circuit. The via-hole conductors are arranged in a first insulating layer so that they are spaced apart from each other by a first distance. The via-hole conductors are arranged in a second insulating layer so that they are spaced apart from each other by a second distance that is different from the first distance. | 2013-04-18 |
20130093537 | ACOUSTIC WAVE DEVICE - An acoustic wave device includes: an electrode that is located on a substrate and excites an acoustic wave; and an oxide silicon film that is doped with an element and provided so as to cover the electrode, wherein a normalized reflectance obtained by normalizing a local maximum value of a reflectance when a light is caused to enter an upper surface of the oxide silicon film doped with the element by a reflectance when a light having a wavelength at the local maximum value is caused to enter an upper surface of the substrate directly is equal to or larger than 0.96. | 2013-04-18 |
20130093538 | SURFACE ACOUSTIC WAVE DEVICE AND ELECTRONIC COMPONENT - Disclosed is a surface acoustic wave device which has IDT electrodes arranged over a lithium tantalate piezoelectric substrate and is capable of suppressing propagation losses even at a high frequency band equal to or higher than 2 GHz as low as possible in order to utilize surface acoustic waves including LSAW. For this purpose, 45° to 46° rotated YX-cut lithium tantalate substrate is used as the piezoelectric substrate, a thickness of the IDT electrode is set to 7.5% λ to 8% λ, and a metallization ratio in electrode fingers of the IDT electrode is set to 0.55 to 0.65. | 2013-04-18 |
20130093539 | METHOD FOR MANUFACTURING AN RF FILTER AND AN RF FILTER - The invention relates to a method for manufacturing an RF filter comprising several resonator cavities and an RF filter manufactured by the method. The resonator cavities are formed into shape from a copper plate in a first manufacturing phase. In a second manufacturing phase the formed resonator cavities are inserted or integrated into a chassis material of the RF filter. | 2013-04-18 |
20130093540 | INDUCTION GENERATOR - An induction generator for a radio switch having a magnet element as well as an induction coil with a coil core wherein the coil core is U-shaped, wherein a first rest position and a second rest position are in each case defined for the magnet element, in contact with the limbs of the coil core, and a flux direction reversal takes place in the coil core, whenever a change takes place between these positions, wherein a movement path for the magnet element is predetermined for a movement between the rest positions, wherein the induction generator has a first mechanical energy storage device which is operatively connected to the magnet element and first of all stores energy in the course of forcing a movement from a rest position and, after reaching an intermediate position, which is defined along the movement path and corresponding to which the magnetic forces on the coil core suddenly decrease, emits this energy to the magnet element in order to mechanically accelerate the movement of the magnet element to the respective other rest position after leaving the intermediate position. | 2013-04-18 |
20130093541 | SHORT-CIRCUIT RELEASE HAVING AN OPTIMIZED COIL CONNECTION - A short-circuit release is disclosed, in particular for a power circuit-breaker, including an armature and a pole, that are located inside of a coil element; and a yoke plate and a terminal connection, which are arranged around the coil element. In at least one embodiment, a coil is wound on the coil element, the two ends of which are weldable on corresponding coil terminals from the same side. | 2013-04-18 |
20130093542 | ELECTROMAGNETIC RELAY - An electromagnetic relay includes a fixed iron core, a movable iron core opposed to the fixed iron core, a magnetizing coil for generating a magnetic force when energized to make the movable iron core attracted by the fixed iron core, a movable contact coupled with the movable iron core, a fixed contact opposed to be contacted with the movable contact, a reset spring for reset the movable iron core, and a repulsive-force generating coil. The repulsive-force generating coil generates a magnetic field opposing to a remaining magnetic field of the movable iron core while the movable iron core moves from a position where the movable contact has passed through an arc field where an arc discharge between movable contact and the fixed contact to be occurred to a position where the movable iron core is just about to expand the reset spring fully. | 2013-04-18 |
20130093543 | WIND SWITCH AND METHOD FOR ITS ADJUSTMENT AND TARING - Wind switch to be installed on outdoor devices to be protected from the wind. The switch comprises a spring, strip or coil ( | 2013-04-18 |
20130093544 | BISTABLE HIGH-PERFORMANCE MINIATURE RELAY - Bistable high-performance miniature relay, comprising an insulating housing having a first housing chamber ( | 2013-04-18 |
20130093545 | MAGNETO-RESISTANCE QUADRUPOLE MAGNETIC CODED SWITCH - A quadrupole magnetic coded switch includes a switch housing, an actuator housing, a first pair of actuator dipole magnets, a first pair of switch dipole magnets, and a pair of first magneto-resistance (MR) sensors. The actuator housing is movable relative to the switch housing. The first pair of actuator dipole magnets is coupled to the actuator housing and is movable therewith, and the first pair of switch dipole magnets is coupled to the switch housing. The first pair of actuator dipole magnets and the first pair of switch dipole magnets are arranged to generate a first quadrupole magnetic field. Each of the first MR sensors is disposed within the switch housing and is configured to vary in resistance in response to relative movement of the actuator housing and the switch housing. | 2013-04-18 |