16th week of 2013 patent applcation highlights part 56 |
Patent application number | Title | Published |
20130097348 | METHOD AND SYSTEM FOR COMMUNICATING WITH AND PROGRAMMING A SECURE ELEMENT - A method, device, and system are disclosed that enable the in-situ programming of an on-board secure element. A communication bus normally used to facilitate communications between the secure element and a microprocessor is borrowed to facilitate the in-situ programming with an off-board secure element. The microprocessor is disclosed to include the functionality to switch the configuration of the communication bus to enable the in-situ programming. | 2013-04-18 |
20130097349 | Quality of Service Arbitration Method and Quality of Service Arbiter Thereof - A quality of service (QoS) arbitration method for an on-chip bus is disclosed. The bus arbitration method includes steps of classifying each of a plurality of requestors into one of a plurality of first QoS types; classifying the each of the plurality of requestors into one of a plurality of second QoS types corresponding to a plurality of service priorities according to a due date or a data rate of the each of the plurality of requestors and the one of the plurality of first QoS types; and choosing a requestor with a highest service priority among the plurality of requestors to service. | 2013-04-18 |
20130097350 | QOS BASED DYNAMIC EXECUTION ENGINE SELECTION - In one embodiment, a processor includes processing cores, and instruction stores storing instructions at least one instructions having a group number, each instruction store having a unique identifier. The processor also includes a group execution matrix having group execution masks and a store execution matrix having store execution masks. The processor further includes a core selection unit that, for each instruction, selects a store execution mask using the unique identifier as an index. The core selection unit for each instruction, selects at least one group execution mask using the group number as an index, and performs logic operations on the selected group execution mask and the store execution mask to create a core request mask. The processor also includes an arbitration unit that determines instruction priority, assigns an instruction for each available core, and signals the instruction store of the assigned instruction to send the assigned instruction to the available core. | 2013-04-18 |
20130097351 | System and Method for High-Performance, Low-Power Data Center Interconnect Fabric - A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch. | 2013-04-18 |
20130097352 | Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits - A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system. | 2013-04-18 |
20130097353 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 2013-04-18 |
20130097354 | PROTECTING MEMORY OF A VIRTUAL GUEST - The method for protecting memory of a virtual guest includes initializing a virtual guest on a host computing system. The host computing system includes a virtual machine manager that manages operation of the virtual guest. The virtual guest includes a distinct operating environment executing in a virtual operation platform provided by the virtual machine manager. The method includes receiving an allocation of run-time memory for the virtual guest, the allocation of run-time memory comprising a portion of run-time memory of the host computing system. The method includes setting, by the virtual guest, at least a portion of the allocation of run-time memory to be inaccessible by the virtual machine manager. | 2013-04-18 |
20130097355 | SYSTEM AND METHOD FOR KERNEL ROOTKIT PROTECTION IN A HYPERVISOR ENVIRONMENT - A system and method in one embodiment includes modules for creating a soft whitelist having entries corresponding to each guest kernel page in a guest operating system in a hypervisor environment, generating a page fault when an access attempt is made to a guest kernel page, fixing the page fault to allow access and execution if the guest kernel page corresponds to one of the entries in the soft whitelist, and denying execution if the guest kernel page does not correspond to any of the entries in the soft whitelist. If the page fault is an instruction page fault, and the guest kernel page corresponds to one of the entries in the soft whitelist, the method includes marking the guest kernel page as read-only and executable. The soft whitelist includes a hash of machine page frame numbers corresponding to virtual addresses of each guest kernel page. | 2013-04-18 |
20130097356 | SYSTEM AND METHOD FOR KERNEL ROOTKIT PROTECTION IN A HYPERVISOR ENVIRONMENT - A system and method for rootkit protection in a hypervisor environment includes modules for creating a soft whitelist having entries corresponding to each guest kernel page of a guest operating system in a hypervisor environment, wherein each entry is a duplicate page of the corresponding guest kernel page, generating a page fault when a process attempts to access a guest kernel page, and redirecting the process to the corresponding duplicate page. If the page fault is a data page fault, the method includes fixing the page fault, and marking a page table entry corresponding to the guest kernel page as non-executable and writeable. If the page fault is an instruction page fault, the method includes marking a page table entry corresponding to the guest kernel page as read-only. Redirecting changing a machine page frame number in a shadow page table of the hypervisor to point to the corresponding duplicate page. | 2013-04-18 |
20130097357 | METHOD FOR IDENTIFYING MEMORY OF VIRTUAL MACHINE AND COMPUTER SYSTEM THEREOF - A method for identifying memories of virtual machines is provided. The method is adapted to a computer system executing at least one virtual machine, and an operating system is executed on the virtual machine. The method includes the following steps. A kernel file of the operating system is obtained, and the kernel file includes version information of the operation system. A source code and a configuration file of the operating system are obtained according to the version information, and the versions of the source code and the configuration file are complied with the version of the operating system. An object file is generated by compiling a fixed interface function with the source code according to the configuration file. Memory pages of the virtual machine are identified according to the object file. Furthermore, a computer system using the foregoing method is also provided. | 2013-04-18 |
20130097358 | METHOD FOR SHARING MEMORY OF VIRTUAL MACHINE AND COMPUTER SYSTEM USING THE SAME - A method for sharing memories of virtual machines is provided. The method is applied for a computer system configured to execute at least one virtual machine. The method includes the following steps. A memory map corresponding to the virtual machines is obtained, wherein usage states of memory pages of the virtual machine are stored in the corresponding memory map. Unused memory pages of the virtual machines are marked as free pages according to the corresponding memory map. The free pages of the virtual machines are shared. Therefore, the unused memory pages in the virtual machine can be shared. A computer system using the foregoing method is also provided. | 2013-04-18 |
20130097359 | SYSTEM AND METHOD TO ENHANCE MEMORY PROTECTION FOR PROGRAMS IN A VIRTUAL MACHINE ENVIRONMENT - In a computer system supporting execution of virtualization software and at least one instance of virtual system hardware, an interface is provided into the virtualization software to allow a program to directly define the access characteristics of its program data stored in physical memory. The technique includes providing data identifying memory pages and their access characteristics to the virtualization software which then derives the memory access characteristics from the specified data. Optionally, the program may also specify a pre-defined function to be performed upon the occurrence of a fault associated with access to an identified memory page. In this manner, programs operating both internal and external to the virtualization software can protect his memory pages, without intermediation by the operating system software. | 2013-04-18 |
20130097360 | MAINTAINING PROCESSOR RESOURCES DURING ARCHITECTURAL EVENTS - In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced. | 2013-04-18 |
20130097361 | MEMORY DEVICE - A memory device includes a control part and a storage part. The control part includes a first interface, a second interface, and a storage controller. The first interface is connected to an electronic device through a first bus. The second interface is connected to the storage controller through a second bus. The storage part includes a third interface and a storage unit. The storage unit is connected to the third interface through a third bus. The control part and the storage part are connected through a connection of the second interface and the third interface. | 2013-04-18 |
20130097362 | DATA WRITING METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME - A data writing method, a memory controller using the method, and a memory storage apparatus using the method are provided. The method includes selecting a physical block as a reserved physical block for a plurality of updated physical blocks. The method also includes, when a host system is about to write updated data into a logical page belonging to a logical block and a physical page, which corresponds to the logical page, of a substitute physical block, which corresponds to an updated physical block mapped to the logical block, has stored data, independently assigning the reserved physical block to the updated physical block mapped to the logical block and writing the updated data into the reserved physical block. Accordingly, the method can complete data writing without performing a data merge operation, thereby shortening the time for performing a write command. | 2013-04-18 |
20130097363 | MEMORY CONTROL DEVICE - A memory control device for controlling a primary controller and a secondary controller to access a flash memory is provided. A bus switch is coupled to the primary controller, the secondary controller and the flash memory via a first, second and third serial peripheral interface (SPI) buses, respectively. A selecting unit selectively couples the third SPI bus to one of the first and second buses. When the bus switch receives an access request from the primary controller via the first SPI bus, the selecting unit couples the third SPI bus to the first SPI bus, so as to transmit a chip select signal, a clock signal and a master output slave input (MOSI) signal from the primary controller to the flash memory for accessing the flash memory. The first access request is provided by the first chip select signal. | 2013-04-18 |
20130097364 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A method of operating a nonvolatile memory device comprises defining a bit ordering for a plurality of n-bit (n>2) multi-level cells such that bit-reading numbers associated with different pages of the n-bit multi-level cells are substantially equalized, wherein the bit ordering assigns at least one bit “0” to an erased state of the n-bit multi-level cells, and programming n-bit data into each of the n-bit multi-level cells according to the bit ordering. | 2013-04-18 |
20130097365 | REDUCING A NUMBER OF CLOSE OPERATIONS ON OPEN BLOCKS IN A FLASH MEMORY - The disclosed subject matter includes a memory system with a flash memory and a flash memory controller. The flash memory controller is configured to divide the flash memory into virtual segments, each segment including blocks of flash memory cells. The controller is also configured to receive a write request to a location designated by a memory identifier and to map the memory identifier to a segment. When the segment matches an open segment and an open block can store the data, the controller is configured to retrieve the open segment and the open block from a collection tracking open blocks and to write the data to the open block. When the segment is different from the open segment, the controller is configured to close the open block, to write the data to a block in the segment, and to update the collection with the block in the segment. | 2013-04-18 |
20130097366 | STORAGE DEVICE AND USER DEVICE USING THE SAME - Provided are a storage device and a user device used by connecting to the user device. The storage device may include a nonvolatile memory and a control unit configured to control the nonvolatile memory. When write data is received from the host, the control unit outputs a first response signal including information indicating whether the write data is successfully received. When the write data is stored in the nonvolatile memory, the control unit outputs a second response signal including on whether the write data is successfully stored in the nonvolatile memory. Since the storage device does not require a program backup memory, it may be implemented in a small area. | 2013-04-18 |
20130097367 | APPARATUS, SYSTEM, AND METHOD FOR SOLID-STATE STORAGE AS CACHE FOR HIGH-CAPACITY, NON-VOLATILE STORAGE - An apparatus, system, and method are disclosed for solid-state storage as cache for high-capacity, non-volatile storage. The apparatus, system, and method are provided with a plurality of modules including a cache front-end module and a cache back-end module. The cache front-end module manages data transfers associated with a storage request. The data transfers between a requesting device and solid-state storage function as cache for one or more HCNV storage devices, and the data transfers may include one or more of data, metadata, and metadata indexes. The solid-state storage may include an array of non-volatile, solid-state data storage elements. The cache back-end module manages data transfers between the solid-state storage and the one or more HCNV storage devices. | 2013-04-18 |
20130097368 | AD HOC Flash Memory Reference Cells - A method for managing a flash memory that includes a plurality of primary cells and a plurality of spare cells includes interrogating the flash memory to determine which spare cells have been used to replace respective primary cells and using at least a portion of a remainder of the spare cells as reference cells. | 2013-04-18 |
20130097369 | APPARATUS, SYSTEM, AND METHOD FOR AUTO-COMMIT MEMORY MANAGEMENT - An apparatus, system, and method are disclosed for auto-commit memory management. The method includes receiving an auto-commit request from a client, such as a barrier request or a checkpoint request. The auto-commit request is associated with an auto-commit buffer of a non-volatile recording device. The method includes issuing a serializing instruction that flushes data from a processor complex to the auto-commit buffer. The method includes determining completion of the serializing instruction flushing the data to the auto-commit buffer. | 2013-04-18 |
20130097370 | FABRICATING AND OPERATING A MEMORY ARRAY HAVING A MULTI-LEVEL CELL REGION AND A SINGLE-LEVEL CELL REGION - Techniques are disclosed herein for applying different process steps to single-level cell (SLC) blocks in a memory array than to multi-level cell (MLC) blocks such that the SLC blocks will have high endurance and the MLC blocks will have high reliability. In some aspects, different doping is used in the MLC blocks than the SLC blocks. In some aspects, different isolation is used in the MLC blocks than the SLC blocks. Techniques are disclosed that apply different read parameters depending on how many times a block has been programmed/erased. Therefore, blocks that have been cycled many times are read using different parameters than blocks that have been cycled fewer times. | 2013-04-18 |
20130097371 | DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHANNEL - Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface. | 2013-04-18 |
20130097372 | METHOD FOR DETERMINING IDENTIFIERS OF SEGMENTS FORMING AN AUDIOVISUAL DOCUMENT AND RECEIVER IMPLEMENTING THE METHOD - The invention relates to a method for determining identifiers associated with segments of a document. Each segment consists of a series of individual elements such as images or sound sequences. Each segment of the document is subdivided into a determined number of portions comprising the same number of individual elements. An individual element is extracted from the most central portion of each segment and associated with the segment as identifier. | 2013-04-18 |
20130097373 | SYSTEMS AND METHODS OF MANAGING HARD DISK DEVICES - Systems and methods of managing hard disk devices are provided to wirelessly receive instructions from a user to enable safety features with respect to various conditions encountered by the hard disk devices. These conditions include changes in location, orientation, and the light intensity. Such changes initiate functions which serve to backup and protect the data stored on the hard drive. | 2013-04-18 |
20130097374 | EFFICIENT VOLUME MANAGER HOT SWAPPING - A method of updating an extent map is described. The method includes providing in a memory an instance of a first version of the extent map, wherein the instance is referenced by an application. The extent map include entries. The method further includes storing, at each extent map entry, an offset from the beginning of a physical drive which is identified within said each extent map entry, providing a second version of the extent map, comparing the first version of the extent map with the second version of the extent map, in response to the comparing, determining that is at least on segment in the second version of the extent map that is different from a corresponding at least one segment in the first version of the extent map. | 2013-04-18 |
20130097375 | STORAGE DEVICE AND REBUILD PROCESS METHOD FOR STORAGE DEVICE - A storage device includes a plurality of magnetic disk devices each having a write cache, a processor unit that redundantly stores data, a rebuild execution control unit that performs a rebuild process, a write cache control unit that, at the time of the rebuild process, enables a write cache of a storage device that stores rebuilt data, and a rebuild progress management unit that is configured using a nonvolatile memory and manages progress information of the rebuild process. In the case where power discontinuity is caused during the rebuild process and then power is restored, the rebuild execution control unit calculates an address that is before an address of last written rebuilt data by an amount corresponding to the capacity of the write cache based on the progress information of the rebuild process managed by the progress management unit and resumes the rebuild process from that calculated address. | 2013-04-18 |
20130097376 | METHODS AND APPARATUS FOR IMPROVED RAID PARITY COMPUTATION IN A STORAGE CONTROLLER - Methods and apparatus for improved calculation of redundancy information in RAID storage controllers. Features and aspects hereof provide for a firmware/software element (FPE) for generating redundancy information in combination with a custom logic circuit (HPE) designed to generate redundancy information. A scheduler element operable on a processor of a storage controller along with the FPE determines which of the FPE and HPE is best suited to rapidly complete a new redundancy computation operation and activates or queues the new operation for performance by the selected component. | 2013-04-18 |
20130097377 | METHOD FOR ASSIGNING STORAGE AREA AND COMPUTER SYSTEM USING THE SAME - When a method for relocating data to a preferable storage area based on access frequency is applied to virtual machines, it takes a long time for determining volumes that are not accessed, and the access performance is deteriorated. The present invention provides a system and method in which a utilization status of a virtual machine is checked by the storage system, and pages used by virtual machines not being utilized are relocated promptly to lower tiers and pages used by virtual machines being utilized are relocated promptly to higher tiers, according to which the performance of the system is improved. | 2013-04-18 |
20130097378 | STORAGE SYSTEM AND CONTROL METHOD THEREOF AS WELL AS PROGRAM - In a storage system in which computers are connected via a network, in order to avoid a state where communication quality is degraded due to poor performance of an apparatus constituting the network, for a transfer data amount, an amount of data sent out from a storage apparatus is suppressed. Moreover, the storage apparatus inhibits a read-ahead process, in accordance with the suppression of the sending out of the data. Furthermore, proper load allocation is realized by migrating a logical storage unit provided by the storage, to another network interface or a second storage apparatus, without changing a configuration of the network. | 2013-04-18 |
20130097379 | STORAGE SYSTEM AND METHOD OF CONTROLLING STORAGE SYSTEM - It is provided a storage system for storing data requested by a host computer to be written, the storage system comprising: at least one processor, a cache memory and a cache controller. The cache memory includes a first memory which can be accessed by way of either access that can specify an access range by a line or access that continuously performs a read and a write. The cache controller includes a second memory which has a higher flexibility than the first memory in specifying an access range. The cache controller determines an address of an access destination upon reception of a request for an access to the cache memory from the at least one processor, and switches a request for an access to a specific address into an access to a corresponding address in the second memory. | 2013-04-18 |
20130097380 | METHOD FOR MAINTAINING MULTIPLE FINGERPRINT TABLES IN A DEDUPLICATING STORAGE SYSTEM - A system and method for managing multiple fingerprint tables in a deduplicating storage system. A computer system includes a storage medium, a first fingerprint table comprising a first plurality of entries, and a second fingerprint table comprising a second plurality of entries. Each of the first plurality of entries and the second plurality of entries are configured to store fingerprint related data corresponding to data stored in the storage medium. A storage controller is configured to select the first fingerprint table for storage of entries corresponding to data stored in the data storage medium that has been deemed more likely to be successfully deduplicated than other data stored in the data storage medium; and select the second fingerprint table for storage of entries corresponding to data stored in the data storage medium that has been deemed less likely to be successfully deduplicated than other data stored in the storage medium. | 2013-04-18 |
20130097381 | MANAGEMENT APPARATUS, MANAGEMENT METHOD, AND PROGRAM - There is provided a management apparatus including a management unit that manages, based on execution control information indicating an execution sequence of a plurality of applications, an execution area and a cache area of a recording medium which temporarily stores the applications when the applications are executed. | 2013-04-18 |
20130097382 | MULTI-CORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD - A multi-core processor system includes a first processor that among cores of the multi-core processor, identifies other cores having a cache miss-hit rate lower than that of a given core storing a specific program in a cache, based on a task information volume of each core; a control circuit that migrates the specific program from the cache of the given core to a cache of the identified core; and a second processor that, after the specific program is migrated to the cache of the identified core, sets as a write-inhibit area, an area that is of the cache of the identified core and to which the specific program is stored. | 2013-04-18 |
20130097383 | METHODS FOR PROVIDING A RESPONSE AND SYSTEMS THEREOF - A method, computer readable medium, and system for generating a response includes determining from which of a plurality of levels of cache to retrieve a response. The determination is based on a number of matches between current user session data associated with a current request and stored user session data rewritten into each of one or more metadata data variables for the response when a current request for the response matches at least one prior stored request for the response. The response from the determined level of the plurality of levels of cache is provided. | 2013-04-18 |
20130097384 | MULTI-CORE PROCESSOR SYSTEM, CACHE COHERENCY CONTROL METHOD, AND COMPUTER PRODUCT - A multi-core processor system includes a processor configured to establish coherency of shared data values stored in a cache memory accessed by a multiple cores; detect a first thread executed by a first core among the cores; identify upon detecting the first thread, a second thread under execution by a second core other than the first core and among the cores; determine whether shared data commonly accessed by the first thread and the second thread is present; and stop establishment of coherency for a first cache memory corresponding to the first core and a second cache memory corresponding to the second core, upon determining that no shared data commonly accessed is present. | 2013-04-18 |
20130097385 | DUAL-GRANULARITY STATE TRACKING FOR DIRECTORY-BASED CACHE COHERENCE - A system and method of providing directory cache coherence are disclosed. The system and method may include tracking the coherence state of at least one cache block contained within a region using a global directory, providing at least one region level sharing information about the least one cache block in the global directory, and providing at least one block level sharing information about the at least one cache block in the global directory. The tracking of the provided at least one region level sharing information and the provided at least one block level sharing information may organize the coherence state of the at least one cache block and the region. | 2013-04-18 |
20130097386 | CACHE MEMORY SYSTEM FOR TILE BASED RENDERING AND CACHING METHOD THEREOF - A cache memory system and a caching method for a tile-based rendering may be provided. Each of cache lines in the cache memory system may include delayed-replacement information. The delayed-replacement information may indicate whether texture data referred to at a position of an edge of a tile is included in a cache line. When a cache line corresponding to an access-requested address is absent in the cache memory system, the cache memory system may select and remove a cache line to be removed from an associative cache unit, based on delayed-replacement information. | 2013-04-18 |
20130097387 | MEMORY-BASED APPARATUS AND METHOD - Aspects of various embodiments are directed to memory circuits, such as cache memory circuits. In accordance with one or more embodiments, cache-access to data blocks in memory is controlled as follows. In response to a cache miss for a data block having an associated address on a memory access path, data is fetched for storage in the cache (and serving the request), while one or more additional lookups are executed to identify candidate locations to store data. An existing set of data is moved from a target location in the cache to one of the candidate locations, and the address of the one of the candidate locations is associated with the existing set of data. Data in this candidate location may, for example, thus be evicted. The fetched data is stored in the target location and the address of the target location is associated with the fetched data. | 2013-04-18 |
20130097388 | DEVICE AND DATA PROCESSING SYSTEM - A device is disclosed which includes a register storing a plurality of latency data and a control unit responding to the latency data. Each of the latency data indicates a period of time between issue of a data transfer request command responsive to an access request from one of access request sources and initiation of a data transfer operation responsive to the data transfer request command. The control unit controls an order in issue of data transfer request commands responsive to access requests from the access request sources so that between issue of a first data transfer request command responsive to a first access request and initiation of a first data transfer operation responsive to the first data transfer request command, at least issue of a second data transfer request command responsive to a second access request is performed. | 2013-04-18 |
20130097389 | MEMORY ACCESS CONTROLLER, MULTI-CORE PROCESSOR SYSTEM, MEMORY ACCESS CONTROL METHOD, AND COMPUTER PRODUCT - A memory access controller includes a semiconductor circuit configured to classify into a first group of cores having made an exclusive access request to shared memory and a second group of cores not having made an exclusive access request to the shared memory, multiple cores capable of accessing the shared memory; detect a core having completed the exclusive access among the first group of cores; and send to a core among the first group of cores and standing by for the exclusive access, a notification of release from a standby state, when detecting a core having completed the exclusive access. | 2013-04-18 |
20130097390 | Memory controller and methods - A memory controller that allows shared access to a memory device via a plurality of write ports and read ports. | 2013-04-18 |
20130097391 | Concurrent Execution of Critical Sections by Eliding Ownership of Locks - Critical sections of multi-threaded programs, normally protected by locks providing access by only one thread, are speculatively executed concurrently by multiple threads with elision of the lock acquisition and release. Upon a completion of the speculative execution without actual conflict as may be identified using standard cache protocols, the speculative execution is committed, otherwise the speculative execution is squashed. Speculative execution with elision of the lock acquisition, allows a greater degree of parallel execution in multi-threaded programs with aggressive lock usage. | 2013-04-18 |
20130097392 | PROTECTING MEMORY OF A VIRTUAL GUEST - An apparatus and system for protecting memory of a virtual guest includes initializing a virtual guest on a host computing system. The host computing system includes a virtual machine manager that manages operation of the virtual guest. The virtual guest includes a distinct operating environment executing in a virtual operation platform provided by the virtual machine manager. The method includes receiving an allocation of run-time memory for the virtual guest, the allocation of run-time memory comprising a portion of run-time memory of the host computing system. The method includes setting, by the virtual guest, at least a portion of the allocation of run-time memory to be inaccessible by the virtual machine manager. | 2013-04-18 |
20130097393 | MEMORY CONTROL DEVICE, MEMORY CONTROL METHOD, DATA PROCESSING DEVICE, AND IMAGE PROCESSING SYSTEM - A memory control device that transfers data from an external memory to a data processing unit having plural processing mechanisms, includes an absolute address storage unit that stores an absolute address serving as a common reference value in a given data transfer period; a differential address storage unit that stores plural differential addresses therein; a differential address selection unit that selects any one of the plurality of differential addresses in a given order; a memory address generation unit that combines any differential address selected by the differential address selection unit with the absolute address to generate a memory address; and a data transfer unit that inputs the memory address generated by the memory address generation unit to the external memory, reads the data from the memory address, and transfers the data to the data processing unit. | 2013-04-18 |
20130097394 | MEMORY CONTROLLER AND METHODS - A memory controller that allows shared access to a memory device via a plurality of write ports and read ports. A write port includes a data buffer that allows data to be written to a first number of its storage locations at a pre-determined time. A write arbiter is able to read data from a second number of storage locations of a data buffer of a write port at a pre-determined time and write the read data to a memory device. A read port is configured to respond to requests to read data and includes a data buffer. A read arbiter is able to read, at a pre-determined time, data from the memory device on behalf of one of the read ports, and to write the read data into a second number of storage locations of the data buffer of the read port on whose behalf the data was read. | 2013-04-18 |
20130097395 | METHOD AND APPARATUS FOR SENDING DATA FROM MULTIPLE SOURCES OVER A COMMUNICATIONS BUS - In a memory system, multiple memory modules communicate over a bus. Each memory module may include a hub and at least one memory storage unit. The hub receives local data from the memory storage units, and downstream data from one or more other memory modules. The hub assembles data to be sent over the bus within a data block structure, which is divided into multiple lanes. An indication is made of where, within the data block structure, a breakpoint will occur in the data being placed on the bus by a first source (e.g., the local or downstream data). Based on the indication, data from a second source (e.g., the downstream or local data) is placed in the remainder of the data block, thus reducing gaps on the bus. Additional apparatus, systems, and methods are disclosed. | 2013-04-18 |
20130097396 | METHOD AND SYSTEM FOR ENCODING DATA FOR STORAGE IN A MEMORY ARRAY - A method of storing data into a memory array converts an input string into a first binary array with (m−1) rows and (n−1) columns. A second binary array with m rows and n columns in an encoded bit pattern is then generated from the first binary array. The second binary array in the encoded bit pattern has at most n/2 1's in each row and at most m/2 1's in each column, and the m-th row and an n-th column contain information for decoding other entries of the second binary array. The encoded bit pattern of the second binary array is then stored into corresponding memory devices of the memory array. | 2013-04-18 |
20130097397 | METHODS AND SYSTEMS FOR AUTOMATED BACKUPS AND RECOVERY ON MULTI-OS PLATFORMS USING CONTROLLER BASED SNAPSHOTS - A method for backing up and restoring data across multiple operating systems executed by a computing product executing computer implemented instructions, wherein each operating system includes a daemon. Embodiments may include receiving a backup initiation trigger from an initial, daemon on an initial operating system. This method may include relaying the backup initiation trigger to other daemons on other operating systems. This method may also include receiving snapshot requests from the other daemons, wherein each of the snapshot requests are requests for snapshots of storage associated with an operating system of one of the other operating systems. This method may further include sending received snapshot requests from the other daemons to a storage controller. | 2013-04-18 |
20130097398 | GENERATING AND USING CHECKPOINTS IN A VIRTUAL COMPUTER SYSTEM - To generate a checkpoint for a virtual machine (VM), first, while the VM is still running, a copy-on-write (COW) disk file is created pointing to a parent disk file that the VM is using. Next, the VM is stopped, the VM's memory is marked COW, the device state of the VM is saved to memory, the VM is switched to use the COW disk file, and the VM begins running again for substantially the remainder of the checkpoint generation. Next, the device state that was stored in memory and the unmodified VM memory pages are saved to a checkpoint file. Also, a copy may be made of the parent disk file for retention as part of the checkpoint, or the original parent disk file may be retained as part of the checkpoint. If a copy of the parent disk file was made, then the COW disk file may be committed to the original parent disk file. | 2013-04-18 |
20130097399 | INTERFACE FOR MANAGEMENT OF DATA MOVEMENT IN A THIN PROVISIONED STORAGE SYSTEM - A computational device receives a request to copy a source logical block of a thin provisioned source logical unit to a target logical block of a thin provisioned target logical unit, wherein in thin provisioned logical units physical storage space is allocated in response to a write operation being performed but not during creation of the thin provisioned logical units. The computational device generates metadata that stores a correspondence between the source logical block and the target logical block, while avoiding allocating any physical storage space for the target logical block in the thin provisioned target logical unit. | 2013-04-18 |
20130097400 | STORAGE SYSTEM AND CONTROLLING METHODS FOR THE SAME - For the purpose of optimizing the performance separation according to the usage status of the protocol and the storage system performance, in a storage system | 2013-04-18 |
20130097401 | MEMORY MANAGER - A memory management device including a plurality of outputs, each output configured to interface to respective one of a plurality of memories; and a controller configured to cause each buffer allocated to the memories to be divided up substantially equally between each of the plurality of memories. | 2013-04-18 |
20130097402 | DATA PREFETCHING METHOD FOR DISTRIBUTED HASH TABLE DHT STORAGE SYSTEM, NODE, AND SYSTEM - Embodiments of the present disclosure provide a data prefetching method, a node, and a system. The method includes: a first storage node receives a read request sent by a client, determines a to-be-prefetched data block and a second storage node where the to-be-prefetched data block resides according to a read data block and a set to-be-prefetched data block threshold, and sends a prefetching request to the second storage node, the prefetching request includes identification information of the to-be-prefetched data block, and the identification information is used to identify the to-be-prefetched data block; and the second storage node reads the to-be-prefetched data block from a disk according to the prefetching request, and stores the to-be-prefetched data block in a local buffer, so that the client reads the to-be-prefetched data block from the local buffer of the second storage node. | 2013-04-18 |
20130097403 | Address Mapping in Memory Systems - A memory system includes an address mapping circuit. The address mapping circuit receives an input memory address having a first set of address bits. The address mapping circuit applies a logic function to the input memory address to generate a mapped memory address. The logic function uses at least a subset of the first set of address bits in two separate operations that respectively determine two portions of the mapped memory address. | 2013-04-18 |
20130097404 | DATA COMMUNICATIONS IN A PARALLEL ACTIVE MESSAGING INTERFACE OF A PARALLEL COMPUTER - Eager send data communications in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI composed of data communications endpoints that specify a client, a context, and a task, including receiving an eager send data communications instruction with transfer data disposed in a send buffer characterized by a read/write send buffer memory address in a read/write virtual address space of the origin endpoint; determining for the send buffer a read-only send buffer memory address in a read-only virtual address space, the read-only virtual address space shared by both the origin endpoint and the target endpoint, with all frames of physical memory mapped to pages of virtual memory in the read-only virtual address space; and communicating by the origin endpoint to the target endpoint an eager send message header that includes the read-only send buffer memory address. | 2013-04-18 |
20130097405 | APPARATUS AND METHOD FOR ABSTRACT MEMORY ADDRESSING - An apparatus for abstract memory addressing. A processor for generating an abstract memory address. A base register for storing a base memory address. An adder for adding the base memory address to the abstract memory address and generating a physical address for a device memory. A pointer register for storing the physical address, wherein the pointer register is directly coupled to the device memory. | 2013-04-18 |
20130097406 | CLUSTER COMPUTING USING SPECIAL PURPOSE MICROPROCESSORS - In some embodiments, a computer cluster system comprises a plurality of nodes and a software package comprising a user interface and a kernel for interpreting program code instructions. In certain embodiments, a cluster node module is configured to communicate with the kernel and other cluster node modules. The cluster node module can accept instructions from the user interface and can interpret at least some of the instructions such that several cluster node modules in communication with one another and with a kernel can act as a computer cluster. | 2013-04-18 |
20130097407 | UNIFIED, WORKLOAD-OPTIMIZED, ADAPTIVE RAS FOR HYBRID SYSTEMS - A method, system, and computer program product for maintaining reliability in a computer system. In an example embodiment, the method includes managing workloads on a first processor with a first processor architecture by an agent process executing on a second processor with a second processor architecture. The method proceeds by activating redundant computation on the second processor by the agent process. The method continues by performing a same computation from a workload of the workloads at least twice. Finally, the method includes comparing results of the same computation. In this embodiment the first processor is coupled the second processor by a network, and the first processor architecture and second processor architecture are different architectures. | 2013-04-18 |
20130097408 | CONDITIONAL COMPARE INSTRUCTION - An instruction decoder ( | 2013-04-18 |
20130097409 | INSTRUCTION-ISSUANCE CONTROLLING DEVICE AND INSTRUCTION-ISSUANCE CONTROLLING METHOD - In a multithread processor capable of executing a plurality of threads, in order to select a thread and instruction for increasing a throughput of the multithread processor, an instruction-issuance controlling device included in the multithread processor includes a resource management unit configured to manage stall information indicating whether or not each of threads in execution is in a stalled state; a thread selection unit configured to select a thread which is not in the stalled state among the threads in execution; and an instruction-issuance controlling unit configured to perform controlling so that simultaneously issuable instructions are issued from among the selected thread. | 2013-04-18 |
20130097410 | MACHINE PROCESSOR - Disclosed are machine processors and methods performed thereby. The processor has access to processing units for performing data processing and to libraries. Functions in the libraries are implementable to perform parallel processing and graphics processing. The processor may be configured to acquire (e.g., to download from a web server) a download script, possibly with extensions specifying bindings to library functions. Running the script may cause the processor to create, for each processing unit, contexts in which functions may be run, and to run, on the processing units and within a respective context, a portion of the download script. Running the script may also cause the processor to create, for a processing unit, a memory object, transfer data into that memory object, and transfer data back to the processor in such a way that a memory address of the data in the memory object is not returned to the processor. | 2013-04-18 |
20130097411 | TRANSFERRING ARCHITECTED STATE BETWEEN CORES - A method and apparatus for transferring architected state bypasses system memory by directly transmitting architected state between processor cores over a dedicated interconnect. The transfer may be performed by state transfer interface circuitry with or without software interaction. The architected state for a thread may be transferred from a first processing core to a second processing core when the state transfer interface circuitry detects an error that prevents proper execution of the thread corresponding to the architected state. A program instruction may be used to initiate the transfer of the architected state for the thread to one or more other threads in order to parallelize execution of the thread or perform load balancing between multiple processor cores by distributing processing of multiple threads. | 2013-04-18 |
20130097412 | Performing A Boot Sequence In A Multi-Processor System - Methods, apparatuses, and computer program products for performing a boot sequence in a multi-processor system are provided. Embodiments include: in response to detecting initiation of a boot sequence of the multi-processor system, initializing, by a bootstrap processor (BSP), BSP memory associated with the BSP and initializing, by an application processor, memory associated with the application processor; determining, by the BSP, whether the initialization of the BSP memory is completed; and if the initialization of the BSP memory is completed, loading, by the BSP, an operating system on the BSP memory regardless of whether the application processor has completed initialization of the memory associated with the application processor. | 2013-04-18 |
20130097413 | COMPUTING DEVICE AND METHOD FOR CONTROLLING A STARTUP CURRENT OF A STORAGE SYSTEM - A method for controlling a startup current of a storage system using a computing device, the computing device detects a current of each storage device of the storage system when the storage system is turned on, and calculates the power drawn by each storage device according to the current of each storage device. If a sum of powers drawn by all the storage devices is greater than a predetermined value, the computing device turns off the storage system and determines a startup sequence of the storage devices and a startup time of each storage device. The startup time of each storage device is stored in a storage unit. | 2013-04-18 |
20130097414 | METHODS AND RECONFIGURABLE SYSTEMS TO INCORPORATE CUSTOMIZED EXECUTABLE CODE WITHIN A CONDITION BASED HEALTH MAINTENANCE SYSTEM WITHOUT RECOMPILING BASE CODE - A system for reconfiguring a node of a complex system health monitoring system without recompiling and relinking executable code is provided. The system includes a software module containing previously compiled instructions to perform one of a plurality of different standardized functions and a computing node comprising a processor and plurality of software objects, the processor configured to execute the previously compiled instructions. The system further includes a configuration file configured to provide static and dynamic data to the software module, the configuration file comprising a dynamic data store (DDS), a static data store (SDS) and a binary code database (BCD). The BCD comprises a library of externally compiled executable algorithms that are callable by the software module. The BCD being configured with database identification and retrieval data structures associated with library of externally compiled executable algorithms. | 2013-04-18 |
20130097415 | Central Processing Unit Monitoring and Management Based On A busy-Idle Histogram - The aspects enable a computing device or microprocessor to adjust the operations of a processor in view of a current processor workload based on a histogram-like data structure. A histogram-like data structure characterizing one of processor busy and/or idle durations or busy/idle ratios is generated at runtime and used to model the processor workload. The processor workload is used to predict future processing requirements and to adjust the processor's operations such that they are commensurate with the processing and workload requirements. The histogram-like data structure may alternatively be used to estimate a current quality of service (QoS) of a communication link so that link management actions may be taken. | 2013-04-18 |
20130097416 | DYNAMIC PROFILE SWITCHING - Methods and apparatuses are disclosed for dynamic switching of user profiles on computing devices. In one method, the computing device identifies a first user profile under which the computing device is operating. The first user profile is associated with a first user value indicative of a first user. The computing device receives an image from an image-sensing device, generates a current user value indicative of a current user based on the received image, and determines if the current user value corresponds to the first user value. If the current user value does not correspond to the first user value, the computing device configures at least some programs operating on the computing device using a second user profile that is selected based on the current user value. If the current user value does correspond to the first user value, the computing device continues to operate using the first user profile. | 2013-04-18 |
20130097417 | SECURE PRIVATE COMPUTATION SERVICES - An encryption scheme allows meaningful, efficient computation of encrypted data in various application domains, including without limitation patient health care, financial analysis, market research, and targeted advertising. Data providers, computational services, and results consumers work in concert using a somewhat homomorphic encryption scheme to preserve the secrecy while providing practical computational performance. Encrypted data is stored within network-accessible storage. The data is encrypted using an encryption scheme that allows predictive analysis on the encrypted data without decrypting the encrypted data. The predictive analysis includes evaluation of polynomials of bounded degree on elements of the encrypted data. The evaluation includes ciphertext addition compositions and a bounded number of ciphertext multiplication compositions. The predictive analysis is performed on the encrypted data without decrypting the encrypted data to create encrypted results, which are transmitted to an entity possessing a decryption key capable of decrypting the encrypted results. | 2013-04-18 |
20130097418 | METHODS AND APPARATUSES TO PROVIDE SECURE COMMUNICATION BETWEEN AN UNTRUSTED WIRELESS ACCESS NETWORK AND A TRUSTED CONTROLLED NETWORK - A secure communication channel between an access point (AP) device associated with a wireless network and a mobile gateway (GW) device of a packet core network is established. Data is exchanged between the wireless network and the packet core network through the secure channel. A client device (UE) is authenticated through the secure communication channel. Device identity information is received from the AP device. A session request is sent to the packet core network. An IP address for the device is received from the packet core network. The communication between the AP device and the packet core network becomes secure without need to run an IP secure protocol on the UE that saves the battery power on the UE. Establishing the fully secure communication between the UE and the packet core network while saving the UE power provides a significant advantage for the mobile technology world. | 2013-04-18 |
20130097419 | METHOD AND SYSTEM FOR ACCESSING E-BOOK DATA - Provided is a method for accessing e-book data, including: step A: e-book hardware establishes a connection with an electronic device and negotiates a reading key; step B: the electronic device downloads e-book data via a client, specifically is: firstly, the electric device establishes a connection with the client; the client sends a connection establishment request to a server; the server verifies the identification of the electronic device via the client; if the verification is not passed, then the access will be refused; if the verification is passed, then the server uses a downloaded key to encrypt the e-book data and sends the encrypted e-book data to the electronic device via the client; and step C: the electronic hardware establishes a connection with the electronic device, processes the encrypted e-book data using the downloaded key and/or the reading key, and the e-book hardware displays the e-book data. The method provided in the present embodiment not only enables the download and reading of the e-book to be more rapid but also protects the copyright of the e-book. | 2013-04-18 |
20130097420 | Verifying Implicit Certificates and Digital Signatures - Methods, systems, and computer programs for verifying a digital signature are disclosed. The verifier accesses an implicit certificate and a digital signature provided by the signer. The implicit certificate includes a first elliptic curve point representing a public key reconstruction value of the signer. The verifier accesses a second elliptic curve point representing a pre-computed multiple of the certificate authority's public key. The verifier uses the first elliptic curve point and the second elliptic curve point to verify the digital signature. The verifier may also use a third elliptic curve point representing a pre-computed multiple of a generator point. Verifying the digital signature may provide verification that the implicit certificate is valid. | 2013-04-18 |
20130097421 | Protecting Information Using Policies and Encryption - A technique and system protects documents at rest and in motion using declarative policies and encryption. Encryption in the system is provided transparently and can work in conjunction with policy enforcers installed at a system. A system can protect information or documents from: (i) insider theft; (ii) ensure confidentiality; and (iii) prevent data loss, while enabling collaboration both inside and outside of a company. | 2013-04-18 |
20130097422 | METHOD AND SYSTEM FOR AUTHENTICATING PEER DEVICES USING EAP - A system and method for authenticating a peer device onto a network using Extensible Authentication Protocol (EAP). The key lifetime associated with the keying material generated in the peer device and the authentication server is communicated from the authenticator to the peer device within the EAP Success message. The peer device, having been provided with the key lifetime, can anticipate the termination of its authenticated session and initiate re-authentication prior to expiry of the key lifetime. | 2013-04-18 |
20130097423 | PROCESSING DEVICE AND COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN PROCESSING PROGRAM - A processing device for executing predetermined process associated with information to be processed at preset key time, the processing device includes a processor, wherein the processor determines whether or not key time is included in a check period which is between key time at which previous process was performed and current time, at a check timing set for each predetermined time; and the processor executes the predetermined process which is to be performed at the key time, when it is determined that the key time is included in the check period. | 2013-04-18 |
20130097424 | DISCOVERY OF SECURE NETWORK ENCLAVES - A hierarchical key generation and distribution mechanism for a computer system in which devices are organized into secure enclaves. The mechanism enables network access to be tailored to approximate minimum needed privileges for each device. At the lowest level of the hierarchy, keys are used to form security associations between devices. Keys at each level of the hierarchy are generated from keys at a higher level of the hierarchy and key derivation information. Key derivation information is readily ascertainable, either from identifiers for devices or from within messages, supporting hardware offload of cryptographic functions. Because keys may be generated based on the enclaves in which the hosts participating in a security association are located, the system includes a mechanism by which devices can discover the enclave in which they are located. | 2013-04-18 |
20130097425 | Providing Consistent Cryptographic Operations Across Several Applications - Providing consistent cryptographic operations across several applications using secure structured data objects includes a security middleware component, using an application programming interface, receiving a data input from an originating application operating in application space. Both the application and the middleware component execute in the data processing system. A security schema object is retrieved by the security middleware component from an object store, the security schema object describing a sequence of cryptographic operations and includes several components describing aspects of the cryptographic operations. The data input is transformed from a first format to a second format where one of the formats is a secure structured data object formed using the sequence of cryptographic operations. A property of the secure structured data object contains data about the security schema object. The data input is transmitted in the second format to a consumer application operating in application space. | 2013-04-18 |
20130097426 | WATERMARKING AND SCALABILITY TECHNIQUES FOR A VIRTUAL DESKTOP PLANNING TOOL - A method for measuring performance of virtual desktop services offered by a server including a processor is described. A first encoded watermark is embedded into user interface display generated by a virtual desktop when initiating an operation. The first encoded watermark includes pixels identifying the operation and indicating its initiation. A second encoded watermark is embedded into the user interface upon completion of the operation indicating completion of the operation. An action performance time is then computed and stored in a memory. Multiple performance times may be compiled from multiple operations of multiple virtual desktops to assess the performance of the system as a whole. | 2013-04-18 |
20130097427 | Soft-Token Authentication System - A system for authenticating a user and his local device to a secured remote service with symmetrical keys, which utilizes a PIN from the user and a unique random value from the local device in such a way that prevents the remote service from ever learning the user's PIN, or a hash of that PIN. The system also provides mutual authentication, verifying to the user and local device that the correct remote service is being used. At the same time, the system protects against PIN guessing attacks by requiring communication with the said remote service in order to verify if the correct PIN is known. Also, the system works in such a way as to change the random value stored on the user's local device after each authentication session. | 2013-04-18 |
20130097428 | ELECTRONIC APPARATUS AND ENCRYPTION METHOD THEREOF - An electronic apparatus includes a secure unit to store public key information, an input unit to receive user authentication information and a data searching word, a user authenticating unit to perform user authentication with the inputted user authentication information, an encryption generating unit to generate a searching word encryption to use in data search, and a control unit to control generating the searching word encryption using the previously-stored public key information, the inputted user authentication information, and the data searching word. | 2013-04-18 |
20130097429 | Method and System for Secure Authentication of a User by a Host System - A method and system for securely logging onto a banking system authentication server so that a user credential never appears in the clear during interaction with the system in which a user's credential is DES encrypted, and the DES key is PKI encrypted with the public key of an application server by an encryption applet before being transmitted to the application server. Within the HSM of the application server, the HSM decrypts and re-encrypts the credential under a new DES key known to the authentication server, the re-encrypted credential is forwarded to the authentication server, decrypted with the new DES key known to the authentication server, and verified by the authentication server. | 2013-04-18 |
20130097430 | ENCRYPTING DATA AND CHARACTERIZATION DATA THAT DESCRIBES VALID CONTENTS OF A COLUMN - A method, computer-readable storage medium, and computer system are provided. In an embodiment, in response to receiving a first command that specifies first data, a first cryptographic key, and a column identifier that identifies a column of rows in a database, the first data is encrypted into encrypted data using the first cryptographic key. The encrypted data is stored to a first row in the column in the database. In response to the receiving the first command, characterization data is created that specifies valid contents of the column of the rows. In response to receiving a query command that specifies a second cryptographic key and the column, the column is decrypted using the second key to create decrypted data. If the decrypted data does not satisfy the valid contents specified by the characterization data, an invalid cryptographic key action is performed. | 2013-04-18 |
20130097431 | SYSTEMS AND METHODS OF SOURCE SOFTWARE CODE MODIFICATION - Some embodiments of the present invention provide a method for modifying computer-executable instructions. In various embodiments, the method includes applying, with a processor, a data transformation to one or more value representations in the computer-executable instructions to create one or more transformed code segments; dividing the one or more transformed code segments into portions, the portions including a first portion and a second portion, the first portion including instructions for providing a first set of data for use by the second portion; altering the first portion of instructions so that it includes instructions for encrypting the first set of data; and storing the first portion of instructions with corresponding computer executable instructions on non-transient storage media. | 2013-04-18 |
20130097432 | PROVIDING CONSISTENT CRYPTOGRAPHIC OPERATIONS - A method, system, and computer usable program product for providing consistent cryptographic operations in a data processing environment using protected structured data objects are provided in the illustrative embodiments. A data input is received from an originating application by a security plug-in, both the application and the security plug-in executing in the data processing system. A security schema object is received by the security plug-in, the security schema object describing a sequence of cryptographic operations, wherein the security schema object includes a plurality of components each component describing an aspect of the cryptographic operations. The data input is transformed into a secure structured data object by the security plug-in using the sequence of cryptographic operations. A property of the secure structured data object is populated using data about the security schema object. The secure structured data object is transmitted to a consumer application. | 2013-04-18 |
20130097433 | SYSTEMS AND METHODS FOR DYNAMIC RESOURCE MANAGEMENT IN SOLID STATE DRIVE SYSTEM - The disclosed subject matter relates to methods and systems for dynamically controlling the power consumed by solid state drive. One embodiment includes a method that measures the power consumed by the solid state drive system and configures a programmable resource manager to grant the usage/activation of flash memory devices, thereby maintaining the power consumed by the flash memory devices and, as a result, the power consumed by the whole drive, within a specified power budget. | 2013-04-18 |
20130097434 | IMAGE FORMING APPARATUS AND CONTROL METHOD THEREOF - An image forming apparatus including an image forming unit to form an image, a user switch unit to output a user operation signal to switch between a power-on state and a power-off state of the image forming apparatus, a main controller to control the image forming unit and to output a power control signal based on the user operation signal, a power switching unit to selectively supply operation power to the main controller based on the user operation signal and the power control signal, and an auxiliary controller to control the power switching unit such that the operation power is not supplied to the main controller when the power control signal is changed in a power-off state. | 2013-04-18 |
20130097435 | METHOD AND SYSTEM FOR SUPPORTING WAKE-ON-LAN IN A VIRTUALIZED ENVIRONMENT - A method and system for supporting Wake-on-LAN technology in a virtualized environment is described. An improved virtual switch comprises a listener, which receives a power-on message on behalf of virtual machines, extracts addresses of the virtual machines to be powered on, which are embedded in the power-on message, compares the extracted addresses with addresses of the virtual machines stored in a database, and selectively powers on those virtual machines for which the extracted and stored addresses match. | 2013-04-18 |
20130097436 | SYSTEMS AND METHODS TO FILTER DATA PACKETS - A mobile communication device includes a receiver system configured to receive unicast data packets and non-unicast data packets. The receiver system may include a hardware packet filter. The mobile communication device further includes a processor coupled to the receiver system. The processor may be configured to detect a power state change and activate the hardware packet filter at the receiver system in response to the power state change indicating a power-conservation state being entered. When the hardware packet filter is activated, the unicast data packets received at the receiver system may be provided to the processor to be filtered and the non-unicast data packets received at the receiver system are dropped at the receiver system. When the hardware packet filter is not activated, the unicast data packets and the non-unicast data packets received at the receiver system may be provided to the processor. | 2013-04-18 |
20130097437 | METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING OPTIMIZING C-STATE SELECTION UNDER VARIABLE WAKEUP RATES - A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations (1) the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and (2) the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate. | 2013-04-18 |
20130097438 | INFORMATION PROCESSING DEVICE AND MANAGEMENT METHOD OF POWER SAVING MODE - In an information processing device, when shifting to a power saving mode, a volatile storage unit is controlled to continuously hold a program loaded to the volatile storage unit even in the power saving mode, and a logical value indicating the power saving mode is set to an input/output port of a third control unit. At time of activation, a second control unit determines if the logical value indicating the power saving mode has been set to the input/output port, and when the logical value has been set, recognizes the activation as a return from the power saving mode and executes the program held in the volatile memory, and when the logical value has not been set, recognizes the activation as a normal activation, loads the program held in the nonvolatile memory to the volatile memory and executes the loaded program. | 2013-04-18 |
20130097439 | Electronic Apparatus that Controls Switching to Energy-Saving Mode - Provided is an electronic apparatus including: a network interface configured to receive data via a network; a communication processing unit configured to notify of a network communication type and a network communication amount of the received data; and an operation mode control unit configured to switch an operation mode from a normal mode to an energy-saving mode when a network communication does not occur in the network interface before a waiting time based on the network communication amount for each network communication type notified of from the communication processing unit has elapsed. | 2013-04-18 |
20130097440 | EVENT SERVICE FOR LOCAL CLIENT APPLICATIONS THROUGH LOCAL SERVER - In server/client architectures, the server application and client applications are often developed in different languages and execute in different environments specialized for the different contexts of each application (e.g., low-level, performant, platform-specialized, and stateless instructions on the server, and high-level, flexible, platform-agnostic, and stateful languages on the client) and are often executed on different devices. Convergence of these environments (e.g., server-side JavaScript using Node.js) enables the provision of a server that services client applications executing on the same device. The local server may monitor local events occurring on the device, and may execute one or more server scripts associated with particular local events on behalf of local clients subscribing to the local event (e.g., via a subscription model). These techniques may enable development of local event services in the same language and environment as client applications, and the use of server-side code in the provision of local event service. | 2013-04-18 |
20130097441 | MULTI-CORE PROCESSOR SYSTEM, POWER CONTROL METHOD, AND COMPUTER PRODUCT - A multi-core processor system includes a core configured to detect among multiple cores, a state of migration of first software from a first core to the core whose specific processing capacity value is lower than that of the first core; and set the processing capacity value of the first core at a time of the detection to be a processing capacity value that is lower than that before the migration when detecting the state of migration. | 2013-04-18 |
20130097442 | MOBILE DEVICE CHIP AND MOBILE DEVICE CONTROLLING METHOD THEREFOR - A mobile device chip is provided. The mobile device chip includes a main processor, a multimedia processor, and a direct memory access (DMA) circuit. The multimedia processor is electrically coupled to the main processor. The DMA circuit accesses storage, and the DMA circuit is electrically coupled to the multimedia processor. When the mobile device chip operates in a normal mode, the main processor provides file accessing information of at least part of an audio file stored in the storage to the multimedia processor. When the mobile device chip operates in a power-saving mode, the multimedia processor obtains the data of the at least part of the audio file stored in the storage through the DMA circuit according to the file accessing information provided by the main processor. | 2013-04-18 |
20130097443 | DYNAMIC VOLTAGE AND CLOCK SCALING CONTROL BASED ON RUNNING AVERAGE, VARIANT AND TREND - The aspects enable a computing device or microprocessor to scale the frequency and/or voltage of a processor to an optimal value balancing performance and power savings in view of a current processor workload. Busy and/or idle duration statistics are calculated from the processor during execution. The statistics may include a running average busy and/or idle duration or idle/busy ratio, a variance of the running average and a trend of the running average. Current busy or idle durations or an idle-to-busy ratio may be computed based on collected statistics. The current idle-to-busy ratio may be compared to a target idle-to-busy ratio and the frequency/voltage of the processor may be adjusted based on the results of the comparison to drive the current running average toward the target value. The target value of idle-to-busy ratio may be adjusted based on the calculated variance and/or trend values. | 2013-04-18 |
20130097444 | USING LATCHED EVENTS TO MANAGE SLEEP/WAKE SEQUENCES ON COMPUTER SYSTEMS - The disclosed embodiments provide a system that performs power management on a computer system. The system includes an embedded controller and an operating system. During the execution of a sleep sequence by the operating system, the embedded controller latches events associated with use of the computer system. After the sleep sequence has completed, the embedded controller compares the latched events with a set of enabled wake events for the computer system and a current state of the computer system. If the latched events indicate that the current state corresponds to one of the enabled wake events, the embedded controller triggers a wake sequence on the computer system. | 2013-04-18 |
20130097445 | Method and Apparatus for Power Management Control of an Embedded Memory Having Sleep and Shutdown Features - A power management controller controls a power mode associated with a memory device and includes a logic element operative to provide a power mode control signal. The logic element is responsive to first and second control signals, the second control signal being a delayed version of the first control signal. The first control signal is provided by a processing device, and the power mode control signal transitions (i) inactive before a chip select signal transitions active and/or (ii) active after the chip select signal transitions inactive. The chip select signal controls the memory device, and the power mode control signal controls the power mode associated with the memory device. A corresponding method, computer-readable medium, and electronic system are also disclosed. A method that selects a power control mode associated with the power management controller, which controls a power mode associated with the memory device, is also disclosed. | 2013-04-18 |
20130097446 | METHOD OF CONTROL OF AN ACCESS POINT OF A HOME GATEWAY OF A HOME NETWORK - A method of controlling a domestic gateway, intended to connect at least one domestic terminal of a domestic computer network to a telecommunication network. The domestic gateway includes an access point configured so as to establish a connection between the domestic terminal and the domestic gateway. Method includes: a step of verifying the state of the connection between the domestic gateway and the domestic terminal via the access point, and a step of cyclically placing the access point on standby if the connection is inactive, in which the access point is alternately enabled for a duration of activity and disabled for a duration of sleep. | 2013-04-18 |
20130097447 | METHOD AND APPARATUS FOR CONTROLLING SLEEP MODE IN A PORTABLE TERMINAL - A method of controlling a sleep mode of a portable terminal is provided. The method includes setting a sleep mode timer according to a default setting; displaying, upon reaching a predetermined time point before expiration of the sleep mode timer, a notice screen including the sleep mode timer and a timer setting area for re-setting the sleep mode timer according to a temporary setting; and entering, when a sleep mode timer temporary resetting command is received while the notice screen is displayed, a screen maintaining mode in which the sleep mode timer is temporarily re-set from the default setting to a temporary setting according to the sleep mode timer temporary resetting command. | 2013-04-18 |