16th week of 2018 patent applcation highlights part 49 |
Patent application number | Title | Published |
20180108395 | SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR WRITING OF THE SAME - A semiconductor storage device includes a memory cell, a switch, a source driver, a drain driver, a voltage measurement circuit and a control electrode driver. The memory cell has a control electrode, a floating electrode, a source and a drain. In a writing to the memory cell, the voltage measurement circuit measures a voltage generated between the control electrode and the source when the switch is in an on state connecting the control electrode and the drain and a predetermined current flows from the current source to the memory cell, and the control electrode driver applies to the control electrode a voltage that is controlled based on the voltage measured by the voltage measurement circuit. | 2018-04-19 |
20180108396 | METHOD AND APPARATUS FOR DECODING COMMANDS - Method and Apparatuses for of decoding commands for a semiconductor device are described. An example method includes receiving a portion of a command at first and second clock cycles: validating the portion of the command received at the first and second clock cycles at a third clock cycle when a chip select signal indicates a first state and continuing to receive the remaining portion of the command at the third clock cycle and a fourth clock cycle so that the command can be completely received by the semiconductor device by the fourth clock cycle; and invalidating the portion of the command received at the first and second clock cycles at the third clock cycle when the chip select signal indicates a second state different from the first state, so that a new command can be input to the semiconductor device at the third clock cycle. | 2018-04-19 |
20180108397 | APPARATUSES AND METHODS TO PERFORM LOGICAL OPERATIONS USING SENSING CIRCUITRY - The present disclosure includes apparatuses and methods related to performing logic operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to the sensing circuitry and is configured to cause storing of a first operand in a first compute component storage location, transfer of the first operand to a second compute component storage location, and performance of a logical operation between the first operand in the second compute component storage location and a second operand sensed by the sense amplifier. | 2018-04-19 |
20180108398 | CIRCUIT AND LAYOUT FOR SINGLE GATE TYPE PRECHARGE CIRCUIT FOR DATA LINES IN MEMORY DEVICE - Some embodiments include apparatus and methods using a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region; a first channel region located between a portion of the first diffusion region and a portion of the third diffusion region; a second channel region located between the portion of the third diffusion region and a portion of the second diffusion region; a third channel region located between the portion of the second diffusion region and a portion of the fourth diffusion region; and a gate located over the first, second, and third channel regions. The first and second diffusion regions are located on a first side of the gate. The third and fourth diffusion regions are located on a second side of the gate opposite from the first side. | 2018-04-19 |
20180108399 | DATA SENSE AMPLIFICATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A semiconductor memory device includes: a first memory cell coupled to a first bit line; a second memory cell coupled to a second bit line; and a sense amplification circuit for sensing and amplifying a voltage difference between the first and second bit lines, wherein the sense amplification circuit includes: a first sense amplifier including a cross-coupled pair of first and second transistors coupled to the first bit line and the second bit line, respectively; a second sense amplifier including a cross-coupled pair of third and fourth transistors coupled to the first and second bit lines, respectively; and an offset supplier for controlling a timing for supplying a voltage of the first bit line to the first transistor and a timing for supplying a voltage of the second bit line to the second transistor according to a selected memory from the first and second memory cells. | 2018-04-19 |
20180108400 | MEMORY DEVICE AND OPERATING METHOD THEREOF - A memory device includes a plurality of word lines; a plurality of bit lines; a plurality of memory cells, each memory cell coupled to a corresponding word line among the plurality of word lines and a corresponding bit line among the plurality of bit lines; and a control block suitable for controlling at least two word lines among the plurality of word lines to be activated together, and determining whether or not a weak cell exists, based on a voltage of a bit line corresponding to the activated word lines. | 2018-04-19 |
20180108401 | MEMORY DEVICE - A memory device includes a plurality of memory cells, a weak address storage block suitable for storing a weak address of a weak cell of which data retention time is shorter than a reference time, among the plurality of memory cells, a refresh counter suitable for generating a counting address, and an address selection block suitable for outputting a refresh address by selecting one of the counting address and the weak address, wherein, in selecting the counting address, the address selection block selects the weak address for a predetermined period, when a value of at least one preset bit of the counting address is changed. | 2018-04-19 |
20180108402 | METHOD, SYSTEM AND DEVICE FOR NON-VOLATILE MEMORY DEVICE STATE DETECTION - Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a sense circuit may enable a determination of a current impedance state of a non-volatile memory element while avoiding an unintentional change in the state of the non-volatile memory element. | 2018-04-19 |
20180108403 | TEMPERATURE COMPENSATION CIRCUITS - A temperature compensation circuit may comprise a temperature sensor to sense a temperature signal of a memristor crossbar array, a signal converter to convert the temperature signal to an electrical control signal, and a voltage compensation circuit to determine a compensation voltage based on the electrical control signal and pre-calibrated temperature data of the memristor crossbar array. | 2018-04-19 |
20180108404 | NONVOLATILE MEMORY CONTROL METHOD, CONTROL DEVICE, AND SEMICONDUCTOR STORAGE DEVICE - Disclosed is a nonvolatile memory control method in which a unit of erase and a unit of read are different from each other. The control method includes: allocating a physical address of the nonvolatile memory to a logical address in a predetermined unit; and controlling a size of the unit of erase in which a physical address allocated to a logical address is included according to a write access state with respect to the logical address in the predetermined unit. | 2018-04-19 |
20180108405 | Phase Change Memory Device and Method of Operation - A phase change memory device includes two portions with local bitlines connected to memory cells. A reading stage is configured to read logic data stored by the first and second memory cells. A first main bitline extends between the reading stage and the first local bitlines and a first main switch is coupled between the first main bitline and reading stage and likewise for the second portion. Local switches are associated with respective ones of the local bitlines. A first reference signal generator is coupled to the reading stage. The phase change memory device is configured to operate in a first reading mode, in which the logic data stored by the first memory cell is read by the reading stage by comparison with the reference signal. | 2018-04-19 |
20180108406 | RESISTIVE MEMORY DEVICE AND METHOD RELATING TO A READ VOLTAGE IN ACCORDANCE WITH VARIABLE SITUATIONS - A resistive memory device and a method may be provided. The resistive memory device may include a reset voltage-detecting circuit, a set voltage-detecting circuit, a control circuit and a read voltage-generating circuit. The reset voltage-detecting circuit may receive a variable preliminary reset current to detect reference reset voltage information. The set voltage-detecting circuit may receive a variable preliminary set current to detect reference set voltage information. The control circuit may receive the reference reset voltage information and the reference set voltage information to determine middle voltage information of the reference reset voltage information and the reference set voltage information. The read voltage-generating circuit may receive the middle voltage information to generate a read voltage. | 2018-04-19 |
20180108407 | VOLTAGE REGULATOR AND RESISTANCE VARIABLE MEMORY APPARATUS HAVING THE SAME - A voltage compensation circuit may be provided. The voltage compensation circuit may include a replica circuit block configured to be selected and driven to generate a resistance value for compensating a voltage level. | 2018-04-19 |
20180108408 | RESISTIVE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A resistive memory device includes a first region including a first region including a plurality of first resistive memory cells, and a second region including a plurality of second resistive memory cells, wherein the resistive memory device is suitable for applying a first recovery pulse cyclically at a regular interval to the first resistive memory cells for recovering a drift of the first memory cells, and for applying a second recovery pulse to a read target memory cell among the second memory resistive cells. | 2018-04-19 |
20180108409 | Circuits and Methods for Preventing Over-Programming of ReRam-Based Memory Cells - A method for preventing over-programming of resistive random access (ReRAM) based memory cells in a ReRAM memory array includes applying a programming voltage in a programming circuit path including a ReRAM memory cell to be programmed, sensing programming current drawn by the ReRAM cell while the programming voltage is applied across the memory cell, and decreasing the programming current as a function of a rise in programming current. | 2018-04-19 |
20180108410 | MEMRISTANCE FEEDBACK TUNING - An example device in accordance with an aspect of the present disclosure includes at least one current comparator, a plurality of threshold currents, and a controller. The current comparator is to compare a memristor current to a plurality of threshold currents. The controller is to set a desired memristance state of a memristor according to a memristance feedback tuning loop based on a plurality of threshold levels. The controller is to apply positive and negative voltages to the memristor during the feedback tuning loop to achieve the desired memristance state of the memristor. | 2018-04-19 |
20180108411 | RESISTIVE MEMORY APPARATUS, SELECTIVE WRITE CIRCUIT THEREFOR, AND OPERATION METHOD THEREOF - A resistive memory apparatus may include a memory cell array and a selective write circuit. The memory cell array may include a plurality of resistive memory cells coupled between a plurality of word lines and a plurality of bit lines. The selective write circuit may determine whether or not to perform a pre-read/comparison operation for a memory cell on which a next write operation is scheduled to be performed, based on a logic level of input data provided for a write operation. The selective write circuit may control the write operation for the memory cell array according to a determination result of the pre-read/comparison operation. | 2018-04-19 |
20180108412 | VOLTAGE-CONTROLLED RESISTIVE DEVICES - Systems, methods, and apparatus are provided for tuning a memristive property of a device. The device (500) includes a layer of a dielectric material ( | 2018-04-19 |
20180108413 | Method for Managing a Fail Row of the Memory Plane of a Non Volatile Memory and Corresponding Memory Device - A non-volatile memory is erasable by page and equipped with a row redundancy mechanism. In the case of the detection of a defective row of the memory plane, the storing of the address of the row in a non-volatile register is carried out and a redundant row having a new address is assigned. In the case of an attempt to write to the defective row, a write to the redundant row is carried out. When writing to the redundant row, the new content of the redundant row is loaded into a volatile memory and, following an operation for writing to any other row of the memory plane, a re-loading of the new content of the redundant row into the volatile memory. | 2018-04-19 |
20180108414 | DATA HOLDING DEVICE, NONVOLATILE DATA HOLDING DEVICE, AND DATA READING METHOD - A data holding device | 2018-04-19 |
20180108415 | METHODS AND APPARATUS FOR PATTERN MATCHING - Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory. | 2018-04-19 |
20180108416 | THREE-DIMENSIONAL VERTICAL NOR FLASH THIN-FILM TRANSISTOR STRINGS - A memory structure includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form a plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions. The thin film transistors associated with each active column are organized into one or more vertical NOR strings. | 2018-04-19 |
20180108417 | MEMORY SYSTEM OF 3D NAND FLASH AND OPERATING METHOD THEREOF - An apparatus of a memory system and an operating method thereof include: memory blocks, each of the memory blocks includes strings, each of the stings has flash cells and select gates thereon, wherein the select gates of each of the strings with a same index number in each of the memory blocks are connected with each other, in each of the memory blocks, the strings are divided into groups, each of the groups includes at least one string, and each of the groups has own read counts management thereof. | 2018-04-19 |
20180108418 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line. | 2018-04-19 |
20180108419 | MEMORY SYSTEM WITH FILE LEVEL SECURE ERASE AND OPERATING METHOD THEREOF - An apparatus of a memory system and an operating method thereof include: a plurality of memory devices, wherein each of the plurality of memory devices includes a plurality of blocks, each of the plurality of blocks has multiple pages corresponding to multiple wordlines, respectively; and a memory controller coupled with the plurality of memory devices, wherein the memory controller is configured to determine an overhead of an erase block where a deleted file resides therein, perform file level secure erase operation on the erase block in accordance with at least the overhead, and mark target pages corresponding to the deleted file as “trimmed” in a logic block address (LBA) table. | 2018-04-19 |
20180108420 | APPARATUSES AND METHODS FOR TRANSISTOR PROTECTION BY CHARGE SHARING - Apparatuses and methods for protecting transistors through charge sharing are disclosed herein. An example apparatus includes a transistor comprising a gate node and a bulk node, a charge sharing circuit coupled between the gate and bulk nodes, and logic. The charge sharing circuit is configure to equalize charge differences between the gate and bulk nodes, and the logic is configured to enable the charge sharing circuit based at least in part on a combination of first and second signals, which indicate the presence of a condition. | 2018-04-19 |
20180108421 | APPARATUSES AND METHODS FOR CHARGING A GLOBAL ACCESS LINE PRIOR TO ACCESSING A MEMORY - Apparatuses and methods for charging a global access line prior to accessing a memory are described. An example apparatus may include a memory array of a memory. A plurality of global access lines may be associated with the memory array. The global access line may be charged to a ready-access voltage before any access command has been received by the memory. The global access line may be maintained at the ready-access voltage during memory access operations until the receipt of a post-access command. The post-access command may reset the global access line to an inactive voltage. | 2018-04-19 |
20180108422 | STORAGE DEVICE, MEMORY SYSTEM, AND READ VOLTAGE DECISION METHOD THEREOF - A memory system includes multiple storage devices that each include a nonvolatile memory device. A client device is configured to collect deterioration information of the nonvolatile memory devices provided from the storage devices. A server device is configured to receive the collected deterioration information and to predict a degree of deterioration of the nonvolatile memory devices in real time by performing machine learning based on the collected deterioration information and initial deterioration information. The client device determines a read level of the nonvolatile memory device based on the degree of deterioration of the nonvolatile memory devices from the server device. The storage device sets the nonvolatile memory device to operate based on the read level determined in the client device. | 2018-04-19 |
20180108423 | MULTI-GATE NOR FLASH THIN-FILM TRANSISTOR STRINGS ARRANGED IN STACKED HORIZONTAL ACTIVE STRIPS WITH VERTICAL CONTROL GATES - Multi-gate NOR flash thin-film transistor (TFT) string arrays (“multi-gate NOR string arrays”) are organized as stacks of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by vertical local word-lines provided along one or both sidewalls of the stack of active strips. Each active strip includes at least a channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines. Each active strip may provide TFTs that belong to one or two NOR strings, depending on whether one or both sides of the active strip are used. | 2018-04-19 |
20180108424 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes a fuse array section suitable for performing program and read operations; a control signal generation section suitable for generating a precharge control signal and a word line control signal; a bit line control section suitable for controlling a precharge operation of a bit line in response to the precharge control signal and a source signal; and a word line control section suitable for controlling activation of a program word line and a read word line for performing the program and read operations in response to the word line control signal, wherein the control signal generation section controls the word line control signal to be activated after a predetermined time from the activation of the precharge control signal. | 2018-04-19 |
20180108425 | ONE-TIME PROGRAMMABLE (OTP) MEMORY DEVICE FOR READING MULTIPLE FUSE BITS - A one-time programmable (OTP) memory device includes an OTP cell array, a latch controller, a column selection circuit, and a latch circuit. The OTP cell array includes a plurality of OTP memory cells respectively connected to a plurality of bitlines. The latch controller generates a latch address signal indicating an address that is changed sequentially in an enable mode to initialize the OTP memory device. The column selection circuit electrically connects a plurality of bitline groups of the bitlines to a plurality of input-output lines sequentially based on the latch address signal in the enable mode. The latch circuit receives and stores fuse bits provided sequentially through the bitline groups and the input-output lines in the enable mode. | 2018-04-19 |
20180108426 | SHIFT REGISTER UNIT, GATE DRIVING CIRCUIT AND DRIVING METHOD, AND DISPLAY APPARATUS - The present application discloses a method of driving a gate driving circuit in an operation cycle divided into a first sub-cycle and a second sub-cycle, including providing a gate driving circuit having a first plurality of shift register units with a second plurality of shift register units, the first plurality of shift register units being configured so that each odd/even numbered shift register unit includes a first bias-control terminal to receive a first/second bias signal CLK | 2018-04-19 |
20180108427 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus may include a control circuit, a decoding circuit, and a memory circuit. The control circuit may output one of bank group signals as either a first bank group distribution signal or a second bank group distribution signal and output one of data designation addresses as either a first data designation distribution address or a second data designation distribution address, in response to a first test signal and a second test signal. The decoding circuit may generate decoding signals depending on remaining bank group signals, remaining data designation addresses, bank designation signals, the first and second bank group distribution signals, and the first and second data designation distribution addresses. The memory may select certain memory location to output or store data, in response to the decoding signals. | 2018-04-19 |
20180108428 | INPUT/OUTPUT TERMINAL CHARACTERISTIC CALIBRATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME - An input/output terminal characteristic calibration circuit may include a plurality of input/output terminals a subset of which is configured to partially and selectively receive a characteristic calibration signal according to an external input, such that characteristics of the input/output terminals corresponding to the characteristic calibration signal are calibrated. The input/output terminal characteristic calibration circuit may also include a characteristic calibration signal generation circuit coupled to the plurality of input/output terminals in common through a test signal line, and configured to provide the characteristic calibration signal to the plurality of input/output terminals in common through the test signal line. | 2018-04-19 |
20180108429 | TEST MODE CIRCUIT FOR MEMORY APPARATUS - Apparatuses for error detection and correction for a semiconductor device are described. An example apparatus includes: at least one memory cell array including a plurality of memory cells; and a control circuit that receives read data from the plurality of memory cells, compares the read data with reference data, and further provides an error signal. The control circuit further provides the error signal when a number of bit errors detected is greater than or equal to a predetermined number, and suppresses providing the error signal when the number of bit errors detected is less than the predetermined number. | 2018-04-19 |
20180108430 | METHOD AND SYSTEM FOR POPULATION HEALTH MANAGEMENT IN A CAPTIVATED HEALTHCARE SYSTEM - Methods and systems are provided for managing patient or patient populations within a fully integrated captivated healthcare system, which includes creating a patient profile or a patient population profile; screening, assessing and treating a patient or patient population; reviewing, analyzing, and comparing a patient or patient population to a control group or pre-treatment patient profile or patient population profile; and prioritizing, scheduling, and care coordination for a patient or patient population as part of follow-up healthcare assessment and services included in the fully integrated healthcare delivery system. Part of the methods and system includes the ability to utilize comparative patient and patient population data to assess and control healthcare access, quality, and costs. | 2018-04-19 |
20180108431 | METHODS AND SYSTEMS FOR ASSESSING FERTILITY BASED ON SUBCLINICAL GENETIC FACTORS - The invention provides methods for generating a likelihood of achieving ongoing pregnancy in an individual by combining both clinical and genetic data. These methods involve the determination of one or more correlations between clinical characteristics and known pregnancy and infertility-related outcomes from a reference set of data to provide a model representative of a cumulative probability of ongoing pregnancy. The methods further involve the determination of one or more correlations between genetic characteristics and known pregnancy and infertility-related outcomes from the reference set of data to adjust the model. The model can then be applied to the input data to generate the likelihood of achieving ongoing pregnancy in the subject. | 2018-04-19 |
20180108432 | SYSTEM AND METHOD FOR PROVIDING A DRUG THERAPY COORDINATION RISK SCORE AND IMPROVEMENT MODEL-OF-CARE - The present invention generally relates to pharmacy claim data processing, and in particular it relates to coordination scoring, patient profiling, patient and prescriber behavior analysis and modeling. More specifically, it relates to coordination of medication use risk modeling using the inputs of pharmacy claims data, prescriber data, and, optionally, medical claims data. | 2018-04-19 |
20180108433 | SYSTEM AND COMPUTER PROGRAM FOR ANALYZING AND MANAGING HEALTH, FITNESS AND NUTRITIONAL WELLNESS - A system and computer program product for serving web pages offering fitness and nutritional wellness information. The system includes a plurality of remote computers in communication with a respective plurality of remote users, a central server having a computer program stored in non-transient memory and one or more microprocessors, a network interface in communication with the central server and the plurality of remote computers over a network, and a shared database in communication with the central server. The network interface is configured to receive patient information. The central server is programmed by means of the computer program to receive configuration and setup information, wherein the configuration and setup information includes configuration of user configurable fitness and wellness questions derived from validated questionnaires in a plurality of subspecialty fields, and user configurable correlation rules associated with the fitness and wellness questions, receive and store patient information in the database, wherein the patient information includes responses to the user configurable fitness and wellness questions, correlate the responses based on the user configurable correlation rules to a plurality of functional scores using the one or more microprocessors, provide a health and wellness recommendation based on the functional scores, and transmit one or more web pages, via the network interface, representing the functional scores within the user configurable thresholds, and display the one or more web pages on respective displays of one or more of the plurality of remote computers in communication with respective one or more of the plurality of remote users. The user configurable correlation rules include one or more predefined thresholds. The user configurable threshold includes an upper threshold value and a lower threshold value. Functional scores greater than the upper threshold value are assigned a standard maximum value in the health and wellness recommendation. Functional scores less than the lower thresholds are not included in a final health and wellness recommendation. | 2018-04-19 |
20180108434 | Multi-Application Personal Health Record Microprocessor Card - A personal health record card for storing instantly accessible medical information pertaining to the individual associated with the personal health record card is provided. The memory device for storing an individual's personal health information, said memory device comprising: a memory that stores computer readable data, said memory storing: a primary information section comprising information that identifies the individual associated with the memory device and basic information related to the identity of the individual, the primary information accessible by a memory device reader without any authentication; a secondary information section comprising a first level of the individual's sensitive and confidential health information, said secondary information section being accessible only by the memory device reader after authentication; and optionally, a tertiary information section comprising a second level of the individual's sensitive and confidential health information, said tertiary information section being accessible only by the memory device reader after a second level of authentication. | 2018-04-19 |
20180108435 | DOSAGE CONFIRMATION APPARATUS - An apparatus for determining the volume of a liquid in a container. A digital camera is provided to view the container. A processor can optically detect certain characteristics of the container as viewed by the camera and accesses a computer memory having stored characteristics of a plurality of known containers, and the compare the detected certain characteristics with the stored characteristics to identify the container from the plurality of known containers. The processor can calculate the volume of the container as a function of the distance between the first and second ends of the container as viewed by the camera. The processor can receive at least one image from the camera and determine whether the liquid in the container contains any air pockets based on the at least one image. Methods are provided, including a method for use by an apparatus having a camera and a processor electrically coupled to the camera to confirm the dosage of a medicament in a container. | 2018-04-19 |
20180108436 | FRAME OPTIMIZATION SYSTEM AND METHOD - The disclosed embodiments include a system that has a processor for executing computer-executable instructions and a computer-readable storage media for storing the computer-executable instructions. These instructions, when executed by the processor, enable the system to receive prescription data of a patient for corrective lenses and image data associated with the face of the patient. The system is configured to determine lens attributes for the patient based upon the prescription data and also determine facial attributes of the patient from the image data. Based on the lens attributes and the facial attributes of the patient, the system determines at least one frame recommendation for the patient. | 2018-04-19 |
20180108437 | METHOD FOR CREATING A PERSONALIZED MEMORY COMPILATION FOR COLLABORATIVE THERAPEUTIC REMINISCENCE - The present invention may provide a method and apparatus for generating a Personalized Memory Compilation, soliciting memories from members of a first group, collecting content from one or more data for the memories into a content collection, identifying preferences of the members of the first group, analyzing portions of the content collection to identify collaborative memories presenting the collaborative memories to a user for indication of social support, developing latent memories from collaboration between group members, reconsolidating memories from the collaborative memories and the developed latent memories, and compiling a collaborative output from the content. The method may include steps of increasing or decreasing social support or altering perceived social support. | 2018-04-19 |
20180108438 | Market Measures and Outcomes for App Prescribing - The disclosure generally describes computer-implemented methods, software, and systems for receiving and aggregating anonymized data reports about when prescribers provide wireless device applications to patients. The disclosure discusses ways of analyzing the data reports in combination with other electronic medical information to generate useful conclusions about scenarios in the health care process. | 2018-04-19 |
20180108439 | ENDOSCOPE INSPECTION REPORT CREATING APPARATUS, CREATING METHOD OF ENDOSCOPE INSPECTION REPORT AND STORAGE MEDIUM - An endoscope inspection report creating method includes creating, before an endoscopic inspection to be performed on an inspection target by a user, at least one folder and a folder name of the at least one folder in a memory, the at least one folder storing an endoscopic image file of the inspection target, the folder name including inspection information related to the endoscopic inspection; setting a storage destination folder in which the endoscopic image file is stored from the at least one folder by the user specifying the storage destination folder; creating a file name of the endoscopic image file, after the storage destination folder is set and an inspection result of the endoscopic inspection comes out, inspection result information of the endoscopic inspection and the folder name of the set storage destination folder being added to the file name; storing the endoscopic image file, the file name of which has been created, in the set storage destination folder; reading the file name of the endoscopic image file for which an inspection report is created; and creating the inspection report by writing the folder name, the inspection result information, and the endoscopic image of the inspection target in a predetermined report template format based on the read file name and the endoscopic image file having the read file name. | 2018-04-19 |
20180108440 | SYSTEMS AND METHODS FOR MEDICAL DIAGNOSIS AND BIOMARKER IDENTIFICATION USING PHYSIOLOGICAL SENSORS AND MACHINE LEARNING - Predictive healthcare systems utilize the signal produced by physiological and, in some embodiments, environmental sensors to infer, computationally, a physiological parameter of the patient. The physiological sensors may include a vibro-acoustic sensor in contact with a patient over at least the frequency band 0.001 Hz to 40 kHz and a bio-electric sensor. The physiological parameter may be the magnitude or existence of an internal process, such as blood flow; the presence of a biomarker; or the existence or likelihood of a disease. In some embodiments, the computational inference is based on additional data such as the patient's position and orientation and/or historical health information of the patient. | 2018-04-19 |
20180108441 | System For Searching Data Structures Stored In A Database - A computer-implemented method includes transmitting information indicative of an outcome questionnaire; receiving, from the first client device, answers to the series of questions; generating, based on the answers, an outcome score that is indicative of the severity of the functional limitation; determining a modifier that is indicative of a range of impairment, limitation or restriction of the portion of the user's anatomy; receiving a request to generate an insurance report, with the request comprising a selected type of functional limitation and a visit type; identifying a code that is indicative of the functional limitation that is being treated by the service provider and that is indicative of a point in time in a course of treatment of the user; generating, based on the identified code and the modifier, the insurance report; and submitting the insurance report to an insurance provider. | 2018-04-19 |
20180108442 | TELEMEDICINE REFERRAL PLATFORM - A method for telemedicine referral implemented on a computer is provided. The computer includes a server and a data storage device in communication with the server. The data storage device includes a database of information for each of a plurality of dermatologists stored thereon. The method includes receiving, by the server, a case information package from a patient-facing computing device; The method further includes selecting, by the server, at least one dermatologist from the plurality of dermatologists to be provided with at least a portion of the case information package; transmitting, by the server, at least a portion of the case information package to a dermatologist-facing computing device corresponding to each of the selected at least one dermatologist; and receiving, by the server, from the dermatologist-facing computing device, assessment information of the skin condition; and transmitting, by the server, the assessment information to the patient-facing computing device. | 2018-04-19 |
20180108443 | APPARATUS AND METHOD FOR ANALYZING NATURAL LANGUAGE MEDICAL TEXT AND GENERATING A MEDICAL KNOWLEDGE GRAPH REPRESENTING THE NATURAL LANGUAGE MEDICAL TEXT - The present application discloses an apparatus for analyzing natural language medical text and generating a medical knowledge graph representing the natural language medical text. The apparatus includes a memory; and one or more processors; the memory and the one or more processors are communicatively connected with each other; the memory gores computer-executable instructions for controlling the one or more processors to acquire a plurality of medical data from a medical data source; extract from the plurality of medical data to obtain a first set of plurality of medical information comprising a first entity of a first entity type and a second entity of a second entity type, a first attribute value of the first entity, a second attribute value of the second entity, and one or more relationships; and generate the medical knowledge graph based on at least a portion of the first set of plurality of medical information. | 2018-04-19 |
20180108444 | ULTRAVIOLET (UV) LIGHT INHIBITING APPARATUS AND SYSTEM - An Ultraviolet light inhibiting apparatus is adapted to be attached to a UV curing device on a front-right or front-left portion of the UV curing device. When attached, the UV light inhibiting apparatus shields at least a portion of UV light illuminated from UV bulbs of the UV curing device. | 2018-04-19 |
20180108445 | RADIONUCLIDE GENERATION SYSTEM AND METHOD OF PRODUCING RADIONUCLIDES - A method of producing radionuclides from irradiation targets in a nuclear reactor uses at least one instrumentation tube system of a commercial nuclear reactor. Irradiation targets and dummy targets are inserted into an instrumentation finger and the irradiation targets are activated by exposing them to neutron flux in the nuclear reactor core to form a radionuclide. The dummy targets hold the irradiation targets at a predetermined axial position in the reactor core corresponding to a pre-calculated neutron flux density sufficient for converting the irradiation targets to the radionuclide. Separating the dummy targets from the activated irradiation targets includes exposure to a magnetic field to retain either the dummy targets or the activated irradiation targets in the instrumentation tube system and release the other one of the activated irradiation target or the dummy target from the instrumentation tube system. An apparatus adapted to the above method is also provided. | 2018-04-19 |
20180108446 | SEMICONDUCTOR DEVICE FOR DIRECTLY CONVERTING RADIOISOTOPE EMISSIONS INTO ELECTRICAL POWER - A device for producing electricity. In one embodiment, the device comprises a doped germanium or a doped GaAs substrate and a plurality of stacked material layers (some of which are doped) above the substrate. These stacked material layers, which capture the beta particles and generate electrical current, may include, in various embodiments, GaAs, InAlP, InGaP, InAlGaP, AlGaAs, and other semiconductor materials. A beta particle source generates beta particles that impinge the stack, create electron-hole pairs, and thereby generate electrical current. In another embodiment the device comprises a plurality of epi-liftoff layers and a backing support material. | 2018-04-19 |
20180108447 | Compact X-Ray Images - Small, portable, and collapsible X-ray devices are described in this application. In particular, this application describes a portable X-ray device that contains a C-shaped support arm, an X-ray source contained near one end of the support arm, and an X-ray detector contained near the other end of the support arm, and the X-ray source is enclosed in a housing that also encloses a power source and a power supply. The X-ray device is portable since it can be configured to be carried by hand from location to location without using wheels or a gantry. The C-shaped support arm capable of rotating around an object to be analyzed that remains in a substantially fixed location when removably attached to a support structure using a connection that also allows the connection point to slide along the arc of the C-shaped support arm. The x-ray device can be quickly de-coupled from the support structure for handheld or table-top use. The C-shaped support arm can be configured to change the location of the X-ray source and X-ray detector relative to each other by being collapsible, reducing the volume of the x-ray device making it easier to transport. Other embodiments are described. | 2018-04-19 |
20180108448 | DOPED-CARBON NANO-ARCHITECTURED STRUCTURES AND METHODS FOR FABRICATING SAME - In an exemplary method, a nano-architectured carbon structure is fabricated by forming a unit (e.g., a film) of a liquid carbon-containing starting material and at least one dopant. A surface of the unit is nano-molded using a durable mold that is pre-formed with a pattern of nano-concavities corresponding to a desired pattern of nano-features to be formed by the mold on the surface of the unit. After nano-molding the surface of the unit, the first unit is stabilized to render the unit and its formed nano-structures capable of surviving downstream steps. The mold is removed from the first surface to form a nano-molded surface of a carbonization precursor. The precursor is carbonized in an inert-gas atmosphere at a suitable high temperature to form a corresponding nano-architectured carbon structure. A principal use of the nano-architectured carbon structure is a carbon electrode used in, e.g., Li-ion batteries, supercapacitors, and battery-supercapacitor hybrid devices. | 2018-04-19 |
20180108449 | THERMOELECTRIC COMPOSITE MATERIAL AND METHOD FOR PREPARING THERMOELECTRIC COMPOSITE MATERIAL - The present invention relates to a thermoelectric composite material and a method for preparing a thermoelectric composite material. Specifically, the invention relates to a thermoelectric composite material in which graphene oxide attached with conductive metal nanoparticles is dispersed in a thermoelectric material and a method for preparing a thermoelectric composite powder comprising the steps of: growing conductive metal nanoparticles on the surface of graphene oxide (step 1); and introducing the graphene oxide attached with the conductive metal nanoparticles prepared in step 1 into a thermoelectric material precursor solution, followed by heat treatment (step 2). | 2018-04-19 |
20180108450 | Polymer Composition for W&C Application with Advantageous Electrical Properties - The invention relates to power cable polymer composition which comprises a single site polyethylene (SSPE), a power cable, for example, a high voltage direct current (HV DC), a power cable polymer insulation, use of a polymer composition for producing a layer of a power cable, and a process for producing a power cable. | 2018-04-19 |
20180108451 | COMPOUNDS FOR DIELECTRICALLY INSULATING ELECTRIC ACTIVE PARTS - The invention concerns compounds, gas mixtures as well as methods for dielectrically insulating electric active parts using certain fluorinated peroxide compounds. | 2018-04-19 |
20180108452 | METHODS FOR DIELECTRICALLY INSULATING ELECTRICAL ACTIVE PARTS - The invention concerns methods for dielectrically insulating electrical active parts using certain fluorinated phosphorous-bearing compounds as well as compositions and apparatus comprising such compounds. | 2018-04-19 |
20180108453 | CABLE HARNESS - A cable harness ( | 2018-04-19 |
20180108454 | ULTRA-FLEXIBLE INDOOR ACCOMPANYING PHOTOELECTRIC COMPOSITE CABLE - The invention provides an ultra-flexible indoor accompanying photoelectric composite cable, and the cable comprises a plurality of power transmission components, optical fiber transmission components and structural strengthening components, which are covered by a highly flame-retardant outer protective layer. The power transmission component comprises a cable core which is a soft conductor and an insulating material layer wrapped around the cable core. The optical fiber transmission component is a tight tube optical fiber, and the power transmission components and the optical fiber transmission components are arranged in parallel inside the highly flame-retardant outer protective layer. The composite cable of the invention has very strong pressure resistance, stress resistance, and reciprocating resistance, good electrical and physical properties and more excellent environment resistant performance. Furthermore, the composite cable can simplify construction procedures, improve working efficiency and reduce construction cost. | 2018-04-19 |
20180108455 | PARALLEL PAIR CABLE - A parallel pair cable includes a pair of metal wires aligned in parallel at a predetermined interval, an insulating resin configured to integrally cover the pair of metal wires and having a cross-sectional shape of an ellipse, and a shield layer provided on an outer periphery of the insulating resin. The shield layer is a layer formed by plating or vapor-depositing metal on an outer peripheral surface of the insulating resin. | 2018-04-19 |
20180108456 | ACOUSTO-OPTIC AUDIO SIGNAL CABLE - The invention discloses an acousto-optic audio signal cable which includes an audio wire cluster, at least one LED marquee light wire or at least one illuminating line parallel or spiral twining around outside or external wall of the audio wire cluster and an acousto-optic controller. The audio wire cluster and the LED marquee light wires form a cluster which is coated by a transparent insulating layer. A main circuit board of the acousto-optic controller includes a sampling amplifier circuit component, an analog-digital conversion circuit component, a microprocessor and an output driver sequentially connected. The audio wire cluster is connected to the input end of the sampling amplifier circuit component. The LED marquee light wires are connected to the output driver. The acousto-optic audio signal cable is simple in structure, convenient to operate, dynamic, fashionable and capable of synchronously flickering light during tone and rhythm changes of instrumental performances and speeches. | 2018-04-19 |
20180108457 | Method of Depositing Niobium Doped Titania Film on a Substrate and the Coated Substrate Made Thereby - A coated article includes an applied transparent electrically conductive oxide film of niobium doped titanium oxide. The article can be made by using a coating mixture having a niobium precursor and a titanium precursor. The coating mixture is directed toward a heated substrate to decompose the coating mixture and to deposit a transparent electrically conductive niobium doped titanium oxide film on the surface of the heated substrate. In another coating process, the mixed precursors are moved toward the substrate positioned in a plasma area between spaced electrodes to coat the surface of the substrate. Optionally, the substrate can be heated or maintained at room temperature. The deposited niobium doped titanium oxide film has a sheet resistance greater than 1.2 ohms/square and an index of refraction of 1.00 or greater. The chemical formula for the niobium doped titanium oxide is Nb:TiO | 2018-04-19 |
20180108458 | WIRE HARNESS ASSEMBLING DEVICE AND WIRE HARNESS MANUFACTURING METHOD - The present invention aims to provide technology for performing both the step of inserting terminals and the step of performing wiring, without transferring the wire harness or the electrical wires included therein between the steps. A wire harness assembling device includes: a connector bar that has a rod shape and to which a plurality of connectors can be set; a setting bar that has a rod shape and is configured to hold a plurality of terminal-equipped electrical wires; and a frame to which at least one set composed of the connector bar and the setting bar is attached such that the setting bar is located forward of the connector bar. | 2018-04-19 |
20180108459 | CHIP RESISTOR AND METHOD FOR MAKING THE SAME - A chip resistor includes first and second electrodes spaced apart from each other, a resistor element arranged on the first and the second electrodes, a bonding layer provided between the resistor element and the two electrodes, and a plating layer electrically connected to the resistor element. The first electrode includes a flat outer side surface, and the resistor element includes a side surface facing in the direction in which the thirst and the second electrodes are spaced. The outer side surface of the first electrode is flush with the side surface of the resistor element. The plating layer covers at least a part of the outer side surface of the first electrode in a manner such that the covering portion of the plating layer extends from one vertical edge of the outer side surface to the other vertical edge. | 2018-04-19 |
20180108460 | THICK FILM RESISTOR AND PRODUCTION METHOD FOR SAME - A thick film resistor excluding a toxic lead component from a conductive component and glass and having characteristics equivalent to or superior to conventional resistors in terms of, in a wide resistance range, resistance values, TCR characteristics, current noise characteristics, withstand voltage characteristics and the like. The thick film resistor is formed of a fired product of a resistive composition, wherein the thick film resistor contains ruthenium-based conductive particles containing ruthenium dioxide and a glass component essentially free of a lead component and has a resistance value in the range of 100 Ω/□ to 10 MΩ/□ and a temperature coefficient of resistance within ±100 ppm/° C. | 2018-04-19 |
20180108461 | Arrester Temperature Monitor - An instrumented electric power arrester includes a temperature sensor, wireless transmitter, and a visual over-temperature indicator. A disk shaped module, a replacement varister block, or a dummy block containing the sensor/transmitter is placed between varister blocks inside the arrester housing. A strap-on module is attached to the outside of the arrester housing. The sensor/transmitter utilizes a harvesting power supply that draws electric power for the electronics from the power line protected by the arrester. An ambient temperature sensor may be utilized to enhance accuracy. The temperature sensor/transmitter typically sends arrester monitoring data wirelessly to an RTU or handheld unit located outside the arrester, which relays the monitoring data to an operations control center that scheduled replacement of the arrester based on the monitoring data. A surge counter keeps track of the number of equipment and lightening related temperature surges experienced by the arrester. | 2018-04-19 |
20180108462 | RECTANGULAR CHIP RESISTOR AND MANUFACTURING METHOD FOR SAME - The chip resistor includes insulating substrate | 2018-04-19 |
20180108463 | RARE EARTH MAGNET - A rare earth magnet includes main phase grains having an R | 2018-04-19 |
20180108464 | SINTERED BODY FOR FORMING RARE-EARTH MAGNET, AND RARE-EARTH SINTERED MAGNET - Provided are: a sintered body that forms a rare-earth magnet and is configured in a manner such that the divergence between the orientation angles of the easy axes of magnetization of magnet material particles and the orientation axis angle of the magnet material particles is kept within a prescribed range in an arbitrary micro-section of a magnet cross-section; and a rare-earth sintered magnet. This sintered body for forming a rare-earth magnet has two or more different regions exhibiting an orientation axis angle of at least 20°, given that the orientation axis angle is defined as the highest-frequency orientation angle among the orientation angles of the easy magnetization axes, relative to a pre-set reference line, of a plurality of magnet material particles in a rectangular section at an arbitrary position in a plane including the thickness direction and the widthwise direction. | 2018-04-19 |
20180108465 | MAGNETIC POWDER AND PRODUCTION METHOD THEREOF, MAGNETIC CORE AND PRODUCTION METHOD THEREOF, AND COIL COMPONENT - A magnetic powder contains at least the first alloy powder and the second alloy powder in which those composition are different. The second alloy powder has a smaller median diameter than the first alloy powder and contains Cr of 0.3-14 at %. The first alloy powder has a Cr content of 0.3 at % or less. With respect to the total sum of the first alloy powder and the second alloy powder, a content of the second alloy powder is 20-50 vol % and the ratio of the median diameter of the first alloy powder to the second alloy powder is 4-20. The first alloy powder comprises either an amorphous phase or a crystalline phase having an average crystallite size of 50 nm or smaller. Thereby, a magnetic powder having low magnetic loss and good corrosion resistance without damaging insulation resistance and saturation magnetic flux density can be realized. | 2018-04-19 |
20180108466 | SPIRAL NEAR FIELD COMMUNICATION (NFC) ANTENNA COIL - A Near Field Communications (NFC) antenna coil, having a first loop; and a second loop connected to the first loop to form a spiral shape, wherein the first loop and the second loop have different sizes to be mutually couplable with a first antenna pairing coil and a second antenna pairing coil, respectively. | 2018-04-19 |
20180108467 | INDUCTIVE LOAD CONTROL - A plurality of inductive loads ( | 2018-04-19 |
20180108468 | PLANAR SOLENOID INDUCTORS WITH ANTIFERROMAGNETIC PINNED CORES - A planar magnetic structure includes a closed loop structure having a plurality of core segments divided into at least two sets. A coil is formed about one or more core segments. A first antiferromagnetic layer is formed on a first set of core segments, and a second antiferromagnetic layer is formed on a second set of core segments. The first and second antiferromagnetic layers include different blocking temperatures and have an easy axis pinning a magnetic moment in two different directions, wherein when current flows through the coil, the magnetic moments rotate to form a closed magnetic loop in the closed loop structure. | 2018-04-19 |
20180108469 | COIL ELECTRONIC COMPONENT - A coil electronic component includes a body including metal powder particles having shape anisotropy and a coil unit disposed in the body and having an axis perpendicular with respect to a thickness direction of the body. The metal powder particles having shape anisotropy are arranged such that a plane-shaped surface thereof is parallel to a direction of flow of magnetic flux. | 2018-04-19 |
20180108470 | INDUCTOR AND CONVERTER HAVING THE SAME - The present disclosure discloses an inductor and a converter having the same. The inductor includes a magnetic core and a winding, the winding is provided within a window of the magnetic core, the winding includes a main body part and a sampling part, the main body part and the sampling part are connected in series, and a length ratio of the sampling part to the main body part is less than 2; wherein the main body part is formed of a low resistivity conductive material, the sampling part is formed of a low temperature coefficient conductive material, and a current flowing through the inductor is sampled across two ends of the sampling part. The inductor can obtain a current detection signal with high accuracy and low temperature drift with a compact structure, without increasing detection loss. | 2018-04-19 |
20180108471 | WIRELESS POWER TRANSMITTING APPARATUS - A wireless power transmitting apparatus including a first transmitting coil; a second transmitting coil; a third transmitting coil on the first transmitting coil and the second transmitting coil; and a substrate to accommodate the first transmitting coil, the second transmitting coil, and the third transmitting coil, further the substrate includes a wall to surround a part of an outer circumference of the first transmitting coil and a part of an outer circumference of the second transmitting coil; a first protrusion to surround a first part of an outer circumference of the third transmitting coil; and a second protrusion to surround a second part of the outer circumference of the third transmitting coil. | 2018-04-19 |
20180108472 | ENHANCED COMMON MODE CURRENT REDUCTION IN THREE-PHASE INDUCTORS, TRANSFORMERS, AND MOTOR DRIVE SYSTEMS - Enhanced common mode current reduction in three-phase inductors, transformers, and motor drive systems. A motor drive system includes an iron core transformer, a common-mode transformer coupled to a three-phase motor, and a variable speed drive providing a three-phase power signal to drive the three-phase motor, and coupled to the iron core transformer and the common mode transformer. The system includes a DC bus having a DC bus midpoint. The common-mode transformer includes a toroidal ferrite core, a first choke winding, a second choke winding, a third choke winding, a first coupling winding collocated with the first choke winding, a second coupling winding collocated with the second choke winding, and a third coupling winding collocated with the third choke winding. The first, second, and third coupling windings are coupled in parallel to one another. The coupled windings couple a neutral point of the iron core transformer to the DC bus midpoint. | 2018-04-19 |
20180108473 | IGNITION COIL FOR INTERNAL COMBUSTION ENGINE - An ignition coil for an internal combustion engine includes a coil main body portion, a connecting portion, and a conducting member. A convex surface forming portion, which is a portion constituting an inner peripheral convex surface, is disposed in the connecting portion. The convex surface forming portion has an outer peripheral concave surface. The connecting portion has a boundary portion which is a boundary between the convex surface forming portion and other portions in the axial direction. In the convex surface forming portion, at least a part of a region where the outer peripheral concave surface is formed has a portion having an area, in a cross-section orthogonal to the axial direction, equal to or smaller than that of the boundary portion. A thickness of the convex surface forming portion is equal to or thicker than that of the boundary portion. | 2018-04-19 |
20180108474 | DETECTION APPARATUS, POWER SUPPLY SYSTEM, AND METHOD OF CONTROLLING DETECTION APPARATUS - A detection apparatus includes: a measurement coil disposed in a vicinity of a power reception coil configured to receive power supplied through a magnetic field; a measurement section configured to measure a voltage of the measurement coil as a measurement coil voltage; and a foreign object detection section configured to obtain an electrical characteristic value of at least one of the power reception coil and the measurement coil on the basis of the measurement coil voltage, and to detect a foreign object in the magnetic field if the electrical characteristic value is lower than a predetermined lower limit threshold value. | 2018-04-19 |
20180108475 | METHOD OF MANUFACTURING COIL COMPONENT - A method of manufacturing a coil component includes the steps of disposing a dummy metal layer on a base; laminating a base insulating resin on the dummy metal layer; exposing the dummy metal layer by disposing an opening part in the base insulating resin; disposing a spiral wiring on the base insulating resin and disposing a sacrificial conductor on the dummy metal layer in the opening part of the base insulating resin; enlarging the sacrificial conductor by plating by energizing the dummy metal layer; covering the spiral wiring and the sacrificial conductor with an insulating resin; exposing the sacrificial conductor by disposing an opening part in the insulating resin; forming a hole part by removing the sacrificial conductor by etching from the opening part of the insulating resin; and constructing the inner magnetic path of a magnetic resin by filling the hole part with the magnetic resin. | 2018-04-19 |
20180108476 | METHOD FOR PRODUCING RARE-EARTH MAGNETS, AND RARE-EARTH-COMPOUND APPLICATION DEVICE - When a slurry | 2018-04-19 |
20180108477 | TUNABLE THREE DIMENSIONAL INDUCTOR - A tunable three-dimensional (3D) inductor comprises a plurality of vias arranged with spacing among them, a plurality of interconnects in a metal layer, wherein the plurality of interconnects connect the plurality of vias on one end, and a plurality of tunable wires that connects to the plurality of vias on the other end to form the 3D inductor. The physical configuration and inductance value of the 3D inductor are adjustable by tuning the plurality of tunable wires during manufacturing process. | 2018-04-19 |
20180108478 | Solid Electrolytic Capacitor Assembly - A capacitor assembly that is capable of exhibiting good electrical properties even under a variety of conditions is provided. More particularly, the capacitor assembly includes a capacitor element, which comprises a porous anode body that contains a valve metal compound, a dielectric that overlies the anode body and includes an oxide of the valve metal compound, and a solid electrolyte that overlies the dielectric. The solid electrolyte includes a conductive polymer and a hydroxy-functional polymer. Further, the capacitor element comprises an organofunctional silane compound that is bonded to the oxide of the dielectric and is capable of bonding to the hydroxy-functional polymer. | 2018-04-19 |
20180108479 | MULTILAYER CERAMIC CAPACITOR - In an embodiment, a multilayer ceramic capacitor | 2018-04-19 |
20180108480 | MULTILAYER CERAMIC CAPACITOR AND MULTILAYER CERAMIC CAPACITOR MOUNT STRUCTURE - A multilayer ceramic capacitor satisfies L≤about 1.4 mm, about 1.1≤L/W≤about 1.6, e≥about 0.10 mm, i/L>about 0.40 and i/g>about 2. L and W are maximum outer dimensions in length and width directions, e is a length direction distance along which a first or second end surface outer electrode located on a first side surface extends or along which the first or second end surface outer electrode located on a second side surface extends, g is a smallest distance among length direction distances between the first end surface outer electrode and a first or second side surface outer electrode and between the second end surface outer electrode and the first or second side surface outer electrode, and i is a distance on the side where g is among distances in the length direction along which the first and second side surface outer electrodes extend. | 2018-04-19 |
20180108481 | Ceramic Electronic Component and Method of Producing the Same - A ceramic electronic component includes a ceramic body and an external electrode. The external electrode is formed along a surface of the ceramic body and includes a tin layer as an outermost layer. The tin layer includes dispersed pores | 2018-04-19 |
20180108482 | MULTI-LAYER CERAMIC CAPACITOR AND METHOD OF PRODUCING THE SAME - A multi-layer ceramic capacitor includes a multi-layer unit and a side margin. The multi-layer unit includes ceramic layers laminated in a first direction and internal electrodes disposed between the ceramic layers. The side margin covers the multi-layer unit from a second direction orthogonal to the first direction and has a porosity of 1% or less. | 2018-04-19 |
20180108483 | METHOD FOR MANUFACTURING MULTILAYER CERAMIC CAPACITOR - A method for manufacturing a multilayer ceramic capacitor includes preparing a green multilayer body including a stack of dielectric sheets printed with inner electrodes, coating the green multilayer body with a conductive paste that is connected to the inner electrodes, and firing the conductive paste and the green multilayer body at the same time, wherein a rate of temperature increase from about 800° C. to about 1,100° C. during the firing is about 15° C. per minute or more. | 2018-04-19 |
20180108484 | POLYPROPYLENE FILM STRUCTURE - The present invention is a structure comprising a biaxially oriented film having a layer comprising a homopolymer of propylene which layer is in contact with oil, characterised in that the homopolymer of propylene has a content of isotactic pentads of from 95% to 98% and a content of ash of not more than 30 ppm. | 2018-04-19 |
20180108485 | MULTILAYER CERAMIC CAPACITOR AND BOARD FOR MOUNTING OF THE SAME - A multilayer ceramic capacitor may include a ceramic body including a plurality of dielectric layers; a first internal electrode disposed in the ceramic body and exposed to a first side surface in a width direction of the ceramic body and a second internal electrode disposed in the ceramic body and exposed to the first side surface in the width direction of the ceramic body; and first to third external electrodes disposed on the first side surface in the width direction of the ceramic body. | 2018-04-19 |
20180108486 | Devices Comprising A Capacitor And Support Material That Laterally Supports The Capacitor - A device comprises a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is elongated and extends elevationally. The first electrode comprises elevationally-extending first conductive material and comprises second conductive material that projects laterally outward from an elevationally-extending part of the first conductive material. The laterally-projecting second conductive material has a vertical thickness that is less than that of the elevationally-extending first conductive material. Support material laterally supports the capacitor and contacts a tip end of the laterally-projecting second conductive material. | 2018-04-19 |
20180108487 | Solid Electrolytic Capacitor with Improved Performance at High Temperatures and Voltages - A capacitor assembly that is capable of exhibiting good electrical properties even under a variety of conditions is provided. More particularly, the capacitor contains a capacitor element that includes a porous anode body that contains a valve metal compound, a dielectric that overlies the anode body and includes an oxide of the valve metal compound, a solid electrolyte that overlies the dielectric, wherein the solid electrolyte includes at least one conductive polymer layer that contains a sulfonyl ion, and an organofunctional silane that is bonded to the oxide of the dielectric and is capable of bonding to the sulfonyl ion of the conductive polymer layer. | 2018-04-19 |
20180108488 | ELECTROLYTIC CAPACITOR AND METHOD FOR MANUFACTURING SAME - An electrolytic capacitor includes an anode body, a dielectric layer formed on the anode body, a first conductive polymer layer covering at least a part of the dielectric layer, and a second conductive polymer layer covering at least a part of the first conductive polymer layer. The first conductive polymer layer contains a first conductive polymer and a first silane compound. The second conductive polymer layer contains a second conductive polymer and a basic compound. The basic compound may be an amine compound. | 2018-04-19 |
20180108489 | Solid Electrolytic Capacitor with Improved Leakage Current - A capacitor assembly that is capable of exhibiting good electrical properties even under a variety of conditions is provided. More particularly, the capacitor contains a capacitor element that includes a sintered porous anode body, a dielectric that overlies the anode body, and a solid electrolyte that overlies the dielectric. The solid electrolyte contains an adhesion layer that is positioned between an inner conductive polymer layer and an outer conductive polymer layer. The adhesion layer is formed from an organometallic compound and the outer layer is formed from pre-polymerized conductive polymer particles. | 2018-04-19 |
20180108490 | ELECTRICAL STORAGE DEVICE, MANUFACTURING METHOD OF THE SAME, AND SEPARATOR - An electrical storage device includes an electrical storage element and an electrolytic solution. The electrical storage element is formed of an anode body, a cathode body facing the anode body, and a separator interposed between the anode body and the cathode body. The separator includes a separator substrate and a conductive polymer adhering to the separator substrate. The electrical storage element is impregnated with the electrolytic solution. The separator includes a first surface layer having a first surface facing the anode body and a second surface layer having a second surface facing the cathode body. The first surface layer includes a first region that is not provided with the conductive polymer, and the second surface layer includes a second region provided with the conductive polymer. | 2018-04-19 |
20180108491 | PEROVSKITE PHOTOVOLTAIC DEVICE - A photovoltaic device, comprises (1) a first conductive layer, (2) an optional blocking layer, on the first conductive layer, (3) a semiconductor layer, on the first conductive layer, (4) a light-harvesting material, on the semiconductor layer, (5) a hole transport material, on the light-harvesting material, and (6) a second conductive layer, on the hole transport material. The light-harvesting material comprises a perovskite absorber, and the second conductive layer comprises nickel. The semiconductor layer may comprise Ti0 | 2018-04-19 |
20180108492 | PHOTOELECTRIC CONVERSION ELEMENT, SOLAR CELL, AND COMPOSITION - Provided are a photoelectric conversion element, a solar cell using the photoelectric conversion element, and a composition. The photoelectric conversion element includes a first electrode including a photosensitive layer, which includes a light absorbing agent, on a conductive support. The light absorbing agent includes a compound having a perovskite-type crystal structure that includes organic cations represented by the following Formulae (1) and (2), a cation of a metal atom, and an anion. | 2018-04-19 |
20180108493 | STACKED-TYPE SOLID ELECTROLYTIC CAPACITOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - The present disclosure provides a stacked-type solid electrolytic capacitor package structure and a method of manufacturing the same. The capacitor package structure includes a capacitor unit, a solder unit, a package unit and a conductive unit. The capacitor unit includes a plurality of first stacked capacitors. Each first stacked capacitor includes a first positive portion and a first negative portion. The first positive portion has at least one first through hole. The first through holes of the first positive portions are in communication with each other to form a first communication hole. The solder unit includes a first connection solder for filling the first communication hole so as to connect the first positive portions with each other. The package unit includes a package body for enclosing the capacitor unit and the solder unit. The conductive unit includes a first conductive terminal and a second conductive terminal. | 2018-04-19 |
20180108494 | ELECTROCHEMICAL DEVICE - In an embodiment, an electrochemical device includes a winding structure which has a negative electrode, a positive electrode, and separators stacked and wound together; a negative-electrode terminal; a positive-electrode terminal; a first protective tape which covers the negative-electrode terminal and a negative-electrode active material layer; a second protective tape which covers the positive-electrode terminal and a positive-electrode active material layer; and electrolyte, wherein the positive-electrode terminal is separated from the negative-electrode terminal by a first distance. The width corresponding to the sum of a first width of the first protective tape along a winding direction of the winding structure, and a second width of the second protective tape along the winding direction, is smaller than a value obtained by multiplying the first distance by pi. | 2018-04-19 |