16th week of 2018 patent applcation highlights part 50 |
Patent application number | Title | Published |
20180108495 | ELECTRIC DOUBLE-LAYER CAPACITOR - An electric double-layer capacitor includes a capacitor element, which includes a positive electrode and a negative electrode that face each other in a predetermined direction; a positive plate-like terminal portion connected to one end of the capacitor element in the predetermined direction; a negative plate-like terminal portion connected to another end of the capacitor element in the predetermined direction; and an exterior body configured to encapsulate the capacitor element, the positive plate-like terminal portion, and the negative plate-like terminal portion. The positive and the negative plate-like terminal portions have parts that face each other in the predetermined direction, and at least one protruding portion that protrudes from any one of the parts. The protruding portion has a distal end portion that is located between a first surface that is orthogonal to the predetermined direction and includes an outermost portion of the positive plate-like terminal portion in the predetermined direction, and a second surface that is orthogonal to the predetermined direction and includes an outermost portion of the negative plate-like terminal portion in the predetermined direction. | 2018-04-19 |
20180108496 | Method of Assembly of Electrochemical Cells for High Temperature Applications - Heat resistant, highly conductive electrochemical cells for high temperature applications and methods of their assembly are described herein. The cells have at least two electrodes and at least one separator enclosed in heat resistant ceramic enclosure with metalized terminals on its bottom. Methods of the electrodes' tabs welding to inside connectors and the electrodes' coating are also disclosed. The resulting cells are solderable to circuit boards or various circuits. | 2018-04-19 |
20180108497 | SMART SPEAKER WITH MULTIFUNCTIONAL FACEPLATE AND DISPLAY - In one embodiment a sound generating system comprises: a housing; a speaker located at least partially inside the housing; and an interactive faceplate subassembly comprising:
| 2018-04-19 |
20180108498 | Intelligent Switch For Automotive Application - An intelligent switch for automotive application. In particular, a resettable and/or programmable fuse comprising at least one inlet, at least one outlet, and a switch circuit electrically connecting the at least one inlet and the at least one outlet. In order to provide an intelligent switch for automotive applications that provides more than one switching function, the switch circuit comprises at least two switching submodules selected from an electromechanical switching submodule and an electric switching submodule. The intelligent switch further comprises a control unit for controlling an operating state of the at least two switching submodules. | 2018-04-19 |
20180108499 | MAGNETIC SENSOR ALIGNMENT WITH BREAKAWAY - Disclosed herein are electronic devices with a sensor configured to breakaway from an input button or input/output interface. In one example, the electronic device includes a button positioned within an opening of a chassis or housing. A sensor is in communication with the button, wherein the button is configured to contact the sensor in a first sensor position upon application of an activation force. At least one magnet is configured to retain the sensor in the first sensor position by a frictional or magnetic force. Additionally, the sensor is configured to move from the first sensor position to a second sensor position upon application of a force greater than the frictional or magnetic force and less than a sensor damage force. The activation force is less than the frictional or magnetic force, which is less than the sensor damage force. | 2018-04-19 |
20180108500 | APPARATUS AND METHODS FOR LATCHING, AND SYSTEMS INCLUDING THE SAME - The latching apparatus of the present disclosure includes an actuator configured to change from a first position to a second position; a core connector coupled to the actuator at a first end, and having a cam disposed thereon; and a follower located between the actuator and the cam; wherein the actuator pushes the follower when changing from the first position to the second position, such that the follower engages with the cam on the core connector and causes the cam to rotate an angle to enter a latching state, wherein during the latching state, the core connector configured to hold the actuator secured at the second position. Switch systems and Methods for switching a latching apparatus are also disclosed. | 2018-04-19 |
20180108501 | SPRING PLATE AND PUSH SWITCH INCLUDING SPRING PLATE - In a first aspect of the present disclosure, a spring plate includes a central portion; an opening that is positioned at a center of the central portion; and a strip extending from a part of an inner edge of the opening that is positioned at the center of the central portion. The strip includes a first width that is positioned adjacent to the part of the inner edge of the opening and a second width that is positioned adjacent to an end of the strip. The first width of the strip is wider than the second width that is positioned adjacent to the end of the strip. | 2018-04-19 |
20180108502 | MULTIMETER WITH PROTECTION MECHANISM OF CHARGE SWITCHING - A multimeter has a protection mechanism of charging. A measuring body includes a shell and a knob-turning set, and the shell has a charging socket. A control module is disposed in the shell and includes a circuit board and a connector electrically connected with the circuit board. The connector is disposed corresponding to the charging socket, and the circuit board is electrically connected with the knob-turning set and selectively actuated through a rotation of the knob-turning set. A charging unit is disposed in the shell and electrically connected with the connector. A stopper moves with the knob-turning set together. An external plug is inserted with the connector via the charging socket, and the stopper is actuated so that the knob-turning set will not to be rotated. Thus, it ensures the multimeter cannot perform a measurement when it is charging for avoiding danger. | 2018-04-19 |
20180108503 | ELECTRICAL TEST SWITCH WITH SOLIDIFYING BASE - A test switch for use in electrical power distribution networks is provided. The test switch facilitates the connection between the power distribution networks' equipment and test equipment used to effect tests on the power distribution networks' equipment. The test switch has a solidifying base which decouples the fastening of the body of the switch to the base of the test switch from the fastening of the test switch on an external surface/equipment. Various locking mechanisms for preventing use of or tampering with the test switch are also provided. | 2018-04-19 |
20180108504 | MEDIUM VOLTAGE CIRCUIT BREAKER IN SUBSEA ENVIRONMENT - In an embodiment, the present invention provides a medium voltage circuit breaker in high pressure subsea environment, including: a vacuum circuit breaker; and a drive in a pressure tight housing. For an electrical three-phase arrangement, one vacuum circuit breaker per phase is in arranged in a separate pole housing each, and the resulting three pole housings are mounted to a common base compartment, in which all the three drives for the three vacuum circuit breaker are arranged. The three pole housings and the common base compartment are attached such that they form commonly a pressure tight compartment. | 2018-04-19 |
20180108505 | CIRCUIT BREAKERS WITH HANDLE BEARING PINS - Circuit breakers with handles having at least one handle bearing pin that contacts an upper end portion of a moving arm and allows the arm to rotate to “OFF”, “ON” and “TRIP” positions, typically about 90 degrees of rotation. | 2018-04-19 |
20180108506 | FUSES WITH INTEGRATED METALS - Fuse assemblies are disclosed. In one implementation, a fuse assembly may be disposed that includes a first portion of the second portion. The first portion may be formed of a first metal. The second portion may be formed of a second metal different from the first metal. The second metal may be copper, and the copper may be tin plated or silver plated. | 2018-04-19 |
20180108507 | FUSE ELEMENT AND METHOD OF FABRICATION - A method of fabricating a fuse includes providing a fuse element within a casing. The fuse element has a plurality of ligaments configured to direct a current therethrough. A mechanical tension is then applied to the fuse element and a filler material is added to the casing so as to support the fuse element. The filler material is then solidified. Next, the mechanical tension is removed with the fuse element retaining a residual tensile stress after removal of the mechanical tension. | 2018-04-19 |
20180108508 | FOLD OVER EMITTER AND COLLECTOR FIELD EMISSION TRANSISTOR - A field emission transistor includes a gate, a fold over emitter, and fold over collector. The emitter and the collector are separated from the gate by a void and are separated from a gate contact by gate contact dielectric. The void may be a vacuum, ambient air, or a gas. Respective ends of the emitter and the collector are separated by a gap. Electrons are drawn across gap from the emitter to the collector by an electrostatic field created when a voltage is applied to the gate. The emitter and collector include a first conductive portion substantially parallel with gate and a second conductive portion substantially perpendicular with gate. The second conductive portion may be formed by bending a segment of the first conductive portion. The second conductive portion is folded inward from the first conductive portion towards the gate. Respective second conductive portions are generally aligned. | 2018-04-19 |
20180108509 | IMAGE INTENSIFIER BLOOM MITIGATION - Image intensifiers may include a photocathode that emits photoelectrons in proportion to the rate photons impact the photocathode. The photoelectrons are multiplied using a microchannel plate that includes a plurality of microchannels. Photoelectrons are scattered by the microchannel plate when the photoelectrons strike the surface of the microchannel plate rather than enter one of the microchannels. Electron scatter within an image intensifier results in a halo or bloom around bright or luminous objects. Halo or bloom may be minimized by reducing the electron scatter within the image intensifier. Deposition of an anti-scattering layer on the surface of the microchannel plate within the image intensifier can absorb photoelectrons that fail to enter a microchannel and may thus reduce the incidence of halo or bloom. | 2018-04-19 |
20180108510 | STABLE SUPPORT FILMS FOR ELECTRON MICROSCOPY - This disclosure provides systems, methods, and apparatus related to arrangements including electron microscopy grids. In one aspect an arrangement includes an electron microscopy grid. The electron microscopy grid comprises a first surface and a second surface, with the first surface having a holey carbon film disposed thereon. A plurality of lipid molecules are disposed in a hole in the holey carbon film. Each lipid molecule of the plurality of lipid molecules has a hydrophilic head and a hydrophobic tail. A biotin-binding protein is attached to the hydrophilic heads of the plurality of lipid molecules. The biotin-binding protein is crystalline. | 2018-04-19 |
20180108511 | MULTIBEAM-FOCUS ADJUSTING METHOD, MULTIBEAM-FOCUS MEASURING METHOD, AND CHARGED-PARTICLE-BEAM LITHOGRAPHY APPARATUS - A multibeam-focus adjusting method in a charged-particle-beam lithography apparatus that draws a pattern by irradiating a sample with multibeams having a plurality of beam lines through a plurality of lines of opening portions provided on an aperture member, the method adjusting a focus of the multibeams and including: acquiring a rotation angle of the beam lines with respect to an end edge of a mark provided at a predetermined position; determining selection beams to be used for adjustment among the multibeams based on the acquired rotation angle; and adjusting a focus of the multibeams based on reflected electrons acquired by irradiating the mark with the selection beams and scanning the mark in a direction orthogonal to the end edge of the mark. | 2018-04-19 |
20180108512 | Charged Particle Beam Apparatus, Alignment Method of Charged Particle Beam Apparatus, Alignment Program, and Storage Medium - The present invention shortens the time spent in a search for a visual field by a user in a charged particle beam apparatus in which an observation range on a sample is set by using a captured image of the sample. When the contour of a sample table is circularly configured, for example, the central position of a sample table image on an optical image is quickly, easily, and accurately obtained by calculating, from the coordinates of the respective vertices of a triangle circumscribed about the contour created on the optical image by the user, the incenter of the triangle without direct recognition by automatic image analysis, which is complex and time-consuming, of the contour of the sample table image on the optical image. | 2018-04-19 |
20180108513 | METHOD AND SYSTEM FOR DIMENSIONAL UNIFORMITY USING CHARGED PARTICLE BEAM LITHOGRAPHY - A method for mask process correction or forming a pattern on a reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern, and where pattern exposure information is modified to increase edge slope of the reticle pattern where sensitivity of the wafer pattern is high. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern. | 2018-04-19 |
20180108514 | Multi-Column Electron Beam Lithography Including Field Emitters on a Silicon Substrate with Boron Layer - A multi-column electron beam device includes an electron source comprising multiple field emitters fabricated on a surface of a silicon substrate. To prevent oxidation of the silicon, a thin, contiguous boron layer is disposed directly on the output surface of the field emitters. The field emitters can take various shapes including a pyramid, a cone, or a rounded whisker. Optional gate layers may be placed on the output surface near the field emitters. The field emitter may be p-type or n-type doped. Circuits may be incorporated into the wafer to control the emission current. A light source may be configured to illuminate the electron source and control the emission current. The multi-column electron beam device may be a multi-column electron beam lithography system configured to write a pattern on a sample. | 2018-04-19 |
20180108515 | PLASMA PROCESS APPARATUS - A plasma process apparatus that utilizes plasma so as to perform a predetermined process on a substrate, and includes a process chamber that houses a substrate subjected to the predetermined plasma process; a microwave generator; a dielectric window attached to the process chamber and provided with a concave portion provided at an outer surface of the dielectric window opposite to the process chamber and a through hole penetrating the dielectric window to the process chamber; a microwave transmission line; and a first process gas supplying portion including a gas conduit including a first portion provided at a front end and a second portion having a larger diameter than the first portion, the gas conduit being inserted from outside of the process chamber such that the first portion is inserted in the through hole and the second portion is inserted in the concave portion. | 2018-04-19 |
20180108516 | ION BEAM IRRADIATION APPARATUS AND SUBSTRATE PROCESSING APPARATUS - Disclosed is an ion beam irradiation apparatus including: a plurality of plate-like grid electrodes arranged in a beam irradiation direction so as to overlap each other and each having a plurality of apertures; a power supply unit that applies a voltage to each of the grid electrodes; and a controller that controls the voltage applied to each of the grid electrodes by the power supply unit. The plurality of grid electrodes include first to fourth grid electrodes. Central axes of apertures of the first grid electrode and apertures of the second grid electrode are coaxial along the beam irradiation direction, and a central axis of apertures of the third grid electrode is offset in a direction orthogonal to the beam irradiation direction with respect to the central axes of the apertures of the first grid electrode and the second grid electrode. | 2018-04-19 |
20180108517 | COATING ARCHITECTURE FOR PLASMA SPRAYED CHAMBER COMPONENTS - A method of plasma spraying an article comprises inserting the article into a vacuum chamber for a low pressure plasma spraying system. A low pressure plasma spray process is then performed by the low pressure plasma spraying system to form a first plasma resistant layer having a thickness of 20-500 microns and a porosity of over 1%. A plasma spray thin film, plasma spray chemical vapor deposition or plasma spray physical vapor deposition process is then performed by the low pressure plasma spraying system to deposit a second plasma resistant layer on the first plasma resistant layer, the second plasma resistant layer having a thickness of less than 50 microns and a porosity of less than 1%. | 2018-04-19 |
20180108518 | FILM FORMING APPARATUS, CLEANING METHOD FOR FILM FORMING APPARATUS AND RECORDING MEDIUM - A film forming apparatus | 2018-04-19 |
20180108519 | POWER DELIVERY FOR HIGH POWER IMPULSE MAGNETRON SPUTTERING (HiPIMS) - A system for the generation and delivery of a pulsed, high voltage signal for a process chamber includes a remotely disposed high voltage supply to generate a high voltage signal, a pulser disposed relatively closer to the process chamber than the high voltage supply, a first shielded cable to deliver the high voltage signal from the remotely disposed high voltage supply to the pulser to be pulsed, and a second shielded cable to deliver a pulsed, high voltage signal from the pulser to the process chamber. A method for generating and delivering a pulsed, high voltage signal to a process chamber includes generating a high voltage signal at a location remote from the process chamber, delivering the high voltage signal to a location relatively closer to the process chamber be pulsed, pulsing the delivered, high voltage signal, and delivering the pulsed, high voltage signal to the process chamber. | 2018-04-19 |
20180108520 | RATE ENHANCED PULSED DC SPUTTERING SYSTEM - A sputtering system and method are disclosed. The system includes a first power source that is configured to apply a first voltage at a first electrode that alternates between positive and negative relative to a second electrode during each of multiple cycles. A second power source is coupled to a third electrode and the second electrode, and the second power source is configured to apply a second voltage to the third electrode that alternates between positive and negative relative to the second electrode during each of the multiple cycles. A controller is configured to control the first power source and the second power source to phase-synchronize the first voltage with the second voltage, so both, the first voltage and the second voltage, are simultaneously negative during a portion of each cycle and simultaneously positive relative to the second electrode during another portion of each cycle. | 2018-04-19 |
20180108521 | Method of Increasing Quality of Tandem Mass Spectra - A method and apparatus for improving the quality of spectra of a sample obtained from a tandem mass spectrometer system containing an ion trap. The method and apparatus includes the setting of an upper and lower threshold limit on peak intensity and only triggering an enhanced product ion scan when a detected intensity of a peak in an initial scan falls between the upper and lower threshold limits. The spectra obtained from an enhanced product ion scan conducted in this manner are useful in library matching of spectra. The ion trap may be a linear ion trap and the sample may be a peptide. | 2018-04-19 |
20180108522 | IMR-MS DEVICE - Ion-molecule-reaction-mass spectrometry (IMR-MS) device, comprising an ion source, an adjacent reaction chamber and a mass spectrometer subsequent to the reaction chamber, wherein the reaction chamber comprises an RF device for creating a temporally changing electromagnetic field and wherein an adjustable reduced electric field strength (E/N) can be applied to the reaction chamber, characterized by an input device for entering a desired reduced electric field strength (E/N) by an operator when operating said IMR-MS device for analysing a sample, and a controlling device that operates the IMR-MS device by adjusting the settings of the IMR-MS device relating to a defined data set of a pseudo reduced electric field strength (PE/N | 2018-04-19 |
20180108523 | Mass Spectrometry Device and Analysis Method for Gas Phase Molecule-ion Reaction - A mass spectrometry device and analysis method for a gas phase molecule-ion reaction. The device comprises a reaction gas introduction device and a gas phase molecule-ion reaction mass spectrometry analysis device, wherein the reaction gas introduction device is connected to the gas phase molecule-ion reaction mass spectrometry analysis device; the reaction gas introduction device is configured to introduce reaction gas into the gas phase molecule-ion reaction mass spectrometry analysis device; and the gas phase molecule-ion reaction mass spectrometry analysis device is configured to enable molecules or ions to be subjected to a reaction and carry out mass spectrometry analysis on a reaction result. The reaction gas introduction device comprises a reaction gas container, the reaction gas container being configured to contain gas or volatile liquid or solid and generate gas molecules needed by a reaction; and a reaction gas quantitation device, configured to carry out flow control on the gas molecules. | 2018-04-19 |
20180108524 | BONDED SEMICONDUCTOR STRUCTURES - A method is disclosed that includes operations as follows. With an ion-implanted layer which is disposed between an epitaxial layer and a first semiconductor substrate, the epitaxial layer is bonded directly to a second semiconductor substrate. The ion-implanted layer is split to separate the first semiconductor substrate from the epitaxial layer completely. | 2018-04-19 |
20180108525 | Method for Forming a Thin Film Comprising an Ultrawide Bandgap Oxide Semiconductor - A method is disclosed for depositing a high-quality thin films of ultrawide bandgap oxide semiconductors at growth rates that are higher than possible using prior-art methods. Embodiments of the present invention employ LPCVD deposition using vapor formed by evaporating material as a precursor, where the material has a low vapor pressure at the growth temperature for the thin film. The vapor is carried to a reaction chamber by an inert gas, such as argon, where it mixes with a second precursor. The reaction chamber is held at a pressure that nucleation of the precursor materials occurs preferentially on the substrate surface rather than in vapor phase. The low vapor pressure of the material gives rise to growth rates on the substrate surface that a significantly faster than achievable using prior-art growth methods. | 2018-04-19 |
20180108526 | METHOD OF FORMING NANOWIRES - The disclosed technology generally relates semiconductor devices and more particularly to semiconductor devices comprising nanowires. In one aspect, a method of fabricating a semiconductor device includes providing a semiconductor substrate having one or more elongated structures thereon and forming a strained layer of semiconductor material on at least one surface of the elongated structures, and annealing the strained layer to form a semiconductor nanowire. | 2018-04-19 |
20180108527 | Self-Aligned Double Spacer Patterning Process - A method includes forming a mask layer over a target layer. A merge cut feature is formed in the mask layer. A first mandrel layer is formed over the mask layer and the merge cut feature. The first mandrel layer is patterned to form first openings therein. First spacers are formed on sidewalls of the first openings. The first openings are filled with a dielectric material to form plugs. The first mandrel layer is patterned to remove portions of the first mandrel layer interposed between adjacent first spacers. The merge cut feature is patterned using the first spacers and the plugs as a combined mask. The plugs are removed. The mask layer is patterned using the first spacers as a mask. The target layer is patterned, using the mask layer and the merge cut feature as a combined mask, to form second openings therein. | 2018-04-19 |
20180108528 | GATE OXIDE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for forming a gate oxide layer on a substrate is provided, in which a region of the substrate is defined out by a shallow trench isolation (STI) structure. An oxide layer covers over the substrate and a mask layer with an opening to expose oxide layer corresponding to the region with an interface edge of the STI structure. The method includes forming a silicon spacer on a sidewall of the opening. A cleaning process is performed through the opening to expose the substrate at the region. An oxidation process is performed on the substrate at the region to form the gate oxide layer, wherein the silicon spacer is also oxidized to merge to an edge of the gate oxide layer. | 2018-04-19 |
20180108529 | INTEGRATED DIRECT DIELECTRIC AND METAL DEPOSITION - Efficient integrated sequential deposition of alternating layers of dielectric and conductor, for example oxide/metal or metal nitride, e.g., SiO | 2018-04-19 |
20180108530 | METHOD FOR MANUFACTURING NIOBATE-SYSTEM FERROELECTRIC THIN-FILM DEVICE - This method for manufacturing a niobate-system ferroelectric thin-film device includes: a lower electrode film formation step of forming a lower electrode film on a substrate; a ferroelectric thin film formation step of forming a niobate-system ferroelectric thin film on the lower electrode film; an etch mask pattern formation step of forming an etch mask in a desired pattern on the niobate-system ferroelectric thin film, the etch mask being an amorphous fluororesin film laminated via a noble metal film; and a ferroelectric thin film etching step of shaping the niobate-system ferroelectric thin film into a desired fine pattern by wet etching using an etchant comprising: a chelating agent; an aqueous alkaline solution containing an aqueous ammonia solution; and an aqueous hydrogen peroxide solution. | 2018-04-19 |
20180108531 | HIGH ASPECT RATIO ETCH - A method for etching a layer in a processing chamber is provided. A plurality of cycles is provided, where each cycle comprises a deposition phase, a clearing phase, and an etching phase. The deposition phase comprises flowing a deposition gas comprising a fluorocarbon or hydrofluorocarbon gas into the processing chamber, maintaining a deposition phase pressure of at least 50 mTorr, transforming the deposition gas into a plasma, and stopping the deposition phase. The clearing phase comprises flowing a clearing gas comprising a halogen containing gas into the processing chamber, maintaining a clearing phase pressure of less than 40 mTorr, transforming the clearing gas into a plasma, and stopping the clearing phase. The etching phase comprises flowing an etching gas comprising a halogen containing gas into the processing chamber, maintaining an etching phase pressure of at least 30 mTorr, transforming the etching gas into a plasma, and stopping the etching phase. | 2018-04-19 |
20180108532 | SILICON OXIDE SILICON NITRIDE STACK ION-ASSISTED ETCH - A method for ion-assisted etching a stack of alternating silicon oxide and silicon nitride layers in an etch chamber is provided. An etch gas comprising a fluorine component, helium, and a fluorohydrocarbon or hydrocarbon is flowed into the etch chamber. The gas is formed into an in-situ plasma in the etch chamber. A bias of about 10 to about 100 volts is provided to accelerate helium ions to the stack and activate a surface of the stack to form an activated surface for ion-assisted etching, wherein the in-situ plasma etches the activated surface of the stack. | 2018-04-19 |
20180108533 | METHOD AND APPARATUS FOR USING UNIVERSAL CAVITY WAFER IN WAFER LEVEL PACKAGING - An electronics module assembly is described herein that packages dies using a universal cavity wafer that is independent of electronics module design. In one embodiment, the electronics module assembly can include a cavity wafer having a single frontside cavity that extends over a majority of a frontside surface area of the cavity wafer and a plurality of fillports. The assembly can also include at least one group of dies placed in the frontside cavity and encapsulant that secures the position of the at least one group of dies relative to the cavity wafer. Further, a layer of the encapsulant can cover a backside of the cavity wafer. | 2018-04-19 |
20180108534 | METHOD OF FORMING TITANIUM OXIDE FILM AND METHOD OF FORMING HARD MASK - A method for forming a titanium oxide film on a substrate to be processed, which has a silicon portion on a surface thereof, the method including: forming a first titanium oxide film on the surface of the substrate to be processed, which includes the silicon portion, by means of thermal ALD by alternately supplying a titanium-containing gas and a gas containing hydrogen and oxygen serving as an oxidizing agent in a first stage; and forming a second titanium oxide film on the first titanium oxide film by means of plasma ALD by alternately supplying a titanium-containing gas and plasma of an oxygen-containing gas as an oxidizing agent in a second stage. | 2018-04-19 |
20180108535 | CONTROLLING OF ETCH DEPTH IN DEEP VIA ETCHING PROCESSES AND RESULTANT STRUCTURES - The present disclosure relates to semiconductor structures and, more particularly, to a method to control depth of etch in deep via etching and related structures. The method includes: forming an interface within the substrate between an etch control dopant and material of the substrate; etching a via within substrate; and terminating the etching of the via at the interface upon detection of the interface. | 2018-04-19 |
20180108536 | SLURRY, POLISHING LIQUID SET, POLISHING LIQUID, METHOD FOR POLISHING SUBSTRATE, AND SUBSTRATE - The polishing liquid according to the embodiment comprises abrasive grains, an additive and water, wherein the abrasive grains include a tetravalent metal element hydroxide, and produce a liquid phase with a nonvolatile content of 500 ppm or greater when an aqueous dispersion with a content of the abrasive grains adjusted to 1.0 mass % has been centrifuged for 50 minutes at a centrifugal acceleration of 1.59×10 | 2018-04-19 |
20180108537 | GAS COMPOSITION FOR DRY ETCHING AND DRY ETCHING METHOD - A silicon oxide film or a silicon nitride film is selectively etched by using an etching gas composition including a hydrofluorocarbon that has an unsaturated bond in its molecule and is represented by CxHyFz, wherein x is an integer of from 3 to 5, and relationships y+z≤2x and y≤z are satisfied. Also, a silicon oxide film is etched with high selectivity relative to a silicon nitride film by controlling the ratio among the hydrofluorocarbon, oxygen, argon, etc., included in the hydrofluorocarbon-containing etching gas composition. | 2018-04-19 |
20180108538 | SILICON EPITAXIAL WAFER AND METHOD OF PRODUCING SAME - A silicon single crystal is pulled up such that nitrogen concentration of the crystal is 1×10 | 2018-04-19 |
20180108539 | METHOD FOR MANUFACTURING WIRING PATTERN, METHOD FOR MANUFACTURING TRANSISTOR, AND MEMBER FOR TRANSFER - An object is to provide a novel method in place of the above-described conventional technology, as a technique for obtaining a thin film with a wiring pattern applied. A method for manufacturing a wiring pattern according to the present invention is characterized in that the method includes: a laminate forming step of forming a laminate by bringing a first member that has a resist layer and a metal layer formed on the resist layer into contact with a second member that includes a substrate; a resist layer patterning step of subjecting the resist layer to patterning; and an etching step of selectively removing the metal layer. | 2018-04-19 |
20180108540 | METHOD OF FORMING AN INTERPOSER AND A METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A method of manufacturing a semiconductor package including forming a photoresist pattern on a first surface of an interposer substrate. The interposer substrate includes an electrode zone and a scribe line zone. The interposer substrate is etched using the photoresist pattern as a mask to form a first opening and a second opening respectively on the electrode zone and the scribe line zone. An insulation layer and a conductive layer are formed on the first surface of the interposer substrate. A width of the second opening is smaller than a width of the first opening. The insulation layer contacts each of the first surface of the interposer substrate, an inner surface of the first opening, and an inner surface of the second opening. | 2018-04-19 |
20180108541 | INFORMATION MANAGEMENT DEVICE AND INFORMATION MANAGEMENT METHOD - A management device that, when a component is mounted on a substrate, acquires pickup source information that includes pickup position information of the mounted component and mounting destination information that includes mounting position information of the mounted component and memorizes mounting result information that links both the above information on an HDD. By referencing the mounting result information memorized on the HDD and obtaining the pickup source information from the mounting destination information of the mounted component, it is possible to identify the pickup position at the wafer from which the mounted component was picked up. | 2018-04-19 |
20180108542 | Semiconductor Device and Method of Forming Interposer with Opening to Contain Semiconductor Die - A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die. | 2018-04-19 |
20180108543 | NOZZLE AND ETCHING APPARATUS - A nozzle for use in an etching apparatus and an etching apparatus including the nozzle are provided. The nozzle includes: a hollowed main body having a connector at one end thereof and a main-body outlet at the other end thereof, a main-body connection part being provided at an outer wall of the main body, said one end of the main body being connected with a pipe via the connector and a nozzle sleeve including a nozzle-sleeve connection part and a nozzle-sleeve outlet, the nozzle sleeve being connected to an outer side of said the other end of the main body having the main-body outlet through the nozzle-sleeve connection part and the main-body connection part and the nozzle sleeve is movable relative to the main body in an outflow direction of the main body. | 2018-04-19 |
20180108544 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus includes a substrate holding unit configured to hold a substrate; a first processing liquid nozzle configured to supply a first processing liquid to a peripheral portion of the substrate; a second processing liquid nozzle configured to supply a second processing liquid, the temperature of which is lower than that of the first processing liquid, to the peripheral portion of the substrate; a first gas supply port configured to supply a first gas at a first temperature to a first gas supplied place on the peripheral portion of the substrate; and a second gas supply port configured to supply a second gas at a second temperature lower than the first temperature to a place closer to the center in the radial direction as compared to the first gas supplied place with respect to the substrate. | 2018-04-19 |
20180108545 | WET ETCHING DEVICE AND EXPLOSION PREVENTION METHOD THEREOF - The present invention provides a wet etching device and an explosion prevention method thereof. The heater ( | 2018-04-19 |
20180108546 | METHOD AND APPARATUS FOR CLEANING COMPONENT OF SUBSTRATE PROCESSING APPARATUS - Disclosed are an apparatus and a method for cleaning a component of a substrate dry processing apparatus. The method for cleaning a component of a substrate dry processing apparatus includes dipping the component in a cleaning solution received in a cleaning bath, generating radicals from the cleaning solution, and cleaning the component with the radicals. The component is cleaned with hydrogen radicals (H | 2018-04-19 |
20180108547 | Semiconductor Bonding Apparatus and Related Techniques - A semiconductor structure bonding apparatus is disclosed. The apparatus may include a leveling adjustment system configured to provide leveling adjustment of upper and lower block assemblies of the apparatus. In some cases, the leveling adjustment system may include a plurality of threaded posts, differentially threaded adjustment collars, and leveling sleeves. In some instances, the leveling adjustment system further may include a plurality of preload springs configured to provide a given preload capacity and range of adjustment. In some instances, the leveling adjustment system further may include a load cell through which one of the threaded posts may be inserted. In some embodiments, the upper block assembly further may include a reaction plate configured to reduce deformation of the upper block assembly. In some embodiments, the upper block assembly further may include a thermal isolation plate configured to provide compliance deflection and being of monolithic or polylithic construction, as desired. | 2018-04-19 |
20180108548 | Systems and Methods for Workpiece Processing - Systems and methods for processing workpieces, such as semiconductor workpieces are provided. One example embodiment is directed to a processing system for processing a plurality of workpieces. The plasma processing system can include a loadlock chamber. The loadlock chamber can include a workpiece column configured to support a plurality of workpieces in a stacked arrangement. The system can further include at least two process chambers. The at least two process chambers can have at least two processing stations. Each processing station can have a workpiece support for supporting a workpiece during processing in the process chamber. The system further includes a transfer chamber in process flow communication with the loadlock chamber and the process chamber. The transfer chamber includes a rotary robot. The rotary robot can be configured to transfer a plurality of workpieces from the stacked arrangement in the loadlock chamber to the at least two processing stations. | 2018-04-19 |
20180108549 | SUBSTRATE PROCESSING APPARATUS - The disclosure provides a substrate processing apparatus. The substrate processing apparatus includes: an etching region and one or more aerosol absorption devices arranged outside a substrate inlet of the etching region. The aerosol absorption device includes one or more spraying pipes. The aerosol absorption device is capable of absorbing the aerosol of the etching solution from the etching region, thereby reducing the damage of the aerosol to the substrate processing components. | 2018-04-19 |
20180108550 | Semiconductor Wafer Transportation - A method includes causing a carrier of an overhead hoist transfer system (OHT) to latch onto a top latch of a first semiconductor wafer transportation pod, the first semiconductor wafer transportation pod comprising a top latching mechanism configured to selectively connect to another pod or a carrier mechanism of an overhead hoist transfer (OHT) system, and a bottom latching mechanism configured to selectively connect to another pod. The method further includes rotating the first semiconductor wafer transportation pod such that the top latching mechanism of the first semiconductor wafer transportation pod latches on to a second semiconductor wafer transportation pod. | 2018-04-19 |
20180108551 | Substrate Transport Vacuum Platform - An apparatus including a first device configured to support at least one substrate thereon; and a first transport having the device connected thereto. The transport is configured to carry the device. The transport includes a plurality of supports which are movable relative to one another along a linear path; at least one magnetic bearing which at least partially couples the supports to one another. A first one of the magnetic bearings includes a first permanent magnet and a second magnet. The first permanent magnet is connected to a first one of the supports. A magnetic field adjuster is connected to the first support which is configured to move the first permanent magnet and/or vary influence of a magnetic field of the first permanent magnet relative to the second magnet. | 2018-04-19 |
20180108552 | Substrate Transport Vacuum Platform - A transport apparatus including a robot drive; an arm having a first end connected to the robot drive; and at least one end effector connected to a second end of the arm. The arm includes at least three links connected in series to form the arm. The arm is configured to be moved by the robot drive to move the at least one end effector among load locks and two or more sets of opposing process modules. | 2018-04-19 |
20180108553 | Substrate Transport Vacuum Platform - A transport apparatus including a robot drive; an arm having a first end connected to the robot drive; and at least one end effector connected to a second end of the arm. The arm includes at least three links connected in series to, form the arm. The arm is configured to be moved by the robot drive to move the at least one end effector among load locks and two or more sets of opposing process modules. | 2018-04-19 |
20180108554 | METHOD FOR SELF-ALIGNING A THIN-FILM DEVICE ON A HOST SUBSTRATE - A method for self-aligning a thin-film device on a host substrate is provided. A predetermined location on a host substrate is treated with a hydrophobic lubricant to alter its interfacial energy. A needle is used to transfer a thin-film device, under water, to the location. Upon contact with the lubricant, the device adheres and self-aligns to the location to minimize the interfacial energy. | 2018-04-19 |
20180108555 | ELECTROSTATIC CHUCK DEVICE - An electrostatic chuck device includes: a placing plate having a placement surface on which a plate-like sample is placed on one side thereof; an electrostatic attraction electrode provided on the other side of the first ceramic plate; and a first organic insulating layer provided between the first ceramic plate and the electrostatic attraction electrode. The electrostatic chuck device further has a supporting plate provided between the first organic insulating layer and the electrostatic attraction electrode. | 2018-04-19 |
20180108556 | MEMBER FOR SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD FOR PRODUCING THE SAME - A method for producing a member for a semiconductor manufacturing apparatus | 2018-04-19 |
20180108557 | DEVICE COMPRISING FILM FOR ELECTROSTATIC COUPLING OF A SUBSTRATE TO A SUBSTRATE CARRIER - The invention relates to an apparatus for electrostatic coupling of a substrate with a substrate carrier, wherein the apparatus includes a flexible plastic carrier film on which an electrically contactable electrode structure is unilaterally deposited, and a cover layer which can be brought into contact with the electrode structure on the side of the electrode structure facing away from the carrier film, wherein the apparatus is configured such that, in a coupled state, the same is arranged at least in sections between the substrate and the substrate carrier and, in a non-coupled state, the same can be removed from the substrate carrier in a reusable manner. | 2018-04-19 |
20180108558 | WAFER DE-BONDING DEVICE - A wafer de-bonding device comprises a stage ( | 2018-04-19 |
20180108559 | Methods and Systems for Chucking a Warped Wafer - Methods and systems for vacuum mounting a warped, thin substrate onto a flat chuck are presented herein. A vacuum chuck includes three or more collapsible bellows that move above the chuck and into contact with a warped substrate. The bellows seal and vacuum clamp onto the backside surface of the substrate. In some embodiments, the bellows collapse by at least five hundred micrometers while clamping. An extensible sealing element is mounted in a recessed annular channel on the surface of the chuck body. As the substrate moves toward the chucking surface, the extensible sealing element extends at least five millimeters above the chuck body and into contact with the substrate. As the space between the chuck and the substrate is evacuated, the extensible sealing element collapse into the recessed annular channel, and the substrate is clamped onto the flat chucking surface of chuck body. | 2018-04-19 |
20180108560 | SUBSTRATE HOLDER - Substrate holders having support plates for mounting of substrates are disclosed. The substrate holders use a combination of spring clamping elements and pins to grip the substrates. The substrate edge contact height of the spring clamping elements and pins may be selected such that upper portions of the side edges of the substrates are substantially unobstructed, allowing coating to be applied to upper surfaces and upper portions of the side edges of the substrates contemporaneously. | 2018-04-19 |
20180108561 | Robot Having Arm with Unequal Link Lengths - An apparatus including at least one drive; a first robot arm having a first upper arm, a first forearm and a first end effector. The first upper arm is connected to the at least one drive at a first axis of rotation. A second robot arm has a second upper arm, a second forearm and a second end effector. The second upper arm is connected to the at least one drive at a second axis of rotation which is spaced from the first axis of rotation. The first and second robot arms are configured to locate the end effectors in first retracted positions for stacking substrates located on the end effectors at least partially one above the another. The first and second robot arms are configured to extend the end effectors from the first retracted positions in a first direction along parallel first paths located at least partially directly one above the other. The first and second robot arms are configured to extend the end effectors in at least one second direction along second paths spaced from one another which are not located above one another. The first upper arm and the first forearm have different effective lengths. The second upper arm and the second forearm have different effective lengths. | 2018-04-19 |
20180108562 | PROTECTIVE COVER FOR ELECTROSTATIC CHUCK - In embodiments, manufacturing a protective cover for an electrostatic chuck comprises coating a top surface and side walls of a conductive wafer with a plasma resistant ceramic, masking an inner region of a bottom surface of the conductive wafer, coating inner region of the bottom surface with the plasma resistant ceramic, and grinding the inner region of the bottom surface to a flatness of less than approximately 300 microns. In embodiments, a protective cover is manufactured by a process comprising applying a mask to an outer perimeter of a bottom surface of a plasma resistant ceramic wafer, coating the bottom surface of the plasma resistant ceramic wafer with an electrically conductive layer, and removing the mask, wherein an inner region of the bottom surface of the plasma resistant ceramic wafer is coated with the conductive layer. | 2018-04-19 |
20180108563 | METHOD OF FABRICATING ISOLATION STRUCTURE - A method of fabricating an isolation structure is provided. A first oxide layer and a first, second, and third hard mask layers are formed on a substrate. A patterned third hard mask layer is formed. Second oxide layers are formed on sidewalls of the patterned third hard mask layer and a fourth hard mask layer is formed between the second oxide layers. The second oxide layers and the second hard mask layer are removed using the patterned third hard mask layer and the fourth hard mask layer as a mask, to form a patterned second hard mask layer. The patterned third hard mask layer and the fourth hard mask layer are removed. A portion of the patterned second hard mask layer is removed to form trench patterns. A patterned first hard mask layer and first oxide layer, and trenches located in the substrate are defined. An isolation material is formed. | 2018-04-19 |
20180108564 | DESIGN AND INTEGRATION OF FINFET DEVICE - An integrated circuit containing finFETs may be formed with fins extending above isolation oxide. A first finFET and a second finFET have exposed fin heights which are different by at least 25 percent. The exposed fin height is a vertical height of a sidewall of the fin above the isolation oxide. Gates are formed over the fins. In one version, a fin height of the first finFET is less than a fin height of the second finFET; a thickness of the isolation oxide adjacent to fins of the first finFET and the second finFET is substantially uniform. The fin height is the height of a top of the fin above the substrate. In another version, the isolation oxide is thinner at the first finFET than at the second finFET; the fin heights of the first finFET and the second finFET are substantially equal. | 2018-04-19 |
20180108565 | METHOD OF LASER-PROCESSING DEVICE WAFER - There is provided a method of laser-processing a device wafer with a laser beam applied thereto. The device wafer has a face side having thereon a plurality of crossing projected dicing lines and devices formed in respective areas demarcated by the projected dicing lines. The method includes a covering step of supplying the face side of the device wafer with water and a powdery protective film agent to cover the face side with an aqueous solution in which the powdery protective film agent is dispersed, a protective film forming step of evaporating the water content of the aqueous solution to form a protective film on the face side, and a laser processing step of applying a laser beam having a wavelength that is absorbable by the device wafer to the device wafer along the projected dicing lines to form laser-processed grooves in the device wafer along the projected dicing lines. | 2018-04-19 |
20180108566 | INTEGRATED CIRCUIT STRUCTURE HAVING DEEP TRENCH CAPACITOR AND THROUGH-SILICON VIA AND METHOD OF FORMING SAME - One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include providing a substrate having a front side and a back side, the substrate including a deep trench (DT) capacitor within the substrate extending toward the back side of the substrate; etching the substrate on the back side of the substrate to remove at least a portion of the substrate on the back side; forming a first dielectric layer covering the back side of the substrate and extending away from the front side of the substrate; and forming a through silicon via (TSV) adjacent to the DT capacitor, the TSV extending through the first dielectric layer toward the front side of the substrate. | 2018-04-19 |
20180108567 | SEMICONDUCTOR DEVICE AND A METHOD FOR FORMING A SEMICONDUCTOR DEVICE - A method for forming a semiconductor device comprises forming an insulation trench structure comprising insulation material extending into the semiconductor substrate from a surface of the semiconductor substrate. The insulation trench structure laterally surrounds a portion of the semiconductor substrate. The method further comprises modifying the laterally surrounded portion of the semiconductor substrate to form a vertical electrically conductive structure comprising an alloy material. The alloy material is an alloy of the semiconductor substrate material and at least one metal. | 2018-04-19 |
20180108568 | LASER LIFT-OFF METHOD OF WAFER - The present invention relates to a laser lift-off method of wafer. The method includes the steps as follows: focusing laser in an inside for a wafer ( | 2018-04-19 |
20180108569 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD - A semiconductor apparatus and its manufacturing method are presented. The method entails providing a substrate structure comprising a substrate, one or more fins positioned along a first direction on the substrate, and a separation region surrounding the fins. The separation region comprises a first separation region neighboring a first side of the fins and a second separation region neighboring a second side of the fins; forming a first and a second insulation layers on the substrate structure; forming a barrier layer; performing a first etching process using the barrier layer as a mask; removing the barrier layer; performing a second etching process using the remaining second insulation layer as a mask; forming a third insulation layer on side surfaces of the remaining first and second insulation layers; and performing a third etching process using the remaining second insulation layer and the third insulation layer as a mask. | 2018-04-19 |
20180108570 | METHOD FOR MANUFACTURING FINS - A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process. | 2018-04-19 |
20180108571 | METHOD, APPARATUS, AND SYSTEM FOR USING A COVER MASK FOR ENABLING METAL LINE JUMPING OVER MOL FEATURES IN A STANDARD CELL - At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature. | 2018-04-19 |
20180108572 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - The present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor. The semiconductor device includes a substrate; two fins located on the substrate and extending along a first direction; an isolation material layer surrounding the fins, comprising a first isolation regions located at an end region between the two fins along the first direction, and a second isolation region located at sides of the fins along a second direction that is different from the first direction, wherein an upper surface of the first isolation region substantially align with an upper surfaces of the fins, and an upper surface of the second isolation region is lower than the upper surface of the fins; and a first insulating layer on the first isolation region | 2018-04-19 |
20180108573 | FIN-FET DEVICES AND FABRICATION METHODS THEREOF - A method for fabricating a Fin-FET device includes providing a base structure and a plurality of fin structures protruding from the base structure. Along a direction perpendicular to the surface of the base structure and from the bottom to the top of each fin structure, the width of the fin structure perpendicular to the length direction of the fin structure decreases. The method further includes forming a gate structure on the base structure across each fin structure and covering a portion of top and sidewall surfaces of the fin structure, and removing a portion of the fin structure on each side of the gate structure to form a trench in the fin structure. Along the length direction of the fin structure, the bottom width of the trench is smaller than the top width of the trench. The method also includes filling each trench with a doped source/drain epitaxial layer. | 2018-04-19 |
20180108574 | FINFET DEVICE AND FABRICATION METHOD THEREOF - A FinFET device and fabrication method thereof is provided. The fabrication method include: providing a semiconductor substrate with a fin protruding from the semiconductor substrate, and a gate structure across a length portion of the fin and covering a portion of the fin; etching a partial thickness of the fin on both sides of the gate structure to form grooves; forming a doped layer in a bottom and sidewalls of the grooves; annealing the doped layer to allow the doping ions to diffuse into the fin and to form a lightly doped source/drain region; removing the doped layer after the annealing; and forming epitaxial layers to fill up the grooves. | 2018-04-19 |
20180108575 | FINFET DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a Fin-FET device includes forming fin structures on a substrate and an isolation structure to cover a portion of sidewall surfaces of the fin structures, forming gate structures to cover a portion of sidewall and top surfaces of the fin structures, forming doped source/drain regions in the fin structures, forming a metal layer on the doped source/drain regions and the gate structures, performing a reaction annealing process to convert the metal layer formed on the doped source/drain regions into a metal contact layer and then removing the unreacted metal layer, forming a dielectric layer on the metal contact layer and the gate structures with a top surface higher than the top surfaces of the gate structures, forming a plurality of vias through the dielectric layer above the metal contact layer, and forming a plurality of conductive plugs by filling the vias. | 2018-04-19 |
20180108576 | SEMICONDUCTOR ARRANGEMENT AND METHOD OF FORMING - A semiconductor arrangement is provided comprising a guard region. The semiconductor arrangement comprises an active region disposed on a first side of the guard region. The active region comprises an active device. The guard region of the semiconductor arrangement comprises residue from the active region. A method of forming a semiconductor arrangement is also provided. | 2018-04-19 |
20180108577 | IC UNIT AND METHOND OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE INCLUDING THE SAME - There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device. | 2018-04-19 |
20180108578 | Metrology Systems And Methods For Process Control - Methods and systems for estimating values of parameters of interest based on repeated measurements of a wafer during a process interval are presented herein. In one aspect, one or more optical metrology subsystems are integrated with a process tool, such as an etch tool or a deposition tool. Values of one or more parameters of interest measured while the wafer is being processed are used to control the process itself. The measurements are performed quickly and with sufficient accuracy to enable yield improvement of a semiconductor fabrication process flow. In one aspect, values of one or more parameters of interest are estimated based on spectral measurements of wafers under process using a trained signal response metrology (SRM) measurement model. In another aspect, a trained signal decontamination model is employed to generate decontaminated optical spectra from measured optical spectra while the wafer is being processed. | 2018-04-19 |
20180108579 | SOLAR CELL EMITTER CHARACTERIZATION USING NON-CONTACT DOPANT CONCENTRATION AND MINORITY CARRIER LIFETIME MEASUREMENT - A method and apparatus for estimating an effect of variations of wafer properties on operating parameters of photovoltaic cells during manufacturing is provided. Measurements of emitter sheet resistance, minority carrier lifetime, and wafer resistivity of a wafer are obtained during manufacture of the wafer into a photovoltaic cell. Measurements may be made in-line with manufacturing. Current and voltage (I-V) parameters of the photovoltaic cell, such as V | 2018-04-19 |
20180108580 | METHOD FOR MANUFACTURING A SEMICONDUCTOR PRODUCT WAFER - Improved methods for manufacturing semiconductor product wafer with the additional use of non-product masks are described. According to certain aspects of the invention, an evaluation wafer is first manufactured by utilizing at least one non-product mask to process one or more layer(s) on the evaluation wafer, and subsequently utilizing at least one unaltered product mask to process an evaluation-region-of-interest on the evaluation wafer. The evaluation-region-of-interest is evaluated by measuring the state of one or more feature(s) in the evaluation-region-of-interest using voltage contrast inspection (VCi). The measurements are then used to identify failures in the evaluation-region-of-interest. In response to identifying a failure in the evaluation-region-of-interest, the manufacturing process is improved by modifying at least one parameter associated with at least one processing step and manufacturing product wafers utilizing the at least one processing step(s) with the at least one modified parameter(s). | 2018-04-19 |
20180108581 | LID, AND OPTICAL DEVICE PACKAGE - A lid constitutes, together with a housing, a package that encloses an optical element. The lid includes a frame plate divided into a first member and a second member; and a window plate that closes an opening of the frame plate. The window plate includes a lower surface whose outer peripheral part is bonded to the first member and an upper surface whose outer peripheral part is bonded to the second member. | 2018-04-19 |
20180108582 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate with a recess subsiding from a selected surface of the substrate to accommodate a semiconductor element. Connected to the semiconductor element, an electroconductive portion extends from the recess onto the selected surface. A post, formed at the selected surface, has a first surface in contact with the electroconductive portion, a second surface, and a side surface between the first and second surfaces. A sealing resin covers the side surface of the post and the semiconductor element, and has a mounting surface facing in the same direction as the selected surface of the substrate. A pad, on the mounting surface of the sealing resin, is in contact with the second surface of the post. In the thickness direction, the second surface of the post is offset from the mounting surface of the sealing resin toward the selected surface of the substrate. | 2018-04-19 |
20180108583 | DEVICE CHIP, ACCOMMODATING TRAY, AND METHOD OF ACCOMMODATING DEVICE CHIPS - A device chip is shaped as an inverted frustum with a device formed on an upper surface thereof. An accommodating tray for accommodating a plurality of device chips each shaped as an inverted frustum with a device formed on an upper surface thereof, has a plurality of open recesses defined in an upper surface thereof, for accommodating device chips therein, each of the recesses having a bottom surface and a side surface which form an obtuse angle therebetween. A method of accommodating the device chips in the accommodating tray includes a supplying step of supplying the device chips onto the accommodating tray, and after the device chips supplying step is performed, an accommodating step of imparting vibrations to the accommodating tray to cause the device chips into the recesses thereby placing the device chips in the recesses. | 2018-04-19 |
20180108584 | Semiconductor Substrate - A semiconductor substrate includes a device carrier, a plurality of stiffener structures and a plurality of spaced areas. The device carrier includes a plurality of trace layout units and a periphery around the trace layout units. The stiffener structures are disposed on the device carrier along the periphery of the trace layout units. The spaced areas are disposed between the stiffener structures. | 2018-04-19 |
20180108585 | CHIP PACKAGING STRUCTURE AND PACKAGING METHOD - A chip package and packaging method are provided. The package includes: a substrate; a sensing chip coupled with the substrate, where the sensing chip has a first surface and a second surface opposite to the first surface and facing the substrate, where the sensing chip includes a sensing area arranged on the first surface and a peripheral area surrounding the sensing area, where the peripheral area is provided with a groove, and surfaces of sidewall and bottom of the groove and a surface of the peripheral area are provided with a rewiring layer, and the groove is exposed from sidewall of the sensing chip; and a plastic packaging layer arranged on the substrate, where the plastic packaging layer surrounds the sensing chip and fills the groove, and a surface of the sensing area is exposed from the plastic packaging layer. | 2018-04-19 |
20180108586 | LEAD BONDING STRUCTURE - A lead bonding structure includes: a plurality of leads extending outward from a package; and a plurality of electrode pads formed on a circuit board. The plurality of leads are soldered to the electrode pads, respectively. Each of the leads includes a lower wide portion having a width dimension greater than a width dimension of each of the electrode pads. The lower wide portion of each of the leads is soldered to the corresponding electrode pad. | 2018-04-19 |
20180108587 | METHOD FOR PASSIVATING A SURFACE OF A SEMICONDUCTOR AND RELATED SYSTEMS - A system and a method for passivating a surface of a semiconductor. The method includes providing the surface of the semiconductor to a reaction chamber of a reactor, exposing the surface of the semiconductor to a gas-phase metal containing precursor in the reaction chamber and exposing the surface of the semiconductor to a gas-phase chalcogenide containing precursor. The methods also include passivating the surface of the semiconductor using the gas-phase metal containing precursor and the gas-phase chalcogenide containing precursor to form a passivated surface. The system for passivating a surface of a semiconductor may include a reactor, a metal containing precursor source fluidly coupled to the reactor, and a chalcogenide containing precursor source fluidly couple to the reactor, wherein the metal containing precursor source provides a gas-phase metal containing precursor to a reaction chamber of the reactor, and wherein the chalcogenide containing precursor source provides a gas-phase chalcogenide containing precursor to a reaction chamber of the reactor. | 2018-04-19 |
20180108588 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a semiconductor element formed in or on the semiconductor substrate, a metal layer connected to the semiconductor element, and a passivation film that protects the semiconductor element. The passivation film is formed by alternately stacking a first insulation film that has larger tensile stress and a second insulation film that has smaller tensile stress. Each of the first insulation film and the second insulation film is one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film. The passivation film as a whole generates tensile stress. | 2018-04-19 |
20180108589 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a semiconductor element formed in or on the semiconductor substrate, a metal layer connected to the semiconductor element, and a passivation film that protects the semiconductor element. The passivation film is formed by alternately stacking a first insulation film that generates compressive stress and has low density and a second insulation film that generates compressive stress and has high density. The first insulation film is disposed in a lowest layer of the passivation film, the lowest layer being nearest to the semiconductor substrate. Each of the first insulation film and the second insulation film is one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film. | 2018-04-19 |
20180108590 | Conductive Line System and Process - A system and method for providing a conductive line is provided. In an embodiment the conductive line is formed by forming two passivation layers, wherein each passivation layer is independently patterned. Once formed, a seed layer is deposited into the two passivation layers, and a conductive material is deposited to fill and overfill the patterns within the two passivation layers. A planarization process such as a chemical mechanical polish may then be utilized in order to remove excess conductive material and form the conductive lines within the two passivation layers. | 2018-04-19 |
20180108591 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor module and a cooler. The semiconductor device includes semiconductor element(s) within a molded resin and a heat sink plate exposed on the molded resin. The cooler includes a cooling plate located on the heat sink plate of the semiconductor module via thermal grease. The cooling plate includes a bimetal structure in which two layers having different linear expansion coefficients are laminated. The heat sink plate includes a first facing surface facing the cooling plate and the semiconductor module is configured to thermally expand such that the first facing surface displaces with respect to the cooling plate. The cooling plate includes a second facing surface facing the heat sink plate, and the bimetal structure is configured to thermally expand such that the second facing surface of the cooling plate displaces in a same direction as the first facing surface of the heat sink plate. | 2018-04-19 |
20180108592 | STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS AND MOLDED UNDERFILL - Semiconductor die assemblies having high efficiency thermal paths and molded underfill material. In one embodiment, a semiconductor die assembly comprises a first die and a plurality of second dies. The first die has a first functionality, a lateral region, and a stacking site. The second dies have a different functionality than the first die, and the second dies are in a die stack including a bottom second die mounted to the stacking site of the first die and a top second die defining a top surface of the die stack. A thermal transfer structure is attached to at least the lateral region of the first die and has a cavity in which the second dies are positioned. An underfill material is in the cavity between the second dies and the thermal transfer structure, and the underfill material covers the top surface of the die stack. | 2018-04-19 |
20180108593 | BONDED BODY, SUBSTRATE FOR POWER MODULE WITH HEAT SINK, HEAT SINK, METHOD FOR PRODUCING BONDED BODY, METHOD FOR PRODUCING SUBSTRATE FOR POWER MODULE WITH HEAT SINK, AND METHOD FOR PRODUCING HEAT SINK - A bonded body is provided that is formed by bonding a metal member formed from copper, nickel, or silver, and an aluminum alloy member formed from an aluminum alloy of which a solidus temperature is lower than a eutectic temperature of aluminum and a metal element that constitutes the metal member. The aluminum alloy member and the metal member are subjected to solid-phase diffusion bonding. A chill layer, in which a Si phase of which an aspect ratio of a crystal grain is 2.5 or less and a crystal grain diameter is 15 μm or less is dispersed, is formed on a bonding interface side with the metal member in the aluminum alloy member. The thickness of the chill layer is set to 50 μm or greater. | 2018-04-19 |
20180108594 | CARBON NANOTUBE STRUCTURE, HEAT DISSIPATION SHEET, AND METHOD OF MANUFACTURING CARBON NANOTUBE STRUCTURE - A carbon nanotube structure includes a plurality of carbon nanotubes, and a graphite film that binds one ends of the plurality of carbon nanotubes. And a heat dissipation sheet includes a plurality of carbon nanotube structures arranged in a sheet form, wherein each of the carbon nanotube structures includes a plurality of carbon nanotubes, and a graphite film that binds one ends of the plurality of carbon nanotubes. | 2018-04-19 |