16th week of 2011 patent applcation highlights part 3 |
Patent application number | Title | Published |
20110089449 | LIGHT EMITTING DIODE PACKAGE STRUCTURE - An LED package structure includes a house, an LED chip, a transparent cover, and a surrounding wall. The house has an upper surface, a cavity exposed by the upper surface, and a surrounding plane. The LED chip is disposed on the bottom surface of the cavity. The transparent cover is disposed on the surrounding plane and the opening of the cavity is sealed by the transparent cover. The surrounding wall is disposed on the upper surface of the house and surrounds the transparent cover. | 2011-04-21 |
20110089450 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor light-emitting device is provided. The semiconductor light-emitting device may include a light-emitting structure, an electrode, an ohmic layer, an electrode layer, an adhesion layer, and a channel layer. The light-emitting structure may include a compound semiconductor layer. The electrode may be disposed on the light-emitting structure. The ohmic layer may be disposed under the light-emitting structure. The electrode layer may include a reflective metal under the ohmic layer. The adhesion layer may be disposed under the electrode layer. The channel layer may be disposed along a bottom edge of the light-emitting structure. | 2011-04-21 |
20110089451 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor light-emitting device is provided that may include an electrode layer, a light-emitting structure including a compound semiconductor layer on the electrode layer, and an electrode on the light-emitting structure, wherein the electrode includes an ohmic contact layer that contacts the compound semiconductor layer, a first barrier layer on the ohmic contact layer, a conductive layer including copper on the first barrier layer, a second barrier layer on the conductive layer, and a bonding layer on the second barrier layer. | 2011-04-21 |
20110089452 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor light-emitting device is provided. The semiconductor light-emitting device may include a light-emitting structure, an electrode, a reflective layer, a conductive support member, and a channel layer. The light-emitting structure may include a plurality of compound semiconductor layers. The electrode may be disposed on the compound semiconductor layer. The reflective layer may be disposed under the compound semiconductor layer. The conductive support member may be disposed under the reflective layer. The channel layer may be disposed along a bottom edge of the compound semiconductor layer. | 2011-04-21 |
20110089453 | LIGHT EMITTING APPARATUS - Disclosed is a light emitting apparatus. The light emitting apparatus includes a package body; first and second electrodes; a light emitting device electrically connected to the first and second electrodes and including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer between the first and second conductive semiconductor layers; and a lens supported on the package body and at least a part of the lens including a reflective structure. The package body includes a first cavity, one ends of the first and second electrodes are exposed in the first cavity and other ends of the first and second electrodes are exposed at lateral sides of the package body, and a second cavity is formed at a predetermined portion of the first electrode exposed in the first cavity. | 2011-04-21 |
20110089454 | SURFACE-TEXTURED ENCAPSULATIONS FOR USE WITH LIGHT EMITTING DIODES - Surface-textured encapsulations for use with light emitting diodes. In an aspect, a light emitting diode apparatus is provided that includes a light emitting diode, and an encapsulation formed upon the light emitting diode and having a surface texture configured to extract light. In an aspect, a method includes encapsulating a light emitting diode with an encapsulation having a surface texture configured to extract light. In an aspect, a light emitting diode lamp is provided that includes a package, at least one light emitting diode disposed within the package, and an encapsulation formed upon the at least one light emitting diode having a surface texture configured to extract light. In another aspect, a method includes determining one or more regions of an encapsulation, the encapsulation configured to cover a light emitting diode, and surface-texturing each region of the encapsulation with one or more geometric features that are configured to extract light. | 2011-04-21 |
20110089455 | OPTICAL DESIGNS FOR HIGH-EFFICACY WHITE-LIGHT EMITTING DIODES - A method for increasing the luminous efficacy of a white light emitting diode (WLED), comprising introducing optically functional interfaces between an LED die and a phosphor, and between the phosphor and an outer medium, wherein at least one of the interfaces between the phosphor and the LED die provides a reflectance for light emitted by the phosphor away from the outer medium and a transmittance for light emitted by the LED die. Thus, a WLED may comprise a first material which surrounds an LED die, a phosphor layer, and at least one additional layer or material which is transparent for direct LED emission and reflective for the phosphor emission, placed between the phosphor layer and the first material which surrounds the LED die. | 2011-04-21 |
20110089456 | SEMICONDUCTOR LIGHT EMITTING DEVICES WITH APPLIED WAVELENGTH CONVERSION MATERIALS AND METHODS FOR FORMING THE SAME - A semiconductor structure includes an active region configured to emit light upon the application of a voltage thereto, a window layer configured to receive the light emitted by the active region, and a plurality of discrete phosphor-containing regions on the window layer and configured to receive light emitted by the active region and to convert at least a portion of the received light to a different wavelength than a wavelength of light emitted by the active region. Methods of forming a semiconductor structure including an active region configured to emit light and a window layer include forming a plurality of discrete phosphor-containing regions on the window layer. | 2011-04-21 |
20110089457 | SURFACE-TEXTURED ENCAPSULATIONS FOR USE WITH LIGHT EMITTING DIODES - Surface-textured encapsulations for use with light emitting diodes. In an aspect, a light emitting diode apparatus is provided that includes a light emitting diode, and an encapsulation formed upon the light emitting diode and having a surface texture configured to extract light. In an aspect, a method includes encapsulating a light emitting diode with an encapsulation having a surface texture configured to extract light. In an aspect, a light emitting diode lamp is provided that includes a package, at least one light emitting diode disposed within the package, and an encapsulation formed upon the at least one light emitting diode having a surface texture configured to extract light. In another aspect, a method includes determining one or more regions of an encapsulation, the encapsulation configured to cover a light emitting diode, and surface-texturing each region of the encapsulation with one or more geometric features that are configured to extract light. | 2011-04-21 |
20110089458 | Light Emitting Device and Method for Manufacturing a Light Emitting Device - A light emitting device and a method for manufacturing a light emitting device, wherein the light emitting device comprises a light emitting diode (LED) emitting light in a first emission spectrum, and a composition comprising at least two components and being adapted to absorb at least a part of the light in the first emission spectrum and upon absorption to emit an up-converted light in a second emission spectrum, wherein the light in said second emission spectrum has a wavelength range lower than the wavelength range of the light in the first emission spectrum, whereby the light emitted by the light emitting device comprises a mixture at least of light in the first emission spectrum and of light in the second emission spectrum. | 2011-04-21 |
20110089459 | OPTOELECTRONIC APPARATUS - An optoelectronic apparatus includes an optical device with an optical structure including a plurality of optical elements, and a radiation-emitting or radiation-receiving semiconductor chip with a contact structure which includes a plurality of contact elements that make electrical contact with the semiconductor chip and are spaced apart vertically from the optical structure, wherein the contact elements are arranged in interspaces between the optical elements upon a projection of the contact structure into the plane of the optical structure. | 2011-04-21 |
20110089460 | LIGHT EMITTING DIODE ASSEMBLY - An electronic assembly includes a Light Emitting Diode (LED) mounted on a top surface of a heat spreader, at least two electrical contacts co-planar with the heat spreader, and at least one heat slug mounted on the top surface of the heat spreader, where the heat slug is made of high thermal conductive plastic. | 2011-04-21 |
20110089461 | LED package structure and manufacturing process thereof - A process for manufacturing an LED package structure includes the following steps: (A) providing a T-shaped heat-sink block and an integral material sheet, wherein the T-shaped heat-sink block includes a base portion and a rise portion extending from the base portion, and wherein the integral material sheet includes a side frame and a pair of electrode lead frames extending, respectively, from two opposite internal sides of the side frame; (B) forming an insulating layer on an upper surface of the base portion; (C) disposing the electrode lead frames on the insulating layer; and (D) forming an insulating outer frame around the T-shaped heat-sink block, wherein the insulating layer is enveloped in the insulating outer frame, and part of the base portion of the heat-sink block exposes out of the insulating outer frame. As a result, the LED package structure can improve voltage resistance and insulation. | 2011-04-21 |
20110089462 | METHOD FOR LOW TEMPERATURE BONDING OF ELECTRONIC COMPONENTS - A method for bonding an LED assembly ( | 2011-04-21 |
20110089463 | Light Source - Light sources are disclosed herein. One embodiment comprises a substrate having a first surface and a second surface located opposite the first surface. At least one first electrically conductive layer is affixed to the first surface of the substrate and partially covering the first surface of the substrate. At least one second electrically conductive layer is affixed to the first surface of the substrate and partially covering the first surface of the substrate. A light emitter is affixed to the first surface of the substrate in an area not covered by either of the at least one first electrically conductive layer or the at least one second electrically conductive layer. The substrate may be thinner in the area where the light emitter is affixed than in the areas where the first and second electrically conductive layers are affixed. A heat sink may be attached to the second surface of the substrate. | 2011-04-21 |
20110089464 | LIGHT EMITTING DIODE PACKAGE AND METHOD OF FABRICATING THE SAME - A light emitting diode package includes a base having a first surface, an electrode portion attached to the base, a pair of inner electrodes disposed on the first surface, a pair of outer electrodes, a pair of conductive pillars, a light emitting diode die, and a cap layer. Each outer electrode includes an end surface section and a side surface section. The end surface sections are disposed, corresponding to the inner electrodes, on the second surface. Each side surface section extends onto the side surface of the electrode portion. The conductive pillar penetrates between the inner electrode and the outer electrode. The light emitting diode die is on the first surface, electrically connecting the inner electrode. The cap layer covers the light emitting diode die. | 2011-04-21 |
20110089465 | SEMICONDUCTOR CHIP ASSEMBLY WITH POST/BASE HEAT SPREADER WITH ESD PROTECTION LAYER - A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a post, a base, an ESD protection layer and an underlayer. The conductive trace includes a pad and a terminal. The semiconductor device is electrically connected to the conductive trace, electrically isolated from the underlayer and thermally connected to the heat spreader. The post extends upwardly from the base into an opening in the adhesive, the base extends laterally from the post and the ESD protection layer is sandwiched between the base and the underlayer. The conductive trace provides signal routing between the pad and the terminal. | 2011-04-21 |
20110089466 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes a substrate | 2011-04-21 |
20110089467 | OHMIC CONTACT OF III-V SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - Heavily doped epitaxial SiGe material or epitaxial In | 2011-04-21 |
20110089468 | HEMT Device and a Manufacturing of the HEMT Device - A HEMT device and a manufacturing of the HEMT device, the HEMT device includes: a buffer layer ( | 2011-04-21 |
20110089469 | Method for Manufacturing a Low Defect Interface Between a Dielectric and a III-V Compound - The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance. | 2011-04-21 |
20110089470 | SEMICONDUCTOR DEVICE HAVING LAYOUT OF LOGIC CELL AND INTERFACE CELL WITH UNIFICATION OF TRANSISTOR ORIENTATION - In a semiconductor device, a plurality of interface cells is disposed on four sides of an LSI chip in connection with a logic circuit area including a plurality of logic cells. Each interface cell may include four functional blocks which are vertically or horizontally aligned without being rotated, thus forming an I/O buffer. The left I/O buffer has a vertical layout in which functional blocks are vertically aligned, whilst the upper I/O buffer has a horizontal layout in which functional blocks are horizontally aligned. This makes it possible to fix the same length direction of gates of transistors with respect to both the functional blocks of I/O buffers and the logic cells, so that engineers do not need to consider characteristic variations of transistors due to positional differences of transistors when designing the circuitry of an LSI chip. | 2011-04-21 |
20110089471 | Demodulation Pixel Incorporating Majority Carrier Current, Buried Channel and High-Low Junction - A demodulation pixel improves the charge transport speed and sensitivity by exploiting two effects of charge transport in silicon in order to achieve the before-mentioned optimization. The first one is a transport method based on the CCD gate principle. However, this is not limited to CCD technology, but can be realized also in CMOS technology. The charge transport in a surface or even a buried channel close to the surface is highly efficient in terms of speed, sensitivity and low trapping noise. In addition, by activating a majority carrier current flowing through the substrate, another drift field is generated below the depleted CCD channel. This drift field is located deeply in the substrate, acting as an efficient separator for deeply photo-generated electron-hole pairs. Thus, another large amount of minority carriers is transported to the diffusion nodes at high speed and detected. | 2011-04-21 |
20110089472 | INTEGRATED MOS SENSOR HAVING TEMPERATURE SENSOR - A single chip wireless sensor comprises a microcontroller connected by a transmit/receive interface to a wireless antenna. The microcontroller is also connected to an 8 kB RAM, a USB interface, an RS232 interface, 64 kB flash memory, and a 32 kHz crystal. The device senses humidity and temperature, and a humidity sensor is connected by an 18 bit ΣΔ A-to-D converter to the microcontroller and a temperature sensor is connected by a 12 bit SAR A-to-D converter to the microcontroller. The device is an integrated chip manufactured in a single process in which both the electronics and sensor components are manufactured using standard CMOS processing techniques, applied to achieve both electronic and sensing components in an integrated process. | 2011-04-21 |
20110089473 | Method for improved mobility using hybrid orientation technology (HOT) in conjunction with selective epitaxy and related apparatus - A semiconductor apparatus includes a first substrate and a second substrate located over a first portion of the first substrate and separated from the first substrate by a buried layer. The semiconductor apparatus also includes an epitaxial layer located over a second portion of the first substrate and isolated from the second substrate. The semiconductor apparatus further includes a first transistor formed at least partially in the second substrate and a second transistor formed at least partially in or over the epitaxial layer. The second substrate and the epitaxial layer have bulk properties with different electron and hole mobilities. At least one of the transistors is configured to receive one or more signals of at least about 5V. The first substrate could have a first crystalline orientation, and the second substrate could have a second crystalline orientation. | 2011-04-21 |
20110089474 | SEMICONDUCTOR DEVICE INCLUDING MISFET AND ITS MANUFACTURE METHOD - An active region made of Si or SiGe is formed in a surface part of a substrate. A gate electrode is disposed over the active region. A gate insulating film is disposed between the gate electrode and the substrate. A source and a drain are formed in the surface part of the substrate on sides of the gate electrode. A surface of the active region under the gate electrode includes a slope surface being upward from a border of the active region toward an inner side of the active region. The slope surface has a crystal plane equivalent to ( | 2011-04-21 |
20110089475 | MEMORY DEVICE AND SEMICONDUCTOR DEVICE - A memory device capable of data writing at a time other than during manufacturing is provided by using a memory element including an organic material. In a memory cell, a third conductive film, an organic compound, and a fourth conductive film are stacked over a semiconductor film provided with an n-type impurity region and a p-type impurity region, and a pn-junction diode is serially connected to the memory element. A logic circuit for controlling the memory cell includes a thin film transistor. The memory cell and the logic circuit are manufactured over one substrate at the same time. The n-type impurity region and the p-type impurity region of the memory cell are manufactured at the same time as the impurity region of the thin film transistor. | 2011-04-21 |
20110089476 | Checkerboarded high-voltage vertical transistor layout - In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged. | 2011-04-21 |
20110089477 | NANOSTRUCTURED MOS CAPACITOR - The present invention provides nanostructured MOS capacitor that comprises a nanowire (2) at least partly enclosed by a dielectric layer (5) and a gate electrode (4) that encloses at least a portion of the dielectric layer (5). Preferably the nanowire (2) protrudes from a substrate (12). The gate electrode (4) defines a gated portion (7) of the nanowire (2), which is allowed to be fully depleted when a first predetermined voltage is applied to the gate electrode (4). A method for providing a variable capacitance in an electronic circuit by using such an nanostructured MOS capacitor is also provided. Thanks to the invention it is possible to provide a MOS capacitor having an increased capacitance modulation range. It is a further advantage of the invention to provide a MOS capacitor which has relatively low depletion capacitance compared to prior art MOS capacitances. | 2011-04-21 |
20110089478 | Semiconductor device and method for manufacturing the same - It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto. | 2011-04-21 |
20110089479 | SCALABLE FLASH EEPROM MEMORY CELL WITH FLOATING GATE SPACER WRAPPED BY CONTROL GATE AND METHOD OF MANUFACTURE - A polysilicon spacer as a floating gate of a Flash memory device. An advantage of such spacer structure is to reduce a cell size, which is desirable for state-of-the-art Flash memory technology. In a preferred embodiment, the floating gate can be self-aligned to a nearby and/or within a vicinity of the select gate of the cell select transistor. In a preferred embodiment, the present invention preserves a tunnel oxide layer after the removal, using dry etching, a polysilicon spacer structure on the drain side of the select transistor gate. More preferably, the present method provides for a certain amount of tunnel oxide to remain so as to prevent the active silicon area in the drain region of the memory cell from being etched by the dry etching gas. | 2011-04-21 |
20110089480 | MEMORY AND MANUFACTURING METHOD THEREOF - A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer. | 2011-04-21 |
20110089481 | MOS TRANSISTOR WITH ELEVATED GATE DRAIN CAPACITY - A MOS transistor having an increased gate-drain capacitance is described. One embodiment provides a drift zone of a first conduction type. At least one transistor cell has a body zone, a source zone separated from the drift zone by the body zone, and a gate electrode, which is arranged adjacent to the body zone and which is dielectrically insulated from the body zone by a gate dielectric. At least one compensation zone of the first conduction type is arranged in the drift zone. At least one feedback electrode is arranged at a distance from the body zone, which is dielectrically insulated from the drift zone by a feedback dielectric and which is electrically conductively connected to the gate electrode. | 2011-04-21 |
20110089482 | METHOD AND APPARATUS FOR CONTROLLING A CIRCUIT WITH A HIGH VOLTAGE SENSE DEVICE - A control circuit with a high voltage sense device. In one embodiment, a circuit includes a first transistor disposed in a first substrate having first, second and third terminals. A first terminal of the first transistor is coupled to an external voltage. A voltage provided at a third terminal of the first transistor is substantially proportional to a voltage between the first and second terminals of the first transistor when the voltage between the first and second terminals of the first transistor is less than a pinch-off voltage of the first transistor. The voltage provided at the third terminal of the first transistor is substantially constant and less than the voltage between the first and second terminals of the first transistor when the voltage between the first and second terminals of the first transistor is greater than the pinch-off voltage of the first transistor. The circuit also includes a control circuit disposed in the first substrate and coupled to the third terminal of the first transistor. The circuit further includes a second transistor disposed in a second substrate. A first terminal of the second transistor coupled to the external voltage. | 2011-04-21 |
20110089483 | METHOD OF FORMING A POWER SEMICONDUCTOR DEVICE AND POWER SEMICONDUCTOR DEVICE - A method of forming a power semiconductor device comprises forming a first semiconductor layer of a first conductivity type extending across the power semiconductor device; forming an epitaxial layer of the first conductivity type over the first semiconductor layer, the epitaxial layer having a doping concentration that increases from a first surface of the epitaxial layer towards the first semiconductor layer; forming a body region of a second conductivity type in the epitaxial layer extending from the first surface of the epitaxial layer into the epitaxial layer, wherein a junction between the body region and the epitaxial layer is at or substantially adjacent to a region of the epitaxial layer having a maximum doping concentration; and forming a gate region such that the gate region is adjacent at least a portion of the body region. In operation of the semiconductor device, the portion of the body region adjacent the gate region functions as a channel region of the semiconductor device. | 2011-04-21 |
20110089484 | METHOD AND SYSTEM FOR METAL GATE FORMATION WITH WIDER METAL GATE FILL MARGIN - A method includes providing a semiconductor substrate having a gate trench and depositing a metal layer, using a physical vapor deposition (PVD) process, over the substrate to partially fill the trench. The metal layer includes a bottom portion and a sidewall portion that is thinner than the bottom portion. The method also includes forming a coating layer on the metal layer, etching back the coating layer such that a portion of the coating layer protects a portion of the metal layer within the trench, and removing the unprotected portion of the metal layer. A different aspect involves a semiconductor device that includes a gate that includes a trench having a top surface, and a metal layer formed over the trench, wherein the metal layer includes a sidewall portion and a bottom portion, and wherein the sidewall portion is thinner than the bottom portion. | 2011-04-21 |
20110089485 | SPLIT GATE SEMICONDUCTOR DEVICE WITH CURVED GATE OXIDE PROFILE - A split gate semiconductor device includes a trench gate having a first electrode region and a second electrode region that are separated from each other by a gate oxide layer and an adjacent dielectric layer. The boundary of the gate oxide layer and the dielectric layer is curved to avoid a sharp corner where the gate oxide layer meets the sidewalls of the trench. | 2011-04-21 |
20110089486 | SUPER-HIGH DENSITY TRENCH MOSFET - A method, in one embodiment, can include forming a plurality of trenches in a body region for a vertical metal-oxide semiconductor field-effect transistor (MOSFET). In addition, the method can include angle implanting source regions into the body region. Furthermore, dielectric material can be grown within the plurality of trenches. Gate polysilicon can be deposited within the plurality of trenches. Moreover, the method can include chemical mechanical polishing the gate polysilicon. The method can also include etching back the gate polysilicon within the plurality of trenches. | 2011-04-21 |
20110089487 | SEMICONDUCTOR DEVICE - A semiconductor device includes a base layer that has a first conductivity type, a source layer that is formed on the base layer and has a second conductivity type, and an insulating film that is formed on the source layer. The semiconductor device further includes a plurality of gate structures that penetrate the base layer, and a plurality of conductive parts that penetrate the insulating film and the source layer and electrically connect the source layer and the base layer to each other. The gate structures are formed in a strip shape in plan view. Parts in which the conductive portion is connected to the base layer are formed in a stripe shape in plan view, and are formed between the gate structures. Further, a dimension of the part in which the source layer and the base layer are in contact with each other between the gate structure and the conductive portion is 0.36 μm or more. | 2011-04-21 |
20110089488 | Power Device with Improved Edge Termination - A field effect transistor includes an active region and a termination region surrounding the active region. A resistive element is coupled to the termination region, wherein upon occurrence of avalanche breakdown in the termination region an avalanche current starts to flow in the termination region, and the resistive element is configured to induce a portion of the avalanche current to flow through the termination region and a remaining portion of the avalanche current to flow through the active region. | 2011-04-21 |
20110089489 | Semiconductor device including capacitor element and method of manufacturing the same - A semiconductor device includes a memory region, and a logic region formed on a substrate, in which a trench recess is provided in the substrate in the memory region. A first transistor is provided in the memory region and a second transistor is provided in the logic region. The first transistor includes a first gate electrode. The first gate electrode is provided to be buried in the recess and to protrude to outside of the recess. The second transistor includes a second gate electrode having a same material as that of the first gate electrode. | 2011-04-21 |
20110089490 | Method for fabricating a MOS transistor with reduced channel length variation and related structure - According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor. | 2011-04-21 |
20110089491 | POWER MOS ELECTRONIC DEVICE AND CORRESPONDING REALIZING METHOD - Power MOS device of the type comprising a plurality of elementary power MOS transistors having respective gate structures and comprising a gate oxide with double thickness having a thick central part and lateral portions of reduced thickness. Such device exhibiting gate structures comprising first gate conductive portions overlapped onto said lateral portions of reduced thickness to define, for the elementary MOS transistors, the gate electrodes, as well as a conductive structure or mesh. Such conductive structure comprising a plurality of second conductive portions overlapped onto the thick central part of gate oxide and interconnected to each other and to the first gate conductive portions by means of a plurality of conducive bridges. | 2011-04-21 |
20110089492 | High voltage semiconductor device with JFET regions containing dielectrically isolated junctions and method of fabricating the same - A high-voltage field-effect device contains an extended drain or “drift” region including an embedded stack of JFET regions separated by intervening layers of the drift region. Each of the JFET regions is filled with material of an opposite conductivity type to that of the drift region, and the floor and ceiling of each JFET region is lined with an oxide layer. When the device is blocking a voltage in the off condition, the semiconductor material inside the JFET regions and in the drift region that separates the JFET regions is depleted. This improves the voltage-blocking ability of the device while conserving chip area. The oxide layer prevents dopant from the JFET regions from diffusing into the drift region. | 2011-04-21 |
20110089493 | FINFET METHOD AND DEVICE - A finFET structure is made by forming a fin ( | 2011-04-21 |
20110089494 | Semiconductor device having fuse and protection circuit - A semiconductor device having a semiconductor substrate, an insulating layer, a fuse, a diffusion layer and a resistor. The semiconductor substrate has a first conductivity type. The insulating layer is selectively formed on the surface of the semiconductor substrate. The fuse is formed on the insulating layer. The diffusion layer has a second conductivity type. The diffusion layer is formed on the surface of the semiconductor substrate and electrically connected to the fuse. The first resistor is electrically connected to the fuse. | 2011-04-21 |
20110089495 | APPLICATION OF CLUSTER BEAM IMPLANTATION FOR FABRICATING THRESHOLD VOLTAGE ADJUSTED FETS - Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step. | 2011-04-21 |
20110089496 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD - The object to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit is achieved by forming an inverter which comprises: a first transistor including; an first island-shaped semiconductor layer; a first gate insulating film; a gate electrode; a first first-conductive-type high-concentration semiconductor layer arranged above the first island-shaped semiconductor layer; and a second first-conductive-type high-concentration semiconductor layer arranged below the first island-shaped semiconductor layer, and a second transistor including; a second gate insulating film surrounding a part of the periphery of the gate electrode; a second semiconductor layer in contact with a part of the periphery of the second gate insulating film; a first second-conductive-type high-concentration semiconductor layer arranged above the second semiconductor layer; and a second second-conductive-type high-concentration semiconductor layer arranged below the second semiconductor layer. | 2011-04-21 |
20110089497 | SEMICONDUCTOR DEVICE HAVING NICKEL SILICIDE LAYER - A method for manufacturing a semiconductor device includes: forming an isolation region for defining a plurality of active regions in a silicon substrate; doping p-type impurities in at least one of the plurality of active regions to form a p-type well; forming an NMOS gate electrode traversing the p-type well via a gate insulating film; implanting n-type impurity ions into the p-type well on both sides of the NMOS gate electrode to form n-type extension regions; forming an NMOS gate side wall spacer on side walls of the NMOS gate electrode; implanting n-type impurity ions into the p-type well outside the NMOS gate side wall spacers to form n-type source/drain regions; forming a nickel silicide layer in surface regions of the n-type source/drain regions; and implanting Al ions the said n-type source/drain regions to dope Al in the nickel silicide layer surface regions. | 2011-04-21 |
20110089498 | INTEGRATION OF LOW AND HIGH VOLTAGE CMOS DEVICES - A method of fabricating a semiconductor device is provided that includes providing a semiconductor substrate having a first portion and a second portion, forming a first transistor in the first portion of the substrate, the first transistor being operable at a first voltage, and forming a second transistor in the second portion of the substrate, the second transistor being operable at a second voltage greater than the first voltage. The formation of the second transistor includes forming an extended feature of the second transistor with a photomask that is used to adjust a threshold voltage of the first transistor. | 2011-04-21 |
20110089499 | STRUCTURE AND METHOD FOR MANUFACTURING ASYMMETRIC DEVICES - A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures. | 2011-04-21 |
20110089500 | MULTI-GATE SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate, a source region formed over the substrate, a drain region formed over the substrate, a first gate electrode over the substrate adjacent to the source region and between the source and drain regions, and a second gate electrode over the substrate adjacent to the drain region and between the source and drain regions. | 2011-04-21 |
20110089501 | Tunable Stressed Polycrystalline Silicon on Dielectrics in an Integrated Circuit - A method of forming an integrated circuit device is disclosed. A polycrystalline silicon layer is formed in direct contact with a dielectric material so that the dielectric material induces a stress in the polycrystalline silicon layer as the polycrystalline silicon layer is formed. A MOS transistor that includes a gate comprising the polycrystalline silicon is then completed. | 2011-04-21 |
20110089502 | MULTI-LAYER GATE DIELECTRIC - A transistor gate dielectric including a first dielectric material having a first dielectric constant and a second dielectric material having a second dielectric constant different from the first dielectric constant. | 2011-04-21 |
20110089503 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE - To provide a semiconductor device prevented from giving a limitation on the sensitivity of HEMS devices due to isolation regions thereof and a method of fabricating the same. The semiconductor device includes: a semiconductor substrate with a recess portion formed in an upper surface; a supporting body provided around the recess portion on the semiconductor substrate; a beam-type movable portion which includes a movable electrode provided above the recess portion and is fixed to the supporting body at a position away from the movable electrode; a beam-type fixed electrode provided above the recess portion to be opposed to the movable electrode and fixed to the supporting body; and isolation regions each including a separation column made of a semiconductor and a separation insulating film provided on a side surface of the separation column, the isolation regions being provided between the movable electrode and the supporting body and between the fixed electrode and the supporting body to electrically separate the movable and fixed electrodes from the supporting body. | 2011-04-21 |
20110089504 | MEMS PROCESS AND DEVICE - A method of fabricating a micro-electrical-mechanical system (MEMS) transducer comprises the steps of forming a membrane ( | 2011-04-21 |
20110089505 | METHOD FOR MANUFACTURING A SENSOR COMPONENT WITHOUT PASSIVATION, AND A SENSOR COMPONENT - A sensor component and a method for manufacturing a sensor component, in which a sealing passivation of a sensor layer may be dispensed with. For this purpose, the sensor component includes, in particular, a thin film high-pressure sensor, a deformation body and a piezoresistive sensor layer, which is applied to the deformation body, the piezoresistive sensor layer including at least one metal as well as carbon and/or hydrocarbon and terminating the layer structure of the sensor component. Based on the materials used a sealing cover of the sensor layer by a thin film passivation layer may be dispensed with. Additional contact layers for contacting the sensor layer may advantageously also be dispensed with. Contacting may then take place directly on the sensor layer, using a bond wire. | 2011-04-21 |
20110089506 | INTRUSION PROTECTION USING STRESS CHANGES - The invention relates to a integrated circuit comprising an electronic circuit integrated on a substrate ( | 2011-04-21 |
20110089507 | Novel bit line preparation method in MRAM fabrication - A MRAM structure is disclosed that includes a metal contact bridge (MCB) which provides an electrical connection between a MTJ top electrode and an overlying bit line. The MCB has a width greater than a MTJ top electrode and serves as an etch stop during bit line etching to prevent sub-trenches from forming adjacent to the top electrode and causing shorts. MCBs also prevent insufficient etching that causes open circuits. A MCB is preferably a metal, metal compound, or alloy such as Ta with low resistivity and high conductivity. The MCB layer is patterned prior to using a dual damascene process to form a bit line contacting each MCB and a bit line pad connection to a word line pad. MCB thickness is thin enough to allow a strong bit line magnetic field for switching a free layer and large enough to function as an efficient oxide etch stop. | 2011-04-21 |
20110089508 | MAGNETIC TUNNEL JUNCTION STRUCTURE WITH PERPENDICULAR MAGNETIZATION LAYERS - Disclosed is a magnetic tunnel junction structure having perpendicular anisotropic free layers, and it could be accomplished to reduce a critical current value required for switching and maintain thermal stability even if a device is fabricated small in size, by maintaining the magnetization directions of the free magnetic layer and the fixed magnetic layer constituting the magnetic tunnel junction structure perpendicular to each other. | 2011-04-21 |
20110089509 | MAGNETIC MEMORY WITH SEPARATE READ AND WRITE PATHS - Magnetic memory having separate read and write paths is disclosed. The magnetic memory unit includes a ferromagnetic strip having a first end portion with a first magnetization orientation, an opposing second end portion with a second magnetization orientation, and a middle portion between the first end portion and the second end portion, the middle portion having a free magnetization orientation. The first magnetization orientation opposes the second magnetization orientation. A tunneling barrier separates a magnetic reference layer from the middle portion forming a magnetic tunnel junction. A bit line is electrically coupled to the second end portion. A source line is electrically coupled to the first end portion and a read line is electrically coupled to the magnetic tunnel junction. | 2011-04-21 |
20110089510 | MAGNETIC MEMORY CELL CONSTRUCTION - A magnetic tunnel junction cell having a free layer, a ferromagnetic pinned layer, and a barrier layer therebetween. The free layer has a central ferromagnetic portion and a stabilizing portion radially proximate the central ferromagnetic portion. The construction can be used for both in-plane magnetic memory cells where the magnetization orientation of the magnetic layer is in the stack film plane and out-of-plane magnetic memory cells where the magnetization orientation of the magnetic layer is out of the stack film plane, e.g., perpendicular to the stack plane. | 2011-04-21 |
20110089511 | Magnetic Random Access Memory (MRAM) Manufacturing Process for a Small Magnetic Tunnel Junction (MTJ) Design with a Low Programming Current Requirement - A method of making a magnetic random access memory cell includes forming a magnetic tunnel junction (MTJ) on top of a wafer, depositing oxide on top of the MTJ, depositing a photo-resist layer on top of the oxide layer, forming a trench in the photo-resist layer and oxide layer where the trench has a width that is substantially the same as that of the MTJ. Then, the photo-resist layer is removed and a hard mask layer is deposited on top of the oxide layer in the trench and the wafer is planarized to remove the portion of the hard mask layer that is not in the trench to substantially level the top of oxide layer and the hard layer on the wafer. The remaining oxide layer is etched and the the MTJ is etched to remove the portion of the MTJ which is not covered by the hard mask layer. | 2011-04-21 |
20110089512 | MAGNETO-IMPEDANCE SENSOR ELEMENT - A magneto-impedance sensor element 1 has a base body 2, a magnetic amorphous wire 3, a coating insulator 4, a detecting coil 5, a terminal base 6 having a terminal mounting surface 61, wire electrode terminals 11 and coil electrode terminals 12 formed on the terminal mounting surface 61, wire connecting wirings 110 for electrically connecting the wire electrode terminals 11 and a pair of wire conducting terminals 31 provided to the magnetic amorphous wire 3, and coil connecting wirings 120 for electrically connecting the coil electrode terminals 12 and a pair of coil conducting terminals 51 provided to the detecting coil 5. A normal of the terminal mounting surface 61 has a longitudinal direction component of the magnetic amorphous wire 3, and the terminal mounting surface 61 is arranged between both ends of the magnetic amorphous wire 3 in the longitudinal direction of the magnetic amorphous wire 3. | 2011-04-21 |
20110089513 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device has an active region formed on a semiconductor substrate, a trench-type element isolation region formed on the semiconductor substrate, and a diffusion region in which fluorine is diffused that surrounds the element isolation region and is formed on the semiconductor substrate so as not to contact the active region. | 2011-04-21 |
20110089514 | COLOR-OPTIMIZED IMAGE SENSOR - An image sensor pixel array includes a photoelectric conversion unit comprising a second region in a substrate and vertically below a gate electrode of a transistor. A first region under a top surface of the substrate and above the second region supports a channel of the transistor. A color filter transmits a light via a light guide, the gate electrode and the first region to generate carriers collected by the second region. The gate electrode may be made thinner by a wet etch. An etchant for thinning the gate electrode may be introduced through an opening in an insulating film on the substrate. The light guide may be formed in the opening after the thinning. An anti-reflection stack may be formed at a bottom of the opening prior to forming the light guide. | 2011-04-21 |
20110089515 | SEMICONDUCTOR LIGHT RECEIVING DEVICE - A semiconductor light receiving device includes: a first semiconductor light receiving element that is provided on a semiconductor substrate and has a mesa structure having an upper electrode to be coupled to an electrode wiring of a mounting carrier and a lower electrode; a first mesa that is provided on the semiconductor substrate and has an upper electrode coupled electrically to a lower electrode of the first semiconductor light receiving element with a wiring provided on the semiconductor substrate; and a second mesa that is provided on the semiconductor substrate and has an upper electrode that has a same electrical potential as the upper electrode of the first semiconductor light receiving element when coupled to the electrode wiring on the mounting carrier. | 2011-04-21 |
20110089516 | RECTIFIER - Provided is a rectifier such as a detector in which a cutoff frequency may be increased in a view point different from the reduction in size of the structure. The rectifier includes: a Schottky barrier portion including a Schottky electrode; a barrier portion having a rectifying property with respect to a majority carrier in the Schottky barrier portion; and an ohmic electrode in electrical contact with the barrier portion having the rectifying property, in which each of the Schottky barrier portion and the barrier portion having the rectifying property has an asymmetrical band profile whose gradient on one side is larger than a gradient of another side, and the Schottky barrier portion and the barrier portion having the rectifying property are connected to each other so that the steep gradient side of the band profile is located on a side of the Schottky electrode. | 2011-04-21 |
20110089517 | CMOS IMAGE SENSOR WITH HEAT MANAGEMENT STRUCTURES - An image sensor includes a device wafer substrate of a device wafer, a device layer of the device wafer, and optionally a heat control structure and/or a heat sink. The device layer is disposed on a frontside of the device wafer substrate and includes a plurality of photosensitive elements disposed within a pixel array region and peripheral circuitry disposed within a peripheral circuits region. The photosensitive elements are sensitive to light incident on a backside of the device wafer substrate. The heat control structure is disposed within the device wafer substrate and thermally isolates the pixel array region from the peripheral circuits region to reduce heat transfer between the peripheral circuits region and the pixel array region. The heat sink conducts heat away from the device layer. | 2011-04-21 |
20110089518 | Array of concentric CMOS photodiodes for detection and de-multiplexing of spatially modulated optical channels - An octagonal structure of photodiodes using standard CMOS technology has been developed to serve as a de-multiplexer for spatially multiplexed fiber optic communication systems. | 2011-04-21 |
20110089519 | Chip Lead Frame and Photoelectric Energy Transducing Module - The invention discloses a chip lead frame and a photoelectric energy transducing module. The chip lead frame includes an insulator and a plurality of conductors. The insulator includes a first surface, a second surface, a first recess structure formed on the first surface, a through hole passing through the second surface and the first recess structure, and a venting structure. The first recess structure forms an accommodating space. The venting structure communicates with the accommodating space so that when a substrate is being bound to the first recess structure, the air in the accommodating space pressed by the substrate could flow through the venting structure out of the insulator without remaining between the substrate and the first recess structure. A photoelectric energy transducing semiconductor structure could be disposed on the substrate and electrically connected to the conductors, so as to form the photoelectric energy transducing module of the invention. | 2011-04-21 |
20110089520 | GROWTH OF MONOCRYSTALLINE GeN ON A SUBSTRATE - The present invention relates a method for forming a monocrystalline GeN layer ( | 2011-04-21 |
20110089521 | Electronic Device and Method For Manufacturing Thereof - An electronic device, including a substrate, a functional structure constituting a functional element formed on the substrate, and a cover structure forming a cavity portion in which the functional structure is disposed, is disclosed. In the electronic device, the cover structure includes a laminated structure of an interlayer insulating film and a wiring layer, the laminated structure being formed on the substrate in such a way that it surrounds the cavity portion, and the cover structure has an upside cover portion covering the cavity portion from above, the upside cover portion being formed with part of the wiring layer that is disposed above the functional structure. | 2011-04-21 |
20110089522 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor wafer has a main surface. A main chip region is formed on the main surface. A sub-chip region is smaller in area than the main chip region, and positioned on an edge side of the semiconductor wafer relative to the main chip region. The sub-chip region is identical to the main chip region in design pattern. Accordingly, a semiconductor device in which occurrence of a pattern failure at the edge of the wafer can be prevented when chips are arranged in the surface of the semiconductor wafer and a method of manufacturing the same can be obtained. | 2011-04-21 |
20110089523 | SYSTEMS AND PROCESSES FOR FORMING THREE-DIMENSIONAL CIRCUITS - Provided are systems and processes for forming a three-dimensional circuit on a substrate. A radiation source produces a beam that is directed at a substrate having an isolating layer interposed between circuit layers. The circuit layers communicate with reach other via a seed region exhibiting a crystalline surface. At least one circuit layer has an initial microstructure that exhibits electronic properties unsuitable for forming circuit features therein. After being controllably heat treated, the initial microstructure of the circuit layer having unsuitable properties is transformed into one that exhibits electronic properties suitable for forming circuit feature therein. Also provided are three-dimensional circuit structures optionally formed by the inventive systems and/or processes. | 2011-04-21 |
20110089524 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same capable of reducing variations in the thickness of a semiconductor device are provided. The amount of oxygen implanted ions is less than the amount of implanted oxygen ions in the conventional epitaxial SIMOX wafers. Oxygen is ion-implanted into the surface layer of a silicon wafer from the surface of the wafer. Then, by heat treating the wafer, a thinning stop layer, which is an imperfect buried oxide film, is formed along the entire plane of the wafer. As a result, variation of the thickness of the semiconductor device formed in an active layer can be reduced, since the, the reliability of the accuracy of the end point of silicon wafer thinning is higher than that of a thinning using the conventional deep trench structure as an end point detector. | 2011-04-21 |
20110089525 | Manufacturing method for semiconductor device and semiconductor device - A trench is formed on a semiconductor substrate with a first insulation film patterned on the semiconductor substrate as a mask; a second insulation film is embedded in the trench and flattened; an upper portion of the first insulation film is selectively removed, and a part of a side face of the second insulation film is exposed; a part of the second insulation film is isotropically removed; a lower portion of the remaining first insulation film is selectively removed; and then a part of the remaining second insulation film is further isotropically removed so that an upper face of the second insulation film is at a predetermined height from a surface of the semiconductor substrate, a taper having a minimum taper angle of 90° or more is formed on the side face of the second insulation film, and a STI is formed. | 2011-04-21 |
20110089526 | Integrated Circuit with Multi Recessed Shallow Trench Isolation - A system and method for forming multi recessed shallow trench isolation structures on substrate of an integrated circuit is provided. An integrated circuit includes a substrate, at least two shallow trench isolation (STI) structures formed in the substrate, an oxide fill disposed in the at least two STI structures, and semiconductor devices disposed on the oxide fill in the at least two STI structures. A first STI structure is formed to a first depth and a second STI structure is formed to a second depth. The oxide fill fills the at least two STI structures, and the first depth and the second depth are based on semiconductor device characteristics of semiconductor devices disposed thereon. | 2011-04-21 |
20110089527 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING - A semiconductor and method for manufacturing a semiconductor device. In one embodiment the method includes providing a semiconductor substrate with a first substrate surface and at least one trench having at least one trench surface. The trench extends from the first substrate surface into the semiconductor substrate. The trench has a first trench section and a second trench section. The trench surface is exposed in an upper portion of the first and second trench sections and covered with a first insulating layer in a lower portion. A second insulating layer is formed at least on the exposed trench surface in the upper portion. A conductive layer is formed on the second insulating layer at least in the upper portion, wherein the second insulating layer electrically insulates the conductive layer from the semiconductor substrate. The conductive layer is removed in the first trench section without removing the conductive layer in the second trench section. | 2011-04-21 |
20110089528 | SEMICONDUCTOR HAVING OPTIMIZED INSULATION STRUCTURE AND PROCESS FOR PRODUCING THE SEMICONDUCTOR - A semiconductor having an optimized insulation structure which is simple and inexpensive to produce and can be made smaller than LOCOS insulation structures is disclosed. An implantation mask on a surface of a semiconductor substrate is used to implant elements into the semiconductor substrate, which elements, on thermal activation, form an insulation region together with the further elements of the semiconductor substrate. The thermal activation is effected by means of laser irradiation, during which the semiconductor substrate is briefly melted and then recrystallizes during the subsequent cooling, so that the implanted elements form the insulation region together with the further elements of the semiconductor substrate. | 2011-04-21 |
20110089529 | Open Cavity Leadless Surface Mountable Package for High Power RF Applications - An RF semiconductor package includes a substrate having generally planar top and bottom surfaces. The substrate includes a metallic base region and one or more metallic signal terminal regions extending from the top surface to the bottom surface, and an insulative material separating the metallic regions from one another. The bottom surface of an RF semiconductor die is surface-mounted to the base region at the top substrate surface. The RF semiconductor die has a terminal pad disposed at a top surface of the RF semiconductor die. The terminal pad is electrically connected to one of the signal terminal regions at the top substrate surface. A lid is attached to the top substrate surface so that the RF semiconductor die is enclosed by the lid to form an open-cavity around the RF semiconductor die. The base and signal terminal regions are configured for surface-mounting at the bottom substrate surface. | 2011-04-21 |
20110089530 | Semiconductor Device - This application relates to a semiconductor device comprising a first chip comprising a first electrode on a first face of the first chip, and a second chip attached to the first electrode, wherein the second chip comprises a transformer comprising a first winding and a second winding. | 2011-04-21 |
20110089531 | Interposer Based Monolithic Microwave Integrate Circuit (iMMIC) - A system is disclosed for IC fabrication, including seating an integrated circuit (“IC”) having at least one contact into a recess of a silicon interposer substrate, applying an insulator in liquid form to fill portions of the recess not otherwise occupied by the IC and to cover a top surface of the IC and the silicon interposer substrate, introducing the insulator to a ramped environmental temperature, holding the environmental temperature at a reflow temperature to reflow the insulator and ramping down the environmental temperature to cure the insulator. | 2011-04-21 |
20110089532 | INTEGRATED CIRCUIT WITH ESD STRUCTURE - An integrated circuit includes a semiconductor body of a first conductivity type. The semiconductor body includes a first semiconductor zone of a second conductivity type opposite the first conductivity type. The first semiconductor zone extends to a surface of the semiconductor body. A second semiconductor zone of the first conductivity type is embedded in the first semiconductor zone and extends as far as the surface. A third semiconductor zone of the second conductivity type at least partly projects from the first semiconductor zone along a lateral direction running parallel to the surface. A contact structure provides an electrical contact with the first and second semiconductor zones at the surface. The second semiconductor zone is arranged, along the lateral direction, between the part of the third semiconductor zone which projects from the first semiconductor zone and a part of the contact structure in contact with the first semiconductor zone. | 2011-04-21 |
20110089533 | SEMICONDUCTOR DEVICE - An active barrier structure has a p-type region and an n-type region, each of which is in contact with a p-type impurity region and which are ohmic-connected to each other to attain a floating potential. A trench isolation structure is formed between an active barrier region and the other region (an output transistor formation region and a control circuit formation region). The trench isolation structure has a trench extending from the main surface of the semiconductor substrate through then epitaxial layer to reach the p-type impurity region. Therefore, a semiconductor device is obtained which allows the chip size to be reduced easily and is highly effective in preventing movement of electrons from the output transistor formation region to the other element formation region. | 2011-04-21 |
20110089534 | Semiconductor Integrated Circuit Devices Having Conductive Patterns that are Electrically Connected to Junction Regions - A semiconductor integrated circuit device includes a semiconductor substrate; a dummy pattern extending in one direction on the semiconductor substrate; a junction region electrically connecting the dummy pattern to the semiconductor substrate; and a voltage applying unit that is configured to apply a bias voltage to the dummy pattern. | 2011-04-21 |
20110089535 | Electrostatic Discharge Protection Device - The invention provides an electrostatic discharge (ESD) protection device having an ESD path between a first circuit and a second circuit. The electrostatic discharge protection device includes a first doped region having a first conductive type. A first well has a second conductive type opposite to the first conductive type. A second doped region and a third doped region are in the first well, respectively having the first and second conductive types. The first doped region is coupled to a power supply terminal or a ground terminal of the first circuit, and the second and third doped regions are both coupled to a power supply terminal or a ground terminal of the second circuit, respectively. | 2011-04-21 |
20110089536 | ORIENTATION OF ELECTRONIC DEVICES ON MIS-CUT SUBSTRATES - A microelectronic assembly in which a semiconductor device structure is directionally positioned on an off-axis substrate. In an illustrative implementation, a laser diode is oriented on a GaN substrate wherein the GaN substrate includes a GaN (0001) surface off-cut from the <0001> direction predominantly towards either the <11 | 2011-04-21 |
20110089537 | GROWING PROCESS FOR GROUP III NITRIDE ELEMENTS - The disclosure relates to a method for growing an element III nitride, wherein the growth is carried out on a substrate made of a material capable of maintaining the same crystalline structure from the element III nitride growth temperature to room temperature, the substrate being an M-V—O | 2011-04-21 |
20110089538 | LOW ETCH PIT DENSITY (EPD) SEMI-INSULATING III-V WAFERS - Systems and methods of manufacturing wafers are disclosed using a low EPD crystal growth process and a wafer annealing process are provided resulting in III-V/GaAs wafers that provide higher device yields from the wafer. In one exemplary implementation, there is provided a method of manufacturing a group III based material with a low etch pit density (EPD). Moreover, the method includes forming polycrystalline group III based compounds, and performing vertical gradient freeze crystal growth using the polycrystalline group III based compounds. Other exemplary implementations may include controlling temperature gradient(s) during formation of the group III based crystal to provide very low etch pit density. | 2011-04-21 |
20110089539 | PACKAGED MICROELECTRONIC IMAGERS AND METHODS OF PACKAGING MICROELECTRONIC IMAGERS - Methods for forming electrically conductive through-wafer interconnects in microelectronic devices and microelectronic devices are disclosed herein. In one embodiment, a microelectronic device can include a monolithic microelectronic substrate with an integrated circuit has a front side with integrated circuit interconnects thereon. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, first and second conductive layers deposited onto at least a portion of the dielectric liner, and a conductive fill material deposited into the passage over at least a portion of the second conductive layer and electrically coupled to the bond-pad. | 2011-04-21 |
20110089540 | SEMICONDUCTOR DIE WITH INTEGRATED ELECTRO-STATIC DISCHARGE DEVICE - A semiconductor die is described. This semiconductor die includes an electro-static discharge (ESD) device with a metal component coupled to an input-output (I/O) pad, and coupled to a ground voltage via a signal line. Moreover, adjacent edges of the metal component and the I/O pad are separated by a spacing that defines an ESD gap. When a field-emission or ionization current flows across the ESD gap, the metal component provides a discharge path to the ground voltage for transient ESD signals. Furthermore, the ESD gap is at least partially enclosed so that there is gas in the ESD gap. | 2011-04-21 |
20110089541 | Area reduction for electrical diode chips - Using electrical printing technologies to form package level conductor leads for electrical diode circuit, the preferred embodiments of the present invention significantly reduces the areas of surface mount electrical diodes or ESD circuits. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance. Additional cost reduction can be achieved by using none-crystalline semiconductor electrical diodes. | 2011-04-21 |
20110089542 | Area reduction for electrical diode chips - Using electrical printing technologies to form package level conductor leads for electrical diode circuit, the preferred embodiments of the present invention significantly reduces the areas of surface mount electrical diodes or ESD circuits. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance. Additional cost reduction can be achieved by using none-crystalline semiconductor electrical diodes. | 2011-04-21 |
20110089543 | SEMICONDUCTOR DEVICE WITH A BALUN - A semiconductor integrated circuit device with a balun which is formed above a conductive semiconductor substrate and which includes a dielectric film, an unbalanced line for transmitting an unbalanced signal, and balanced lines for transmitting a balanced signal. The unbalanced line is placed opposite to the balanced lines via a nano-composite film that is a region of the dielectric film. The nano-composite film, interposed between the unbalanced line and the balanced lines, has a relative permittivity higher than that of other regions of the dielectric film. This allows suppression of electromagnetic coupling of transmission lines or passive elements other than the balun, thereby providing a semiconductor device with a wide-band and small-size balun. | 2011-04-21 |
20110089544 | PACKAGE, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE - A package for mounting a semiconductor chip is provided. The package includes a frame member including an aperture, a first lead including a portion connectable to the semiconductor chip and a portion projecting outside from an outer sidewall of the frame member, and a second lead including a portion connectable to the semiconductor chip and a portion projecting inside the aperture from an inner sidewall of the frame member. | 2011-04-21 |
20110089545 | APPARATUS AND METHOD CONFIGURED TO LOWER THERMAL STRESSES - An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a lead frame and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the lead frame. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range. | 2011-04-21 |
20110089546 | MULTIPLE LEADFRAME PACKAGE - Apparatuses and methods directed to a semiconductor chip package having multiple leadframes are disclosed. Packages can include a first leadframe having a die attach pad and a first plurality of electrical leads, a second leadframe that is generally parallel to the first leadframe and having a second plurality of electrical leads, and a plurality of direct electrical connectors between the first and second leadframes, where such direct electrical connectors control the distance between the leadframes. Additional device components can include a primary die, an encapsulant, a secondary die, an inductor and/or a capacitor. The plurality of direct electrical connectors can comprise polymer balls having solder disposed thereabout. Alternatively, the direct electrical connectors can comprise metal tabs that extend from one leadframe to the other. The first and second leadframes can be substantially stacked atop one another, and one or both leadframes can be leadless leadframes. | 2011-04-21 |
20110089547 | METHODS AND DEVICES FOR MANUFACTURING CANTILEVER LEADS IN A SEMICONDUCTOR PACKAGE - A method of manufacturing a semiconductor package includes providing a metallic leadframe having a plurality of cantilever leads and a mounting area for mounting a die, and disposing one or more non-conductive supports adjacent to a recessed surface of the cantilever leads to support the leads during die mount, wire bond, and encapsulation processes. The method further includes mounting the die in the mounting area and electrically connecting the die to the cantilever leads, and then encapsulating at least a portion of the die, the leadframe, and the supports with an encapsulant. | 2011-04-21 |
20110089548 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - There are constituted by a tab ( | 2011-04-21 |