16th week of 2016 patent applcation highlights part 56 |
Patent application number | Title | Published |
20160111531 | Semiconductor Devices Including Channel Regions with Varying Widths - A semiconductor device includes a semiconductor substrate, a fin-type structure on the semiconductor substrate, and a gate on a portion of a top surface and portions of two side surfaces of the fin-type structure. The gate has a first width at a first level from the top surface of the substrate and a second width at a second level from the top surface of the substrate that is lower than the first level. The first width is greater than the second width, and a width of the gate is reduced from the first width to the second width between the first level and the second level. | 2016-04-21 |
20160111532 | SOURCE/DRAIN CONTACTS FOR NON-PLANAR TRANSISTORS - The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure. | 2016-04-21 |
20160111533 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide (SiC) semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) and integrated with an anti-parallelly connected Schottky diode includes: an n-type substrate, an n-type drift layer, a plurality of doped regions, a gate dielectric layer, a gate electrode, an inter-layer dielectric layer, a plurality of source openings, a plurality of junction openings, a plurality of gate openings, a first metal layer and a second metal layer. The second metal layer at the junction openings forms the Schottky diode. | 2016-04-21 |
20160111534 | DUAL GATE FD-SOI TRANSISTOR - Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (FD-SOI) technology. Lowering the threshold voltages of the transistors can be accomplished through dynamic secondary gate control in which a back-biasing technique is used to operate the dual gate FD-SOI transistors with enhanced switching performance. Consequently, such transistors can operate at very low core voltage supply levels, down to as low as about 0.4 V, which allows the transistors to respond quickly and to switch at higher speeds. Performance improvements are shown in circuit simulations of an inverter, an amplifier, a level shifter, and a voltage detection circuit module. | 2016-04-21 |
20160111535 | SEMICONDUCTOR DEVICE WITH ONE-SIDE-CONTACT AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench. | 2016-04-21 |
20160111536 | SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF - Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device including receiving a FinFET precursor including a fin structure formed between isolation regions, and a gate structure formed over a portion of the fin structure such that a sidewall of the fin structure is in contact with a gate spacer of the gate structure; patterning the fin structure to comprise a pattern of at least one upward step rising from the isolation region; forming a capping layer over the fin structure, the isolation region, and the gate structure; performing an annealing process on the FinFET precursor to form at least two dislocations along the upward step; and removing the capping layer. | 2016-04-21 |
20160111537 | CONTACT RESISTANCE REDUCTION TECHNIQUE - An embodiment is a method of manufacturing a semiconductor device, the method including forming a first gate over a substrate, forming a recess in the substrate adjacent the first gate, epitaxially forming a strained material stack in the recess, the strained material stack comprising at least three layers, each of the at least three layers comprising a dopant. The method further includes co-implanting the strained material stack with dopants comprising boron, germanium, indium, tin, or a combination thereof, forming a metal layer on the strained material stack, and annealing the metal layer and the strained material stack forming a metal-silicide layer. | 2016-04-21 |
20160111538 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region. | 2016-04-21 |
20160111539 | HIGH MOBILITY PMOS AND NMOS DEVICES HAVING Si-Ge QUANTUM WELLS - At least one method, apparatus and system disclosed involves semiconductor base structure adapted for accepting at least one of a NMOS device and a PMOS device. A substrate is formed. A strained relaxed layer is formed on the substrate. A first tensile strained layer is formed on the strained relaxed layer. A first compressive strain layer is formed on the first tensile strained layer. | 2016-04-21 |
20160111540 | FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD FOR FORMING THE SAME - A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and an isolation structure formed on the substrate. The FinFET structure also includes a fin structure extending above the substrate, and the fin structure is embedded in the isolation structure. The FinFET structure further includes an epitaxial structure formed on the fin structure, the epitaxial structure has a pentagon-like shape, and an interface between the epitaxial structure and the fin structure is lower than a top surface of the isolation structure. | 2016-04-21 |
20160111541 | GATE LAST SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a metal gate structure formed over a fin structure of the substrate. The semiconductor structure further includes a spacer formed on a sidewall of the metal gate structure and a source/drain structure formed in the fin structure. In addition, the spacer is in direct contact with the fin structure. | 2016-04-21 |
20160111542 | FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD FOR FORMING THE SAME - A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and a fin structure extending above the substrate. The FinFET structure includes an epitaxial structure formed on the fin structure, and the epitaxial structure has a first height. The FinFET structure also includes fin sidewall spacers formed adjacent to the epitaxial structure. The sidewall spacers have a second height and the first height is greater than the second height, and the fin sidewall spacers are configured to control a volume and the first height of the epitaxial structure. | 2016-04-21 |
20160111543 | Metal Gate with Silicon Sidewall Spacers - A method includes forming an opening in a dielectric to reveal a protruding semiconductor fin, forming a gate dielectric on sidewalls and a top surface of the protruding semiconductor fin, and forming a conductive diffusion barrier layer over the gate dielectric. The conductive diffusion barrier layer extends into the opening. The method further includes forming a silicon layer over the conductive diffusion barrier layer and extending into the opening, and performing a dry etch on the silicon layer to remove horizontal portions and vertical portions of the silicon layer. After the dry etch, a conductive layer is formed over the conductive diffusion barrier layer and extending into the opening. | 2016-04-21 |
20160111544 | METHOD OF FABRICATING ELECTROSTATICALLY ENHANCED FINS AND STACKED NANOWIRE FIELD EFFECT TRANSISTORS - Non-planar semiconductor devices including semiconductor fins or stacked semiconductor nanowires that are electrostatically enhanced are provided. The electrostatic enhancement is achieved in the present application by epitaxially growing a semiconductor material protruding portion on exposed sidewalls of alternating semiconductor material portions of at least one hard mask capped semiconductor-containing fin structure that is formed on a substrate. | 2016-04-21 |
20160111545 | SEMICONDUCTOR DEVICE, MODULE, AND ELECTRONIC DEVICE - A semiconductor device includes a first conductor, a second conductor, a first semiconductor, a second semiconductor, a third semiconductor, and an insulator. The second semiconductor is in contact with an upper surface of the first semiconductor. The first conductor overlaps with the second semiconductor. The insulator is located between the first conductor and the first semiconductor. The second conductor is in contact with an upper surface of the second semiconductor. The third semiconductor is in contact with the upper surface of the first semiconductor, the upper surface of the second semiconductor, and an upper surface of the second conductor. | 2016-04-21 |
20160111546 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Stable electrical characteristics and high reliability are provided for a miniaturized semiconductor device including an oxide semiconductor, and the semiconductor device is manufactured. The semiconductor device includes a base insulating layer; an oxide stack which is over the base insulating layer and includes an oxide semiconductor layer; a source electrode layer and a drain electrode layer over the oxide stack; a gate insulating layer over the oxide stack, the source electrode layer, and the drain electrode layer; a gate electrode layer over the gate insulating layer; and an interlayer insulating layer over the gate electrode layer. In the semiconductor device, the defect density in the oxide semiconductor layer is reduced. | 2016-04-21 |
20160111547 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, MODULE, AND ELECTRONIC DEVICE - A transistor with stable electrical characteristics or a transistor with normally-off electrical characteristics. The transistor is a semiconductor device including a conductor, a semiconductor, a first insulator, and a second insulator. The semiconductor is over the first insulator. The conductor is over the semiconductor. The second insulator is between the conductor and the semiconductor. The first insulator includes fluorine and hydrogen. The fluorine concentration of the first insulator is higher than the hydrogen concentration of the first insulator. | 2016-04-21 |
20160111548 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, DISPLAY DEVICE, AND DISPLAY MODULE - A semiconductor device including an oxide semiconductor film in which a change in electrical characteristics is inhibited and which has improved reliability is provided. The semiconductor device includes a gate electrode, a first insulating film over the gate electrode, an oxide semiconductor film over the first insulating film, a source electrode electrically connected to the oxide semiconductor film, a drain electrode electrically connected to the oxide semiconductor film, and a second insulating film over the oxide semiconductor film, the source electrode, and the drain electrode. The second insulating film includes a region including a halogen element, and the halogen element is distributed in the region at a higher concentration toward a surface of the second insulating film. | 2016-04-21 |
20160111549 | METHODS OF FORMING A SEMICONDUCTOR CIRCUIT ELEMENT AND SEMICONDUCTOR CIRCUIT ELEMENT - The present disclosure provides methods of forming a semiconductor circuit element and a semiconductor circuit element, wherein the semiconductor circuit element includes a first semiconductor device with a first gate structure disposed over a first active region of a semiconductor substrate and a second semiconductor device with a second gate structure disposed over a second active region of the semiconductor substrate, the first gate structure comprising a ferroelectric material buried into the first active region before a gate electrode material is formed on the ferroelectric material and the second gate structure comprising a high-k material different from the ferroelectric material. | 2016-04-21 |
20160111550 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a flexible device with fewer defects caused by a crack or a flexible device having high productivity. A semiconductor device including: a display portion over a flexible substrate, including a transistor and a display element; a semiconductor layer surrounding the display portion; and an insulating layer over the transistor and the semiconductor layer. When seen in a direction perpendicular to a surface of the flexible substrate, an end portion of the substrate is substantially aligned with an end portion of the semiconductor layer, and an end portion of the insulating layer is positioned over the semiconductor layer. | 2016-04-21 |
20160111551 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME - An electronic device including at least one electronic component and a method of manufacturing the same are provided. The electronic device may include a substrate, a semiconductor layer disposed on the substrate, an insulating layer disposed on the semiconductor layer, and a first metal layer disposed on the insulating layer. The insulating layer may have a pattern corresponding to a pattern of the semiconductor layer or the first metal layer. The flexible layer has a Young's modulus less than 40 GPa and is disposed on the substrate to encapsulate the semiconductor layer. At least one first opening penetrates the flexible layer. At least one second metal layer is disposed on the flexible layer and in the first opening and electrically connected to the semiconductor layer. | 2016-04-21 |
20160111552 | Semiconductor Device And Manufacturing Method Thereof - A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon. | 2016-04-21 |
20160111553 | LOCALIZED FIN WIDTH SCALING USING A HYDROGEN ANNEAL - Transistors including one or more semiconductor fins formed on a substrate. The one or more semiconductor fins are thinner in a channel region than in source and drain regions and have rounded corners formed by an anneal in a gaseous environment. A gate dielectric layer is on the channel region of the one or more semiconductor fins, conforming to the contours of the one or more semiconductor fins. A gate structure is on the gate dielectric layer. | 2016-04-21 |
20160111554 | SEMICONDUCTOR DEVICE - A semiconductor device, such as a pressure contact type semiconductor device, includes a frame body comprising ceramic and having an annular cylindrical shape which satisfies a relationship: (2/5E)·(D/t) | 2016-04-21 |
20160111555 | CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing chip package includes providing a semiconductor wafer having a plurality of semiconductor chips. An outer spacer and a plurality of inner spacers are formed on the semiconductor wafer. A protection lid is formed and disposed on the outer spacer and the inner spacers. A plurality of cavities is formed on each of the semiconductor chips from a lower surface thereof to expose the conductive pad disposed on the upper surface of the semiconductor chip. A plurality of conductive portions is formed and fills each of the cavities and electrically connected to each of the conductive pads. A plurality of solder balls is disposed on the lower surface and electrically connected to each of the conductive portions. The semiconductor chips are separated by cutting along a plurality of cutting lines between each of the semiconductor chips. | 2016-04-21 |
20160111556 | HIGH TEMPERATURE SOLAR CELL MOUNT - A high temperature electro-mechanical pressure mount for a solar cell includes a plate which is electrically insulating and thermally conductive. A center flat strip is disposed on or in the plate front surface. A first flat strip and a second flat strip are disposed on or in the plate front surface on either side of a solar cell foot print area respectively. A first flat lead and a second flat lead are disposed on and about perpendicular to the first flat strip and the second flat strip respectively and mechanically, thermally, and electrically couple respectively to the busbar edges on either side of the solar cell disposed over about a solar cell footprint area and hold the solar cell in the high temperature electro-mechanical pressure mount by a mechanical pressure. A method for mounting a solar cell in a high temperature electro-mechanical pressure mount is also described. | 2016-04-21 |
20160111557 | SEMICONDUCTOR DEVICE - A semiconductor device includes a filter circuit to sub-divide and output a received signal as a relatively low frequency first signal and a relatively high frequency second signal, a first channel containing a photocoupler to convey the first signal output from the filter circuit, a second channel containing an isolator, the isolator conveying the second signal output from the filter circuit, and a signal synthesis circuit to sum and output the first signal conveyed by way of the first channel and the second signal conveyed by way of the second channel. The isolator that is mounted in the second channel includes a capacitive coupling type isolator. The photocoupler that is mounted in the first channel contains a light emitting diode to emit light according to the first signal, and a photodiode to receive light from the light emitting diode. The isolator mounted in the second channel contains a capacitor. | 2016-04-21 |
20160111558 | PHOTOVOLTAIC CELLS HAVING A BACK SIDE PASSIVATION LAYER - A process for making a photovoltaic cell includes providing a semiconducting substrate having a back side passivation layer, and coating a self-assembling emulsion that includes glass frit particles onto the back side passivation layer. The emulsion is allowed to self-assemble into a network of traces that define cells. An electrode is formed over the network to create a precursor cell, which is then fired to cause the network to burn through the passivation layer and establish electrical contact between the semiconducting substrate and the electrode. | 2016-04-21 |
20160111559 | SOLAR CELL DEGRADATION CONTROL-COATING LIQUID AND THIN FILM AND SOLAR CELL DEGRADATION CONTROL METHOD - Provided is a solar cell degradation control-cover glass having a thin film that is formed by applying to a cover glass back surface a coating liquid comprising either an aqueous solution of a water-soluble compound of at least one metal selected from silicon, aluminum, zirconium, tin and zinc or a fine particle dispersion liquid of an oxide of such metal. | 2016-04-21 |
20160111560 | SOLAR CELL - A solar cell is discussed. The solar cell includes a substrate of a first conductive type, an emitter region which is positioned at a front surface of the substrate and has a second conductive type different from the first conductive type, a front passivation region including a plurality of layers which are sequentially positioned on the emitter region, a back passivation region which is positioned on a back surface opposite the front surface of the substrate and includes three layers, a plurality of front electrodes which pass through the front passivation region and are connected to the emitter region, and at least one back electrode which passes through the back passivation region and is connected to the substrate. | 2016-04-21 |
20160111561 | PACKAGE STRUCTURE WITH OPTICAL BARRIER, OPTICAL PACKAGE STRUCTURE AND MANUFACTURING METHODS THEREOF - A package structure with an optical barrier is provided. An emitter for emitting an optical signal and a detector for receiving the optical signal are disposed on a substrate. The optical barrier is disposed between the emitter and the detector for shielding the excess optical signal. A package material is used to completely cover the optical barrier, the emitter and the detector so that the optical barrier is completely disposed within the package material. | 2016-04-21 |
20160111562 | MULTISPECTRAL AND POLARIZATION-SELECTIVE DETECTOR - Described herein are devices operable to detect various portions of radiation incident on a receiving area of the device, systems incorporating the same, methods of using and methods of manufacturing thereof. Such a device comprises a substrate; at least one first feature; and at least one second feature, both extending substantially perpendicularly from the substrate. The at least one first feature and the at least second feature are operable to selectively absorb various portions of the radiation defined by their respective ranges of wavelengths and linear polarization. The at least one first feature and the at least one second feature are positioned on the substrate such that at least 50% of the first portion and at least 50% of the second portion of the radiation incident on the receiving area is selectively absorbed by the at least one first feature and the at least one second feature, respectively. | 2016-04-21 |
20160111563 | PHOTON AND CARRIER MANAGEMENT DESIGN FOR NONPLANAR THIN-FILM COPPER INDIUM GALLIUM DISELENIDE PHOTOVOLTAICS - Photovoltaic structures are disclosed. The structures can comprise randomly or periodically structured layers, a dielectric layer to reduce back diffusion of charge carriers, and a metallic layer to reflect photons back towards the absorbing semiconductor layers. This design can increase efficiency of photovoltaic structures. The structures can be fabricated by nanoimprint. | 2016-04-21 |
20160111564 | Pre-Equilibrium System and Method Using Solid-State Devices as Energy Converters Using Nano-Engineered Porous Network Materials - An energy conversion device for conversion of various energy forms into electricity. The energy forms may be chemical, photovoltaic or thermal gradients. The energy conversion device has a first and second electrode. A substrate is present that has a porous semiconductor or dielectric layer placed thereover. The substrate itself can be planar, two-dimensional, or three-dimensional, and possess internal and external surfaces. These substrates may be rigid, flexible and/or foldable. The porous semiconductor or dielectric layer can be a nano-engineered structure. A porous conductor material is placed on at least a portion of the porous semiconductor or dielectric layer such that at least some of the porous conductor material enters the nano-engineered structure of the porous semiconductor or dielectric layer, thereby forming an intertwining region. | 2016-04-21 |
20160111565 | BACK CONTACT SOLAR CELL AND FABRICATION METHOD THEREOF - The present invention discloses a back contact solar cell. The back contact solar cell includes a semiconductor substrate having a front surface and a rear surface; a first conductive type semiconductor region having a first conductive type and a second conductive type semiconductor region having a second conductive type at an interval on the rear surface of the semiconductor substrate. Furthermore, the rear surface of the semiconductor substrate has a texturing structure at the interval between the first conductive type semiconductor region and the second conductive type semiconductor region. | 2016-04-21 |
20160111566 | ABSORBER SURFACE MODIFICATION - The present disclosure provides systems and methods for depositing an alkaline metal layer on an absorber to generate a copper-poor region at a surface of the absorber. The copper-poor region provides an increased efficiency over non-treated absorbers having copper-rich surfaces. The alkaline metal layer may be deposited by any suitable deposition method, such as, for example, a wet deposition method. After the alkaline metal layer is deposited, the absorber is annealed, causing the alkaline metal layer to interact with the absorber to reduce the copper-profile of the absorber at the interface between the alkaline metal layer and the absorber. | 2016-04-21 |
20160111567 | Photovoltaic Lead-Salt Detectors - Disclosed is at least one embodiment of an infrared (IR) photovoltaic (PV) detector, comprising a IV-VI Lead (Pb)-salt layer disposed on a substrate and a charge-separation-junction (CSJ) structure associated with the IV-VI Pb-salt layer, wherein the CSJ structure comprises a plurality of element areas disposed upon or within the IV-VI Pb-salt layer, wherein the plurality of element areas are spaced apart from each other. Each element area may be connected to a first Ohmic contact thereby forming a plurality of interconnected first Ohmic contacts, and a second Ohmic contact may be disposed upon a portion of the IV-VI Pb-salt layer. In another non-limiting embodiment, a PV detector, comprising a heterojunction region that comprises at least one IV-VI Pb-salt material layer coupled to at least one non-Pb-salt layer, wherein the at least one IV-VI Pb-salt layer and the at least one non-Pb-salt layer form a p-n junction or Schottky junction with a type II band gap alignment. | 2016-04-21 |
20160111568 | METHOD FOR FORMING THIN FILM CHALCOGENIDE LAYERS - The disclosed technology generally relates to chalcogenide thin films, and more particularly to ternary and quaternary chalcogenide thin films having a wide band-gap, and further relates to photovoltaic cells containing such thin films, e.g., as an absorber layer. In one aspect, a method of forming a ternary or quaternary thin film chalcogenide layer containing Cu and Si comprises depositing a copper layer on a substrate. The method additionally comprises depositing a silicon layer on the copper layer with a [Cu]/[Si] atomic ratio of at least 0.7, and thereafter annealing in an inert atmosphere. The method further includes performing a first selenization or a first sulfurization, thereby forming a ternary thin film chalcogenide layer on the substrate. In another aspect, a composite structure includes a substrate having a service temperature not exceeding 600° C. and a ternary chalcogenide thin film or a quaternary chalcogenide thin film on the substrate, where the ternary or quaternary chalcogenide thin film comprises a selenide and/or a sulfide containing Cu and Si. | 2016-04-21 |
20160111569 | LATTICE MATCHABLE ALLOY FOR SOLAR CELLS - An alloy composition for a subcell of a solar cell is provided that has a bandgap of at least 0.9 eV, namely, Ga | 2016-04-21 |
20160111570 | RIBBON-FREE SOLAR CELL MODULE AND METHOD FOR PREPARING SAME - A ribbon-free solar cell module and a method for preparing the same are provided. The solar cell module is in a five-layer structure, including a first layer of conductive back plate, a second layer of conductive adhesive connection joints, a third layer of back contact cells, a fourth layer of packaging material, and a fifth layer of tempered glass which are successively laminated together, wherein the first layer of conductive back plate is in a novel laminated structure. Such a design provides a ribbon-free solar cell module and a method for preparing the same which are low in cost, and easy to implement. | 2016-04-21 |
20160111571 | PRIMED EDGE SEALING TAPE FOR PHOTOVOLTAIC MODULE - An edge sealing tape for photovoltaic modules includes a primer suitable for bonding the edge sealing tape to the top sheet of the module. In one exemplary configuration, the edge sealing tape is a polyisobutylene-based material such as butyl and carries a primer disposed between one side of the edge sealing tape and a release liner wherein the primer is configured to bond with a fluoropolymer-based top sheet such that the edge sealing tape cohesively fails after the primer bonds the tape to the top sheet. | 2016-04-21 |
20160111572 | Solar Panel Having Fire Protection - A fire-protected solar module comprises on an upper side a glass pane ( | 2016-04-21 |
20160111573 | HIGHLY DENSIFIED PV MODULE - In an example, a photovoltaic (PV) module includes multiple PV cells, a continuous backsheet, a circuit card, and a buried first polarity contact. The PV cells are arranged in rows and columns. The continuous backsheet is positioned behind the PV cells, includes a ground plane for the PV cells, and is electrically coupled between a first row and a last row of the PV cells. The circuit card is mechanically coupled to a back of the PV module and includes a first connector with a first polarity and a second connector with an opposite second polarity. The buried first polarity contact is positioned behind the PV cells, is electrically coupled to a back of each PV cell in one of the rows of the PV cells, and extends through a slot formed in the continuous backsheet to electrical contact with the first connector of the circuit card. | 2016-04-21 |
20160111574 | SOLAR CELL MODULE AND METHOD OF MANUFACTURING SAME - A solar cell module includes: solar cells, each of which includes first and second principal surfaces, on which a first and second bus bar electrodes are provided respectively; a wiring member connecting the first bus bar electrode of one of adjacent solar cells and the second bus bar electrode of the other adjacent solar cell; a first resin adhesive layer connecting the wiring member and the first bus bar electrode; and a second resin adhesive layer connecting the wiring member and the second bus bar electrode. The wiring member includes a first bent section bent toward the second principal surface at an end of the first bus bar electrode or the first resin adhesive layer on the adjacent side, and a second bent section bent toward the first principal surface at an end of the second bus bar electrode or the second resin adhesive layer on the adjacent side. | 2016-04-21 |
20160111575 | MESOSCOPIC SOLAR CELL BASED ON PEROVSKITE LIGHT ABSORPTION MATERIAL AND METHOD FOR MAKING THE SAME - A mesoscopic solar cell, including: a conductive substrate, a hole blocking layer, a mesoporous nanocrystalline layer, an insulation separating layer, and a hole collecting layer, and perovskite light absorption materials. The hole blocking layer, the mesoporous nanocrystalline layer, the insulation separating layer, and the hole collecting layer are sequentially laminated on the conductive substrate. The perovskite semiconductor materials are filled in the mesoporous nanocrystalline layer, the insulation separating layer, and the hole collecting layer, which enables the mesoporous nanocrystalline layer to be an active light absorption layer operating as a photoanode, and enables the insulation separating layer to be a hole transporting layer. | 2016-04-21 |
20160111576 | COST-EFFICIENT HIGH POWER PECVD DEPOSITION FOR SOLAR CELLS - A method for forming a photovoltaic device includes providing a substrate. A layer is deposited to form one or more layers of a photovoltaic stack on the substrate. The depositing of the amorphous layer includes performing a high power flash deposition for depositing a first portion of the layer. A low power deposition is performed for depositing a second portion of the layer. | 2016-04-21 |
20160111577 | COMPOUND-SEMICONDUCTOR PHOTOVOLTAIC CELL AND MANUFACTURING METHOD OF COMPOUND-SEMICONDUCTOR PHOTOVOLTAIC CELL - A compound-semiconductor photovoltaic cell includes a compound-semiconductor substrate; a first photoelectric conversion cell formed on the compound-semiconductor substrate; a first junction layer formed on the first photoelectric conversion cell; a second junction layer joined to the first junction layer directly or indirectly; and a second photoelectric conversion cell joined to the first photoelectric conversion cell via the first and second junction layers, and arranged on a light incident side of the first photoelectric conversion cell in a light incident direction. Band gaps of the first and second photoelectric conversion cells are made smaller from the incident side toward a deep side in the light incident direction in order. A band gap of the second junction layer is greater than or equal to a band gap of the second photoelectric conversion cell. The second photoelectric conversion cell is a GaAs-based photovoltaic cell, and the second junction layer is a GaPAs layer. | 2016-04-21 |
20160111578 | CONTACT FOR SILICON HETEROJUNCTION SOLAR CELLS - A photovoltaic device and method include a substrate coupled to an emitter side structure on a first side of the substrate and a back side structure on a side opposite the first side of the substrate. The emitter side structure or the back side structure include layers alternating between wide band gap layers and narrow band gap layers to provide a multilayer contact with an effectively increased band offset with the substrate and/or an effectively higher doping level over a single material contact. An emitter contact is coupled to the emitter side structure on a light collecting end portion of the device. A back contact is coupled to the back side structure opposite the light collecting end portion. | 2016-04-21 |
20160111579 | Photovoltaic Lead-Salt Detectors - Disclosed is at least one embodiment of an infrared (IR) photovoltaic (PV) detector, comprising a IV-VI Lead (Pb)-salt layer disposed on a substrate and a charge-separation-junction (CSJ) structure associated with the IV-VI Pb-salt layer, wherein the CSJ structure comprises a plurality of element areas disposed upon or within the IV-VI Pb-salt layer, wherein the plurality of element areas are spaced apart from each other. Each element area may be connected to a first Ohmic contact thereby forming a plurality of interconnected first Ohmic contacts, and a second Ohmic contact may be disposed upon a portion of the IV-VI Pb-salt layer. In another non-limiting embodiment, a PV detector, comprising a heterojunction region that comprises at least one IV-VI Pb-salt material layer coupled to at least one non-Pb-salt layer, wherein the at least one IV-VI Pb-salt layer and the at least one non-Pb-salt layer form a p-n junction or Schottky junction with a type II band gap alignment. | 2016-04-21 |
20160111580 | METHOD OF MANUFACTURING A LOW NOISE PHOTODIODE - A method of manufacturing a photodiode including a useful layer made of a semi-conductor alloy. The useful layer has a band gap value which decreases from its upper face to its lower face. A step of producing a first doped region forming a PN junction with a second doped region of the useful layer, said production of a first doped region including a first doping step, so as to produce a base portion; and a second doping step, so as to produce at least one protuberance protruding from the base portion and in the direction of the lower face. | 2016-04-21 |
20160111581 | PACKAGED SEMICONDUCTOR DEVICES AND RELATED METHODS - A packaged semiconductor device includes a substrate, a die, at least one electrical connector, a first mold compound formed of translucent material, and a second mold compound. A first face of the die is electrically and mechanically coupled to the substrate. The at least one electrical connector electrically couples at least one electrical contact on a second face of the die with at least one conductive path of the substrate. The first mold compound formed of a translucent material at least partially encapsulates the die and the at least one electrical connector. The second mold compound at least partially encapsulates the first mold compound and forms a window through which the first mold compound is exposed. In implementations the second mold compound is opaque and the first mold compound is transparent. In implementations the substrate includes a lead frame having a die flag and a plurality of lead frame fingers. | 2016-04-21 |
20160111582 | MODULAR INTERDIGITATED BACK CONTACT PHOTOVOLTAIC CELL STRUCTURE ON OPAQUE SUBSTRATE AND FABRICATION PROCESS - A back contact integrated photovoltaic cell includes a substrate having a dielectric surface and a patterned metal layer with parallel spaced alternately positive and negative electrode fingers forming an interdigitated two-terminal structure over the dielectric surface of the substrate. A dielectric filler may be in the interstices of separation between adjacent spaced parts of the patterned metal layer. Parallel spaced strips, alternately of p | 2016-04-21 |
20160111583 | ETCHING PROCESSES FOR SOLAR CELL FABRICATION - A method of fabricating a solar cell can include forming a first dopant region over a silicon substrate and an oxide region over the first dopant region. In an embodiment, the oxide region can protect the first dopant region from a first etching process. In an embodiment, a second dopant region can be formed over the silicon substrate, where a mask can be formed to protect a first portion of the second dopant region from the first etching process. In an embodiment, the first etching process can be performed to expose portions of the silicon substrate and/or a silicon region. A second etching process can be performed to form a trench region to separate a first and second doped region of the solar cell. A third etching process can be performed to remove contaminants from the solar cell and remove any remaining portions of the oxide region. | 2016-04-21 |
20160111584 | METHODS OF GROWING HETEROEPITAXIAL SINGLE CRYSTAL OR LARGE GRAINED SEMICONDUCTOR FILMS AND DEVICES THEREON - A method is disclosed for making semiconductor films from a eutectic alloy comprising a metal and a semiconductor. Through heterogeneous nucleation said film is deposited at a deposition temperature on flexible substrates, such as glass. Specifically said film is vapor deposited at a fixed temperature in said deposition temperature where said deposition temperature is above a eutectic temperature of said eutectic alloy and below a temperature at which the substrate softens. Such films are nearly to entirely free of metal impurities and have widespread application in the manufacture and benefit of photovoltaic and display technologies. | 2016-04-21 |
20160111585 | METHOD OF ABSORBER SURFACE REPAIRING BY SOLUTION PROCESS - Methods and systems for repairing oxidation of CIGS surfaces during manufacture of a CIGS solar cell are generally disclosed. Oxidation of an absorber reduces the photoluminescence intensity of the CIGS surface. The absorber is immersed in a reduction tank having a reducing reagent therein. The reducing reagent reverses the oxidation of the CIGS absorber, increasing the interface quality and corresponding photoluminescence intensity. After reversing the oxidation, a buffer layer is deposited on the CIGS absorber to prevent further surface oxidation. | 2016-04-21 |
20160111586 | Method and Apparatus For Reduction of Solar Cell LID - Reduction of solar wafer LID by exposure to continuous or intermittent High-Intensity full-spectrum Light Radiation, HILR, by an Enhanced Light Source, ELS, producing 3-10 Sols, optionally in the presence of forming gas or/and heating to within the range of from 100° C.-300° C. HILR is provided by ELS modules for stand-alone bulk/continuous processing, or integrated in wafer processing lines in a High-Intensity Light Zone, HILZ, downstream of a wafer firing furnace. A finger drive wafer transport provides continuous shadowless processing speeds of 200-400 inches/minute in the integrated furnace/HILZ. Wafer dwell time in the peak-firing zone is 1-2 seconds. Wafers are immediately cooled from peak firing temperature of 850° C.-1050° C. in a quench zone ahead of the HILZ-ELS modules. Dwell in the HILZ is from about 10 sec to 5 minutes, preferably 10-180 seconds. Intermittent HILR exposure is produced by electronic control, a mask, rotating slotted plate or moving belt. | 2016-04-21 |
20160111587 | INFRA RED DETECTORS AND METHODS OF MANUFACTURE - A method of forming infra red detector arrays is described, starting with the manufacture of a wafer. The wafer is formed from a GaAs or GaAs/Si substrate having CMT deposited thereon by MOVPE. The CMT deposited comprises a number of layers of differing composition, the composition being controlled during the MOVPE process and being dependent on the thickness of the layer deposited. Other layers are positioned between the active CMT layers and the substrate. A CdTe buffer layer aids the deposition of the CMT on the substrate and an etch stop layer is also provided. Once the wafer is formed, the buffer layer, the etch stop layer and all intervening layers are etched away leaving a wafer suitable for further processing into an infra red detector. | 2016-04-21 |
20160111588 | ENCAPSULATED FLEXIBLE ELECTRONIC DEVICE, AND CORRESPONDING MANUFACTURING METHOD - The disclosure relates to an encapsulated flexible electronic device comprising a flexible electronic device, wherein the flexible electronic device is protected by a protective coating layer, a first cover sheet and a second cover sheet being made of patterned and developed dry photoresist films. The encapsulated flexible electronic device may be used to directly realize different type of electronic devices, such as smart sensor devices. | 2016-04-21 |
20160111589 | LOW-COST SOLAR CELL METALLIZATION OVER TCO AND METHODS OF THEIR FABRICATION - Methods for fabricating busbar and finger metallization over TCO are disclosed. Rather than using expensive and relatively resistive silver paste, a high conductivity and relatively low cost copper is used. Methods for enabling the use of copper as busbar and fingers over a TCO are disclosed, providing good adhesion while preventing migration of the copper into the TCO. Also, provisions are made for easy soldering contacts to the copper busbars. | 2016-04-21 |
20160111590 | Manufacturing Method of Semiconductor Film, Manufacturing Method of Semiconductor Device, and Manufacturing Method of Photoelectric Conversion Device - A method for forming an amorphous semiconductor which contains an impurity element and has low resistivity and a method for manufacturing a semiconductor device with excellent electrical characteristics with high yield are provided. In the method for forming an amorphous semiconductor containing an impurity element, which utilizes a plasma CVD method, pulse-modulated discharge inception voltage is applied to electrodes under the pressure and electrode distance with which the minimum discharge inception voltage according to Paschen's Law can be obtained, whereby the amorphous semiconductor which contains an impurity element and has low resistivity is formed. | 2016-04-21 |
20160111591 | LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a light-emitting device, the method including forming a first resin comprising a phosphor inside a cavity of a package body on which a light-emitting diode chip is mounted, measuring color coordinates of light emitted by combination of the light-emitting diode chip and the phosphor, and correcting the color coordinates by forming a second resin on the first resin. The first resin is not fully cured before measuring and correcting the color coordinates. | 2016-04-21 |
20160111592 | LIGHT EMITTING DEVICES AND METHODS OF MANUFACTURING THE SAME - Light emitting devices and methods of manufacturing the light emitting devices. The light emitting devices include a silicon substrate; a metal buffer layer on the silicon substrate, a patterned distributed Bragg reflector (DBR) on the metal buffer layer; and a nitride-based thin film layer on the patterned DBR and regions between patterns of the DBR. | 2016-04-21 |
20160111593 | OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING SAME - An optoelectronic device comprises a substrate; pads on a surface of the substrate; semiconductor elements, each element resting on a pad; a portion covering at least the lateral sides of each pad, the portion preventing the growth of the semiconductor elements on the lateral sides; and a dielectric region extending in the substrate from the surface and connecting, for each pair of pads, one of the pads in the pair to the other pad in the pair. A method of manufacturing an optoelectronic device is also disclosed. | 2016-04-21 |
20160111594 | Optoelectronic Component And Method For The Production Thereof - An optoelectronic device ( | 2016-04-21 |
20160111595 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device may include: a first conductivity-type semiconductor layer; an active layer disposed on the first conductivity-type semiconductor layer and including a plurality of quantum barrier layers and a plurality of quantum well layers which are alternately stacked; and a second conductivity-type semiconductor layer disposed on the active layer. A quantum barrier layer closest to the second conductivity-type semiconductor layer, among the plurality of quantum barrier layers, may include a first undoped region and a first doped region disposed on the first undoped region and having a thickness greater than or equal to that of the first undoped region. Each of the first undoped region and the first doped region may include a plurality of first unit layers having different energy band gaps, and at least one hole accumulation region. | 2016-04-21 |
20160111596 | LIGHTING SYSTEM - A lighting system includes a lighting unit comprising at least one lighting device, a sensing unit configured to measure at least one of atmospheric temperature and humidity, a controlling unit configured to compare the at least one of the temperature and the humidity measured by the sensor unit with set values and determine a color temperature of the lighting unit as a result of the comparison, and a driving unit configured to drive to the lighting unit to have the determined color temperature. | 2016-04-21 |
20160111597 | GRAPHICAL MICROSTRUCTURE OF LIGHT EMITTING DIODE SUBSTRATE - The invention relates to a patterned microstructure of a light emitting diode (LED) substrate. The substrate is provided with patterned microstructures arranged in an array. Each patterned microstructure includes a bottom surface and a lateral surface adjacent to the bottom surface. There is an angle θ between the lateral surface and the bottom surface, where 0°<θ<90°. The length of the bottom surface ranges between 2.5 microns and 2.8 microns. An end of the lateral surface far away from the bottom surface is gradually shrunk into an intersection, and the height between the intersection and the bottom surface ranges between 1.5 microns and 1.9 microns. Accordingly, the invention can effectively achieve improving light extraction efficiency of the LED by optimizing the size of the patterned microstructure cyclically and alternately arranged on the LED substrate. | 2016-04-21 |
20160111598 | LIGHT EMITTING DEVICE HAVING LIGHT EXTRACTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A light emitting device including a support layer; a reflective electrode disposed on the support layer; an ohmic electrode disposed on the reflective electrode, the ohmic electrode including a transparent electrode; and a semiconductor structure disposed on the ohmic electrode, the semiconductor structure including a p-type semiconductor layer disposed on the ohmic electrode; a light emitting layer disposed on the p-type semiconductor layer; and an n-type semiconductor layer disposed on the light emitting layer. Further, the transparent electrode has a thickness in the range of 40 nm to 90 nm. | 2016-04-21 |
20160111599 | LED ELEMENT - In order to achieve appropriate light distribution using light distribution characteristics resulting from diffraction while improving light extraction efficiency using a diffraction effect, an LED element provided with: a substrate in which periodic depressions or projections are formed on a front surface; a semiconductor laminated part that is formed on the front surface of the sapphire substrate, includes a light-emitting layer, and is formed of a group-III nitride semiconductor; and a reflecting part that reflects at least a part of light emitted from the light-emitting layer toward the front surface of the substrate, the LED element obtaining a diffraction effect of light emitted from the light-emitting layer at an interface between the substrate and the semiconductor laminated part, wherein a relation of 1/2×λ≦P≦16/9×λ, is satisfied, where a period of the depressions or the projections is P and a peak wavelength of the light emitted from the light-emitting layer is λ. | 2016-04-21 |
20160111600 | LIGHT EMITTING DIODE, METHOD OF FABRICATING THE SAME AND LED MODULE HAVING THE SAME - A light emitting diode is provided to include a first conductive-type semiconductor layer; a mesa including a second conductive-type semiconductor layer disposed on the first conductive-type semiconductor layer and an active layer interposed between the first and the second conductive-type semiconductor layers; and a first electrode disposed on the mesa, wherein the first conductive-type semiconductor layer includes a first contact region disposed around the mesa along an outer periphery of the first conductive-type semiconductor layer; and a second contact region at least partially surrounded by the mesa, the first electrode is electrically connected to at least a portion of the first contact region and at least a portion of the second contact region, and a linewidth of an adjoining region between the first contact region and the first electrode is greater than the linewidth of an adjoining region between the second contact region and the first electrode. | 2016-04-21 |
20160111601 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE, AND LIGHTING APPARATUS INCLUDING THE PACKAGE - Embodiments provide a light emitting device including a substrate, a light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, disposed under the substrate, a reflective layer disposed under the second conductive semiconductor layer, the reflective layer having at least one first through-hole formed in a first direction, the first direction being a thickness direction of the light emitting structure, a contact layer embedded in at least one second through-hole penetrating the reflective layer, the second conductive semiconductor layer, and the active layer so as to be connected to the first conductive semiconductor layer, and an insulation layer disposed between the contact layer and each of the reflective layer, the second conductive semiconductor layer, and the active layer, the insulation layer being embedded in the first through-hole. | 2016-04-21 |
20160111602 | LIGHT-EMITTING DIODE CHIP - A light-emitting diode (LED) chip is disclosed. The chip includes a light-emitting diode and an electrode layer on the light-emitting diode. The electrode layer includes a reflective metal layer. The reflective metal layer includes a first composition and a second composition. The first composition includes aluminum or silver, and the second composition includes copper, silicon, tin, platinum, gold, palladium or a combination thereof. The weight percentage of the second composition is greater than 0% and less than 20%. | 2016-04-21 |
20160111603 | Indium Zinc Oxide for Transparent Conductive Oxide Layer and Methods of Forming Thereof - Provided are light emitting diodes (LEDs) and methods of fabricating such LEDs. Specifically, an LED has an epitaxial stack and current distribution layer disposed on and interfacing the epitaxial stack. The current distribution layer includes indium oxide and zinc oxide such that the concentration of indium oxide is between about 5% and 15% by weight. During fabrication, the current distribution layer is annealed at a temperature of less than about 500° C. or even at less than about 400° C. These low anneal temperature helps preserving the overall thermal budget of the LED while still yielding a current distribution layer having a low resistivity and low adsorption. A particular composition and method of forming the current distribution layer allows using lower annealing temperatures. In some embodiments, the current distribution layer is sputtered using indium oxide and zinc oxide targets at a pressure of less than 5 mTorr. | 2016-04-21 |
20160111604 | METHOD FOR EXPANDING SPACINGS IN LIGHT-EMITTING ELEMENT ARRAY AND LIGHT-EMITTING ELEMENT ARRAY UNIT - A method for expanding spacings in a light-emitting element array includes the following steps of: providing a light-emitting element array unit including a stretchable supporting film, and a plurality of light-emitting elements disposed on the stretchable supporting film and arranged into a two-dimensional array; stretching the stretchable supporting film along a first direction and a second direction. The first direction and the second direction respectively correspond to a row direction and a column direction of the two-dimensional array. | 2016-04-21 |
20160111605 | METHOD FOR TRANSFERRING LIGHT-EMITTING ELEMENTS ONTO A PACKAGE SUBSTRATE - A method for transferring light-emitting elements onto a package substrate includes: providing a light-emitting unit including a supporting substrate and a plurality of light-emitting elements, each of the light-emitting elements being removably connected to the supporting substrate and having a surface opposite to the supporting substrate; disposing the light-emitting unit spacingly above a package substrate in such a manner that the surface of each of the light-emitting elements faces the package substrate; and disconnecting the light-emitting elements from the supporting substrate to allow the light-emitting elements to fall onto the package substrate by gravity, so as to connect the light-emitting elements with the package substrate in a non-contact transferring method. | 2016-04-21 |
20160111606 | LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed are a light-emitting device and a manufacturing method thereof. A light-emitting device according to a preferred embodiment of the disclosure comprises: a frame portion having a bottom and a sidewall; a light-emitting portion which is disposed on the frame portion and emits light; and a window portion disposed over the frame portion so as to cover the light-emitting portion. | 2016-04-21 |
20160111607 | PHOSPHOR SHEET, LIGHT-EMITTING DEVICE HAVING THE PHOSPHOR SHEET AND METHOD OF MANUFACTURING THE SAME - A light-emitting device includes a substrate including a first electrode and a second electrode, a light-emitting diode (LED) chip electrically connected to the first and the second electrodes, and a phosphor sheet disposed on an upper surface of the LED chip, a first transparent part disposed under the phosphor sheet, and a second transparent part disposed between the phosphor sheet and the LED chip. The first transparent part contacts the second transparent part. | 2016-04-21 |
20160111608 | THIN FILM WAVELENGTH CONVERTERS AND METHODS FOR MAKING THE SAME - Thin film wavelength converters and methods for making the same are disclosed. In some embodiments, the thin film converters include a first thin film layer of first wavelength conversion material, a conductive layer, and a second thin film layer of a second wavelength conversion material. In one embodiment, a photoresist mask is applied to the conductive layer to form a pattern of by which the second wavelength conversion material may be applied by electrophoretic deposition to the exposed regions of the surface of the conductive layer. | 2016-04-21 |
20160111609 | Conversion LED with High Color Rendition Index - Conversion LED emits primary radiation (peak wavelength 435 nm to 455 nm) and has a luminescent substance-containing layer positioned to intercept the primary radiation and convert it into secondary radiation. First and second luminescent substances are used. The first luminescent substance is a A | 2016-04-21 |
20160111610 | LIGHT EMITTING DEVICE AND RESIN COMPOSITION - Provided a light emitting device comprising:
| 2016-04-21 |
20160111611 | EPOXY RESIN COMPOSITION FOR OPTICAL SEMICONDUCTOR DEVICE, AND LEAD FRAME FOR OPTICAL SEMICONDUCTOR DEVICE, ENCAPSULATION TYPE OPTICAL SEMICONDUCTOR ELEMENT UNIT AND OPTICAL SEMICONDUCTOR DEVICE EACH OBTAINABLE BY USING THE EPOXY RESIN COMPOSITION - An optical semiconductor device includes a metal lead frame including first and second plate portions, an optical semiconductor element mounted on the metal lead frame, and a reflector provided around the optical semiconductor element. A material for the reflector is an epoxy resin composition containing: (A) an epoxy resin; (B) a curing agent; (C) a white pigment; (D) an inorganic filler; and (E) at least one of a carboxylic acid and water. Components (C) and (D) are present in a total proportion of 69 to 94 wt % based on the amount of the overall epoxy resin composition, and the component (E) is present in a proportion of 4 to 23 mol % based on the total amount of the components (B) and (E). The resin composition has a higher glass transition temperature, and is excellent in moldability and blocking resistance and substantially free from warpage. | 2016-04-21 |
20160111612 | LIGHT EMITTING DIODE HAVING MIRROR PROTECTION LAYER AND METHOD FOR MANUFACTURING MIRROR PROTECTION LAYER - The present invention includes an N-type semiconductor layer, an active layer, a P-type semiconductor layer, a metal mirror layer, a protection adhesive layer and a metal buffer layer that are sequentially stacked. The protection adhesive layer is selected from a group consisting of a metal oxide and a metal nitride, fully covers one side of the metal mirror layer away from the P-type semiconductor layer, and includes a plurality of conductive holes. The metal buffer layer penetrates through the conductive holes to be electrically connected to the metal mirror layer. After forming the metal mirror layer on the P-type semiconductor layer, the protection adhesive layer that fully covers the metal mirror layer is directly formed to thoroughly protect the metal mirror layer by using the protection adhesive layer, thereby maintaining a reflection rate of the metal mirror layer and ensuring light emitting efficiency of a light emitting diode. | 2016-04-21 |
20160111613 | LIGHT-EMITTING DIODE AND METHOD FOR MANUFACTURING SAME - A light-emitting diode includes a support substrate, a semiconductor stack disposed on the support substrate, the semiconductor stack including a p-type compound semiconductor layer, an active layer and a n-type semiconductor layer, a reflective metal layer disposed between the support substrate and the semiconductor stack, the reflective metal layer being in ohmic contact with the p-type compound semiconductor layer of the semiconductor stack and having a groove exposing a portion of the semiconductor stack, a first electrode pad contacting the n-type compound semiconductor layer of the semiconductor stack, an electrode extension connected to the first electrode pad, the electrode extension disposed directly over the groove along a line perpendicular to the support substrate, an upper insulation layer disposed between the first electrode pad and the semiconductor stack. The electrode extension includes an Ni layer contacting the n-type compound semiconductor layer, and two Au layers disposed on the Ni layer. | 2016-04-21 |
20160111614 | LIGHT EMITTING DEVICE PACKAGE AND LIGHTING APPARATUS INCLUDING THE PACKAGE - Embodiments provide a light emitting device package including a substrate, a light emitting structure disposed under the substrate and including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, first and second electrodes connected to the first and second conductive semiconductor layers, a first pad connected to the first electrodes in first-first through-holes penetrating the second conductive semiconductor layer and the active layer, and a first insulation layer disposed between the first pad and the second conductive semiconductor layer and between the first pad and the active layer to cover the first electrodes in a first-second through-hole, and a second pad connected to the second electrode through a second through-hole penetrating the first insulation layer and electrically spaced apart from the first pad. The second pad does not overlap the first insulation layer in the first-second through-hole in a thickness direction of the light emitting structure. | 2016-04-21 |
20160111615 | Method for Producing a Plurality of Optoelectronic Semiconductor Chips, and Optoelectronic Semiconductor Chip - An optoelectronic semiconductor chip includes a semiconductor body that has a semiconductor layer sequence and at least one opening that extends through a second semiconductor layer into a first semiconductor layer. The chip also includes a support, which includes at least one recess, and a metallic connecting layer between the semiconductor body and the support. The metallic connecting layer includes a first region and a second region. The first region is connected to the first semiconductor layer in an electrically conductive manner through the opening and the second region is connected to the second semiconductor layer in an electrically conductive manner. A first contact is connected to the first region in an electrically conductive manner through the recess or a second contact is connected to the second region in an electrically conductive manner through the recess. | 2016-04-21 |
20160111616 | WAFER LEVEL PACKAGING OF ELECTRONIC DEVICE - Wafer level packaging of LED devices is accomplished using a bottom wafer that includes one or more vias. A passivation layer is placed over the top surface of the bottom wafer including the surface of the vias. Metal pads are placed on the top surface of the passivation layer and extend to the bottom of the vias. Bond pads are then associated with the metal pads and ultimately used in attaching an LED device bottom wafer assembly. An encapsulation layer is applied and in contact with the LED device and a top wafer is attached to the encapsulation layer. The thickness of the bottom wafer is reduced, removing the lower portion to expose the metal pads at the bottom of the vias. An isolation layer is applied to the bottom wafer and holes are formed in the isolation layer to expose the metal pads. Electroplated structures are in contact with the isolation layer and in contact with the exposed metal pads. | 2016-04-21 |
20160111617 | LIGHT EMITTING DIODE PACKAGE - A light emitting diode (LED) package includes an LED chip, a first lead frame and a second lead frame electrically connected to the LED chip and separated by a space, and a housing disposed on the first lead frame and the second lead frame. The housing includes an external housing surrounding a cavity, the cavity exposing a first portion of the first lead frame and a first portion of the second lead frame, and an internal housing disposed in the space, the internal housing covering a top portion of the first lead frame and a top portion of the second lead frame. | 2016-04-21 |
20160111618 | OPTOELECTRONIC DEVICE INCLUDING IMPROVED THERMAL MANAGEMENT - A heterostructure for use in fabricating an optoelectronic device with improved thermal management is provided. The heterostructure can include a plurality of epitaxially grown layers including an n-type contact layer, an active layer, and a p-type contact layer. N-type and p-type electrodes for the n-type contact layer and p-type contact layer, respectively, can be embedded within an electrically insulating, thermally conductive semiconductor layer that is adjacent to the epitaxially grown layers. The electrically insulating, thermally conductive semiconductor layer can provide a larger lateral area for extracting heat generated by the active layer, so that there is improved thermal management within the device. | 2016-04-21 |
20160111619 | HIGH PERFORMANCE HIGH TEMPERATURE THERMOELECTRIC COMPOSITES WITH METALLIC INCLUSIONS - The present invention provides a composite thermoelectric material. The composite thermoelectric material can include a semiconductor material comprising a rare earth metal. The atomic percent of the rare earth metal in the semiconductor material can be at least about 20%. The composite thermoelectric material can further include a metal forming metallic inclusions distributed throughout the semiconductor material. The present invention also provides a method of forming this composite thermoelectric material. | 2016-04-21 |
20160111620 | METHODS AND DEVICES FOR CONTROLLING THERMAL CONDUCTIVITY AND THERMOELECTRIC POWER OF SEMICONDUCTOR NANOWIRES - Methods and devices for controlling thermal conductivity and thermoelectric power of semiconductor nanowires are described. The thermal conductivity and the thermoelectric power are controlled substantially independently of the electrical conductivity of the nanowires by controlling dimensions and doping, respectively, of the nanowires. A thermoelectric device comprising p-doped and n-doped semiconductor nanowire thermocouples is also shown, together with a method to fabricate alternately p-doped and n-doped arrays of silicon nanowires. | 2016-04-21 |
20160111621 | Heat Conversion Device - Provided is a heat conversion device, including: a housing; a thermoelectric module received in the housing and including a thermoelectric semiconductor between substrates disposed to face each other; a first temperature conversion portion and a second temperature conversion portion disposed between the substrates, respectively; and a heat reduction portion adopted to guide a part of a fluid flowing in the housing and passing through the first temperature conversion portion to the second temperature conversion portion. | 2016-04-21 |
20160111622 | FLEXIBLE THERMOELECTRIC MODULE APPARATUS - The present invention relates to a flexible thermoelectric module apparatus, and more particularly, to a flexible thermoelectric module apparatus including a heat sink longitudinally extending and a thermoelectric module disposed in the heat sink, in which the heat sink has a pipe-shaped body constituting a main body and a hole longitudinally formed through the center portion of the body, the thermoelectric module has a plurality of thermoelectric plates, the thermoelectric plates are plates having predetermined length and width, are arranged longitudinally in parallel with the heat sink, with a first side in the width direction connected to the inner side of the body and a second side disposed inside the hole, are arranged in parallel with each other at circumferentially predetermined distances from each other in the hole, and have a predetermined angle to the radial direction of the heat sink such that they are inclined at a predetermined angle therebetween. | 2016-04-21 |
20160111623 | THERMOELECTRIC MODULE APPARATUS - Provided is a thermoelectric module apparatus including: a pipe-shaped housing having a hole that is longitudinally formed; a thermoelectric module coupled to the housing; and heat sinks combined with the thermoelectric module, in which the pipe-shaped housing has a plurality of mount holes having predetermined width and length, longitudinally extending, and arranged circumferentially in parallel with each other, the thermoelectric module has a plurality of thermoelectric plates having predetermined width, length, and thickness, the housing is connected to first sides in the width direction of the thermoelectric plates, the thermoelectric plates are disposed in the mount holes respectively with a portion in the width direction inserted and exposed inside the hole as much as a predetermined width and a portion in the width direction protruding and exposed outside the housing as much as a predetermined width, and the heat sinks are connected to the portions exposed outside the housing. | 2016-04-21 |
20160111624 | THERMOELECTRIC DEVICE TECHNOLOGY - A thermoelectric device for use with solar cells or other heat sources. A substrate has a manufactured surface with a plurality of highland features and lowland features. Each highland feature defines a peak adjacent to which there is an interface of two different film regions (formed of two different metals, two different semiconductors, or one metal and one semiconductor). The two film regions diverge away from each other with increasing distance from the interface and terminate at distal end regions. In response to a temperature difference between the interface and the distal end regions, the device produces a voltage. | 2016-04-21 |
20160111625 | Method of Fabricating Piezoelectric MEMS Devices - A single photo mask can be used to define the three critical layers for the piezoelectric MEMS device, specifically the top electrode layer, the piezoelectric material layer, and the bottom electrode layer. Using a single photo mask removes the misalignment source caused by using multiple photo masks. Furthermore, in certain exemplary embodiments, all electrical interconnects use underpass interconnect. This simplifies the process for defining the device electrodes and the process sequence for achieving self-alignment between the piezoelectric element and the top and bottom electrodes. This self-alignment is achieved by using an oxide hard mask to etch the critical region of the top electrode, the piezoelectric material, and the bottom electrode with one mask and different etch chemistries depending on the layer being etched. | 2016-04-21 |
20160111626 | FLEXIBLE CONDUCTIVE MATERIAL AND TRANSDUCER - A flexible conductive material of the present invention is formed by dispersing a conductive agent containing carbon nanotubes in a matrix that contains a polymer formed by amide bond formation or imide bond formation of a polycyclic aromatic component and an oligomer component and that has a glass transition point of 20° C. or less. The flexible conductive material of the present invention has good dispersibility of a conductive agent containing carbon nanotubes and has an excellent following performance to an expanding and shrinking substrate. A transducer of the present invention includes a dielectric layer made of a polymer, a plurality of electrodes with the dielectric layer interposed therebetween, and wirings connected to the respective electrodes, and at least either the electrodes or the wirings include the flexible conductive material of the present invention. The transducer of the present invention has a performance that is unlikely to deteriorate due to the electrodes or the wirings and has excellent durability. | 2016-04-21 |
20160111627 | VIBRATION DEVICE - A vibration device that includes a vibration portion, a support portion connected to the vibration portion, a bending-vibrating portion connected to the support portion, and a frame-shaped base portion connected to the bending-vibration portion and disposed so as to surround the vibration portion. The base portion defines a slit that extends in a first direction crossing a second direction in which the support portion extends from the vibration portion, the slit defining first and second fixed ends of the bending-vibrating portion and which are continuous with the base portion. A length between a portion of the bending-vibrating portion connected to the support portion to one of the first and second fixed ends of the bending-vibrating portion is in a range of λ/8 to 3λ/8, where λ denotes a wavelength of a bending vibration corresponding to a frequency of a characteristic vibration of the vibration portion. | 2016-04-21 |
20160111628 | PIEZOELECTRIC ELEMENT, METHOD FOR MANUFACTURING THE SAME, AND PIEZOELECTRIC ELEMENT-APPLIED DEVICE - A piezoelectric element has, from a substrate side, a first electrode, a piezoelectric layer containing a composite oxide of an ABO | 2016-04-21 |
20160111629 | INTEGRATED CIRCUIT STRUCTURES WITH SPIN TORQUE TRANSFER MAGNETIC RANDOM ACCESS MEMORY AND METHODS FOR FABRICATING THE SAME - A method for fabricating an STT-MRAM integrated circuit includes forming a fixed layer over a bottom electrode layer, forming a silicon oxide layer a hardmask layer over the fixed, and forming a trench within the silicon oxide and hardmask layers, thereby exposing an upper surface of the fixed layer and sidewalls of the silicon oxide and hardmask layer. The method further includes forming a conformal barrier layer along the sidewalls of the silicon oxide and hardmask layers and over the upper surface of the fixed layer, such that the conformal barrier layer comprises sidewall portions adjacent the sidewalls of the silicon oxide and hardmask layers and a central portion in between the sidewall portions and adjacent the upper surface of the fixed layer. The method further includes forming a free layer between the sidewall portions of the barrier layer and over the central portion of the barrier layer. | 2016-04-21 |
20160111630 | SEMICONDUCTOR DEVICE HAVING MAGNETIC SHIELD LAYER SURROUNDING MRAM CHIP - A semiconductor device includes a MRAM chip including a semiconductor substrate and a memory cell array area includes magnetoresistive elements which are provided on the semiconductor substrate, and a magnetic shield layer surrounding the memory cell array area in a circumferential direction of the MRAM chip, and having a closed magnetic path. | 2016-04-21 |