16th week of 2010 patent applcation highlights part 38 |
Patent application number | Title | Published |
20100096688 | NON-VOLATILE MEMORY HAVING CHARGE TRAP LAYER WITH COMPOSITIONAL GRADIENT - A flash memory device and method of forming a flash memory device are provided. The flash memory device includes a silicon nitride layer having a compositional gradient in which the ratio of silicon to nitrogen varies through the thickness of the layer. The silicon nitride layer having a compositional gradient of silicon and nitrogen provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device. | 2010-04-22 |
20100096689 | NON-VOLATILE MEMORY DEVICE INCLUDING NITROGEN POCKET IMPLANTS AND METHODS FOR MAKING THE SAME - In a non-volatile memory structure, the source/drain regions are surrounded by a nitrogen-doped region. As a result, an interface between the substrate and the charge trapping layer above the nitrogen-doped region is passivated by a plurality of nitrogen atoms. The nitrogen atoms can improve data retention, and performance of cycled non-volatile memory devices. | 2010-04-22 |
20100096690 | SEMICONDUCTOR DEVICE WITH INCREASED CHANNEL AREA - A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region. | 2010-04-22 |
20100096691 | SEMICONDUCTOR DEVICE HAVING VERTICALLY ALIGNED PILLAR STRUCTURES THAT HAVE FLAT SIDE SURFACES AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having vertically aligned transistors made from pillar structures that have flat side surfaces is presented. The semiconductor device includes a semiconductor substrate, spacers, and gates. The semiconductor substrate has lo pillar structures that have flat side surfaces. The spacers are on sidewalls only on the upper portions of the pillar structures. The gates surround lower portions of the pillar structures. | 2010-04-22 |
20100096692 | SEMICONDUCTOR DEVICE - A semiconductor device of the invention includes: a super junction structure of an n-type pillar layer and a p-type pillar layer; a base layer provided on the p-type pillar layer; a source layer selectively provided on a surface of the base layer; a gate insulating film provided on a portion being in contact with the base layer, a portion being in contact with the source layer and a portion being in contact with the n-type pillar layer on a portion of a junction between the n-type pillar layer and the p-type pillar layer; a control electrode provided opposed to the base layer, the source layer and the n-type pillar layer through the gate insulating film; and a source electrode electrically connected to the base layer, the source layer and the n-type layer. The source electrode is contact with the surface of the n-type pillar layer located between the control electrodes to form a Schottky junction. | 2010-04-22 |
20100096693 | SEMICONDUCTOR DEVICE WITH VERTICAL GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate; a plurality of active pillars formed over the substrate; bulb-type trenches, each of the bulb-type trenches formed inside the substrate between the active pillars; buried bit lines, each of the buried bit lines being formed on a sidewall of a respective one of the bulb-type trenches; and vertical gates, each of the vertical gates being formed to surround a sidewall of a respective one of the active pillars. | 2010-04-22 |
20100096694 | PLANAR EXTENDED DRAIN TRANSISTOR AND METHOD OF PRODUCING THE SAME - A planar extended drain transistor ( | 2010-04-22 |
20100096695 | HIGH STRESS FILM - A semiconductor device that includes a substrate having an active region prepared with a transistor is presented. The semiconductor device includes a stress structure adjacent to the substrate. The stress structure includes a dielectric layer having nanocrystals embedded therein. The nanocrystals induce a first or a second stress on a channel region of the transistor which improves carrier mobility of the transistor. | 2010-04-22 |
20100096696 | SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTOR FOR USE AS A HIGH-SPEED SWITCHING DEVICE AND A POWER DEVICE - A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film. | 2010-04-22 |
20100096697 | HIGH VOLTAGE DEVICE HAVING REDUCED ON-STATE RESISTANCE - A semiconductor device includes a semiconductor substrate, a source region and a drain region formed in the substrate, a gate structure formed on the substrate disposed between the source and drain regions, and a first isolation structure formed in the substrate between the gate structure and the drain region, the first isolation structure including projections that are located proximate to an edge of the drain region. Each projection includes a width measured in a first direction along the edge of the drain region and a length measured in a second direction perpendicular to the first direction, and adjacent projections are spaced a distance from each other. | 2010-04-22 |
20100096698 | STRESS ENHANCED TRANSISTOR - Stress enhanced MOS transistors are provided. A semiconductor device is provided that comprises a semiconductor-on-insulator structure, a gate insulator layer, a source region, a drain region and a conductive gate overlying the gate insulator layer. The semiconductor-on-insulator structure comprises: a substrate, a semiconductor layer, and an insulating layer disposed between the substrate and the semiconductor layer. The semiconductor layer has a first surface, a second surface and a first region. The gate insulator layer overlies the first region, the conductive gate overlies the gate insulator layer, and the source region and the drain region overlie the first surface and comprise a strain-inducing epitaxial layer | 2010-04-22 |
20100096699 | PREVENTION OF PLASMA INDUCED DAMAGE ARISING FROM ETCHING OF CRACK STOP TRENCHES IN MULTI-LAYERED LOW-K SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device begins by forming a lower interconnection dielectric on a substrate and forming at least one active or passive device in the lower interconnection dielectric. An etch stop layer is formed on the lower interconnection dielectric and an interconnect stack layer is formed on the etch stop layer. At least one interconnect trench structure and at least one crack stop trench are etched in the interconnect stack layer while maintaining electrical isolation between the interconnect structure and the crack stop trench. | 2010-04-22 |
20100096700 | METHOD FOR FABRICATING ASYMMETRIC DOUBLE-GATE TRANSISTORS BY WHICH ASYMMETRIC AND SYMMETRIC DOUBLE-GATE TRANSISTORS CAN BE MADE ON THE SAME SUBSTRATE - A method for fabricating a microelectronic device with one or several asymmetric and symmetric double-gate transistors on the same substrate. | 2010-04-22 |
20100096701 | Semiconductor Device and Method of Manufacturing the Same - A method of manufacturing a semiconductor device and a semiconductor device manufactured by the method, the method comprising: (a) forming a buffer layer on a semiconductor substrate; (b) patterning the buffer layer in a first direction to form buffer layer patterns having lateral surfaces and being spaced from each other at predetermined intervals; (c) forming a semiconductor epitaxial layer on and between the buffer layer patterns; (d) forming a first trench in the semiconductor epitaxial layer in a second direction perpendicular to the first direction to expose lateral surfaces of the buffer layer patterns; (e) selectively removing the buffer layer patterns exposed by the first trench to form spaces; (f) forming buried insulation films in the spaces formed by removal of the buffer layer patterns, a portion of semiconductor epitaxial layer being disposed between the buried insulation films; (g) removing a portion of the semiconductor epitaxial layer disposed between the buried insulation films to form a second trench in the first direction; and (h) forming device isolation films in the first and second trenches. | 2010-04-22 |
20100096702 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device including a substrate, a high voltage device, a medium voltage device and a low voltage device is provided. The substrate includes a high voltage circuit area, a medium voltage circuit area and a low voltage circuit area. The high voltage device, the medium voltage device and the low voltage device are respectively disposed in the high voltage circuit area, the medium voltage circuit area and the low voltage circuit area. The medium voltage device and the high voltage device have the same structure while the medium voltage device and the low voltage device have different structures. Further, the high voltage device, the medium voltage device and the low voltage device respectively include a first gate dielectric layer, a second gate dielectric layer and a third gate dielectric layer, and the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer. | 2010-04-22 |
20100096703 | Semiconductor device and manufacturing method thereof - Flexibility for the design of the pattern layout of the gate lead-out electrode and the source electrode is enhanced without increasing the chip thickness of the semiconductor device. A semiconductor device includes a cell region where plural transistor cells are arranged and a gate finger region different from a region where the cell region is formed. In the cell region, a gate electrode formed of a polysilicon (first conductive material) is formed. A polysilicon layer formed indivisibly with the gate electrode is formed in the gate finger region. An adhesion metal layer and a wiring metal layer are formed above the polysilicon layer by a lift-off method. The gate lead-out electrode is formed of a laminate structure including the polysilicon layer, the adhesion metal layer, and the wiring metal layer. A single layer of interlayer insulation film covering them is formed, on which a source electrode is formed. | 2010-04-22 |
20100096704 | Suspended nanochannel transistor structure and method for fabricating the same - The present invention discloses a suspended nanochannel transistor structure and a method for fabricating the same. The transistor structure of the present invention comprises a substrate; a side gate formed on the substrate; a dielectric layer covering the substrate and the side gate; a suspended nanochannel formed beside the lateral of the side gate with an air gap existing between the suspended nanochannel and the dielectric layer; a source and a drain formed over the dielectric layer and respectively arranged at two ends of the suspended nanochannel. The electrostatic force of the side gate attracts or repels the suspended nanochannel and thus fast varies the equivalent thickness of the side-gate dielectric layer. Thereby, the on/off state of the element is rapidly switched, or the initial voltage of the channel is altered. | 2010-04-22 |
20100096705 | IMPLANTATION METHOD FOR REDUCING THRESHOLD VOLTAGE FOR HIGH-K METAL GATE DEVICE - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a high-k dielectric layer over a semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a metal layer over the capping layer, forming a semiconductor layer over the metal layer, performing an implantation process on the semiconductor layer, the implantation process using a species including F, and forming a gate structure from the plurality of layers including the high-k dielectric layer, capping layer, metal layer, and semiconductor layer. | 2010-04-22 |
20100096706 | SEMICONDUCTOR TRANSISTORS HAVING HIGH-K GATE DIELECTRIC LAYERS, METAL GATE ELECTRODE REGIONS, AND LOW FRINGING CAPACITANCES - A semiconductor structure. The structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a gate dielectric region, and (iv) a gate electrode region, (v) a plurality of interconnect layers on the gate electrode region, and (vi) first and second spaces. The gate dielectric region is disposed between and in direct physical contact with the channel region and the gate electrode region. The gate electrode region is disposed between and in direct physical contact with the gate dielectric region and the interconnect layers. The first and second spaces are in direct physical contact with the gate electrode region. The first space is disposed between the first source/drain region and the gate electrode region. The second space is disposed between the second source/drain region and the gate electrode region. | 2010-04-22 |
20100096707 | Method for Forming Insulation Film - In a process involving the formation of an insulating film on a substrate for an electronic device, the insulating film is formed on the substrate surface by carrying out two or more steps for regulating the characteristic of the insulating film involved in the process under the same operation principle. The formation of an insulating film having a high level of cleanness can be realized by carrying out treatment such as cleaning, oxidation, nitriding, and a film thickness reduction while avoiding exposure to the air. Further, carrying out various steps regarding the formation of an insulating film under the same operation principle can realize simplification of the form of an apparatus and can form an insulating film having excellent property with a high efficiency. | 2010-04-22 |
20100096708 | Chip Module for Installing in Sensor Chip Cards for Fluidic Applications and Method for Producing a Chip Module of This Type - A plate-shaped chip supporting body has a number of write/read contacts for exchanging data with an external chip card. A number of corresponding terminal panels which are electrically connected to the write/read contacts of the front flat side, are arranged on the opposite rear side of the chip supporting body. A sensor ship is attached to the rear side of the chip supporting body and has contact pads electrically connected to the terminal panels of the chip supporting body. Contact panels on the flat side of the sensor chip are oriented toward the chip supporting body and are connected to the pad contact, which are located on the opposite flat side of the sensor chip, by at least one electrical signal line path passing through the sensor chip, and the contact panels are connected to the terminal panels of the chip supporting body by electrically conductive material. | 2010-04-22 |
20100096709 | UNCOOLED IR DETECTOR ARRAYS BASED ON NANOELECTROMECHANICAL SYSTEMS - We describe the use of a high-quality-factor torsional resonator of microscale dimensions. The resonator has a paddle that is supported by two nanoscale torsion rods made of a very low thermal conductivity material, such as amorphous (“a-”) silicon. The body of the torsion paddle is coated with an infrared-absorbing material that is thin and light weight, but provides sufficient IR absorption for the applications. It may be placed above a reflecting material of similar dimensions to form a quarter wave cavity. Sensing of the response of the paddle to applied electromagnetic radiation provides a measure of the intensity of the radiation as detected by absorption, and the resulting temperature change, in the paddle. | 2010-04-22 |
20100096710 | SEMICONDUCTOR FINGERPRINT APPARATUS WITH FLAT TOUCH SURFACE - In a fingerprint apparatus, fingerprint sensing members disposed on a silicon substrate detect skin textures of a finger placed thereon to generate electric signals. A set of integrated circuits formed on the substrate processes the electric signals. First bonding pads are disposed on the substrate and electrically connected to the set of integrated circuits. A first insulating layer is disposed below the first bonding pads. Metal plugs penetrating through the substrate are respectively electrically connected to the first bonding pads. A second insulating layer is formed on the substrate and between the metal plugs and the substrate. Second bonding pads are formed on a rear side of the second insulating layer, and are respectively electrically connected to the first bonding pads through the metal plugs. The protection layer is disposed on the substrate and covers the sensing members to form a flat touch surface to be touched by the finger. | 2010-04-22 |
20100096711 | MICROELECTROMECHANICAL SYSTEM MICROPHONE PACKAGE - An MEMS microphone package includes a substrate, a cover, a plurality of conductive members, and an insulative adhesive. The cover is mounted to the substrate. The conductive members are disposed between the substrate and the cover. Each of the conductive members can be a golden wire, a conductive bump, or a conductive metal. Upper ends of the conductive members are connected with the cover and the lower ends of the conductive members are connected with the substrate to enable a conductive loop. The insulative adhesive encapsulates the conductive members. In this way, the substrate, the conductive members, and the cover jointly construct a shielding against EMI. | 2010-04-22 |
20100096712 | HERMETIC SEALING AND ELECTRICAL CONTACTING OF A MICROELECTROMECHANICAL STRUCTURE, AND MICROSYSTEM (MEMS) PRODUCED THEREWITH - Disclosed are methods and microsystems for vertically through-plating ( | 2010-04-22 |
20100096713 | MEMS PACKAGE AND PACKAGING METHOD THEREOF - Provided are a Micro Electro-Mechanical System (MEMS) package and a method of packaging the MEMS package. The MEMS package includes: a MEMS device including MEMS structures formed on a substrate, first pad electrodes driving the MEMS structures, first sealing parts formed at an edge of the substrate, and connectors formed on the first pad electrodes and the first sealing parts; and a MEMS driving electronic device including second pad electrodes and second sealing parts respectively corresponding to the first pad electrodes and the first sealing parts to be sealed with and bonded to the MEMS device through the connectors to form an air gap having a predetermined width. | 2010-04-22 |
20100096714 | METHOD OF MANUFACTURING MEMS SENSOR AND MEMS SENSOR - A method of manufacturing an MEMS sensor according to the present invention includes the steps of: forming a first sacrificial layer on one surface of a substrate; forming a lower electrode on the first sacrificial layer; forming a second sacrificial layer made of a metallic material on the first sacrificial layer to cover the lower electrode; forming an upper electrode made of a metallic material on the second sacrificial layer; forming a protective film made of a nonmetallic material on the substrate to collectively cover the first sacrificial layer, the second sacrificial layer and the upper electrode; and removing at least the second sacrificial layer by forming a through-hole in the protective film and supplying an etchant to the inner side of the protective film through the through-hole. | 2010-04-22 |
20100096715 | MAGNETIC RANDOM ACCESS MEMORY - A magnetic recording layer | 2010-04-22 |
20100096716 | SPIN-TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY HAVING MAGNETIC TUNNEL JUNCTION WITH PERPENDICULAR MAGNETIC ANISOTROPY - A spin-torque transfer memory random access memory (STTMRAM) element includes a fixed layer formed on top of a substrate and a a tunnel layer formed upon the fixed layer and a composite free layer formed upon the tunnel barrier layer and made of an iron platinum alloy with at least one of X or Y material, X being from a group consisting of: boron (B), phosphorous (P), carbon (C), and nitride (N) and Y being from a group consisting of: tantalum (Ta), titanium (Ti), niobium (Nb), zirconium (Zr), tungsten (W), silicon (Si), copper (Cu), silver (Ag), aluminum (Al), chromium (Cr), tin (Sn), lead (Pb), antimony (Sb), hafnium (Hf) and bismuth (Bi), molybdenum (Mo) or rhodium (Ru), the magnetization direction of each of the composite free layer and fixed layer being substantially perpendicular to the plane of the substrate. | 2010-04-22 |
20100096717 | ELECTRONIC DEVICE AND PROCESS FOR MANUFACTURING ELECTRONIC DEVICE - To reduce cracks in a functional unit of a semiconductor element in a process for manufacturing an electronic device, a frame member surrounds a functional unit and an optically-transparent layer is formed on a wafer. A resin layer is formed by injecting resin into a cavity of an encapsulating metallic mold while a molding surface of the encapsulating metallic mold segment contacts an upper surface of the frame member. After forming the resin layer, an optically-transparent layer is formed inside the frame member. The resin layer is formed by injecting resin while the frame member contacts the molding surface of the encapsulating metallic mold segment. Therefore, pressure applied in the encapsulation is exerted over the frame member around the functional unit. Further, the optically-transparent layer is formed after encapsulation. This avoids pressure applied to the functional unit from the contact of the encapsulating metallic mold segment with the optically-transparent layer. | 2010-04-22 |
20100096718 | BACKSIDE ILLUMINATED IMAGE SENSOR - A backside illuminated image sensor includes a substrate, a backside passivation layer disposed on backside of the substrate, and a transparent conductive layer disposed on the backside passivation layer. | 2010-04-22 |
20100096719 | METHODS OF FORMING FINE PATTERNS IN INTEGRATED CIRCUIT DEVICES - A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are isotropically etched to remove the etch mask pattern from the first mask structure while maintaining at least a portion of the etch mask pattern on the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region using the portion of the etch mask pattern on the second mask structure as a mask to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region. The feature layer may be patterned using the first mask pattern as a mask to define a first feature on the first region, and using the second mask pattern as a mask to define a second feature on the second region having a greater width than the first feature. | 2010-04-22 |
20100096720 | SOI SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - To provide an SOI substrate having a high mechanical strength, and a method for manufacturing the SOI substrate, a single crystal semiconductor substrate is irradiated with accelerated ions so that an embrittled region is formed in a region at a predetermined depth from a surface of the single crystal semiconductor substrate; the single crystal semiconductor substrate is bonded to a base substrate with an insulating layer interposed therebetween; the single crystal semiconductor substrate is heated to be separated along the embrittled region, so that a semiconductor layer is provided over the base substrate with the insulating layer interposed therebetween; and a surface of the semiconductor layer is irradiated with a laser beam so that at least a superficial part of the semiconductor layer is melted, whereby at least one of nitrogen, oxygen, and carbon is solid-dissolved in the semiconductor layer. | 2010-04-22 |
20100096721 | Semiconductor device production method and semiconductor device - A semiconductor device production method according to the present invention includes the steps of: forming a LOCOS oxide film in a surface of a silicon layer by a LOCOS method; forming an impurity region in the silicon layer by introducing an impurity into the silicon layer; and sequentially removing parts of the LOCOS oxide film and the silicon layer to form a trench for isolation of the impurity region after the formation of the LOCOS oxide film and the impurity region. | 2010-04-22 |
20100096722 | Fuse in a Semiconductor Device and Method for Fabricating the Same - The present invention relates to a fuse in a semiconductor device and method for fabricating the same. An oxide film is formed on sidewalls of a barrier metal layer in a bottom portion of a fuse pattern, thereby preventing the barrier metal layer from being exposed. As a result, the oxidation of the barrier metal layer is inhibited to improve characteristics of the device. | 2010-04-22 |
20100096723 | Semiconductor device - A semiconductor device includes an electric fuse and first and second large area wirings for applying a voltage to the electric fuse. The electric fuse includes a fuse unit which includes an upper-layer fuse wiring, a lower-layer fuse wiring, and a via connecting the upper-layer fuse wiring and the lower-layer fuse wiring, an upper-layer lead-out wiring which connects the upper-layer fuse wiring and the first large area wiring and has a bent pattern, and a lower-layer lead-out wiring which connects the lower-layer fuse wiring and the second large area wiring and has a bent pattern. | 2010-04-22 |
20100096724 | Semiconductor device - A semiconductor device ( | 2010-04-22 |
20100096725 | Semiconductor Package with Embedded Spiral Inductor - In some embodiments, the semiconductor package includes a substrate having multiple layers, from a first layer to a final layer, a die coupled to the first layer, an electrical connector such as a solder ball coupled to the final layer, and a spiral trace disposed and electrically coupled between the die and the electrical connector. Inductance of the spiral trace is selected such that the package has a predetermined impedance. Material, cross-sectional area, number and density of windings, and total overall length of the spiral trace are selected accordingly. In other embodiments, the semiconductor package includes a substrate with multiple layers; a die coupled to the first of the layers; an electrical connector coupled to the final layer; and a spiral trace, in or on the substrate. The spiral trace is near the die, and electrically coupled between the die and the electrical connector. | 2010-04-22 |
20100096726 | METAL CAPACITOR AND METHOD OF MAKING THE SAME - A method of making a metal capacitor includes the following steps. A dielectric layer having a metal interconnection and a capacitor electrode is provided. Then, a treatment is performed to increase the dielectric constant of the dielectric layer surrounding the capacitor electrode. The treatment can be UV radiation, a plasma treatment or an ion implantation. Accordingly, the metal capacitor will have a higher capacitance and RC delay between the metal interconnection and the dielectric layer can be prevented. | 2010-04-22 |
20100096727 | SEMI-CONDUCTOR SUBSTRATE AND METHOD OF MASKING LAYER FOR PRODUCING A FREE-STANDING SEMI-CONDUCTOR SUBSTRATE BY MEANS OF HYDRIDE-GAS PHASE EPITAXY - The invention relates to a free-standing semiconductor substrate as well as a process and a mask layer for the manufacture of a free-standing semiconductor substrate, wherein the semiconductor substrate self-separates from the starting substrate without further process steps. | 2010-04-22 |
20100096728 | Nitride semiconductor sustrate and method of fabricating the same. - A nitride semiconductor substrate includes a front surface, a rear surface on an opposite side to the front surface, and a first edge portion including a chamfered edge on the front surface. A ratio of an average surface roughness of the front surface to an average surface roughness of the first edge portion is not more than 0.01. The substrate may include a second edge portion including a chamfered edge on the rear surface. A ratio of an average surface roughness of the rear surface to an average surface roughness of the second edge portion is not more than 0.01. The first edge portion has a visible light transmissivity not more than 0.2 times that of the front surface. The second edge portion has a visible light transmissivity not more than 0.2 times that of the rear surface. | 2010-04-22 |
20100096729 | GEOMETRY AND DESIGN FOR CONFORMAL ELECTRONICS - A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being located to allow the two-dimensional substrate to be shaped, the cuts having at least one stress relief feature, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure, the stress relief features arranged to alleviate stress in the three-dimensional structure. A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being arranged to as to increase a radius of curvature to meet a stress relief parameter when the substrate is shaped, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure. A three-dimensional electronic device having an electronic device formed on a flexible substrate, the flexible substrate formed into a three-dimensional structure, wedged-shaped portions removed from the substrate to allow the substrate to be formed into the three-dimensional structure, and a stress relief feature arranged adjacent to the wedge-shaped portions. | 2010-04-22 |
20100096730 | PASSIVATION TECHNIQUE - A method of semiconductor wafer fabrication. The wafer is fabricated by receiving a semiconductor wafer having a substrate layer and at least one processed layer, cutting a trench into the wafer, wherein the trench penetrates through the at least one processed layer and only partially through the thickness of the substrate layer, and depositing a passivation layer over the at least one processed layer such that the trench is filled with the passivation material. | 2010-04-22 |
20100096731 | Semiconductor Device and Method of Forming Stepped-Down RDL and Recessed THV in Peripheral Region of the Device - A semiconductor die has a peripheral region around the die. An insulating layer is formed over the semiconductor die. A portion of the insulating layer and peripheral is removed to form a recess around the semiconductor die. A conductive layer is deposited over the insulating layer and recess. The conductive layer is electrically connected to contact pads on the semiconductor die and conforms to a step into the recess. A gap is created through the conductive layer and peripheral region around the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. The conductive THV is recessed with respect to a surface of the semiconductor die. The conductive THV is electrically connected to the conductive layer. | 2010-04-22 |
20100096732 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Interconnections are formed over an interlayer insulating film which covers MISFETQ | 2010-04-22 |
20100096733 | PROCESS FOR FABRICATING A SUBSTRATE COMPRISING A DEPOSITED BURIED OXIDE LAYER - A process for fabricating a substrate that includes a buried oxide layer for the production of electronic components or the like. The process includes depositing an oxide layer or a nitride layer on either of a donor or receiver substrate, and bringing the donor and receiver substrates into contact; conducting at least a first heat treatment of the oxide or nitride layer before bonding the substrates, and conducting a second heat treatment of the fabricated substrate of the receiver substrate, the oxide layer and all or part of the donor substrate at a temperature equal to or higher than the temperature applied in the first heat treatment. Substrates that have an oxide or nitride layer deposited thereon wherein the oxide or nitride layer is degassed and has a refractive index smaller than the refractive index of an oxide or nitride layer of the same composition formed by thermal growth. | 2010-04-22 |
20100096734 | THERMALLY IMPROVED SEMICONDUCTOR QFN/SON PACKAGE - A semiconductor device without cantilevered leads uses conductive wires ( | 2010-04-22 |
20100096735 | CLAMPING ASSEMBLY - A clamping assembly for clamping a lead frame with pre-attached semiconductor device, comprising of: a first member, to hold the lead frame, said first member having a surface profile in contact with a surface profile of the semiconductor device, a second member for allowing the mounting of the first member thereon, an attachment means to secure the first member onto the second member, wherein the attachment means is adjustable to conform the surface profile of the first member to the surface profile of the lead frame. | 2010-04-22 |
20100096736 | Semiconductor Device and Manufacturing Method Thereof - A structure capable of changing the characteristic value of an element after the formation of the element in order to prevent the increase of the manufacturing cost and delay in the delivery of a product. A plurality of diodes is connected in series. Then, a part of the plurality of diodes is short-circuited by a wiring. In specific, a diode and a wiring are connected in parallel, whereby a current flows preferentially into the wiring, so that the diode can be regarded as nonexistent. Then, the wiring is cut at a part of the wiring, thereby having the diode which is connected to the wiring in parallel before the cutting functioning. | 2010-04-22 |
20100096737 | STACKABLE SEMICONDUCTOR ASSEMBLIES AND METHODS OF MANUFACTURING SUCH ASSEMBLIES - Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor assembly includes forming a plurality of first side trenches to a first intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes forming a plurality of lateral contacts at sidewall portions of the trenches and electrically connecting first side bond-sites of the dies with corresponding lateral contacts of the trenches. The method further includes forming a plurality of second side channels to a second intermediate depth in the molded portion such that the channels intersect the trenches. The method also includes singulating and stacking the first and second dies with the channels associated with the first die aligned with channels associated with the second die. The method further includes attaching a lead frame to the lateral contacts of the stacked first and second dies. | 2010-04-22 |
20100096738 | IC DIE HAVING TSV AND WAFER LEVEL UNDERFILL AND STACKED IC DEVICES COMPRISING A WORKPIECE SOLDER CONNECTED TO THE TSV - A method of forming integrated circuit (IC) die configured for attachment to another die or a package substrate, and stacked IC devices therefrom. At least one IC die having a top semiconductor surface and a bottom surface and at least one through substrate via (TSV) including a tip protruding beyond the bottom surface to a tip length is provided. The tip has an outer dielectric tip liner, and an electrically conductive portion within the outer dielectric tip liner. A compliant layer is applied to the bottom surface of the IC die. The dielectric tip liner is removed from a distal portion of the tip to expose an electrically conductive tip portion. A solder material is deposited on the exposed distal portion of the tip. The solder material is reflowed and coalesced to form a solder bump on the distal portion of the tip. | 2010-04-22 |
20100096739 | STACKED SEMICONDUCTOR MODULE - A stacked semiconductor module is made by stacking a second semiconductor device having a second semiconductor chip mounted to the top surface of a second semiconductor substrate above the top surface of a first semiconductor device having a first semiconductor chip mounted to a first semiconductor substrate. The top surface of the first semiconductor substrate is provided with a first connection terminal and the bottom surface of the first semiconductor substrate is provided with an external connection terminal. A region of the bottom surface of the second semiconductor substrate lying opposite to the second semiconductor chip is provided with a second connection terminal. A conductive connecting member connects the first connection terminal to the second connection terminal. | 2010-04-22 |
20100096740 | STACKED TYPE CHIP PACKAGE STRUCTURE - A stacked type chip package structure including a backplate, a circuit substrate, a first chip, a second chip, and a conductive film is provided. The backplate comprises a circuit layer. The circuit substrate is disposed on the backplate, and has an upper surface and an opposite lower surface. Besides, the circuit substrate has a receiving hole corresponding to the backplate. The first chip is disposed inside the receiving hole, and the first chip is electrically connected to the circuit substrate through the circuit layer of the backplate. The second chip is disposed above the first chip, and is electrically connected to the circuit substrate. The conductive film is disposed between the first chip and the second chip, wherein the conductive film is electrically connected to a ground of the circuit substrate. | 2010-04-22 |
20100096741 | Chip-Stacked Package Structure and Method for Manufacturing the Same - A chip stacked package structure and applications are provided. The chip-stacked package structure includes a main substrate, a baseboard substrate, and a molding compound. The main substrate has a substrate and a first chip. The substrate has a first surface and a second surface opposite to the first surface. The first chip is disposed on the first surface and electrically connected to the substrate via first bumps. The baseboard substrate has a third surface and a fourth surface faced towards the substrate. The baseboard substrate includes a core layer having a plurality of first through holes and a first accommodation space in which the first chip is received. The second chip is disposed on the third surface of the baseboard substrate. The molding compound is used to encapsulate the main substrate, and the baseboard substrate. | 2010-04-22 |
20100096742 | CUT-OUT HEAT SLUG FOR INTEGRATED CIRCUIT DEVICE PACKAGING - In a package, a heat slug, encapsulated by molding compound, encases an integrated circuit device (IC). In an example embodiment, a semiconductor package structure comprises a substrate having conductive traces and pad landings. The conductive traces have pad landings. An IC is mounted on the substrate. The IC has bonding pads. With conductive wires, the IC bonding pads are connected to the pad landings, which in turn, are connected to the conductive traces. A heat slug, having predetermined height, is disposed on the substrate surface. The heat slug includes a plurality of mounting feet providing mechanical attachment to the substrate. A cavity in the heat slug accommodates the IC. A plurality of first-size openings surrounds the IC. A second-size opening constructed from one of the first size-openings, is larger than the first-size opening. The second size-opening facilitates the introduction of molding compounds into the cavity of the heat slug. | 2010-04-22 |
20100096743 | Input/output package architectures, and methods of using same - A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s. | 2010-04-22 |
20100096744 | PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME - Embodiments of the present invention provide a printed wiring board in which solder bumps of a mounted semiconductor chip are less prone to be ruptured. The printed wiring board includes a coreless substrate which includes: a dielectric layer having a main surface and a connecting pad embedded in the dielectric layer. The connecting pad is shaped like a brimmed hat. That is, the connecting pad includes a plate portion whose diameter φ | 2010-04-22 |
20100096745 | BONDED WAFER STRUCTURE AND METHOD OF FABRICATION - A method of packaging electronics comprises providing a first wafer and providing a second wafer. The method also comprises depositing a polymer material over a surface of the first wafer; and selectively removing a portion of the polymer from the first wafer to create a void in the polymer. The method also comprises placing the first wafer over the second wafer and in contact with the polymer; and curing the polymer to bond the first wafer to the second wafer. A bonded wafer structure is also described. | 2010-04-22 |
20100096746 | PACKAGE MODULE STRUCTURE OF COMPOUND SEMICONDUCTOR DEVICES AND FABRICATING METHOD THEREOF - A compound semiconductor device package module structure includes a heat dissipation film, a dielectric layer, a plurality of compound semiconductor dies, means for mounting the compound semiconductor dies on the heat dissipation film, and a transparent encapsulation material. The dielectric layer includes a plurality of openings formed on the heat dissipation film. The compound semiconductor dies are placed on the heat dissipation film in the openings, and adjacent two compound semiconductor dies are separated by the dielectric layer. The transparent encapsulation material covers the compound semiconductor dies. | 2010-04-22 |
20100096747 | Semiconductor device and method of manufacturing the same - A semiconductor device includes: a substrate; a semiconductor chip with a surface facing down mounted on the substrate; a reinforcement material provided on the substrate in a peripheral region of a region on which the semiconductor chip is mounted; and a heat sink coupled to the semiconductor chip via a highly thermally conductive material. The heat sink is disposed on the semiconductor chip and the reinforcement material by being coupled to the reinforcement material via an adhesive material, and is provided with an uneven area on a side coupled to the reinforcement material. | 2010-04-22 |
20100096748 | Combined semiconductor apparatus with semiconductor thin film - A combined semiconductor apparatus includes a semiconductor substrate having an integrated circuit, a planarized region formed in a surface of the semiconductor substrate, and a semiconductor thin film including at least one semiconductor device and bonded on the planarized region. A surface of the semiconductor thin film, in which the semiconductor device is formed, is disposed on a side of the planarized region. The apparatus may further include a planarized film disposed between the planarized region and the semiconductor thin film. | 2010-04-22 |
20100096749 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - Disclosed are a semiconductor package and a manufacturing method thereof. The semiconductor package can include a semiconductor substrate, having one surface on which a conductive pad is formed; an insulating layer, being formed on one surface of the semiconductor substrate; a metal post, penetrating through the conductive pad, the semiconductor substrate, and the insulating layer; and an outer-layer circuit, being electrically connected to the metal post. With the present invention, it can become unnecessary to form an additional via for electrically connecting both surfaces of the semiconductor substrate, thereby simplifying the manufacturing process, reducing the manufacturing cost, and improving the coupling reliability. | 2010-04-22 |
20100096750 | Packaging substrate - A packaging substrate is disclosed, which comprises: a substrate body, wherein a surface thereof has a plurality of conductive pads and a solder mask disposed on the surface and having a plurality of openings to expose the conductive pads; dielectric rings disposed on the inner walls of the openings and extending to parts of the surface of the solder mask surrounding the openings; and metal bumps disposed in the openings and on the conductive pads exposed thereby, and combined with the dielectric rings. | 2010-04-22 |
20100096751 | SEMICONDUCTOR DEVICE - A semiconductor device, includes: an organic multilayer wiring substrate having an inner conductive layer; a semiconductor element mounted and connected on one surface of the wiring substrate; and a plurality of solder balls disposed on the other surface in a grid array. A defect portion is formed at an area corresponding to a corner solder ball disposed at an outer peripheral corner, or at an area corresponding to the corner solder ball and peripheral solder balls at the inner conductive layer. Temperature rises of the solder balls disposed in a vicinity of the corner are suppressed, and therefore, the semiconductor device of which fatigue life is prolonged and superior in reliability can be obtained. | 2010-04-22 |
20100096752 | SEMICONDUCTOR DEVICE - A semiconductor device according to an aspect of the present invention comprises a package board having first and second surfaces, first external terminals on the first surface which are arranged in matrix, and second external terminals on the first surface which are arranged apart from the first external terminals. Each of the second external terminals includes first and second through holes which extend from the first surface to the second surface, and a metal layer on the first surface which is provided between the first and second through holes. The metal layer passes through the first and second through holes to the second surface. | 2010-04-22 |
20100096753 | THROUGH-SILICON VIA STRUCTURES PROVIDING REDUCED SOLDER SPREADING AND METHODS OF FABRICATING THE SAME - A microelectronic device structure as provided herein includes a conductive via having a body portion extending into a substrate from an upper surface thereof and a connecting portion laterally extending along the upper surface of the substrate. The connecting portion includes a recess therein opposite the upper surface of the substrate. The recess is confined within the connecting portion of the conductive via and does not extend beneath the upper surface of the substrate. A microelectronic device structure is also provided that includes a conductive via having a body portion extending into a substrate from an upper surface thereof and an end portion below the upper surface of the substrate. The end portion has a greater width than that of the body portion. A solder wettable layer is provided on the end portion. The solder wettable layer is formed of a material having a greater wettability with a conductive metal than that of the end portion of conductive via. Related methods of fabrication are also discussed. | 2010-04-22 |
20100096754 | Semiconductor package, semiconductor module, and method for fabricating the semiconductor package - Provided is a semiconductor package, a semiconductor module and a method for fabricating the semiconductor package. The method provides a substrate including a bonding pad. The method forms a dielectric layer for exposing the bonding pad on the substrate. The method forms a redistribution line which is electrically connected to the bonding pad, on the dielectric layer. The method forms an external terminal which is electrically connected to the bonding pad without using a solder mask which limits a position of the external terminal, on the redistribution line. | 2010-04-22 |
20100096755 | Wiring structure and method for fabricating the same - A wiring structure has a silicon layer, a backing layer provided on the silicon layer, the backing layer comprising a copper alloy containing a manganese, and a copper layer provided on the backing layer, and a diffusion barrier layer having an electrical conductivity, the diffusion barrier layer being provided at a region including an interface between the silicon layer and the backing layer, in which a manganese in the diffusion barrier layer is enriched compared with the backing layer. | 2010-04-22 |
20100096756 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a multilayer interconnection including a copper interconnection film formed in a predetermined area within an insulating film, a liner film, and a high-melting-point metal film. The copper interconnection film is polycrystalline, and crystal grains occupying 40% or more of an area of a unit interconnection surface among crystal grains forming the polycrystal are oriented to (111) in a substrate thickness direction. The copper interconnection film has crystal conformity with the noble metal liner film. In a case where the high-melting-point metal film is formed of Ti and the noble metal liner film is a Ru film, the high-melting-point metal of Ti dissolves into Ru in a solid state to form the noble metal liner. Thus, a copper interconnection is formed with both of Cu diffusion barrier characteristics and Cu crystal conformity. | 2010-04-22 |
20100096757 | Method and System for Distributing Clock Signals on Non Manhattan Semiconductor Integrated Circuits - The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that a rotated recursive H clock signal structure is rendered. In another embodiment, a recursive Y structure is used to create a clock signal structure. The recursive Y structure may also be implemented in a rotated alignment. For clock signal redundancy, non Manhattan wiring may be used to create a clock signal mesh network. | 2010-04-22 |
20100096758 | ELECTRIC POWER SEMICONDUCTOR DEVICE - An electric power semiconductor device including first and second circuit patterns formed on main surfaces of first and second insulating substrates, respectively, first and second semiconductor chips mounted on the first and second circuit patterns, respectively, a multilayer electrode plate assembly disposed between the first and second insulating substrates, having first, second and third electrode terminals provided with a distance from each other, a first connecting conductor made by wire bonding for connecting the first and second semiconductor chips to the first and second electrode terminals, and a second connecting conductor having an extending portion extended from a part of the third electrode terminal to be connected to the second circuit pattern, and the connection between the extending portion of the third electrode terminal and the second circuit pattern is implemented by a solder. | 2010-04-22 |
20100096759 | SEMICONDUCTOR SUBSTRATES WITH UNITARY VIAS AND VIA TERMINALS, AND ASSOCIATED SYSTEMS AND METHODS - Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in a semiconductor substrate, applying a protective layer to a sidewall surface of the via, and forming a terminal opening by selectively removing substrate material from an end surface of the via, while protecting from removal substrate material against which the protective coating is applied. The method can further include disposing a conductive material in both the via and the terminal opening to form an electrically conductive terminal that is unitary with conductive material in the via. Substrate material adjacent to the terminal can then be removed to expose the terminal, which can then be connected to a conductive structure external to the substrate. | 2010-04-22 |
20100096760 | Bond Pad Design with Reduced Dishing Effect - An integrated circuit structure includes a semiconductor chip, which further includes a first surface; and a patterned bond pad exposed through the first surface. The patterned bond pad includes a plurality of portions electrically connected to each other, and at least one opening therein. The integrated circuit further includes a dielectric material filled into at least a portion of the at least one opening. | 2010-04-22 |
20100096761 | SEMICONDUCTOR SUBSTRATE FOR BUILD-UP PACKAGES - The present invention provides techniques to fabricate build-up single or multichip modules. In one embodiment, this is accomplished by dispensing die-attach material in one or more pre-etched cavities on a substrate. A semiconductor die is then placed over each pre-etched cavity including the die-attach material by urging a slight downward pressure on the substrate such that an active surface of each placed semiconductor die is disposed across from the substrate and is further substantially coplanar with the substrate. The semiconductor die is then secured to the substrate by curing the die-attach material. A miniature circuit board, including one or more alternating layer of dielectric material and metallization structures, is then formed over the substrate and the active surface of each semiconductor die to electrically interconnect the semiconductor dies. | 2010-04-22 |
20100096762 | Synthesis Method Of Metal Cyclopentadienide In Bulk - The present invention relates to a synthesis method of metal cyclopentadienide by direct reaction of dicyclopentadiene with a group 1 metal in the presence of an aprotic solvent. Unlike the conventional method depending on retro Diels-Alder reaction of dicyclopentadiene to generate indirectly cyclopentadiene, the method of the present invention favors generation of cyclopentadiene and metal cyclopentadienide as well by adding dicyclopentadiene directly when the reaction temperature reaches in the boiling point of a reaction solvent. | 2010-04-22 |
20100096763 | BIOPOLYMER OPTOFLUIDIC DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a biopolymer optofluidic device including providing a biopolymer, processing the biopolymer to yield a biopolymer matrix solution, providing a substrate, casting the biopolymer matrix solution on the substrate, embedding a channel mold in the biopolymer matrix solution, drying the biopolymer matrix solution to solidify biopolymer optofluidic device, and extracting the embedded channel mold to provide a fluidic channel in the solidified biopolymer optofluidic device. In accordance with another aspect, an optofluidic device is provided that is made of a biopolymer and that has a channel therein for conveying fluid. | 2010-04-22 |
20100096764 | Gas Environment for Imprint Lithography - Non-uniformity may be minimized by reducing or eliminating non-uniform evaporation of a viscous liquid disposed on the surface of a substrate. At least one gas source component and one vacuum component may provide a mass flow rate of gas across the surface of the substrate to reduce or eliminate non-uniform evaporation. | 2010-04-22 |
20100096765 | DEVICE FOR PRESS-FORMING A THIN SHEET AND PRESS- FORMING METHOD - A press-forming device includes a punch and a die, as a mold to be measured, and a strain measurement means arranged within the mold and measuring a strain amount generated by press-forming. The strain measurement means is positioned at the press-direction side relative to a radius end of a die shoulder on the material flow-out side when the mold is positioned at a lower dead point of press-forming. The strain measurement means is preferably positioned within a region defined by a surface which is away from the center of curvature of a curved surface of the mold by the distance ten times R, where R is a curvature radius of the curved surface. | 2010-04-22 |
20100096766 | Imprint Lithography System and Method - A loading unit, surface scanning module, and an imprint module may be integrated into a single tool. Template may be loaded on loading unit and positioned within imprint module. Substrate may then be loaded on loading unit and scanned defects using surface scanning module. If substrate passes inspection by surface scanning module, substrate may be positioned imprint module where formable material may be dispensed thereon and imprinted. The imprinted substrate may then be unloaded from imprinting module. | 2010-04-22 |
20100096767 | METHOD AND APPARATUS FOR THE MEASUREMENT OF THE TEMPERATURE OF A PLASTIFIED PLASTIC MATERIAL AT THE EXIT OF AN EXTRUDER - A method for the measurement of the temperature of a plastified plastic material at the exit of an extruder, characterised in that the function of the sound, velocity in dependence of the temperature is measured and memorised for at least one plastified plastic material, the sound velocity is measured during the extrusion of the plastic material, and the respective temperature is determined from the velocity measurement values and the function. | 2010-04-22 |
20100096768 | POLYMER-DISPERSED POLYOL AND PROCESS FOR PRODUCING FLEXIBLE POLYURETHANE FOAM - To provide a process for producing a flexible polyurethane foam having a higher biomass degree than a conventional flexible polyurethane foam and excellent in foam physical properties and its appearance. | 2010-04-22 |
20100096769 | PROCESS FOR PRODUCING FIBER AND METHOD FOR PRODUCING CATALYST LAYER - To provide a process whereby an ultrafine fiber of a fluorinated ion exchange resin can be produced easily at low cost, and a method whereby a catalyst layer having a high gas diffusion property can be produced easily at low cost. | 2010-04-22 |
20100096770 | Method for fabrication of mold for nano imprinting and method for production of photonic crystal using the same - A manufacturing process using a replica mold for nano imprinting having a grid type pattern by combining a nano imprint with a dry etching process is disclosed. In order to attain such a manufacturing process, a method of fabricating a mold for nano imprinting may include arranging a master mold having first patterns over a substrate having metal patterns so that both the first pattern and the metal pattern cross over each other, applying resin between the master mold and the substrate, applying an imprinting treatment of the substrate as well as the master mold, hardening the resin, and etching the hardened resin after the master mold is released, so as to form a replica mold for nano imprint. The nano imprinting process and the etching process may easily form a pattern in a more complicated structure, and therefore, may improve production yield and reduce processing time thereof. | 2010-04-22 |
20100096771 | METHOD FOR FABRICATING INJECTION-MOLDED PRODUCT - A method for fabricating an injection-molded product for a mold in which a pattern carved therein is prepared. An interim injection-molded product with a pattern arranged on an inner face thereof is fabricated using the mold having the carved pattern. Paint or a coloring agent is deposited on the inner face of the molded interim injection-molded product. The pattern on the injection-molded product finished by depositing paint is visible from an exterior of the finished product. | 2010-04-22 |
20100096772 | RELEASE FILM FOR SEMICONDUCTOR RESIN MOLDS - A process of sealing a semiconductor substrate by contacting the semiconductor substrate with a surface of a release layer (I) of a gas barrier release film that is in the form of a mold, which includes vacuum suction; injecting a sealing resin between the semiconductor substrate and the mold; and releasing said mold from said semiconductor substrate having said sealing resin present thereon, where the gas barrier release film has a release layer (I), which has excellent releasability; a plastic support layer (II) supporting the release layer; and a metal or a metal oxide gas restraint layer (III), present between the release layer and the support layer, where the gas barrier release film exhibits a xylene gas permeability of at most 5×10 | 2010-04-22 |
20100096773 | Syringe Body - A method of producing, by injection molding, a hollow cylindrical syringe body which is provided with a scale applied in the longitudinal direction. The scale is applied to a thin carrier film and the carrier film with the scale is inserted into the injection mold prior to the injection molding process. | 2010-04-22 |
20100096774 | IMPRINT LITHOGRAPHY APPARATUS AND METHOD - An imprint lithography apparatus and manufacturing method can lead to mechanical stress being formed in a substrate to which an imprint pattern is being applied. This may cause strain within the substrate leading to misalignment of a subsequent pattern with an earlier pattern in a part of the substrate, which is strained. An apparatus and method is disclosed which allows for stress relaxation in the substrate prior to further patterning to reduce, minimize or prevent such misalignment from residual strain. This is achieved by locally unclamping a portion of substrate (including optionally the entire substrate) from a corresponding portion of substrate holder so that mechanical stress leading to local strain may relax prior to further patterning. To overcome residual frictional force between the substrate and substrate holder, the substrate and substrate holder may be physically separated prior to further patterning. | 2010-04-22 |
20100096775 | MOLD IMPRINTING - A method of patterning an article is disclosed. The method includes providing an article and providing a mold with first and second surfaces. The first surface includes a pattern. The method also includes providing a transfer medium between the mold and a surface of the article. The mold is pressed against the surface of the article with air pressure. A thickness of the mold enables the air pressure to cause the mold to contact the surface to produce an even pattern. | 2010-04-22 |
20100096776 | Reduction of Stress During Template Separation - Separation of an imprint lithography template and a patterned layer in an imprint lithography process may result in stress to features of the template and/or features of the patterned layer. Such stress may be reduced by minimizing open areas on the template, including dummy features within the open areas, and/or selective positioning of features on the template. | 2010-04-22 |
20100096777 | Methods for Manufacturing Three-Dimensional Devices and Devices Created Thereby - In certain exemplary embodiments of the present invention, three-dimensional micro-mechanical devices and/or micro-structures can be made using a production casting process. As part of this process, an intermediate mold can be made from or derived from a precision stack lamination and used to fabricate the devices and/or structures. Further, the micro-devices and/or micro-structures can be fabricated on planar or nonplanar surfaces through use of a series of production casting processes and intermediate molds. The use of precision stack lamination can allow the fabrication of high aspect ratio structures. Moreover, via certain molding and/or casting materials, molds having cavities with protruding undercuts also can be fabricated. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. This abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2010-04-22 |
20100096778 | Methods for Manufacturing Three-Dimensional Devices and Devices Created Thereby - In certain exemplary embodiments of the present invention, three-dimensional micro-mechanical devices and/or micro-structures can be made using a production casting process. As part of this process, an intermediate mold can be made from or derived from a precision stack lamination and used to fabricate the devices and/or structures. Further, the micro-devices and/or micro-structures can be fabricated on planar or nonplanar surfaces through use of a series of production casting processes and intermediate molds. The use of precision stack lamination can allow the fabrication of high aspect ratio structures. Moreover, via certain molding and/or casting materials, molds having cavities with protruding undercuts also can be fabricated. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. This abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2010-04-22 |
20100096779 | FOAMED TOOLS - A tool for use in forming moulded articles, the tool comprising a tool body formed of a foamed material, a resinous material on the tool body and elastomeric material between said tool body and resinous material to inhibit the movement of resin from the resinous material into the tool body. The invention also provides a method of manufacturing a tool, a method of moulding articles using such a tool, and elastomeric material for use in forming a tool. One particular application of the tools of the present invention is in the formation or manufacture of moulded articles using curable, resinous composite materials. | 2010-04-22 |
20100096780 | Method of Forming a Hardened Skin on a Surface of a Molded Article - A method of forming a hardened skin on one or more surfaces of a molded article. In an exemplary method, a formable material is mixed with a blowing agent to form a foam material. The foam material is placed in a flow molding apparatus such that a first surface of the foam material is in contact with a first mold section and a second surface of the foam material is in contact with a second mold section. In operation, an alternating dielectric field is applied across the foam material to form the molded article. At the end of the molding cycle, the first and/or second surfaces of the foam material remain under the decomposition temperature of the blowing agent and are not blown so as to form one or more thicknesses of hardened skin on the molded article. | 2010-04-22 |
20100096781 | Method Of Fabricating An Implantable Medical Device Using Gel Extrusion And Charge Induced Orientation - The invention provides a method of manufacturing a polymeric implantable medical device using gel extrusion of high molecular weight polymers or charge-induced orientation to avoid heat degradation of the polymer that might occur during conventional heat extrusion. | 2010-04-22 |
20100096782 | Apparatus for Heating Preforms - The invention relates to a device for heating of preforms formed of plastic with infrared radiation, whereby the preform is struck by cooling air at its neck finish and on its body. Furthermore, the infrared radiators are struck by cooling air at their ends. The invention relates to a heating device in which the three cooling air streams may be controlled or regulated independently from each other. | 2010-04-22 |
20100096783 | METHOD FOR PRODUCING CERAMIC HONEYCOMB STRUCTURE - A process for producing a ceramic honeycomb structure containing aluminum titanate as main crystals, characterized by extruding a plastic green earth consisting of 45:55 to 55:45, in molar ratio, titania powder and alumina powder, or of 100 parts by mass of the sum of such titania powder and alumina powder mixed with 1 to 10 parts by mass of amorphous silica powder so as to form a honeycomb configuration, drying the same and firing the dried extrudate at 1300° to 1700° C. | 2010-04-22 |
20100096784 | SYSTEM EMPLOYING GENERATION OF CONTROLLED FURNACE ATMOSPHERES WITHOUT THE USE OF SEPARATE GAS SUPPLIES OR STAND-ALONE ATMOSPHERE GENERATORS - In a system for processing metal, a furnace is provided which receives the metal being processed. At least one heating burner is provided in the furnace together with at least one atmosphere burner of substantially a same construction as the heating burner. An exhaust of the atmosphere burner at least partially provides an atmosphere within the furnace for the metal processing. An exhaust of the heating burner is separate from the exhaust of the atmosphere burner. A fuel feed for the atmosphere burner and a fuel feed for the heating burner are each separately controllable. | 2010-04-22 |
20100096785 | DEVICE FOR INTRODUCING METAL BARS INTO A METAL BATH - The invention relates to a device ( | 2010-04-22 |
20100096786 | Air Spring - An air spring for a vehicle suspension, in which air spring the bellows is fastened by way of deformable annular components to the periphery of connection parts. The annular component is fastened at one end of the bellows, to the outer periphery of the connection part in axially spaced-apart clamping regions so as to form an encircling cavity, The annular component, on its outer side, is formed with a rolling contour for the bellows. | 2010-04-22 |
20100096787 | VIBRATION-PROOFING DEVICE - This vibration-proofing device is a vibration-proofing device | 2010-04-22 |