17th week of 2009 patent applcation highlights part 20 |
Patent application number | Title | Published |
20090102459 | Device for Determining the Strength of the Magnetic Field of an Electromagnet - A device and a method for determining the magnetic field strength of an electromagnet is illustrated and described. The object to provide a device and a method for determining the strength of the field of an electromagnet, which allows even minor changes in the magnetic field to be determined quickly is achieved in terms of an apparatus by a device having a measurement device for determining the magnetic field of the electromagnet, a low-pass filter element which is connected to the first supply line and to the second supply line and is adapted to emit a signal at the output of the low-pass filter element from the voltage between the first supply line and the second supply line, which signal approximates to the time profile of the magnetic field strength in the electromagnet, having a low-pass filter downstream from the measurement device, having a high-pass filter connected in series with the low-pass filter element, and having a signal output, wherein the output of the measurement device and the output of the low-pass filter element are connected to the signal output. | 2009-04-23 |
20090102460 | POSITION SENSOR - A method of determining the position of a probe relative to a scale wherein the probe contains a sensor of the type comprising one or more pairs of orthogonal sensing elements X, Y operable to measure properties varying locally with the position of the probe relative to the scale. In use, a sinusoidally varying bias Ix, Iy is applied to each of the elements X, Y. The resultant outputs of elements X and Y are fed to summing means | 2009-04-23 |
20090102461 | ABSOLUTE POSITION MAGNETIC ENCODER WITH BINARY AND DECIMAL OUTPUT - An absolute position magnetic encoder includes a first magnetic track configured for a binary output, a second magnetic track configured for a decimal output, a first magnetic sensor positioned proximate the first magnetic track to detect the magnetic field of the first magnetic track, and a second magnetic sensor positioned proximate the second magnetic track to detect the magnetic field of the second magnetic track. The encoder is selectively operable to provide one of the binary output and the decimal output. | 2009-04-23 |
20090102462 | DISPLACEMENT SENSOR FOR A ROD - A displacement sensor ( | 2009-04-23 |
20090102463 | Sensor Device and Method of Measuring a Position of an Object - A sensor device for measuring a position of an object which is made of an inductivity influencing material. The sensor device includes a sensor unit and a processing logic arrangement. The sensor unit includes a magnetic field generator and a magnetic field detector. The magnetic field detector detects a magnetic field generated by the magnetic field generator. The processing logic arrangement processes signals from the magnetic field detector to determine the position of the object. The object is movable with respect to the magnetic field generator. | 2009-04-23 |
20090102464 | MATCHING OF GMR SENSORS IN A BRIDGE - A magnetoresistive (MR) sensing device includes MR elements electrically connected to form a bridge circuit and one or more non-functional (or “dummy”) MR elements for improved matching of the bridge circuit MR elements. | 2009-04-23 |
20090102465 | MAGNETO-RESISTIVE SENSORS WITH IMPROVED OUTPUT SIGNAL CHARACTERISTICS - The present invention provides a magnetoresistive sensor ( | 2009-04-23 |
20090102466 | Bearing with absolute angel sensor - To provide a rotation sensor equipped bearing capable of detecting a highly precise absolute angle with no correction work required after incorporation into a bearing installed equipment, an absolute angle sensor equipped bearing assembly includes a sensor equipped bearing | 2009-04-23 |
20090102467 | METHOD AND APPARATUS FOR SENSING SHAFT ROTATION - A system or method for sensing rotational parameters of a rotating machine. A rotating element is mounted on a shaft of a rotary machine. The rotating element has predetermined magnetic permeability. An insert is disposed on the first rotating element and characterized by a second magnetic permeability different from that of the rotating element. A sensor is mounted opposite the first rotating element and separated from the rotating element by a gap. The target element has an axis substantially parallel with and offset from the axis of the rotating element. The sensor is disposed in substantial alignment with the target element at least once per rotation when the rotating element is rotating. The sensor is configured to generate an output signal in response to a sensed deviation in a magnetic field induced by the rotation of the target element in proximity to the sensor. | 2009-04-23 |
20090102468 | Rotation sensor and bearing assembly using the same - A rotation sensor includes a magnetic sensor array ( | 2009-04-23 |
20090102469 | Methods and Apparatus for Vibration Detection - Apparatus for detecting vibration of an object adapted to rotate includes one or more vibration processors selected from: a direction-change processor adapted to detect changes in a direction of rotation of the object, a direction-agreement processor adapted to identify a direction of rotation of the object in at least two channels and identify an agreement or disagreement in direction of rotation identified by the at least two channels, a phase-overlap processor adapted to identify overlapping signal regions in signals associated with the rotation of the object, and a running mode processor adapted to identify an unresponsive output signal from at least one of the at least two channels. A method for detecting the vibration of the object includes generating at least one of a direction-change output signal with the direction-change processor, a direction-agreement output signal with the direction-agreement processor, a phase-overlap output signal with the phase-overlap processor, and a running-mode-vibration output signal with the running-mode processor, each indicative of the vibration the object. | 2009-04-23 |
20090102470 | SIMULATION METHOD IMPLEMENTED BY COUPLING ELECTROMAGNETIC FIELD ANALYSIS METHOD AND CIRCUIT ANALYSIS METHOD TOGETHER, SIMULATION APPARATUS, AND COMPUTER-READABLE MEDIUM STORING SIMULATION PROGRAM - A simulation apparatus according to an embodiment performs an electromagnetic field circuit coupling analysis on a first substrate and a second substrate electrically coupled via a circuit element having a finite delay time. A first coupling analysis unit carries out a time domain electromagnetic field analysis and also a circuit analysis on a circuit element at a first analytical domain including the first substrate. The second coupling analysis unit carries out a time domain electromagnetic field analysis and also a circuit analysis on a circuit element at a second analytical domain including the second substrate. A cable internal state analysis unit carries out a circuit analysis on a circuit element, employing an electromagnetic field value obtained at the first coupling analysis unit at one terminal of the circuit element connecting the first substrate and the circuit element, and an electromagnetic field value obtained at the second coupling analysis unit at another terminal of the circuit element connecting the second substrate and the circuit element. | 2009-04-23 |
20090102471 | PROBE FOR A MAGNETIC REMANENCE MEASUREMENT METHOD, AND METHOD FOR DETECTING DEPOSITS OF FOREIGN MATERIAL AND INCLUSIONS IN HOLLOW SPACES - A probe for a magnetic remanence measurement method, in particular for detecting foreign material deposits and inclusions in hollow spaces, the hollow spaces being formed in a non-ferromagnetic material and the foreign material deposits and inclusions being made of a ferromagnetic material, wherein the probe includes at least one magnetic field sensor, at least one first and one second magnet, the magnets being configured before the at least one magnetic field sensor in a direction of introduction into the hollow space, and being situated relative to one another in such a way that their pole axes run non-parallel to one another. | 2009-04-23 |
20090102472 | MAGNETIC SENSOR DEVICE WITH FIELD GENERATORS AND SENSORS - The invention relates to a magnetic sensor device ( | 2009-04-23 |
20090102473 | EDDY CURRENT TESTING METHOD AND EDDY CURRENT TESTING APPARATUS - The present invention provides an eddy current testing method and an eddy current testing apparatus that can reduce detection noise to increase the SN ratio thus improving the defect detection accuracy. | 2009-04-23 |
20090102474 | FIBER LASER MAGNETIC FIELD SENSOR - The device includes two supports and a primary conductive strip. The primary conductive strip includes a neutral surface, a first side, and a second side. The primary conductive strip is connected one of directly and indirectly on the first side to the two supports such that the primary conductive strip is constrained in two dimensions and movable in one dimension. The device also includes a primary distributed feedback fiber laser. The primary distributed feedback fiber laser includes a fiber axis. The primary distributed feedback fiber laser is connected to the primary conductive strip along one of the first side and the second side such that there is a positive distance between the neutral surface of the primary conductive strip and the fiber axis of the primary distributed feedback fiber laser. | 2009-04-23 |
20090102475 | INTEGRATED 3-AXIS FIELD SENSOR AND FABRICATION METHODS - A multi-axis magnetic or other field sensing device and method of fabricating a multi-axis magnetic or other field sensing device. An example sensing device is a 3-axis sensor package on a substrate with sensors on opposing sides of the substrate. One side of the substrate includes an X-axis sensor and a Y-axis sensor (or alternatively an integrated X-Y-axis sensor) and the opposite side of the substrate includes a Z-axis sensor on at least one sloped surface, the surface sloped with respect to both the first and second surface areas. One surface is mechanically and electrically bonded to a circuit board via conductive bumps. The other surface electrically connects to the circuit board through bonded wires and/or vias formed through the substrate. | 2009-04-23 |
20090102476 | MAGNETIC FIELD SENSOR - A magnetic field sensor comprises a first and a second carrier foil and a spacer arranged there between. The spacer delimits a sensing region of the sensor in which the first and second carrier foils can be brought together against the their resiliency. At least two electrodes are arranged in the sensing region in such a way that an electrical contact is provided between them when the first and second carrier foils are brought together. The magnetic field sensor further comprises additional magnetisable layer associated with the first or the second carrier foil so that the first and second carrier foils can be brought together in response to a magnetic field. | 2009-04-23 |
20090102477 | Detecting arrangement and method for a magnetic gripper device - A detecting arrangement for a magnetic gripper device ( | 2009-04-23 |
20090102478 | CONFIGURABLE MAGNET ASSEMBLY FOR USING IN NMR WELL LOGGING INSTRUMENT - A magnet assembly for measuring properties of a formation from a borehole, the magnet assembly including a first device and a second device, each device adapted for insertion into the borehole, the first device producing a first magnetic field, the second device producing a second magnetic field; wherein the second magnetic field is configurable for one of reinforcing and reducing the first magnetic field; and wherein the first device comprises a permanent magnet and the second device comprises at least one of one of a switchable magnet and switching windings. | 2009-04-23 |
20090102479 | MRI Phase Visualization of Interventional Devices - Imaging a device in a magnetic resonance imaging system includes inserting a device having a conductive coil assembly thereon into a subject, obtaining a magnetic resonance image of the subject that includes signal phase variations, determining a position of the device based on discontinuities in the signal phase variations, and displaying an image representation of the device superimposed on a reference image based upon the determined position. | 2009-04-23 |
20090102480 | SHIMMING OF ELECTRIC FIELD FOR ELECTRIC PROPERTIES TOMOGRAPHY - A radio frequency coil system ( | 2009-04-23 |
20090102481 | COMPLEX THRESHOLD METHOD FOR REDUCING NOISE IN NUCLEAR MAGNETIC RESONANCE IMAGES - A method of removing noise while preserving signal in nuclear magnetic resonance images combines steps of performing a magnitude threshold filter and performing a phase threshold filter on the image data. Preferably, a magnitude and phase connectivity algorithm is applied to pixels that fail to meet either the magnitude or phase thresholds. | 2009-04-23 |
20090102482 | NMR probehead with a plurality of resonator systems for simultaneous measurement of a plurality of samples in a coupled mode - A nuclear magnetic resonance(=NMR) probehead, comprising N basic elements ( | 2009-04-23 |
20090102483 | MAGNETIC RESONANCE WITH TIME SEQUENTIAL SPIN EXCITATION - In a magnetic resonance scanner, a main magnet ( | 2009-04-23 |
20090102484 | BANDWIDTH EXPANSION IN MAGNETIC RESONANCE - A magnetic resonance imaging system includes a primary magnet and a secondary magnet operable to produce magnetic fields within a sample being imaged. The MRI system further includes at least one RF coil that is operable to receive electromagnetic frequencies from the sample. The RF coil is formed from tubing that serves as a cooling conduit through which flows a cooling fluid provided by a cooling source. The cooling fluid cools the RF coils to improve imaging of the sample. | 2009-04-23 |
20090102485 | Methods for Interpreting Multi-Component Induction Logs Using the X-Signal Measurements - Multi-component induction measurements are made using a resistivity logging tool in an anistropic earth formation. The X-signal (quadrature) is insensitive to borehole eccentricity. A subset of the multi-component measurements are inverted to first determine horizontal resistivities. Using the determined horizontal resistivities and another subset of the multi-component measurements, the vertical resistivities are obtained. Results of using the in-phase signals are comparable to those obtained using multifrequency focusing of quadrature signals. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72( | 2009-04-23 |
20090102486 | DIMENSIONS DETERMINATION FOR INSULATING COATINGS - Systems and methods for determining the dimensions of insulating coating sections applied to a conductive component are disclosed. The method includes providing a specimen having an insulating coating section of a first surface area and a first thickness. The method further includes conducting a test of the specimen for propagating brush discharges. If the specimen exhibits propagating brush discharges, the method further includes reducing at least one of the first surface area and the first thickness to produce at least one of a second surface area or a second thickness, or reducing a first maximum distance that any portion of the insulating coating may extend from an adjacent static dissipative feature to produced a second maximum distance. In additional embodiments, insulating coating patterns may be established on the component based on at least one of the dimensions of the second surface area, the second thickness, or the second maximum distance. | 2009-04-23 |
20090102487 | Method for Validating Printed Circuit Board Materials for High Speed Applications - A method for testing a printed circuit board to determining the dielectric loss associated with the circuit board material relative to a standard. Dielectric losses in the material generate heat when a high frequency electronic signal, such as a microwave frequency signal, is communicated through a microstrip that is embedded within the printed circuit board. The temperature or spectrum at the surface of printed circuit board is measured and compared against the temperature or spectrum of the standard to determine whether the material under test is acceptable. While various temperature measurement devices may be used, the temperature is preferably measured without contacting the surface, such as using an infrared radiation probe. | 2009-04-23 |
20090102488 | GROUND FAULT DETECTION CIRCUIT FOR USE IN HIGH VOLTAGE MOTOR DRIVE APPLICATIONS - An integrated ground fault detection circuit in accordance with an embodiment of the present application includes a shunt resistor provided on a positive rail of a DC bus, a high voltage pocket including a sensory circuit connected to the shunt resistor and operable to detect a fault condition indicating a short circuit and a transmitter section operable to continuously transmit a fault condition signal indicating the fault condition and a low voltage pocket including a receiver operable to receive the fault condition signal from the sensory circuit and a logic unit, connected to the receiver, and operable to provide a fault output signal indicating the presence of a fault condition based on the fault condition signal. | 2009-04-23 |
20090102489 | Systems and methods for detecting electric discharge - A distributed sensing system for detecting partial electric discharge along the length of an extended object or objects. An optical fiber having a cladding integrated with luminescent material and a silica core of less than 500 micro-meters in diameter with a first reflective end deployed in proximity to test objects. A photo detector is positioned at the second end of the optical sensing fiber and receives and measures both a direct emission light from an electric partial discharge event and the reflected emission light from the reflection end of the optical sensing fiber. The measured signals and their arrival times are used to determine the location and magnitude of a partial electrical discharge. | 2009-04-23 |
20090102490 | APPARATUS FOR PERFORMING A STRESS TEST TO ISOLATE AND MEASURE NOISE IN A PAIRED LINE AND METHOD FOR PERFORMING A STRESS TEST TO ISOLATE AND MEASURE NOISE IN A PAIRED LINE - The present invention provides a circuit for performing a stress test on a paired line. The circuit provides for first and second balanced outlet pathways for applying an AC signals to the paired line. Although each of these first and second balanced outlet pathways include balanced capacitors, the need to vet these capacitors in order to achieve proper operation of the circuit is eliminated. | 2009-04-23 |
20090102491 | MULTIPORT TEST-SET FOR SWITCH MODULE IN NETWORK ANALYZER - A system for measuring a multiport device connected to a network analyzer via a test-set comprising a multiport network analyzer; a test-set having multiple real switches wherein at least one set of real switches is capable of being connected together as needed between selection terminals; and a device for controlling the network analyzer and the test-set, wherein two or more predetermined real switches that have been connected together, including at least one real switch with an open terminal, are regarded as one imaginary switch, and the control device controls the selection status of the real switches related to the imaginary switch based on the combination of terminals to which electricity is to be conducted as instructed by the user for this imaginary switch. | 2009-04-23 |
20090102492 | ANGLE MEASURING DEVICE - An angle measuring device for optical angle measurement has a telescope body which is rotatably mounted around at least one shaft ( | 2009-04-23 |
20090102493 | Power Integrated Circuit with Bond-Wire Current Sense - An integrated circuit product includes: 1) a package, 2) a semiconductor die mounted within the package, 3) a first terminal and a second terminal for connecting the integrated circuit product to an external circuit, 4) one or more bond wires for transferring a current received at the first terminal to the second terminal; and 5) a circuit included in the semiconductor die that measures a voltage difference attributable to the resistance of the bond wires to measure the magnitude of the current passing through the first terminal. | 2009-04-23 |
20090102494 | CONTACTLESS INTERFACING OF TEST SIGNALS WITH A DEVICE UNDER TEST - An interface device receives test data from a tester. A signal representing the test data is transmitted to a device under test through electromagnetically coupled structures on the interface device and the device under test. The device under test processes the test data and generates response data. A signal representing the response data is transmitted to the interface device through electromagnetically coupled structures on the device under test and the interface device. | 2009-04-23 |
20090102495 | Vertical guided probe array providing sideways scrub motion - Improved probing of closely spaced contact pads is provided by an array of guided vertical probes that has a sideways scrub relative to the line of contact pads. With this orientation of scrub motion, the probes can be relatively thin along the contact line, and relatively thick perpendicular to the contact line. The thin dimension of the probes allows for probing closely spaced contact pads, while the thick dimension of the probes provides mechanical robustness and current carrying capacity. The probes have a predetermined curvature in a plane including the contact line, to help determine the amount of scrub motion during contact. In a preferred embodiment, an array of probes is provided for probing two closely spaced and parallel rows of contact pads, offset from each other by half the contact pad pitch. | 2009-04-23 |
20090102496 | TEST SYSTEM AND METHOD FOR REDUCING TEST SIGNAL LOSS FOR INTEGRATED CIRCUITS - An integrated circuit test system includes a probe card, a driver, a receiver, and a first switch. The driver is coupled to the probe card via a first signal line. The receiver is coupled to the probe card via a second signal line. The first switch is coupled between the probe card and the first signal line. After the driver outputs a test signal to a device under test via the first signal line, the first switch is turned off, and then the receiver reads the test signal via the second signal line. Thus, the test signal loss can be reduced. | 2009-04-23 |
20090102497 | PUSHER, PUSHER UNIT AND SEMICONDUCTOR TESTING APPARATUS | 2009-04-23 |
20090102498 | Laser Targeting Mechanism - an automated test equipment system includes a peripheral including first mechanical alignment features; a test head including second mechanical alignment features arranged in a pattern corresponding to the first mechanical alignment features and configured to engage the first mechanical alignment features. The automated test equipment system also includes a laser assisted alignment system including laser devices mounted to the peripheral and operable to emit laser beams; target plates mounted to the test head and including target symbols visible on surfaces of the target plates. The target symbols are arranged in a pattern corresponding to the laser devices such that, when laser beams from the laser devices are substantially aligned with the target symbols, the first mechanical alignment features are substantially aligned with the second mechanical alignment features. | 2009-04-23 |
20090102499 | METHOD AND APPARATUS FOR WAFER LEVEL BURN-IN - A temperature regulation plate | 2009-04-23 |
20090102500 | Interposer and probe card having the same - An interposer may include a first base, at least one first signal line in the first base, and at least one first ground line in the first base, wherein the ground line surrounds the at least one first signal line. The at least one first signal line and the at least one first ground line may be exposed through an upper surface of the first base. The at least one first signal line may be configured to conduct a test current through the first base. An interposer may also include a second base below the first base and may include a printed circuit board between the first base and the second base. A probe card may include a multilayer substrate having at least one contact needle, a coaxial board having at least one coaxial signal cable and the above described interposer between the multilayer substrate and the coaxial board. | 2009-04-23 |
20090102501 | TEST STRUCTURES FOR E-BEAM TESTING OF SYSTEMATIC AND RANDOM DEFECTS IN INTEGRATED CIRCUITS - In accordance with the invention, there are electron beam inspection systems, electron beam testable semiconductor test structures, and methods for detecting systematic defects, such as, for example contact-to-gate shorts, worm hole leakage paths, holes printing issues, and anomalies in sparse holes and random defects, such as, current leakage paths due to dislocations and pipes during semiconductor processing. | 2009-04-23 |
20090102502 | PROCESS TESTERS AND TESTING METHODOLOGY FOR THIN-FILM PHOTOVOLTAIC DEVICES - The present invention generally relates to process testers and methods of fabricating the same using standard photovoltaic cell processes. In particular, the present invention relates to process tester layouts defined by laser scribing, methodology for creating process testers, methodology of using process testers for photovoltaic line diagnostics, placement of process testers in photovoltaic module production, and methodology for creating design rule testers. | 2009-04-23 |
20090102503 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR CHIP, INTERCHIP INTERCONNECT TEST METHOD, AND INTERCHIP INTERCONNECT SWITCHING METHOD - A semiconductor device is provided with a first wiring ( | 2009-04-23 |
20090102504 | Circuit Assemblage and Method for Functional Checking of a Power Transistor - A circuit assemblage for functional checking of a power transistor includes a power transistor having an insulated gate, a first power electrode configured as a drain or as a collector, and a second power electrode configured as a source or an emitter, the first and second power electrode being connected to a power circuit having a DC voltage source and an electrical DC load. The circuit assemblage further includes a control application device having a signal output that is connected to the gate; a capacitance measuring device for measuring the gate terminal capacitance between the gate terminal contact and the second power electrode terminal contact; and an evaluation device for comparing the gate terminal capacitance with the gate capacitance, and outputting a fault signal as a function of the comparison. | 2009-04-23 |
20090102505 | REMOTELY CONFIGURABLE CHIP AND ASSOCIATED METHOD - A chip is provided that includes a plurality of on-chip configurable features having a disabled and an enabled state. The on-chip configurable features are each operable to change from the disabled state to the enabled state upon receipt of a valid enablement configuration from an enabling entity. A method for the chip is provided to disable the plurality of on-chip configurable features before delivery of the chip to a new location. The chip is delivered to a new location where a unique hardware identifier and data for at least one of the on-chip configurable features is retrieved. The unique hardware identifier and the data are transmitted to an enabling entity. The enabling entity sends the enablement configuration to the chip. The chip is programmed with the enablement configuration, which enables the at least one on-chip configurable feature at the new location. | 2009-04-23 |
20090102506 | ADAPTER - An exemplary adapter comprises an input port for connecting to a first hardware device; an output port for connecting to a second hardware device; a standby output port for connecting to the second hardware device; a programmable logic device (PLD) having at least one input terminal connected to the input port, at least one output terminal connected to the output port, at least one standby output terminal connected to the standby output port, and at least one control terminal to receive a voltage signal; and a jumper connected to the control terminal of the PLD to send a voltage signal thereto, wherein the input terminal of the PLD is selectively coupled to the output terminal or the standby output terminal of the PLD under the control of the voltage signal. | 2009-04-23 |
20090102507 | DESIGN STRUCTURE FOR SHUTTING OFF DATA CAPTURE ACROSS ASYNCHRONOUS CLOCK DOMAINS DURING AT-SPEED TESTING - A design structure embodied in a machine readable medium used in a design process includes an apparatus for testing logic devices configured across asynchronous clock domains, including a deactivation mechanism for deactivating, during at-speed fault testing, a local clock signal for each of a first plurality of latches having at least one data input thereto originating from a source located within an asynchronous clock domain with respect thereto; wherein the deactivation mechanism is configured to permit data capture within the first plurality of latches, and wherein the deactivation mechanism is further configured to permit at-speed data launch from the first plurality of latches to downstream latches with respect thereto during at-speed testing. | 2009-04-23 |
20090102508 | Pulsed Dynamic Logic Environment Metric Measurement Circuit - A pulsed dynamic logic environment metric measurement circuit provides self-referenced, low area/cost and low power measurement of circuit environment metrics, such as supply voltage. A cascade of dynamic logic stages is clocked with a pulse having a width substantially independent of an environment metric to which the delay of the dynamic logic stages is sensitive. The number of dynamic logic stages that evaluate within a given pulse provides a direct measure of the pulse width, and thus the value of the circuit metric. The pulse may be generated from a logical exclusive-OR combination of a clock signal provided from two circuit paths that differ in sensitivity to the environment metric to be measured. One circuit path may have a delay substantially determined only by wire delay, which is not substantially sensitive to circuit environment metrics such as power supply voltage. | 2009-04-23 |
20090102509 | REDUCED AREA ACTIVE ABOVE-GROUND AND BELOW-SUPPLY NOISE SUPPRESSION CIRCUITS - A method and apparatus for noise suppression. A circuit has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal. | 2009-04-23 |
20090102510 | CONTROL CIRCUIT FOR CONTROLLING ON-DIE TERMINATION IMPEDANCE - The present invention relates to an ODT control circuit which is controlled in synchronization with an external clock during power-down mode. An ODT control circuit according to the present invention includes a clock control circuit which receives a synchronized internal clock signal and a DLL clock signal, and selects either one of the internal clock signal or the DLL clock signal according to the power mode to output a plurality of delayed clock signals; and an ODT control signal generation circuit which receives an ODT command, and controls the ODT command with the internal clock signal and a plurality of the delayed clock signals to generate and output an ODT control signal. According to the present invention, an ODT control signal for controlling an on-die termination resistor is synchronized with an external clock even during power-down mode, thereby more effectively controlling the ODT control signal. | 2009-04-23 |
20090102511 | Semiconductor device and driver control method - A semiconductor device of the invention has a plurality of P-channel transistors, to which resistance elements are inserted in series, prepared on a pull-up side of a driver such that an ON resistance value on the P-channel transistor side and a resistance value of the resistance element can be selected. In addition, also on a pull-down side of the driver, a plurality of N-channel transistors to which resistance elements are inserted in series are prepared such that an ON resistance value on the N-channel transistor side and a resistance value of the resistance element can be selected. A driver section having a linear current-voltage characteristic is realized by combination of those described. | 2009-04-23 |
20090102512 | Edit structure that allows the input of a logic gate to be changed by modifying any one of the metal or via masks used to form the metal interconnect structure - An edit structure is disclosed that allows the input of a logic gate to be changed by modifying any one of the metal and via masks that are used to form the metal interconnect structure. As a result, a first permanent logic state provided by a tie-in circuit can be changed to a second permanent logic state by modifying any one of the metal and via masks that are used to form the metal interconnect structure. | 2009-04-23 |
20090102513 | Low Power Output Driver - A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or a constant voltage internal ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the constant voltage ground. | 2009-04-23 |
20090102514 | Duty cycle detecting circuit for pulse width modulation - A duty cycle detecting circuit for pulse width modulation (PWM) is disclosed. The circuit comprises a clock generating circuit, a sampling circuit and a calculation circuit. The clock generating circuit is for generating a clock signal. The sampling circuit receives a PWM signal and the clock signal, samples the PWM signal based on the clock signal, and generates a sampling signal. The calculation circuit is for calculating the duty cycle of the PWM signal based on the sampling signal. | 2009-04-23 |
20090102515 | Sense-amplifying circuit having two amplification stages - A sense-amplifying circuit amplifies a voltage difference between a first signal source and a second signal source. A first inverter has a first intermediate node from which a first output extends. A second inverter has a second intermediate node from which a second output extends. The second inverter is recursively cross-coupled with the first inverter. A first power source switch connects the first and second inverters to a first power source line. A second power source switch connects the first and the second inverters to a second power source line. A first sense-amplifying switch connects the first signal source to the first intermediate node. A second sense-amplifying switch connects the second signal source to the second intermediate node. A first pre-charge switch connects the first intermediate node to the second power source line. A second pre-charge switch connects the second intermediate node to the second power source line. | 2009-04-23 |
20090102516 | Comparator - A comparator has P-channel field effect transistors that are supplied at respective gates with input voltages Vin and Vref, which are objects of comparison, and that act as a differential transistor pair; and N-channel field effect transistors that serve as current channels for respective drain currents of these two P-channel field effect transistors and that act as a current mirror circuit. The comparator outputs a drain voltage Vx of an N-channel field effect transistor as a signal showing a result of comparison between the two input voltages. An N-channel field effect transistor diode-connected to the comparator is interposed between drains of the N-channel field effect transistors. | 2009-04-23 |
20090102517 | Track-And-Hold Circuit With Adjustable Charge Compensation - A circuit design incorporates charge compensation devices within a Track-and-Hold (T/H) circuit to control channel charge generated by a tracking switch. Calibrating a T/H circuit requires selecting charge compensation devices from an array of similar devices to function within the T/H circuit to absorb charge ejected from the tracking switch. The charge compensation devices can also be pseudorandomly selected to operate within the T/H circuit. Charge compensation devices are used to enhance the performance of bottom-plate sampling systems as well as bootstrapped T/H circuits. | 2009-04-23 |
20090102518 | DEVICE FOR GENERATING A SIGNAL AND METHOD FOR CONTROLLING OPERATION OF THE SAME - The present invention relates to a device for generating a signal and method for controlling operation of the same. The present invention provides a device for generating a signal, which includes an electrode ( | 2009-04-23 |
20090102519 | A/D CONVERTER - An apparatus is provided. The apparatus comprises a sample and hold circuit, a converter, and an adjustable current circuit. The sample and hold circuit is adapted to receive an analog input signal and to output an amplified signal. The converter is coupled to the sample and hold circuit and that converts the amplified signal to a digital signal. The controller is coupled to the converter and that receives the digital signal. The controller includes a plurality of voltage ranges, wherein each voltage range is associated with a current value, and the controller compares the digital signal to at least one of the voltage ranges to output at least one of the current values. The adjustable current circuit is coupled to the sample and hold amplifier and to the controller so that the adjustable current circuit provides a generally constant operating current that corresponds to the current value output from the controller. | 2009-04-23 |
20090102520 | DIRECT INJECTION-LOCKED FREQUENCY DIVIDER CIRCUIT WITH INDUCTIVE-COUPLING FEEDBACK ARCHITECTURE - A direct injection-locked frequency divider circuit with inductive-coupling feedback architecture is proposed, which is designed for integration to a high-frequency circuit system with a high operating frequency such as 24 GHz (gigahertz), for providing a frequency-dividing function. The proposed frequency divider circuit comprises an injection-locked oscillator (ILO) circuit module and a pair of buffer-stage circuits, wherein the ILO circuit module further includes a signal-injection circuit, a cross-coupled switching circuit, and a variable-capacitance tuning circuit. The proposed circuit architecture is characterized by the circuit arrangement of a direct-injection architecture and an inductive-coupling feedback architecture by coupling the inductive elements of the buffer-stage circuits to the inductive elements of the variable-capacitance tuning circuit in the ILO circuit module. These features allow the proposed frequency divider circuit to have higher operating frequency with wider frequency locking range, low power consumption, and small integrated circuit layout area. | 2009-04-23 |
20090102521 | CIRCUIT AND OSCILLATING APPARATUS - A circuit includes a logic circuit containing a first transistor and a second transistor which are connected in series to each other between a high power supply and a low power supply in such a manner that an emitter of one of the first and second transistors is connected to a collector of the other of the first and second transistors. The first transistor is positioned closer to the high power supply, and the second transistor is positioned closer to the low power supply. The logic circuit operates in accordance with voltages input into bases of the first and second transistors. The circuit further includes a current amplifying circuit containing a third transistor whose collector is connected to one of the high and low power supplies, whose emitter is connected to the other of the high and low power supplies, and whose base is connected to an output from the logic circuit. The current amplifying circuit amplifies a current of a logic signal from the logic circuit and feeds, from the emitter of the third transistor, the current-amplified logic signal back to the base of the second transistor. | 2009-04-23 |
20090102522 | POWER ON RESET CIRCUITRY - One or more embodiments of the present disclosure provide methods, devices, and systems for operating power on reset (POR) circuitry. One method embodiment includes providing a voltage to a POR circuit of the system, detecting when the voltage reaches a number of different trip levels, maintaining a count of the number of times an output signal of the POR circuit trips in response to a detected reaching of one of the number of different trip levels, and adjusting the trip level to be detected based at least partially on the count. | 2009-04-23 |
20090102523 | LINEAR DIGITAL PHASE INTERPOLATOR AND SEMI-DIGITAL DELAY LOCKED LOOP (DLL) - Provided are a digital phase interpolator, which performs linear phase interpolation irrelevantly to input order of two input signals, and a semi-digital delay locked loop (DLL), which includes and controls the same. The phase interpolator includes: a first clocked inverter controlled by a phase indicating signal and providing a first output signal to a common output terminal by inverting a first input signal, and a second clocked inverter controlled by the phase indicating signal and providing a second output signal to the common output terminal by inverting the second input signal. The second clocked inverter is clocked by the first input signal when the phase indicating signal is in a first logic state, and the first clocked inverter is clocked by the second input signal when the phase indicating signal is in a second logic state. The phase indicating signal indicates a lead/lag phase relationship between the first and second input signals and is generated in a controller of a circuit of the semi-digital DLL. | 2009-04-23 |
20090102524 | TIMING CONTROL CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE - Disclosed is a timing control circuit that receives a first clock having a period T1, a group of second clocks of L different phases spaced apart from each other at substantially equal intervals and selection signals m, n supplied thereto and generates a fine timing signal delayed from the rising edge of the first clock signal by a delay td of approximately td=m·T1+n·(T2/L). The timing control circuit includes a coarse delay circuit and a fine delay circuit. The coarse delay circuit includes a counter for counting a rising edge of the first clock signal after an activate signal is activated and generates a coarse timing signal whose amount of delay from the first clock signal is approximately m·T1. The fine delay circuit comprises L-number of multiphase clock control delay circuits disposed in parallel, delays by n·T2/L the timing of sampling of the coarse timing signal by respective clocks of the group of L-phase second clocks, and takes the OR among the resulting delayed pulses to thereby produce the fine timing signal. | 2009-04-23 |
20090102525 | Voltage controlled oscillator (VCO) with a wide tuning range and substantially constant voltage swing over the tuning range - A wide tuning range and constant swing VCO is described that is based on a multipass Ring Oscillator enhanced with feed-backward connections. This VCO is designed to overcome tuning range limitations of prior-art “feed-forward” ring oscillators. The Feedback multipass Ring Oscillator of the invention provides decreasing frequency when tuned by increasing the feedback, thus covering a much wider tuning range irrespective of the speed limit of the technology while at the same time providing almost constant amplitude. | 2009-04-23 |
20090102526 | Spread Spectrum clock generator - A delay-type phase adjusting circuit including a first variable delay circuit for receiving a reference clock signal and adding a delay to the reference clock signal, for output a phase comparator for receiving an output of the first variable delay circuit and the reference clock signal and detecting a phase difference therebetween a control circuit for generating a control signal for variably controlling a delay value of the first variable delay circuit based on a result of phase comparison by said phase comparator a second variable delay circuit for receiving an input signal and adding a delay to the input signal, for output a computation circuit for receiving a predetermined value and the control signal and variably controlling a delay value of the second variable delay circuit. | 2009-04-23 |
20090102527 | Semiconductor device including DLL circuit, and data processing system - A DLL circuit includes: a phase determining circuit that compares phases of respective rising edges of CK and LCLK to generate a determining signal R-U/D; a phase determining circuit that compares phases of respective falling edges of CK and LCLK to generate a determining signal F-U/D; a first adjusting circuit that adjusts a position of an active edge of LCLKR based on the determining signal R-U/D; a second adjusting circuit that adjusts a position of an active edge of LCLKF based on the determining signal F-U/D; a clock generating circuit that generates LCLK based on LCLKR and LCLKF; and a stop circuit that stops an adjusting operation by the second adjusting circuit in response to an adjusting direction of the active edge of LCLKR being opposite to each other to an adjusting direction of the active edge of LCLKF. | 2009-04-23 |
20090102528 | SEMICONDUCTOR INTEGRATED CIRCUIT - During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator. | 2009-04-23 |
20090102529 | SHIFTING INACTIVE CLOCK EDGE FOR NOISE REDUCTION - An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: multiple clocked elements; a clock signal source providing clock signals to the multiple clocked elements; and a clock shifting means coupled between the clock signal source and each of the multiple clocked elements; wherein the clock shifting means shifts clock signals of the multiple clocked elements such that the clock signals of the multiple clocked elements have aligned active edges and misaligned inactive edges to reduce the clock noise generated by the inactive edges of the clock signals. | 2009-04-23 |
20090102530 | Reference pulse discrimination method - The invention relates to a method of forming a reference pulse I | 2009-04-23 |
20090102531 | Semiconductor Integrated Circuit - [Problems] To provide a semiconductor integrated circuit by which what has been referred to as two-pattern test is made possible without greatly increasing an occupying area. | 2009-04-23 |
20090102532 | Latch circuit - A latch circuit includes: a first terminal; a second terminal; a first data-gating circuit coupled to the first terminal and the second terminal, the first data-gating circuit non-reversely gating the second signal in response to the first signal to reveal a third signal; a second data-gating circuit coupled to the first terminal and the second terminal, the second data-gating circuit reversely gating the second signal in response to the first signal to reveal a fourth signal; a third terminal receiving a fifth signal; a selector circuit coupled to the first data-gating circuit and the second data-gating circuit, the selector circuit outputting one of the third signal and the fourth signal in response to the fifth signal to latch one of the third signal and the fourth signal, respectively; and a bistable circuit coupled to the selector circuit, the bistable circuit holding one of the third signal and the fourth signal. | 2009-04-23 |
20090102533 | Temperature Independent Delay Circuits - Delay circuits are provided. Some embodiments of delay circuits herein include a delay line including multiple delay cells connected in series and a variable voltage supplier operative to output a voltage value proportional and/or inversely proportional to a temperature. Delay circuits may include at least one loading capacitor that includes a first end that is connected to an output port of the delay cell and a second end that is connected to an output port of the variable voltage supplier., the at least one loading capacitor including a capacitance that is decreased corresponding to an increase in temperature when a positive voltage is applied across the first end and the second end of the at least one loading capacitor. | 2009-04-23 |
20090102534 | Decentralised fault-tolerant clock pulse generation in vlsi chips - The invention relates to a method for distributed, fault-tolerant clock pulse generation in hardware systems, wherein the system clock pulse is generated in distribution by a plurality of intercommunicating fault-tolerant clock pulse synchronization algorithms (TS-Algs), in which an arbitrary number of such TS-Algs exchange information between one another via a user-defined and permanent network (TS-Net) of clock pulse signals, susceptible to transient faults, and each TS-Alg is assigned to one or more functional units (Fu | 2009-04-23 |
20090102535 | CLOCK SIGNAL CIRCUIT FOR MULTIPLE LOADS - A clock signal circuit for multiple loads includes a clock generator and M loads. The clock generator includes N clock generator pins which output clock signals having a same frequency. The N clock generator pins are all connected to a connection point. The connection point is connected to M loads via M transmitting lines respectively, wherein M is larger than N, M and N each is an integer greater than 2. | 2009-04-23 |
20090102536 | DATA TRANSMISSION SYSTEM - A data transmission system is made up from: a transmission circuit ( | 2009-04-23 |
20090102537 | METHOD OF FORMING A SIGNAL LEVEL TRANSLATOR AND STRUCTURE THEREFOR - In one embodiment, a first portion ( | 2009-04-23 |
20090102538 | ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICE - An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array. | 2009-04-23 |
20090102539 | SWITCH ELEMENTS AND PIXELS - A pixel, according to the invention, comprises a pixel electrode, a data line, and a switch element. The switch element comprises a gate electrode, a first electrode, a second electrode, and a semiconductor layer. The first electrode is electrically connected to the pixel electrode and comprises a first portion and a second portion. The second portion has a curved structure and comprises a first terminal connected to the first portion and a second terminal. The first terminal of the second portion is substantially aligned with the second terminal thereof. The second electrode is electrically connected to the data line. The second electrode forms or the second electrode and the data line together form a concave area where the first electrode is disposed in. The semiconductor layer is disposed between the first electrode, the second electrode, and the gate electrode. | 2009-04-23 |
20090102540 | SWITCH APPARATUS AND CONTROL APPARATUS - There is provided a switching apparatus that switches connection or non-connection between two terminals. The switching apparatus includes a series connection FET (field effect transistor) of which a source and a drain are connected to the two terminals, and a series connection control section that supplies a series connection control signal to perform switching control between the source and the drain to a gate of the series connection FET, and once transits, when switching the series connection FET from an OFF state to an ON state, the series connection control signal from an off-state voltage to hold the OFF state to a voltage exceeding an on-state voltage to hold the ON state and then makes the series connection control signal be the on-state voltage. | 2009-04-23 |
20090102541 | SWITCHING CIRCUIT ARRANGEMENT - A switching circuit arrangement ( | 2009-04-23 |
20090102542 | Switch with Reduced Insertion Loss - A circuit includes an amplifier having an input and an output; and at least one transistor comprising at least one terminal and at least one isolated well. The input of the amplifier is electrically connected to the at least one terminal of the transistor; and the output of the amplifier is electrically connected to the at least one isolated well of the at least one transistor. | 2009-04-23 |
20090102543 | NEGATIVE VOLTAGE GENERATING CIRCUIT - A negative voltage generating circuit for providing a negative voltage for an electronic circuit, includes a voltage input terminal receiving a positive voltage, a voltage output terminal outputting the negative voltage to the electronic circuit, a pulse generator, a first transistor, a second transistor, a first capacitor, at least one first diode, a second diode, a second capacitor, and a first resistor. When the pulse generator outputs a high level signal, the capacitor is charged, and the full voltage of the capacitor equals the difference between the voltage of the voltage input terminal and the voltage of the at least one first diode. When the pulse generator outputs a low level signal, the capacitor discharges through the first resistor, the voltage output terminal outputs a negative voltage, the value of the negative voltage equals the difference between the voltage of the capacitor and the voltage of the second diode. | 2009-04-23 |
20090102544 | SEMICONDUCTOR DEVICE INCLUDING DETECTOR CIRCUIT CAPABLE OF PERFORMING HIGH-SPEED OPERATION - A detector circuit and a negative voltage generating circuit capable of performing a high-speed operation are provided. A negative voltage generating circuit includes a charge pump circuit, a first voltage divider circuit that makes a voltage division between an output of the charge pump circuit and a power supply to output a detect potential, a reference voltage generating circuit that generates a reference potential, and a comparator circuit that compares the detect potential and the reference potential. The charge pump circuit is driven by an output signal of the comparator circuit and generates the negative voltage. In the first voltage divider circuit, NMOS transistors make the voltage division between the negative voltage and the power supply to obtain the detect potential. | 2009-04-23 |
20090102545 | SIGNAL PROCESSING METHOD AND SIGNAL PROCESSING APPARATUS - An input signal (Vin) is divided into n (≧3) number of divided signals which are weighted by first weights (ki). The weighted divided signals are processed by n number of signal processing means | 2009-04-23 |
20090102546 | COMPOSITE BAND-PASS FILTER AND METHOD OF FILTERING QUADRATURE SIGNALS - A composite band-pass filter receives a quadrature input signal and passes an intermediate frequency signal while attenuating all other signals including an undesired image signal. The composite band-pass filter is comprised of a continuous time polyphase filter and a discrete time polyphase filter and can amplify signals. The amplification is distributed through out the composite band-pass filter and the amount of amplification may be selected by control signals. The composite band-pass filter has improved dynamic range and noise characteristics, selectable amplification and replaces an external crystal filter. | 2009-04-23 |
20090102547 | FLYBACK CURRENT CONTROL - One embodiment of the invention includes a power driver system. The power driver system comprises a power transistor that is activated to provide power to a load and a switching circuit configured to control the power transistor based on a control signal. The power driver system further comprises a control circuit configured to detect a flyback current from the load upon deactivation of the power transistor and to cause the switching circuit to steer the flyback current from a first flyback current path to a second flyback current path in response to detecting the flyback current path. The second flyback current path can have an impedance that is greater than the first flyback current path. | 2009-04-23 |
20090102548 | Coil enhancement circuit - An enhancement circuit for enhancing the value of a coil having a first winding. The enhancement circuit comprises a second winding forming a transformer with the first winding and having a first terminal coupled to the ground and a second terminal coupled to an input of a feedback circuit. The feedback circuit senses the voltage over the coil and comprises a transconductance amplifier that amplifies and converts the sensed voltage into a current injected back in the second winding. In a preferred embodiment, the coil has a pair of windings and is used in a double-ended low-pass filter, as an xDSL splitter for telecommunication applications. The pair of windings is then coupled between telecommunication input terminals and output terminals of the low-pass filter. The improved enhancement circuit comprises a third and a fourth winding both coupled to the first and second windings. The third winding has a first terminal coupled to the ground and a second terminal coupled to the input of the feedback circuit, whilst the fourth winding has a first terminal also coupled to the ground and a second terminal coupled to the output of the feedback circuit. This feedback circuit senses the voltage over the coil and comprises a transconductance amplifier that amplifies and converts the sensed voltage into a current injected in the fourth winding via the second terminal thereof. | 2009-04-23 |
20090102549 | DIGITAL PULSE WIDTH MODULATED FEEDBACK SYSTEM FOR A SWITCHING AMPLIFIER AND METHOD THEREFOR - A switching amplifier includes a power stage, a low pass filter, a combining circuit, and a feedback correction circuit. The power stage has an input terminal and an output terminal. The low pass filter has an input terminal coupled to the output terminal of the power stage, and an output terminal for providing a filtered pulse width modulated signal. The combining circuit has a first input terminal coupled to the output terminal of the power stage, a second input terminal coupled to the output terminal of the low pass filter, and an output terminal. The feedback correction circuit has a first input terminal for receiving a reference pulse width modulated signal, a second input terminal coupled to the output terminal of the combining circuit, and an output terminal coupled to the input terminal of the power stage. | 2009-04-23 |
20090102550 | AUDIO SIGNAL AMPLIFIER CIRCUIT WITH A MUTE FUNCTION - An integrator generates analog voltage in a manner that in an active state a duty ratio of an output signal of an class D amplifier is brought close to a duty ratio defined by an analog audio signal. A first mute circuit forcibly turns on the class D amplifier in an active state. In an active state, A voltage-fixing circuit fixes an output terminal of the class D amplifier to a predetermined fixed potential of Vdd/2. A second mute circuit is provided between an output terminal of a filter and ground, and connects the output terminal of the filter to ground in an active state. A mute control unit controls the integrator, the first mute circuit, the voltage-fixing circuit and the second mute circuit, respectively. As a result, the noise at the time of start and stop can be optimally reduced. | 2009-04-23 |
20090102551 | OPERATIONAL AMPLIFIER WITH IMPROVED CURRENT MONITORING AND SCALABLE OUTPUT - A low-power, low-voltage feedback class AB operational amplifier is disclosed. The minimum supply voltage is one gate-source voltage and two saturation voltages. Currents on the output p-type and n-type transistors are monitored as part of the feedback loop control. Accurate monitoring is achieved by connecting current monitors directly to the corresponding voltage rail. Additional output stages may be selectively connected to the primary output stage to dynamically adjust to changes source conditions. Thus by connecting the appropriate number and type of additional output stages, continuous time adaptive power supply compensation is achieved. Both single ended and differential topologies are described. | 2009-04-23 |
20090102552 | SEMICONDUCTOR INTEGRATED CIRCUIT WITH VARIABLE GAIN AMPLIFIER - The variable gain amplifier includes a bias circuit (BC) | 2009-04-23 |
20090102553 | DOHERTY AMPLIFIER - The present invention relates to the construction of output stage of the Doherty amplifier and comprises a main amplifying unit, an auxiliary amplifying unit and a compact λ/4 line connecting two amplifying units. The compact λ/4 line connecting two amplifying units includes a first parallel capacitor grounded by being connected to the main amplifying unit in parallel; a second parallel capacitor grounded by being connected to the auxiliary amplifying unit in parallel; and an inductor or a microstrip transmission line connecting the main amplifying unit and the auxiliary amplifying unit. The Doherty amplifier in accordance with the present invention further comprises a matching network unit connecting to a final output by connecting the main amplifying unit and the auxiliary amplifying unit and; and a λ/4 line used as the voltage inputs of the main amplifying unit and the auxiliary amplifying unit. | 2009-04-23 |
20090102554 | Output Networks In Combination With LINC Technique - The present invention relates to balanced power amplifier network in combination with outphasing techniques such as Chireix. The object of the present invention is to provide a solution to the problem to combine balanced amplifiers like the current mode class D (CMCD) or class E/F with a LINC network. The main problem is that some power amplifiers have balanced output and the LINC network is single-ended so that a high power low loss transformer that works at several impedance levels is needed, which is hard to realize at cellular frequencies. | 2009-04-23 |
20090102555 | Automatic gain Control (AGC) with lock detection - A method, algorithm, circuits, and/or systems for automatic gain control (AGC) are disclosed. In one embodiment, an AGC circuit can include a comparator configured to compare an output of an amplifier against a reference voltage, gain logic configured to decrease a gain of the amplifier when an output of the comparator has a first state, and to periodically increase the gain of the amplifier, a digital-to-analog converter (DAC) configured to receive an output from the gain logic and control the gain of the amplifier, and lock detection logic configured to determine from the output of the gain logic when the gain of the amplifier is in a predetermined range. | 2009-04-23 |
20090102556 | CLASS D AMPLIFIER - A Class D amplifier includes a ramp generator that generates a ramp signal and an inverted ramp signal. A signal generator generates first, second, third and fourth signals by comparing the ramp and inverted ramp signals to an input signal. A frequency of the ramp signal is approximately two orders of magnitude higher than a frequency of the input signal. The signal generator transitions from a first state to a second state of a first control signal after one of the first and second signals occurs, transitions from a first state to a second state of a second control signal after one of the third and fourth signals occurs, and transitions from the second state to the first state of one of the first and second control signals when the other of the first and second control signals transitions to the second state. An output stage includes first and second switches that are controlled based on the first and second control signals, respectively, and generates output current based on the first and second control signals. | 2009-04-23 |
20090102557 | Class D amplifier - The invention is directed to a class D amplifier. According to the class D amplifier, sound data applied to an input terminal is supplied through a compensation circuit to a PWM circuit, from which a PWM signal is output. The PWM signal is converted to an analog signal through a first low pass filter, which is delivered to a speaker. On the other hand, the sound data is delayed by a delay circuit, and is converted to an analog signal by a digital to analog converter. The higher frequency components of the data are removed by a second low pass filter, and the rest of the data is furnished to a differential amplifier. The differential amplifier amplifies a difference between an output of the first low pass filter and an output of the second low pass filter, which is then supplied to an analog to digital converter. The analog to digital converter converts an output from the differential amplifier to digital data, which is then supplied to the compensation circuit. By doing so, a compensation value based on an output from the analog to digital converter is added to the following PCM sound data that is applied to the input terminal. | 2009-04-23 |
20090102558 | OPERATIONAL AMPLIFIER - An operational amplifier includes a first differential stage, a second differential stage, a second cascade amplifier stage, an output unit, a first switching control unit and a second switching control unit. When an external signal for stopping operation is input, the first switching control unit shuts off a connection between a non-inverting input terminal and a control electrode of one input transistor at each first and second differential stage, and shuts off a connection between an inverting input terminal and a control electrode of another input transistor at the first and second differential stages, and the second switching control unit connects the negative-side power supply voltage terminal to each control gate of the input transistors at the first and second differential stages and to the substrate gates of the input transistors at the first differential stage. | 2009-04-23 |