17th week of 2015 patent applcation highlights part 17 |
Patent application number | Title | Published |
20150108591 | VIBRATOR, MANUFACTURING METHOD OF VIBRATOR, ELECTRONIC DEVICE, ELECTRONIC APPARATUS, AND MOVING OBJECT - A vibrator includes a base, a lid, and a functional element that is stored in a cavity formed by the base and the lid, in which the lid is provided with a sealing hole that penetrates through the lid and a sealing member that air-tightly seals the sealing hole, and in which the functional element includes a diffusion object shielding portion having a region of an accommodation opening which overlaps at least part of a region of a first opening of the sealing hole on a surface of the lid on the cavity side in a plan view of the functional element and the lid. | 2015-04-23 |
20150108592 | A MULTIFERRO-HETEROSTRUCTURE COMPOSITION HAVING TUNABLE MAGNETIC COUPLING AT ROOM TEMPERATURE - A ferromagnetic/ferroelectric heterostructure thin film is disclosed that exhibits significant magneto-electric coupling. The ferromagnetic/ferroelectric heterostructure thin film includes a) a base layer of silicon substrate, b) a first copper layer deposited on the silicon substrate, c) a first iron layer deposited on the copper layer, d) first aluminum layer deposited on the first iron layer, e) a polymer layer exhibiting ferroelectric properties deposited on the first aluminum layer, f) a second aluminum layer deposited on the polymer layer; g) a second iron layer deposited on the second aluminum layer, and h) a second copper layer deposited on the second iron layer. | 2015-04-23 |
20150108593 | Magnetic Seed for Improving Blocking Temperature and Shield to Shield Spacing in a TMR Sensor - The blocking temperature of the AFM layer in a TMR sensor has been raised by inserting a magnetic seed layer between the AFM layer and the bottom shield. This gives the device improved thermal stability, including improved SNR and BER. | 2015-04-23 |
20150108594 | Side Shielded Magnetoresistive (MR) Read Head with Perpendicular Magnetic Free Layer - A MR sensor is disclosed that has a free layer (FL) with perpendicular magnetic anisotropy (PMA) which eliminates the need for an adjacent hard bias structure to stabilize free layer magnetization and minimizes shield-FL interactions. In a TMR embodiment, a seed layer, free layer, junction layer, reference layer, and pinning layer are sequentially formed on a bottom shield. After patterning, a conformal insulation layer is formed along the sensor sidewall. Thereafter, a top shield is formed on the insulation layer and includes side shields that are separated from the FL by a narrow read gap. The sensor is scalable to widths <50 nm when PMA is greater than the FL self-demag field. Effective bias field is rather insensitive to sensor aspect ratio which makes tall stripe and narrow width sensors a viable approach for high RA TMR configurations. Sensor sidewalls may extend into the seed layer or bottom shield. | 2015-04-23 |
20150108595 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE - The present invention relates to a solid-state imaging device. In a pixel array section in the solid-state imaging device, a vertical signal line is provided right under power supply wiring apart from a floating diffusion region in order to reduce load capacitance of the vertical signal line. Furthermore, the power supply wiring is wired to make a cover rate of each vertical signal line with respect to the power supply wiring nearly uniform. As a result, it is possible to suppress variation of load capacitance of the vertical signal line for each pixel. It becomes possible to suppress deviation in a black level, variation of charge transfer, and variation of settling. It becomes possible to obtain an image with higher quality. | 2015-04-23 |
20150108596 | METHOD PROVIDING AN EPITAXIAL PHOTONIC DEVICE HAVING A REDUCTION IN DEFECTS AND RESULTING STRUCTURE - A method of forming a photonic device and resulting structure are described in which the photonic device is epitaxially grown over a substrate surface vertically, and laterally over trench isolation regions formed in the substrate surface. | 2015-04-23 |
20150108597 | IMAGE CAPTURING LENS ASSEMBLY, IMAGE CAPTURING DEVICE AND MOBILE TERMINAL - An image capturing lens assembly includes, in order from an object side to an image side, a first lens element, a second lens element and a third lens element. The first lens element with positive refractive power has a convex object-side surface and a convex image-side surface, wherein the surfaces of the first lens element are aspheric. The second lens element with positive refractive power has a concave object-side surface and a convex image-side surface, wherein the surfaces of the second lens element are aspheric. The third lens element with negative refractive power has a concave image-side surface in a paraxial region thereof, wherein the image-side surface of the third lens element has at least one convex shape in an off-axis region thereof, and the surfaces of the third lens element are aspheric. The image capturing lens assembly has a total of three lens elements with refractive power. | 2015-04-23 |
20150108598 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - There is provided a solid-state imaging device including: a semiconductor substrate that is formed with a photodiode for each pixel; a light shielding film that is laminated on the semiconductor substrate on a side of a light irradiated surface which is irradiated with light, and is formed to include an opening corresponding to a spot in which at least the photodiode is arranged; and a photoelectric conversion film that is laminated to cover the light irradiated surface of the semiconductor substrate and the light shielding film, and is configured to generate an electrical charge by absorbing light. The photoelectric conversion film is formed of a material which has higher light absorptivity than light absorptivity of the semiconductor substrate. | 2015-04-23 |
20150108599 | SEMICONDUCTOR APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS, METHOD OF DESIGNING SEMICONDUCTOR APPARATUS, AND ELECTRONIC APPARATUS - A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via. | 2015-04-23 |
20150108600 | METHOD PROVIDING AN EPITAXIAL GROWTH HAVING A REDUCTION IN DEFECTS AND RESULTING STRUCTURE - Disclosed are methods and resulting structures which provide an opening for epitaxial growth, the opening having an associated projection for reducing the size of the contact area on a substrate at which growth begins. During growth, the epitaxial material grows vertically from the contact area and laterally over the projection. The projection provides a stress relaxation region for the lateral growth to reduce dislocation and stacking faults at the side edges of the grown epitaxial material. | 2015-04-23 |
20150108601 | SEMICONDUCTOR DEVICE INCLUDING A WALL OXIDE FILM AND METHOD FOR FORMING THE SAME - A semiconductor device includes an oxide film structure having different thicknesses depending on where the oxide film structure is formed. In the semiconductor device, a wall oxide film is formed to have different thicknesses depending on locations of sidewalls of an active region. The semiconductor device includes an active region, a first wall oxide film disposed over a first sidewall of the active region that extends along a first direction of the active region, the first wall oxide film having a first thickness, and a second wall oxide film disposed over a second sidewall of the active region that extends along a second direction of the active region, a second wall oxide film having a second thickness that is different from the first thickness. | 2015-04-23 |
20150108602 | SEMICONDUCTOR DEVICE INCLUDING FUSE STRUCTURE - A semiconductor device includes a substrate having a fuse area and a device area; a fuse structure in an insulating layer of the fuse area, and a wire structure in the insulating layer of the device area. The fuse structure includes a fuse via, a fuse line electrically connected to a top end of the fuse via pattern and extending in a direction. The wire structure includes a wire via, a wire line electrically connected to a top end of the wire via and extending in the first direction. A width in the first direction of the fuse via is smaller than a width in the first direction of the wire via. | 2015-04-23 |
20150108603 | SEMICONDUCTOR DEVICE WITH PATTERNED GROUND SHIELDING - Semiconductor devices and methods of formation are provided herein. A semiconductor device includes a first inductor, a patterned ground shielding (PGS) proximate the first inductor comprising one or more portions and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. The semiconductor device also has a configuration including a first inductor on a first side of the PGS, a second inductor on a second side of the PGS and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. Selective coupling of portions of the PGS by activating or deactivating switches alters the behavior of the first inductor, or the behavior and interaction between the first inductor and the second inductor. A mechanism is thus provided for selectively configuring a PGS to control inductive or other properties of a circuit. | 2015-04-23 |
20150108604 | SEMICONDUCTOR MODULE CARRYING THE SAME - In the conventional high-speed, large-current semiconductor chip, all the electric connecting terminals were placed on one surface of the chip. For this reason, to supply stable supply currents or reduce noises mixed into the signal system from the power supply, many terminals were assigned to supply current inflow terminals and supply current outflow terminals. As a result, there is a problem that the terminal number of a semiconductor device is increased and the mounting area thereof is increased. | 2015-04-23 |
20150108605 | Integrated Circuit Devices Having Through Silicon Via Structures and Methods of Manufacturing the Same - An integrated circuit device is provided. The integrated circuit device includes: a capacitor including an electrode formed in a first area on a substrate; a through-silicon-via (TSV) landing pad formed in a second area on the substrate, the TSV landing pad including the same material as the electrode; a multi-layered interconnection structure formed on the capacitor and the TSV landing pad; and a TSV structure passing through the substrate, the TSV structure being connected to the multi-layered interconnection structure through the TSV landing pad. | 2015-04-23 |
20150108606 | ELECTRONIC CHIP WITH MEANS OF PROTECTING ITS BACK FACE - Electronic chip comprising:
| 2015-04-23 |
20150108607 | INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF - An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above. | 2015-04-23 |
20150108608 | POLYSILICON RESISTOR STRUCTURE HAVING MODIFIED OXIDE LAYER - Various embodiments include resistor structures. Particular embodiments include a resistor structure having multiple oxide layers, at least one of which includes a modified oxide. The modified oxide can aid in controlling the thermal capacitance and the thermal time constant of the resistor structure, or the thermal dissipation within the resistor structure. | 2015-04-23 |
20150108609 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus ( | 2015-04-23 |
20150108610 | NEARLY BUFFER ZONE FREE LAYOUT METHODOLOGY - In some embodiments, an integrated circuit includes a central array region having a first layout feature density. A background region surrounds the central array region and has a second layout feature density, which is different from the first density. A peripheral array region surrounds the central array region and separates the central array region from the background region. The peripheral array region has a third layout feature density between the first and second layout feature densities. | 2015-04-23 |
20150108611 | SEMICONDUCTOR INTEGRATED DEVICE FOR DISPLAY DRIVE - In a display drive IC chip of an LCD or the like, an alignment mark is arranged in an alignment mark arrangement region on the main surface thereof, a dummy pattern is arranged on a lower layer, and an actual pattern is further arranged on the lower layer. | 2015-04-23 |
20150108612 | METHOD FOR THINNING, METALIZING, AND DICING A SEMICONDUCTOR WAFER, AND SEMICONDUCTOR DEVICE MADE USING THE METHOD - There is provided a method of fabricating a semiconductor device, method including: a) forming semiconductor elements in plural element regions surrounded by assumed dicing lines on a first principal surface of a semiconductor wafer; b) grinding the second principal surface in such a way that an outer peripheral portion of a second principal surface on the opposite side of the first principal surface of the semiconductor wafer becomes thicker than an inner peripheral portion of the second principal surface; c) forming a metal film, in such a way as to avoid sections corresponding to the dicing lines, on the second principal surface that has been ground in the grinding step; and d) cutting the semiconductor wafer from the second principal surface side along portions where the metal film is not formed on the dicing lines. | 2015-04-23 |
20150108613 | SEMICONDUCTOR CHIP WITH SEAL RING AND SACRIFICIAL CORNER PATTERN - A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner. | 2015-04-23 |
20150108614 | SEMICONDUCTOR DEVICE, CIRCUIT SUBSTRATE, AND ELECTRONIC DEVICE - A semiconductor device has a through electrode formed in a through hole which penetrates a Si substrate from one surface to the other surface of the Si substrate, wherein a rectangular electrode pad is provided on the other surface with an insulation film laid between the electrode pad and the other surface, an opening of the through hole on the one surface side is circular, an opening of the through hole on the other surface side is rectangular, and the area of the opening on the other surface side is made smaller than the area of the opening on the one surface side. | 2015-04-23 |
20150108615 | TECHNIQUE FOR CONTROLLING POSITIONS OF STACKED DIES - An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terrace at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component. In particular, the assembly component may include a pair of stepped terraces that approximately mirror the stepped terrace of the chip package and which provide vertical position references for an assembly tool that positions the set of semiconductor dies in the vertical stack during assembly of the chip package. | 2015-04-23 |
20150108616 | MULTI-HEIGHT MULTI-COMPOSITION SEMICONDUCTOR FINS - A dielectric material layer is formed on a semiconductor-on-insulator (SOI) substrate including a top semiconductor layer containing a first semiconductor material. An opening is formed within the dielectric material layer, and a trench is formed in the top semiconductor layer within the area of the opening by an etch. A second semiconductor material is deposited to a height above the top surface of the top semiconductor layer employing a selective epitaxy process. Another dielectric material layer can be deposited, and another trench can be formed in the top semiconductor layer. Another semiconductor material can be deposited to a different height employing another selective epitaxy process. The various semiconductor material portions can be patterned to form semiconductor fins having different heights and/or different compositions. | 2015-04-23 |
20150108617 | Method for Chemically Passivating a Surface of a Product Made of a III-V Semiconductor Material and the Product Obtained by Such a Method - A method for chemically passivating a surface of a product made of a III-V semiconductor material in which a) a P(N) polymer film is formed by deposition in a solvent comprising liquid ammonia. The film is formed by deposition, without electrochemical assistance, in the solvent, in the presence of an oxidizing chemical additive comprising phosphorous and generating electrical charge carriers in said surface. | 2015-04-23 |
20150108618 | COMPOSITION AND METHOD FOR FORMING A DIELECTRIC LAYER - A porous layer is described. The porous layer comprises a solidified sol-gel inorganic material having a distribution of nanometric voids, wherein at least some of nanometric voids are at least partially coated internally by carbon or a hydrophobic substance containing carbon. | 2015-04-23 |
20150108619 | METHOD FOR PATTERNING A SEMICONDUCTOR SUBSTRATE - Embodiments of the present disclosure provide methods for patterning rectangular features with a sequence of lithography, atomic layer deposition (ALD) and etching. Embodiment of the present disclosure includes forming first line clusters along a first direction and second line clusters over the first line clusters in a direction traversing the first direction. The first and second line clusters both include core lines formed from a core material, spacers formed from first and second materials by ALD and etching. After formation of the first and second line clusters, rectangular openings can be formed by selectively etching one or two of the core material, the first material or the second material. | 2015-04-23 |
20150108620 | Superjunction Semiconductor Device and Method for Producing Thereof - A method of forming a superjunction device includes forming at least one trench in a first surface of a first semiconductor layer of a first doping type, and a semiconductor mesa region adjoining the at least one trench. A second semiconductor layer is formed at least on sidewalls and a bottom of the at least one trench. The second semiconductor layer is etched by filling the at least one trench with an etchant, and applying a voltage between the first semiconductor layer and the etchant such that a space charge region expands in the second semiconductor layer and in the first semiconductor layer. The voltage is adjusted such that there is a first region in the semiconductor mesa region that is free of the space charge region when the voltage is applied. | 2015-04-23 |
20150108621 | SHIELDED DEVICE PACKAGES AND RELATED FABRICATION METHODS - Shielded device packages and related fabrication methods are provided. An exemplary device package includes one or more electrical components, a molding compound overlying the one or more electrical components, a frame structure circumscribing the one or more electrical components, and a shielding structure overlying the frame structure and the one or more electrical components. The shielding structure contacts a first surface of the frame structure, at least a portion of the molding compound resides between the shielding structure and the one or more electrical components, and the first surface of the frame structure is aligned with a second surface of the portion of the molding compound. | 2015-04-23 |
20150108622 | INTERCONNECT BOARD AND SEMICONDUCTOR DEVICE - Impedance mismatching to be caused in signal transmission paths is reduced, without any restriction being put on the number of layers. | 2015-04-23 |
20150108623 | COATED LEAD FRAME BOND FINGER - A lead frame includes a lead formed of a conductive material and having first and second ends, opposing first and second main surfaces, and opposing first and second side surfaces each extending between the first and second main surfaces. A polymeric layer is formed at least on the first main surface and the first and second side surfaces of the lead at least proximate the second end of the lead. An opening in the polymeric layer on the first main surface of the lead proximate the second end is provided for connecting the lead to, for example, a semiconductor die via a bond wire. | 2015-04-23 |
20150108624 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor chip, and a lead frame. The semiconductor chip is mounted over a die pad. Four suspension leads are connected with the die pad and at least one of them is provided between first and second lead groups and is deformed to protrude toward the first lead group. At least one of the leads of the second lead group which is nearer to the deformed suspension lead is deformed to be apart from remaining leads of the second lead group. | 2015-04-23 |
20150108625 | SEMICONDUCTOR DEVICE WITH HEAT SPREADER - A semiconductor device includes a package body, a semiconductor die embedded in the package body and a heat spreader attached to a top surface of the package body and spaced from semiconductor die. The heat spreader may be formed of solder that is melted within a recess in the top surface of the package body. | 2015-04-23 |
20150108626 | Multilevel Leadframe - A multilevel leadframe for an integrated circuit package is provided that has a plurality of lead lines formed in a first level and bond pads formed in a second level. A first set of bond pads is arranged in a first row and are separated from an adjacent bond pad by a bond pad clearance distance. A second set of bond pads is arranged in second row adjacent the first row of bond pads. Each bond pad in the second row may be connected to one of the plurality of lead lines on the first level that is routed between adjacent bond pads in the first row. Since the bond pads in the first row are on a different level then the lead lines, the bond pads may be spaced close together. | 2015-04-23 |
20150108627 | ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING ELECTRONIC COMPONENT - An electronic component comprises: a resin frame; a semicionductor substrate housed in the resin frame; a plate shape metal member having at least one end fixed in the resin frame at a position spaced apart from the semiconductor substrate; an electrical connection region portion formed on the surface on the side of the plate shape metal member of the semiconductor substrate with an electrically conductive material; and a solder layer formed on the surface on the side of the plate shape metal member of the electrical connection region portion, wherein the plate shape metal member supports the semiconductor substrate without contact through the solder layer and the electrical connection region portion, and is electrically connected to the electrical connection region portion. | 2015-04-23 |
20150108628 | Packages with Thermal Interface Material on the Sidewalls of Stacked Dies - A package includes a die stack that includes at least two stacked dies, and a Thermal Interface Material (TIM). The TIM includes a top portion over and contacting a top surface of the die stack, and a sidewall portion extending from the top portion down to lower than at least one of the at least two stacked dies. A first metallic heat-dissipating feature is over and contacting the top portion of TIM. A second metallic heat-dissipating feature has a sidewall contacting a sidewall of the sidewall portion of the TIM. | 2015-04-23 |
20150108629 | SEMICONDUCTOR DEVICE - A cooling fin | 2015-04-23 |
20150108630 | ELECTRONIC DEVICE, ELECTRONIC APPARATUS, AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - An electronic device includes a first circuit board; a heat sink fixed to the first circuit board to form a cavity between the heat sink and the first circuit board; and a plurality of electronic components fixed to a surface of the heat sink facing the first circuit board inside the cavity, the plurality of electric components having heights different from each other, wherein each of the plurality of electronic components is electrically coupled to the first circuit board by a second circuit board and being different from the first circuit board. | 2015-04-23 |
20150108631 | 3DIC Packages with Heat Dissipation Structures - A package includes a first die and a second die underlying the first die and in a same first die stack as the first die. The second die includes a first portion overlapped by the first die, and a second portion not overlapped by the first die. A first Thermal Interface Material (TIM) is over and contacting a top surface of the first die. A heat dissipating lid has a first bottom surface contacting the first TIM. A second TIM is over and contacting the second portion of the second die. A heat dissipating ring is over and contacting the second TIM. | 2015-04-23 |
20150108632 | THIN FILM WITH NEGATIVE TEMPERATURE COEFFICIENT BEHAVIOR AND METHOD OF MAKING THEREOF - A conductive thin film including a binder matrix and semiconductor nanowires dispersed therein is disclosed. The semiconductor nanowires are in the range of 30% to 50% by weight percentage of the thin film. The present invention also discloses a method of making such thin film. The method includes the steps of: mixing a plurality of semiconductor nanowires with a polymer binder to obtain a printing ink; thinning the printing ink with a solvent to achieve a predetermined viscosity; printing the printing ink on a substrate to form a conductive thin film thereon and evaporating the solvent at a rate slower than the evaporation rate of water. | 2015-04-23 |
20150108633 | MECHANISMS FOR FORMING PROTECTION LAYER ON BACK SIDE OF WAFER - Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure is provided. The semiconductor device structure includes a substrate having a front side and a back side. The semiconductor device structure also includes devices formed on the front side of the substrate and interconnect structures formed on the devices. The semiconductor device structure further includes a protection layer formed on the back side of the substrate, and the protection layer has a thickness over about 10 A. | 2015-04-23 |
20150108634 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a die, a pad disposed on the die and configured to be electrically coupled with a bump through a conductive trace attached on the pad, a polymer disposed over the die and patterned to provide a path for the conductive trace passing through, and a molding surrounding the die and the polymer. A top surface of the molding is substantially in a same level as a top surface of the polymer. Further, a method of manufacturing a semiconductor device includes providing a die, forming a pad on the die, disposing a first polymer over the die, patterning the first polymer with an opening over the pad, disposing a sacrificial layer over the patterned first polymer, disposing a molding surrounding the die, removing a portion of the molding thereby exposing the sacrificial layer, removing the sacrificial layer thereby exposing the pad and the first polymer, disposing a second polymer on the first polymer, patterning the second polymer with the opening over the pad, and disposing a conductive material on the pad within the opening. | 2015-04-23 |
20150108635 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a three dimensional stack including a first semiconductor die and a second semiconductor die. The second semiconductor die is connected with the first semiconductor die with a bump between the first semiconductor die and the second semiconductor die. The semiconductor structure includes a molding compound between the first semiconductor die and the second semiconductor die. A first portion of a metal structure over a surface of the three dimensional stack and contacting a backside of the second semiconductor die and a second portion of the metal structure over the surface of the three dimensional stack and configured for electrically connecting the three dimensional stack with an external electronic device. | 2015-04-23 |
20150108636 | SUBMOUNT, ENCAPSULATED SEMICONDUCTOR ELEMENT, AND METHODS OF MANUFACTURING THE SAME - The present invention provides a submount which includes a semiconductor element and which can be easily connected to an IC on a main substrate. The submount in one embodiment of the present invention includes: a substrate; electrodes; the semiconductor element; Au wires; and gold bumps. The electrodes, the semiconductor element, the Au wires, and the gold bumps are encapsulated on the substrate by a resin. The gold bumps are formed on the electrodes and the Au wires by ball bonding and are cut by dicing such that side surfaces of the gold bumps are exposed. The exposed surfaces function as side surface electrodes of the submount. | 2015-04-23 |
20150108637 | SEMICONDUCTOR DEVICE INCLUDING TWO OR MORE CHIPS MOUNTED OVER WIRING SUBSTRATE - A semiconductor device includes a composite chip mounted over the a wiring substrate, the composite chip including a first area and a second area that is provided independently from the first area, the first area including a first circuit formed in the first area, and the second area including a second circuit formed in the second area. | 2015-04-23 |
20150108638 | Package on Package Structure and Method of Manufacturing the Same - A package on package structure includes a first substrate having a first region and a second region, a bump formed on the first region of the first substrate, a first semiconductor die bonded to the second region of the first substrate, and a semiconductor die package bonded to the first substrate. The bump includes a metallic structure and a plurality of minor elements dispersed in the metallic structure. The semiconductor die package includes a connector bonded to the bump, and the first semiconductor die is between the semiconductor die package and the first substrate. | 2015-04-23 |
20150108639 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Of three chips ( | 2015-04-23 |
20150108640 | THIN INTEGRATED CIRCUIT CHIP-ON-BOARD ASSEMBLY AND METHOD OF MAKING - An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface, where the first surface of the insulating layer is less than 10 microns below an upper plane of the integrated circuit assembly. An active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the active layer and formed on the second surface of the insulating layer, and is also electrically connected to a printed circuit board. A method of fabricating an integrated circuit assembly includes coupling a handle wafer to the active layer of a semiconductor-on-insulator wafer, removing the substrate of the semiconductor-on-insulator, forming a bond pad connecting to the active layer on the exposed insulator surface, bonding the bond pad to a printed circuit board using a solder bump, and removing the handle wafer. | 2015-04-23 |
20150108641 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device includes providing a carrier including a first layer, a second layer, a first surface of the first layer and a second surface of the second layer, disposing a plurality of solder bumps on the second surface, disposing a molding between the plurality of solder bumps and over the second surface, cutting the first layer to form a first recess in the first layer, wherein the first recess is above a position between at least two of the plurality of solder bumps, and cutting the molding from a bottom surface of the first recess to form a second recess in the molding between the at least two of the plurality of solder bumps. Further, a semiconductor device includes a carrier including a first layer and a second layer, a plurality of solder bumps disposed on the second layer, a molding disposed over the second layer and surrounding the plurality of solder bumps, the molding includes a protruded portion protruding from a sidewall of the first layer adjacent to an end portion of the first layer. | 2015-04-23 |
20150108642 | STRUCTURE TO PREVENT SOLDER EXTRUSION - A spacer structure formed adjacent a solder connection which prevents solder extrusion and methods of manufacture are disclosed. The method includes forming a solder preform connection on a bond pad of a chip. The method further includes forming a spacer structure on sidewalls of the solder preform connection. The method further includes subjecting the solder preform connection to a predetermined temperature to form a solder connection with the spacer structure remaining thereabout. | 2015-04-23 |
20150108643 | SEMICONDUCTOR DEVICE WITH EMBEDDED SEMICONDUCTOR DIE AND SUBSTRATE-TO-SUBSTRATE INTERCONNECTS - A semiconductor device having an embedded semiconductor die and substrate-to-substrate interconnects is disclosed and may include a substrate with a top surface and a bottom surface, a semiconductor die bonded to the top surface of the substrate, a first mold material encapsulating the semiconductor die and at least a portion of the top surface of the substrate, and a first conductive bump that is on the top surface of the substrate and is at least partially encapsulated by the first mold material. An extended substrate may be coupled to the substrate utilizing the first conductive bump. A second conductive bump may be formed on the bottom surface of the substrate, and a second mold material may encapsulate at least a portion of the second conductive bump and at least a portion of the bottom surface of the substrate. A third mold material may be formed between the first mold material and the extended substrate. | 2015-04-23 |
20150108644 | 3D Integrated Circuit and Methods of Forming the Same - An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer. | 2015-04-23 |
20150108645 | INTEGRATED CRACKSTOP - A method including forming a first dielectric layer above a conductive pad and above a metallic structure, the conductive pad and the metallic structure are each located within an interconnect level above a substrate, forming a first opening and a second opening in the first dielectric layer, the first opening is aligned with and exposes the conductive pad and the second opening is aligned with and exposes the metallic structure, and forming a metallic liner on the conductive pad, on the metallic structure, and above the first dielectric layer. The method may further include forming a second dielectric layer above the metallic liner, and forming a third dielectric layer above the second dielectric layer, the third dielectric layer is thicker than either the first dielectric layer or the second dielectric layer. | 2015-04-23 |
20150108646 | ELECTRO-MIGRATION ENHANCING METHOD FOR SELF-FORMING BARRIER PROCESS IN COPPER METTALIZATION - A method of forming a barrier on both the sidewalls and bottom of a via and the resulting device are provided. Embodiments include forming a metal line in a substrate; forming a Si-based insulating layer over the metal line and the substrate; forming a via in the Si-based insulating layer down to the metal line; forming a dual-layer Mn/MnN on sidewalls and a bottom surface of the via; and filling the via with metal. | 2015-04-23 |
20150108647 | HYBRID MANGANESE AND MANGANESE NITRIDE BARRIERS FOR BACK-END-OF-LINE METALLIZATION AND METHODS FOR FABRICATING THE SAME - A method for fabricating an integrated circuit includes providing a conductive material overlying a semiconductor substrate and a dielectric material overlying the conductive material, wherein an opening exposes a surface of the conductive material and sidewalls of the dielectric material and selectively depositing a first layer of a first barrier material on the surface of the conductive material with the sidewalls of the dielectric material remaining exposed, the first barrier material being such that, if annealed in an annealing process, the first barrier material would diffuse into the conductive material. The method further includes modifying the first barrier material on the exposed surface to form a second barrier material, the second barrier material being such that, during an annealing process, the second barrier material does not diffuse into the conductive material and depositing a second layer of the first barrier material along the sidewalls of the opening. Still further, the method includes annealing the semiconductor substrate. Integrated circuits fabricated in accordance with the foregoing method are also disclosed. | 2015-04-23 |
20150108648 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes first and second semiconductor members and a first barrier film. The first semiconductor member includes a first insulating film, and a first wiring film in the first insulating film, the surface of which is exposed in the first insulating film. The second semiconductor member includes a second insulating film, and a second wiring film in the second insulating film, the surface of which is exposed in the second insulating film. The first barrier film forms a barrier to diffusion of the material of the first wiring film into the second insulating film and is formed of a compound of metal element of the first wiring film and an element of the second insulating film in a region where the first wiring film and the second insulating film are in contact with each other at the junction interface of the first and second semiconductor members. | 2015-04-23 |
20150108649 | METHOD OF FORMING HYBRID DIFFUSION BARRIER LAYER AND SEMICONDUCTOR DEVICE THEREOF - In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall. At least one diffusion barrier material is then formed over the wall of the opening by at least two alternating steps, which are selected from the group consisting of a process of physical vapor deposition (PVD) and a process of atomic layer deposition (ALD). A liner layer is formed over the at least one diffusion barrier material. | 2015-04-23 |
20150108650 | EUTECTIC SOLDER STRUCTURE FOR CHIP - The present invention provides a eutectic solder structure for a chip including a substrate and a solder structure on the substrate. The solder structure includes an alternate lamination of a plurality of first metal layers and a plurality of second metal layers, wherein each second metal layer has a continuous region and a plurality of openings and the melting point of the plurality of second metal layers is higher than that of the plurality of first metal layers. The eutectic solder structure for a chip also includes a chip on the solder structure, wherein the chip is bonded to the substrate by a eutectic reaction of the solder structure. | 2015-04-23 |
20150108651 | SELF ALIGNED CONTACT FORMATION - The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal. | 2015-04-23 |
20150108652 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - A semiconductor device and its fabrication method are provided. A first dielectric layer is provided to cover a substrate. The first dielectric layer contains a plurality of first conductive layers. A portion of each first conductive layer is removed to form a plurality of first openings in the first dielectric layer. A second dielectric layer is formed in each first opening. A third dielectric layer having second-openings are formed on the first dielectric layer and on the second dielectric layers. Each second-opening exposes at least two adjacent second dielectric layers. Second dielectric layers exposed by a first second-opening are removed to form third openings to expose corresponding first conductive layers. Second conductive layers are formed in the third opening and the second-openings including the first second-opening. Stable electrical interconnections with high quality electrical isolations can be provided. | 2015-04-23 |
20150108653 | SENSOR DEVICE PACKAGES AND RELATED FABRICATION METHODS - Sensor device packages and related fabrication methods are provided. An exemplary sensor device package includes a first structure having a sensing arrangement thereon, a second structure having circuitry thereon, and a conductive structure within the first structure and coupled to the circuitry to provide an electrical connection to the circuitry through the first structure. Thus, circuitry on the second structure may be electrically connected to an interface of the sensor device package through the first structure. | 2015-04-23 |
20150108654 | RELIABLE PASSIVATION LAYERS FOR SEMICONDUCTOR DEVICES - Device and method for forming a device are disclosed. A substrate which is prepared with a dielectric layer having a top metal level of the device is provided. The top metal level includes top level conductive lines. A top dielectric layer which includes top via openings in communication with the top level conductive lines is formed over the top metal level. A patterned top conductive layer is formed on the top dielectric layer. The patterned top conductive layer includes a top via in the top via opening and a top conductive line. A first passivation sub-layer is formed to line the patterned conductive layer and exposed top dielectric layer. A plasma treatment is performed on the surface of the first passivation sub-layer to form a nitrided layer. A second passivation sub-layer is formed to line the nitrided layer. The plasma treatment improves the passivation integrity of the passivation stack. | 2015-04-23 |
20150108655 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Both enhancement of embeddability of a wiring groove and suppression of the generation of a coupling failure between a wiring and a coupling member are simultaneously achieved. In a cross-section perpendicular to a direction passing through the contact and a direction in which the second wiring extends, the center of the contact is more close to a first side surface of the second wiring than the center of the second wiring. In addition, when a region where the first side surface of the second wiring overlaps the contact in the direction in which the second wiring extends, is set to be an overlapping region, at least the lower part of the overlapping region has an inclination steeper than that of other portions of the side surface of the second wiring. | 2015-04-23 |
20150108656 | STACKED DIE PACKAGE - Disclosed is a package-on-package (PoP) assembly comprises a two-tiered windowed ball grid array (BGA) and a system on a chip (SoC) package. Window openings in the two tiers of the BGA are of different sizes to allow for wirebond landing pads on the first tier. A DRAM die is mounted to the BGA flipped over (i.e., wirebond pads facing the BGA package.) The DRAM die is wirebonded through the window in the BGA. For multi-channel systems and higher memory capacity, the DRAM die will have low-cost through-silicon vias (TSVs) that connect to stacked DRAM die(s). The stacked DRAM dies may be offset or rotated to align active TSVs with passive TSVs thereby enabling unique connections to certain DRAM dies in the stack. | 2015-04-23 |
20150108657 | ELECTRONIC DEVICE - A semiconductor device and electronic device comprising the same includes at least one dummy chip having at least one Through Silicon Via (TSV), and at least one active chip connected to the at least one dummy chip. The at least one active chip exchanges an electrical signal through the at least one TSV. The at least one active chip may be a memory chip and a non-memory chip in a vertically stacked (3D) configuration, connected through an electrical path that includes the TSV of the dummy chip. Embodiments may include multiple memory chips and dummy chips. | 2015-04-23 |
20150108658 | SELF-ALIGNED NANO-STRUCTURES - A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer layer over the dielectric layer. The polymer layer is applied uniformly and fills the apertures at different rates depending on the geometry of the apertures, or on the presence or absence of growth accelerating material. The polymer creates spacers for the etching of additional structure in between the spacers. The method is capable of achieving structures smaller than current lithography techniques. | 2015-04-23 |
20150108659 | 3D-Packages and Methods for Forming the Same - A package includes an interposer, which includes a first substrate free from through-vias therein, redistribution lines over the first substrate, and a first plurality of connectors over and electrically coupled to the redistribution lines. A first die is over and bonded to the first plurality of connectors. The first die includes a second substrate, and through-vias in the second substrate. A second die is over and bonded to the plurality of connectors. The first die and the second die are electrically coupled to each other through the redistribution lines. A second plurality of connectors is over the first die and the second die. The second plurality of connectors is electrically coupled to the first plurality of connectors through the through-vias in the second substrate. | 2015-04-23 |
20150108660 | STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS - A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element. | 2015-04-23 |
20150108661 | MICROELECTRONIC PACKAGES CONTAINING STACKED MICROELECTRONIC DEVICES AND METHODS FOR THE FABRICATION THEREOF - Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method includes encapsulating a device stack within a molded panel having a frontside and a backside. The device stack contains an upper semiconductor die and an interconnect buffer layer, which is formed over the upper semiconductor die and which is covered by the frontside of the molded panel. Material is removed from the frontside the molded panel to expose the interconnect buffer layer therethrough. One or more frontside redistribution layers are produced over the frontside of the molded panel and electrically coupled to the upper semiconductor die through the interconnect buffer layer. The molded panel is then singulated to yield a microelectronic package including a molded package body containing the device stack. | 2015-04-23 |
20150108662 | PACKAGE MODULE WITH OFFSET STACK DEVICE - A package module with offset stacked device is provided which includes a group of stacked device, a carrier and a substrate. The group of stacked device is offset stacked to dispose in the carrier and the substrate is disposed on the bottom of the carrier. A plurality of electric connections is disposed on the surface substrate that is opposite to the carrier. A plurality of outer connections on another surface of the substrate is electrically connected with the plurality of electric connections. The group of the stacked device is electrically connected with the carrier by the connecting the plurality of metal connections and the pads. The plurality of metal connections is extended to the bottom of the carrier to form another metal connection to electrically connect with the electric connection on the substrate. | 2015-04-23 |
20150108663 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor package in which a cell array region and a peripheral circuit region are formed as different semiconductor chips, respectively. First semiconductor chips including memory cells and a second semiconductor chip including only peripheral circuitry common to the first semiconductor chips are electrically connected to each other. Thus, a loading capacitance of the semiconductor package may be reduced. As a result, an RC delay of the semiconductor package may be reduced, thereby improving an operating speed of the semiconductor package. | 2015-04-23 |
20150108664 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device which includes a bonding wire, one end of which is connected to a bipolar device, the other end of which is connected to a conductive member, and the center of which is connected to a unipolar device, said semiconductor device being capable of improving the reliability of wire bonding. A package ( | 2015-04-23 |
20150108665 | CIRCUIT MODULE AND MANUFACTURING METHOD THEREOF - A circuit module including: a wiring substrate having a shape elongated in one direction; a semiconductor chip mounted on the wiring substrate; and a molding material that molds the semiconductor chip, wherein end faces of the molding material that extend along a lengthwise direction of the wiring substrate and intersect with a lateral direction of the wiring substrate are formed by dicing performed along end faces of a partial region of the wiring substrate. | 2015-04-23 |
20150108666 | Thinning in package using separation structure as stop - A method of forming a thinned encapsulated chip structure, wherein the method comprises providing a separation structure arranged within an electronic chip, encapsulating part of the electronic chip by an encapsulating structure, and thinning selectively the electronic chip partially encapsulated by the encapsulating structure so that the encapsulating structure remains with a larger thickness than the thinned electronic chip, wherein the separation structure functions as a thinning stop. | 2015-04-23 |
20150108667 | APPARATUS AND METHOD FOR CHIP PLACEMENT AND MOLDING - An approach is provided for placing and securing a chip package portion in an aligned position during a curing process. The approach involves providing an apparatus having a first reservoir configured to receive a first chip package, a second reservoir, and a third reservoir. The approach also involves placing the first chip package portion into the first reservoir, the second chip package portion into the second reservoir, and the third chip package portion into the third reservoir. The approach further involves causing the first chip package portion to be secured in a first curing position, the second chip package portion to be secured in a second curing position and the third chip package portion to be secured in a third curing position. | 2015-04-23 |
20150108668 | SUBLIMATION PURIFICATION APPARATUS AND METHOD - The invention relates to a sublimation purification apparatus and a method for purifying a material for an organic light-emitting diode (OLED). Conventional sublimation purification apparatuses are batch type, where one sublimation purification process is performed by loading one source material into the processor chamber, and then unloading a purified material from the process chamber. These processes are manually performed, and thus it is not possible to continuously produce the purified material for the OLED. Therefore, it is difficult to increase a throughput and productivity. According to the invention, loading the source material and unloading the purified material are performed automatically, thus enabling a continuous process of purifying the source material for the OLED. | 2015-04-23 |
20150108669 | REFRIGERATOR APPLIANCE AND METHOD FOR USE WITH FRAGRANCE DISPENSER - Refrigerator appliances for use with fragrance dispensers, and methods for operating refrigerator appliances, are provided. A method includes providing a fragrance dispenser in a housing, the housing disposed in a dispenser recess defined in the refrigerator appliance. The method further includes flowing a gas from an outlet conduit into the fragrance dispenser. | 2015-04-23 |
20150108670 | HUMIDIFIED GAS DELIVERY SYSTEM - This invention relates to a method for delivering humidified gas to a user or patient during respiratory gas ventilation support, such as, but not limited to, mechanical ventilation, continuous positive airway pressure breathing, and bi-directional positive airway pressure breathing; the method comprising the steps of heating a humidified gas from a humidified gas reservoir; transferring the heated humidified gas to a patient; receiving expired gas from a patient; heating the expired gas; and transferring the heated expired gas to a gas outlet; wherein the humidified gas and the expired gas are heated to different temperatures. Also disclosed is a humidified gas delivery system, which finds utility as a breathing circuit of a respiratory gas humidification system by delivering humidified gases to a user or patient during mechanical ventilation, continuous positive airway pressure breathing, bi-directional positive airway pressure breathing, or other mode of respiratory support provided to users or patients. | 2015-04-23 |
20150108671 | METHOD FOR PRODUCING FINE PARTICLES AND APPARATUS FOR PRODUCING FINE PARTICLES - A method for producing fine particles, including: discharging a fine particle material liquid, where solid materials to be formed into fine particles are dissolved or dispersed in a solvent or are melted, from two or more discharge holes in a downward vertical direction, to thereby form liquid droplets; and solidifying the liquid droplets discharged to form fine particles, wherein in the discharging a fine particle material liquid, gas flow is supplied at angle of greater than 0° but 90° or smaller to the downward vertical direction, and wherein an initial discharge velocity of the liquid droplets discharged from the discharge hole located at an upstream side of the gas flow in a flowing direction thereof is equal to or higher than an initial discharge velocity of the liquid droplets discharged from the discharge hole located at a downstream side of the gas flow in the flowing direction thereof. | 2015-04-23 |
20150108672 | DEVICE AND METHOD FOR ADJUSTING POST-SPACER HEIGHT IN PRODUCTION OF LIQUID CRYSTAL DISPLAYS - A device and a method for adjusting post-spacer height in production of liquid crystal displays (LCDs), and the device comprises a controller ( | 2015-04-23 |
20150108673 | IMPRINTING APPARATUS AND METHOD FOR IMPRINTING - A micro-contact imprinting apparatus for transferring patterns of a stamp to a substrate. | 2015-04-23 |
20150108674 | IMPRINT APPARATUS, AND METHOD OF MANUFACTURING ARTICLE - The present invention provides an imprint apparatus which performs an imprint process of forming a pattern on a substrate by using a mold, the apparatus comprising a heating unit configured to heat a region to be imprinted on the substrate, thereby deforming the region, and a processing unit configured to determine, as a region to be imprinted first, one region out of a first region and second region to be imprinted, and determine the other region as a region to be imprinted subsequently, wherein an influence on the other region in a case where the heating unit deforms the one region is smaller than an influence on the one region in a case where the heating unit deforms the other region. | 2015-04-23 |
20150108675 | MULTI ZONE CEMENTITIOUS PRODUCT AND METHOD - A multi-zone cementitious product, which includes a base zone made of a first cementitious material composition and forming a portion of the product. At least one facing zone is adjacent to and bonded to the base zone, the facing zone made of a second cementitious material composition and forming at least one exterior face of said product which is visible when the product is installed. A disrupted boundary layer is between the facing zone and the base zone, and includes material from both the facing zone and the base zone. The disrupted boundary layer bonds the facing zone to the base zone. The facing zone has a thickness sufficient to prevent the base zone from being visible when the product is installed. | 2015-04-23 |
20150108676 | Method for Manufacturing Slide Fastener - There is provided a slide fastener and a method for manufacturing a slide fastener. A slide fastener is provided with: a pair of fastener tapes; a pair of fastener element rows provided respectively on the opposing tape-side edges of the pair of fastener tapes and having a plurality of fastener elements; and a slider configured to engage and disengage the pair of fastener element rows with and from each other. Each of the fastener element rows is composed of a monofilament which is made of synthetic resin. The monofilament has, on the surface thereof, a surface layer which can be colored with dyes. A roughened surface having a number of concaves is formed on the surfaces of the surface layer. | 2015-04-23 |
20150108677 | THREE DIMENSIONAL PRINTER WITH COMPOSITE FILAMENT FABRICATION - Various embodiments related to three dimensional printers, and reinforced filaments, and their methods of use are described. In one embodiment, a void free reinforced filament is fed into an conduit nozzle. The reinforced filament includes a core, which may be continuous or semi-continuous, and a matrix material surrounding the core. The reinforced filament is heated to a temperature greater than a melting temperature of the matrix material and less than a melting temperature of the core prior to drag the filament from the conduit nozzle. | 2015-04-23 |
20150108678 | METHOD FOR PRODUCING A LOAD INTRODUCING ELEMENT - A method for producing a load introducing element for a control surface of an aircraft or a spacecraft, includes cutting to size preformed fibrous substructures out of a fibrous material. The method also includes draping the fibrous substructures to mold at least one first component, at least one second component and at least one first flange in the form of a single semi-finished product. Further, the method includes inserting the semi-finished product into a mold, injecting matrix material, and curing said semi-finished product to form a finished product. | 2015-04-23 |
20150108679 | FLAME-RETARDANT POLY LACTIC ACID-CONTAINING FILM OR SHEET, AND METHOD FOR MANUFACTURING THEREOF - A film or sheet composed of a resin composition including a poly lactic acid (A), an acidic functional group-modified olefinic polymer (B) including an acidic functional group and having an acid value of 10 to 70 mg KOH/g and a weight average molecular weight of 10,000 to 80,000, a tetrafluoroethylene polymer (C), and an aromatic cyclic phosphazene-containing flame retardant (D) including a compound of Formula (I) and in (D) is included in an amount of 10 to 70 parts by weight based on 100 parts by weight of (A), and a method for manufacturing the film or sheet by melt film formation. | 2015-04-23 |
20150108680 | DEVICE AND METHOD OF CORRECTING EXTRUDATE BOW - Disclosed apparatus and method to extrude a honeycomb, providing correction in bowing of the extruded honeycomb structure, employs a deflector device having a base plate including an opening aligned in a direction parallel to the extrusion axis through which the plastic material is conveyed to the die. The deflector device includes a bow plate movably mounted to the downstream or upstream side of the base plate. The bow plate includes a constant area aperture. The deflector device positioned upstream of extrusion die imparts a degree of bow reduction by the position of the constant area aperture over the opening imparting a pressure drop gradient on the flow stream entering the die. | 2015-04-23 |
20150108681 | GOLF CLUB HEAD HAVING MULTI-MATERIAL FACE AND METHOD OF MANUFACTURE - A golf club with a multi-material face is disclosed herein. More specifically, the golf club head in accordance with the present invention has a striking face portion that is backed by a composite layer. The multi-material face disclosed in accordance with the present invention may generally be manufactured via a bladder molding process that applies hydrostatic forces to the composite layer to create a more consistent bond between the composite material and the metallic material. | 2015-04-23 |
20150108682 | METHOD OF MAKING A FILTER SEAL - The invention relates to an injection molding process to make a sealing surface about a periphery of a filter cartridge. | 2015-04-23 |
20150108683 | Method of Manufacturing Rubber and Polyolefin Sole Assembly - A sole assembly is formed by preheating a mold assembly, placing a quantity of rubber in a first portion of a lower recess of a mold assembly; placing a middle plate in contact with a bottom plate, and an upper plate in contact with the middle plate; subjecting the top, middle, and bottom plates to heat to semi-cure the rubber in the lower recess to form an outsole member; separating the top plate, the middle plate, and the bottom plate; placing the top plate in contact with the bottom plate, with polyolefin forming a midsole above the semi-cured rubber; moving the movable insert upwardly with respect to the top plate; subjecting the top and bottom plates to heat such that the polyolefin expands within the sole recess and the polyolefin and rubber in the sole recess fully cure, cross-link, and bond to one another to form a sole assembly; cooling the top and bottom plates; and removing the sole assembly. | 2015-04-23 |
20150108684 | MOLD ASSEMBLY FOR MAKING A BOTTOM END CAP IN A PLEATED FILTER CARTRIDGE AND RELATED METHOD - A mold assembly for forming a bottom end cap in a pleated filter cartridge includes a master mold component having a cup-shaped body including a bottom wall and an annular peripheral wall, an interior surface of the bottom wall having a radially outward portion tapered upwardly in a radial inward direction and a flat center section. An associated sleeve component includes a peripheral side wall and a bottom wall shaped to fit within the master mold component, an exterior surface of the bottom wall having a taper complementary to the radially outward tapered portion of the master mold component and a center opening alignable with the flat center section of the master mold component. | 2015-04-23 |
20150108685 | Self-Centering Sealant Applicator - A method and apparatus for applying sealant. The apparatus may comprise a shaping portion, a centering portion, and a support system. The shaping portion may have a cavity configured to receive a fastener system and receive a sealant. The centering portion may have a channel configured to position the shaping portion in a desired position around the fastener system when the fastener system is received in the cavity. The support system may be configured to maintain the desired position of the apparatus. | 2015-04-23 |
20150108686 | CLOTH-LIKE SYNTHETIC TEXTILES - An embossing and texturizing system for imparting a natural cloth-like surface to a flexible thermoplastic material or film simultaneously to either or both of its two exterior surfaces, through the use of a device and technique combining metal rolls, metal and rubber rolls, and embossing and texturizing fabric rolls into an embossing system creating the desired visual and tactile feel of natural fabrics as well as additional performance characteristics. The embossing and texturizing system embosses and texturizes the exterior surface of the flexible thermoplastic material or film by selectively altering the exterior surface, and therefore, the film can be embossed simultaneously on either or both of its two exterior surfaces (face and reverse). The use of the embossing and texturizing mechanism and its alignment to the core and stabilizing reinforcing substrate enables the exterior texturized surface and the bottom side exterior texturized surface to be identical in all manner. | 2015-04-23 |
20150108687 | Manufacturing in Microgravity and Varying External Force Environments - Additive manufacturing devices operable in various external force environments are disclosed. In an aspect, an additive manufacturing device operable in microgravity is disclosed. In other aspects, devices which are operable in high-vibration environments or varying external force environments are disclosed. Additive manufacturing devices herein may produce parts from metal, polymer, or other feedstocks. | 2015-04-23 |
20150108688 | RESIN DISPENSER FOR NANO-IMPRINT - A resin dispenser for nano-imprinting includes a housing including a lower chamber in which a resin is filled, a slit defined in a lower part of the lower chamber and through which the resin is discharged, and an upper chamber in which a pressure-applying fluid is filled, and a membrane separating the lower and upper chambers from each other, and of which an edge is fixed on a middle part of the housing, where the fluid is configured to apply the pressure to the membrane and protrude the membrane toward the slit of the lower chamber. | 2015-04-23 |
20150108689 | PLASTIC MOLDING APPARATUS WITH AN ADJUSTABLE BARREL AND ASSOCIATED METHODS - A molding apparatus includes an extruder to provide a molten composite material, and an adjustable extension barrel coupled to the extruder to receive the molten composite material. The adjustable extension barrel has a drop point to output the molten composite material. The adjustable extension barrel is moveable in a first direction between an extended position and a retracted position to change position of the drop point. A structure is movable in a second direction that is perpendicular to the first direction. A lower mold is carried by the structure and is positioned to receive the molten composite material from the drop point of the adjustable extension barrel. A press includes an upper mold and is operated to press the upper mold against the lower mold to form a molded article. | 2015-04-23 |
20150108690 | SHEET DIE APPARATUS WITH DIRECT EXTRUDER INTERFACE AND ASSOCIATED METHODS - A sheet die apparatus includes an extruder with an auger configured to provide a molten composite material. A sheet die has an opening to receive the auger, and a chamber therein to receive the molten composite material so as to form a sheet. | 2015-04-23 |